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Применить Всего найдено 31. Отображено 30.
03-01-2019 дата публикации

GATE STRUCTURE AND METHODS THEREOF

Номер: US20190006488A1
Автор: CHENG Anhao, KUO Fang-Ting
Принадлежит:

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. 1. A method of fabricating a semiconductor device , comprising:forming a gate dielectric trench within a substrate;depositing a first dielectric layer within the gate dielectric trench, wherein a top surface of the first dielectric layer is co-planar with a top surface of the substrate;forming a second dielectric layer over the first dielectric layer; andforming a metal gate over the second dielectric layer.2. The method of claim 1 , wherein the forming the gate dielectric trench further includes etching the gate dielectric trench to a first depth claim 1 , and wherein the first depth is measured from a plane parallel to the top surface of the substrate to a bottom surface of the gate dielectric trench.3. The method of claim 1 , wherein the forming the gate dielectric trench further includes forming the gate dielectric trench having a first width along the plane parallel to the top surface of the substrate claim 1 , and forming the gate dielectric trench having a second width along a plane parallel to the bottom surface of the gate dielectric trench.4. The method of claim 3 , wherein the second width is less than the first width.5. The method of claim 1 , further ...

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Номер записи: 1
21-01-2021 дата публикации

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

Номер: US20210020506A1
Автор: CHENG Anhao, Liu Chun-Chang
Принадлежит:

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

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Номер записи: 2
23-01-2020 дата публикации

GATE STRUCTURE AND METHODS THEREOF

Номер: US20200027964A1
Автор: CHENG Anhao, KUO Fang-Ting
Принадлежит:

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. 1. A semiconductor device , comprising:a substrate including a gate dielectric trench within an active region of the substrate, wherein the active region is free of a shallow trench isolation feature;a first dielectric layer formed within the gate dielectric trench, wherein a top surface of the first dielectric layer is level with a top surface of the substrate;a second dielectric layer disposed over the first dielectric layer; anda metal gate disposed over the second dielectric layer;wherein the first dielectric layer and the second dielectric layer provide a gate oxide of the semiconductor device.2. The semiconductor device of claim 1 , further including a source region and a drain region formed within the substrate and on either side of the gate dielectric trench.3. The semiconductor device of claim 2 , wherein the gate dielectric trench has a first depth claim 2 , and wherein the source region and the drain region extend into the substrate a second depth greater than the first depth.4. The semiconductor device of claim 1 , wherein the gate dielectric trench has a first width along a plane parallel to the top surface of the substrate claim 1 , and wherein the ...

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Номер записи: 3
01-02-2018 дата публикации

SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND METHOD OF FORMING THE SAME

Номер: US20180033745A1
Автор: CHENG Anhao, Liu Chun-Chang
Принадлежит:

A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer. 1. A semiconductor device comprising:a first passivation layer over an interconnect structure;a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure, wherein the first RDL via comprises a first conductive material;an RDL over the first passivation layer and electrically connected to the first RDL via, wherein the RDL comprises a second conductive material different from the first conductive material, and the RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer; anda second passivation layer over the RDL, wherein a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to the top surface of the first passivation layer.2. The semiconductor device of claim 1 , wherein a top surface of the RDL over the first RDL via is substantially flat.3. The semiconductor device of claim 1 , wherein a top surface of the second passivation layer over the RDL is substantially flat.4. The semiconductor device of claim 1 , wherein the second passivation layer over the RDL is free of voids.5. The semiconductor device of claim 1 , wherein the first RDL via comprises copper and the RDL comprises aluminum.6. The semiconductor ...

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Номер записи: 4
05-05-2022 дата публикации

GATE STRUCTURE AND METHODS THEREOF

Номер: US20220140109A1
Автор: CHENG Anhao, KUO Fang-Ting
Принадлежит:

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

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Номер записи: 5
31-05-2018 дата публикации

Redistribution layer structure and fabrication method therefor

Номер: US20180151525A1
Автор: Anhao CHENG, Chun-Chang Liu, Sheng-Wei YEH
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

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Номер записи: 6
22-09-2022 дата публикации

SEMICONDUCTOR DEVICE HAVING A REDISTRIBUTION LINE

Номер: US20220302060A1
Автор: CHENG Anhao, Liu Chun-Chang, YEH Sheng-Wei
Принадлежит:

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer. 1. A semiconductor device comprising:a first passivation layer over a substrate;a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape;a second passivation layer configured to cause stress to the PPI line; anda polymer material over the second passivation layer.2. The semiconductor device of claim 1 , wherein the top-most portion of the PPI line has a third portion having a convex shape.3. The semiconductor device of claim 2 , wherein the second portion is between the first portion and the third portion.4. The semiconductor device of claim 1 , wherein the second passivation layer comprises:a first sub-layer directly contacting the PPI line; anda second sub-layer over the first sub-layer.5. The semiconductor device of claim 4 , wherein the first sub-layer comprises a first material claim 4 , and the second sub-layer comprises a second material different from the first material.6. The semiconductor device of claim 4 , wherein the first sub-layer has a first thickness claim 4 , and the second sub-layer has a second thickness different from the first thickness.7. The semiconductor device of claim 1 , further comprising an interconnect structure claim 1 , wherein the first passivation layer is over the interconnect structure.8. The semiconductor device of claim 7 , wherein the PPI line is ...

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Номер записи: 7
14-05-2020 дата публикации

Semiconductor device having a redistribution line

Номер: US20200152589A1
Автор: Anhao CHENG, Chun-Chang Liu, Sheng-Wei YEH
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.

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Номер записи: 8
04-10-2018 дата публикации

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE

Номер: US20180286784A1
Автор: CHENG Anhao, Liu Chun-Chang
Принадлежит:

A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL). 1. A method of making a semiconductor device , the method comprising:plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure;planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer;depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening; andpatterning the second conductive material to define a redistribution line (RDL).2. The method of claim 1 , further comprising depositing a second passivation layer over the RDL claim 1 , wherein a top surface of the second passivation layer is flat.3. The method of claim 1 , further comprising depositing a second passivation layer over the RDL claim 1 , wherein the second passivation layer is free of ...

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Номер записи: 9
03-11-2022 дата публикации

SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE

Номер: US20220352022A1
Автор: CHENG Anhao, Liu Chun-Chang
Принадлежит:

A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve. 1. A semiconductor device comprising:a first conductive element electrically connects to an interconnect structure, wherein the first conductive element comprises a first conductive material;an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL comprises a second conductive material different from the first conductive material; anda passivation layer over the RDL, wherein a top portion of a sidewall of the passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.2. The semiconductor device of claim 1 , wherein the first conductive element comprises copper.3. The semiconductor device of claim 2 , wherein the RDL comprises aluminum.4. The semiconductor device of claim 2 , wherein an entirety of the passivation layer over a top surface of the RDL via has a planar ...

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Номер записи: 10
17-11-2022 дата публикации

BARRIER LAYER FOR METAL INSULATOR METAL CAPACITORS

Номер: US20220367606A1
Автор: Chen Yen-Yu, CHENG Anhao, KUO Fang-Ting
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

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Номер записи: 11
30-09-2021 дата публикации

Barrier layer for metal insulator metal capacitors

Номер: US20210305356A1
Автор: Anhao CHENG, Fang-Ting KUO, Yen-Yu Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

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Номер записи: 12
18-01-2022 дата публикации

Gate structure and methods thereof

Номер: US11227935B2
Автор: Anhao CHENG, Fang-Ting KUO
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

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Номер записи: 13
05-06-2018 дата публикации

Semiconductor device having a dual material redistribution line

Номер: US9991189B2
Автор: Anhao CHENG, Chun-Chang Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer.

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Номер записи: 14
29-02-2024 дата публикации

Embedded soi structure for low leakage mos capacitor

Номер: US20240071812A1
Автор: Anhao CHENG, Chung-Lei Chen, Meng-I Kang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.

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Номер записи: 15
02-03-2023 дата публикации

Structure and method for multiple beol k-value dielectric

Номер: US20230061546A1
Автор: Anhao CHENG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

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Номер записи: 16
16-11-2023 дата публикации

Gate structure and methods thereof

Номер: US20230369450A1
Автор: Anhao CHENG, Fang-Ting KUO
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

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Номер записи: 17
24-10-2023 дата публикации

Gate structure and methods thereof

Номер: US11799014B2
Автор: Anhao CHENG, Fang-Ting KUO
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

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Номер записи: 18
29-06-2023 дата публикации

Semiconductor devices and methods of manufacturing thereof

Номер: US20230207313A1
Автор: Anhao CHENG, Chung-Lei Chen, Meng-I Kang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.

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Номер записи: 19
07-05-2024 дата публикации

Partial metal grain size control to improve CMP loading effect

Номер: US11978781B2
Автор: Anhao CHENG, Fang-Ting KUO, Yen-Yu Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

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Номер записи: 20
09-04-2024 дата публикации

Structure and method for interlevel dielectric layer with regions of differing dielectric constant

Номер: US11955421B2
Автор: Anhao CHENG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

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Номер записи: 21
28-03-2024 дата публикации

Semiconductor devices and methods of fabricating the same

Номер: US20240105751A1
Автор: Anhao CHENG, Chung-Lei Chen, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.

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Номер записи: 22
30-11-2023 дата публикации

Partial metal grain size control to improve cmp loading effect

Номер: US20230387244A1
Автор: Anhao CHENG, Fang-Ting KUO, Yen-Yu Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

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Номер записи: 23
02-07-2024 дата публикации

Semiconductor device having a dual material redistribution line

Номер: US12027447B2
Автор: Anhao CHENG, Chun-Chang Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

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Номер записи: 24
14-12-2023 дата публикации

Struktur und verfahren für metall-isolator-metall-kondensatoren

Номер: DE102020110759B4
Автор: Anhao CHENG, Fang-Ting KUO, Yen-Yu Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Struktur, umfassend: eine erste Interconnect-Schicht, die auf einem Substrat (210) angeordnet ist, wobei die erste Interconnect-Schicht leitfähige Strukturen umfasst; eine Kondensatorstruktur (610, 900), die auf einer leitfähigen Struktur der ersten Interconnect-Schicht ausgebildet ist, wobei die Kondensatorstruktur (610, 900) umfasst: eine erste Elektroden-Doppelschicht (300), die eine erste Schicht (310) und eine zweite Schicht (320) umfasst, die jeweils eine andere Stickstoffkonzentration umfassen; eine dielektrische Schicht (400), die auf der zweiten Schicht (320) der ersten Elektroden-Doppelschicht (300) angeordnet ist; und eine zweite Elektroden-Doppelschicht (500) auf der dielektrischen Schicht (400), die eine dritte Schicht (510) und eine vierte Schicht (520) umfasst, die jeweils eine andere Stickstoffkonzentration umfassen; eine zweite Interconnect-Schicht auf der Kondensatorstruktur (610, 900), wobei eine leitfähige Struktur der zweiten Interconnect-Schicht mit der vierten Schicht (520) der zweiten Elektroden-Doppelschicht (500) in Kontakt steht; eine Deckschicht (600), die auf einer Oberseitenfläche der vierten Schicht (520) angeordnet ist; und einen Stapel (700), der eine Oberseitenfläche der Deckschicht (600) und Seitenwandflächen der Kondensatorstruktur (610, 900) bedeckt.

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Номер записи: 25
25-07-2024 дата публикации

Halbleitervorrichtung und verfahren zu ihrer herstellung

Номер: DE102018106266B4
Автор: Anhao CHENG, Fang-Ting KUO
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Verfahren zum Herstellen einer Halbleitervorrichtung, mit den folgenden Schritten:Erzeugen eines Gate-Dielektrikumgrabens (702) in einem Substrat (602), wobei das Erzeugen des Gate-Dielektrikumgrabens weiterhin das Ätzen des Gate-Dielektrikumgrabens bis zu einer ersten Tiefe (D1) umfasst, wobei die erste Tiefe von einer Ebene, die zu der Oberseite des Substrats parallel ist, bis zu einer Unterseite des Gate-Dielektrikumgrabens gemessen wird;Abscheiden und Planarisieren einer ersten dielektrischen Schicht (802) in dem Gate-Dielektrikumgraben (702), sodass eine Oberseite der ersten dielektrischen Schicht (802) koplanar mit einer Oberseite des Substrats ist;Herstellen einer zweiten dielektrischen Schicht (902) über der ersten dielektrischen Schicht (802), wobei die erste dielektrische Schicht und die zweite dielektrische Schicht ein Gate-Oxid der Halbleitervorrichtung bereitstellen; undAusbilden eines Gate Stapels (1102) durch Herstellen einer Polysiliziumschicht (1002) über der zweiten dielektrischen Schicht (902), durch Strukturieren der Polysiliziumschicht (1002) zum Herstellen einer strukturierten Polysiliziumschicht (1002A), durch Strukturieren der zweiten dielektrischen Schicht (902) zum Herstellen einer strukturierten zweiten dielektrischen Schicht (902A), durch Entfernen der strukturierten Polysiliziumschicht (1002A) und durch Herstellen eines Metall-Gates (1210) über der strukturierten zweiten dielektrischen Schicht (902A), wobei eine Grabenbreite des Gate-Dielektrikumgrabens (702) im Wesentlichen gleich einer Breite des Gate-Stapels (1102) ist; Herstellen eines Source-Bereichs und eines Drain-Bereichs (1204, 1206) in dem Substrat und auf beiden Seiten des Gate-Dielektrikumgrabens und zwar so, dass sie mit einer zweiten Tiefe (D2) in das Substrat hineinreichen, wobei die zweite Tiefe größer als die erste Tiefe ist, und wobei der Source-Bereich und der Drain-Bereich epitaxial aufgewachsen sind, und wobei der Source-Bereich und der Drain-Bereich von dem Gate- ...

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Номер записи: 26
18-01-2024 дата публикации

Semiconductor structure and method of manufacturing the same

Номер: US20240021738A1
Автор: Anhao CHENG, Chien-Wei Lee, Ching-Hung Kao, Kai-Chi WU, Meng-I Kang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure including a substrate, a first well region, a second well region, an isolation, a gate structure, and a dielectric layer is provided. The first well region is disposed in the substrate, wherein a dopant of the first well region includes arsenic. The second well region is disposed in the substrate under the first well region, wherein the second well region has a conductivity type different from that of the first doping region. The isolation is disposed in the substrate and surrounds the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate. The gate structure are disposed sequentially over the substrate and overlaps the first well region. A method of forming the semiconductor structure is also provided.

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Номер записи: 27
27-08-2024 дата публикации

Semiconductor devices and methods of manufacturing thereof

Номер: US12074024B2
Автор: Anhao CHENG, Chung-Lei Chen, Meng-I Kang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.

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Номер записи: 28
25-07-2024 дата публикации

Structure and method for interlevel dielectric layer with regions of differing dielectric constant

Номер: US20240250018A1
Автор: Anhao CHENG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

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Номер записи: 29
06-06-2024 дата публикации

Large dimension metal gate field-effect transistor (fet) with metal gate dummy structures

Номер: US20240186397A1
Автор: Anhao CHENG, Meng-I Kang, Yen-Liang Lin, Yu-chen Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.

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Номер записи: 30