18-11-2009 дата публикации
Номер: CN0101582686A
Принадлежит:
The invention discloses a power level shifter comprising a control logic circuit, a plurality of power level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives a plurality of input clock pulse signals and a charge sharing signal, and obtains the power level information of the signals; the output buffers are respectively used for conducting enlarging treatment to corresponding individuals in the input clock pulse signals, and the power level information of the charge sharing signal determines whether the corresponding individuals are output; and each charge sharing circuit is electrically coupled between the output ends of the corresponding individuals in the output buffers and a prearranged power level, and is determined whether to be conducted by the power level information of the input clock pulse signals of the corresponding individuals, and if the charge sharing circuit is conducted, the prearranged power level is electrically communicated ...
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