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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 681. Отображено 193.
25-06-2019 дата публикации

Fin-type field effect transistor structure and manufacturing method thereof

Номер: US0010332879B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

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Номер записи: 1
28-04-2020 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0010636787B2
Автор: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, WU PO-CHI, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Wu, Po-Chi, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

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Номер записи: 2
07-11-2017 дата публикации

Semiconductor structure and fabricating method thereof

Номер: US0009812577B2
Автор: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin, CHANG CHE-CHENG, CHENG TUNG-WEN, CHEN CHANG-YIN, LIN MU-TSANG, Chang Che-Cheng, Cheng Tung-Wen, Chen Chang-Yin, Lin Mu-Tsang
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

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Номер записи: 3
06-07-2017 дата публикации

INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20170194247A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang Che-Cheng, Lin Chih-Han
Принадлежит:

An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

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Номер записи: 4
06-06-2023 дата публикации

Semiconductor device and method

Номер: US0011670635B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.

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Номер записи: 5
10-10-2023 дата публикации

Semiconductor device and method

Номер: US0011784242B2
Автор: Bo-Feng Young, Po-Chi Wu, Che-Cheng Chang
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

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Номер записи: 6
28-07-2020 дата публикации

Fin field effect transistor, semiconductor device and method for fabricating the same

Номер: US0010727132B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

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Номер записи: 7
04-05-2021 дата публикации

Source/drain regions in fin field effect transistors (finFETs) and methods of forming same

Номер: US0010998313B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

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Номер записи: 8
13-03-2018 дата публикации

Method for fabricating FinFET isolation structure

Номер: US0009917176B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang Che-Cheng, Lin Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

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Номер записи: 9
23-04-2019 дата публикации

Semiconductor device and method

Номер: US0010269940B2
Автор: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu, YOUNG BO-FENG, CHANG CHE-CHENG, WU PO-CHI, Young, Bo-Feng, Chang, Che-Cheng, Wu, Po-Chi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

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Номер записи: 10
20-02-2018 дата публикации

Interconnection and manufacturing method thereof

Номер: US0009899320B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE CHENG, LIN CHIH HAN, TSENG HORNG HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between a portion of the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different. The air gaps are located between another portion of the dielectric layer and the second conductive layer.

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Номер записи: 11
23-08-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180240895A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

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Номер записи: 12
15-07-2021 дата публикации

Semiconductor Device and Method

Номер: US20210217750A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит:

A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.

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Номер записи: 13
17-05-2018 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20180138173A1
Автор: Chai-Wei Chang, Po-Chi Wu, Che-Cheng Chang
Принадлежит:

In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

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Номер записи: 14
09-08-2022 дата публикации

Integrated circuit and manufacturing method thereof

Номер: US0011411001B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

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Номер записи: 15
31-08-2023 дата публикации

Structure of Semiconductor Device Structure Having Fins

Номер: US20230275142A1
Автор: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
Принадлежит:

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

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Номер записи: 16
25-07-2017 дата публикации

Semiconductor device

Номер: US0009716093B1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device including a substrate, insulators, a gate dielectric layer, a first gate structure and a second gate structure is provided. The substrate includes trenches, a first semiconductor fin and a second semiconductor fin. The first gate structure is disposed on the gate dielectric layer and partially covers the first semiconductor fin. The first gate structure includes a first metal gate and a first dielectric cap covering the first metal gate. The second gate structure is disposed on the gate dielectric layer and partially covers the second semiconductor fin. The second gate structure includes a second metal gate and a second dielectric cap covering the second metal gate. Work function of the first metal gate is smaller than work function of the second metal gate and thickness of the first dielectric cap is smaller than thickness of the second dielectric cap.

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Номер записи: 17
25-07-2017 дата публикации

Gate structure having designed profile and method for forming the same

Номер: US0009716161B2
Автор: Kai-Li Cheng, Che-Cheng Chang
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C.

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Номер записи: 18
14-04-2020 дата публикации

Semiconductor device

Номер: US0010622353B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 19
11-04-2017 дата публикации

Gate structure of field effect transistor with footing

Номер: US0009620621B2
Автор: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang, CHANG CHE-CHENG, CHEN CHANG-YIN, LIN JR-JUNG, LIN CHIH-HAN, CHANG YUNG JUNG, Chang Che-Cheng, Chen Chang-Yin, Lin Jr-Jung, Lin Chih-Han, Chang Yung Jung
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

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Номер записи: 20
28-03-2017 дата публикации

Semiconductor device structure

Номер: US0009608113B2
Автор: Che-Cheng Chang, Yi-Jen Chen, Yung-Jung Chang, CHANG CHE-CHENG, CHEN YI-JEN, CHANG YUNG-JUNG, Chang Che-Cheng, Chen Yi-Jen, Chang Yung-Jung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack, and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure. The etch stop layer is in contact with the sealing structure.

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Номер записи: 21
20-10-2020 дата публикации

Method of fabricating semiconductor device

Номер: US0010811412B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

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Номер записи: 22
30-11-2021 дата публикации

Method of manufacturing a semiconductor device and a semiconductor device

Номер: US0011189728B2
Автор: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, CHEN CHANG-YIN, CHANG CHE-CHENG, LIN CHIH-HAN, Chen, Chang-Yin, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

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Номер записи: 23
16-04-2020 дата публикации

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200119197A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

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Номер записи: 24
14-05-2020 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20200152516A1
Автор: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu, CHEN HUNG-HAO, CHANG CHE-CHENG, TSENG HORNG-HUEI, CHEN WEN-TUNG, LIU YU-CHENG, Chen, Hung-Hao, Chang, Che-Cheng, Tseng, Horng-Huei, Chen, Wen-Tung, Liu, Yu-Cheng
Принадлежит:

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

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Номер записи: 25
23-01-2018 дата публикации

FinFET isolation structure and method for fabricating the same

Номер: US0009876115B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.

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Номер записи: 26
16-05-2019 дата публикации

Via Structure and Methods Thereof

Номер: US20190148287A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит:

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

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Номер записи: 27
23-03-2021 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0010957777B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Seminconductor Manufacturing Company Limite, TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMINCONDUCTOR MFG COMPANY LIMITE, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

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Номер записи: 28
25-04-2019 дата публикации

Fin Field Effect Transistor (FinFET) Device and Method for Forming the Same

Номер: US20190123205A1
Автор: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang, ZHANG ZHE-HAO, CHENG TUNG-WEN, CHANG CHE-CHENG, CHANG YUNG-JUNG, Zhang, Zhe-Hao, Cheng, Tung-Wen, Chang, Che-Cheng, Chang, Yung-Jung
Принадлежит:

A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.

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Номер записи: 29
22-10-2020 дата публикации

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200335499A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

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Номер записи: 30
14-07-2020 дата публикации

Metal gate process for FinFET device improvement

Номер: US0010714588B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

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Номер записи: 31
11-07-2017 дата публикации

Semiconductor device and method for fabricating the same

Номер: US0009704751B1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until concaves are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

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Номер записи: 32
13-04-2023 дата публикации

FinFET Device and Method of Forming and Monitoring Quality of the Same

Номер: US20230114917A1
Автор: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит:

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

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Номер записи: 33
01-10-2019 дата публикации

Structure and formation method of semiconductor device structure

Номер: US0010431687B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

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Номер записи: 34
17-11-2020 дата публикации

Fin structure and method of forming same through two-step etching processes

Номер: US0010840242B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

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Номер записи: 35
15-12-2020 дата публикации

Semiconductor device and method

Номер: US0010868188B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

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Номер записи: 36
06-07-2017 дата публикации

FIN SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE WIDTH STRUCTURES

Номер: US20170194458A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит:

... a semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

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Номер записи: 37
24-02-2022 дата публикации

Removing Polymer Through Treatment

Номер: US20220059403A1
Автор: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
Принадлежит:

A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively. 1. A structure comprising:a lower conductive line;an etch stop layer over the lower conductive line, the etch stop layer comprising a first sub-layer, a second sub-layer over the first sub-layer, and a third sub-layer over the second sub-layer, wherein the first sub-layer and the third sub-layer comprise a same element, and the second sub-layer comprises a different material from the first sub-layer and the third sub-layer;a dielectric layer over the etch stop layer;an upper conductive line in the dielectric layer and separated from the lower conductive line; anda via in the dielectric layer and the etch stop layer and connecting the lower conductive line to the upper conductive line.2. The structure of claim 1 , wherein the same element is a metal element claim 1 , and wherein the second sub-layer is free from the metal element.3. The structure of claim 2 , wherein the same element comprises aluminum.4. The structure of claim 3 , wherein the first sub-layer comprises aluminum nitride claim 3 , the second sub-layer comprises oxygen-doped silicon carbide (ODC) claim 3 , and the third sub-layer comprises aluminum oxide.5. The structure of claim 1 , wherein the dielectric layer ...

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Номер записи: 38
18-04-2017 дата публикации

FinFET devices and methods of forming the same

Номер: US0009627379B1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

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Номер записи: 39
31-12-2019 дата публикации

Structure and formation method of semiconductor device with gate stacks

Номер: US0010522536B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a substrate and a first fin structure and a second fin structure over the substrate. The semiconductor device also includes a first gate stack and a second gate stack partially covering the first fin structure and the second fin structure, respectively, and a stack structure over the substrate. The stack structure is between the first gate stack and the second gate stack. The stack structure includes a semiconductor layer over the substrate and a protection layer over the semiconductor layer.

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Номер записи: 40
16-07-2019 дата публикации

Semiconductor structure and fabricating method thereof

Номер: US0010355135B2
Автор: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin, CHANG CHE-CHENG, CHENG TUNG-WEN, CHEN CHANG-YIN, LIN MU-TSANG, Chang, Che-Cheng, Cheng, Tung-Wen, Chen, Chang-Yin, Lin, Mu-Tsang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

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Номер записи: 41
19-03-2024 дата публикации

Fin structure and method of forming same through two-step etching processes

Номер: US0011935889B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.

A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

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Номер записи: 42
19-11-2019 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0010483364B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

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Номер записи: 43
20-10-2020 дата публикации

FinFET device and method of forming and monitoring quality of the same

Номер: US0010811536B2
Автор: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHEN CHANG-YIN, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chen, Chang-Yin, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

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Номер записи: 44
10-07-2018 дата публикации

Fin field effect transistor, semiconductor device and fabricating method thereof

Номер: US0010020304B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 45
23-04-2020 дата публикации

Semiconductor Device and Method

Номер: US20200126981A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит:

A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.

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Номер записи: 46
28-12-2021 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0011211380B2
Автор: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

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Номер записи: 47
15-06-2017 дата публикации

FIN FIELD EFFECT TRANSISTOR

Номер: US20170170320A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит:

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 48
17-12-2019 дата публикации

Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same

Номер: US0010510539B2
Автор: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Chun-Lung Ni, Jr-Jung Lin, Chih-Han Lin, CHEN CHANG-YIN, CHENG TUNG-WEN, CHANG CHE-CHENG, NI CHUN-LUNG, LIN JR-JUNG, LIN CHIH-HAN, Chen, Chang-Yin, Cheng, Tung-Wen, Chang, Che-Cheng, Ni, Chun-Lung, Lin, Jr-Jung, Lin, Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

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Номер записи: 49
14-01-2020 дата публикации

Method of forming interconnection structure

Номер: US0010535603B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.

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Номер записи: 50
12-12-2017 дата публикации

Semiconductor device structure and method for forming the same

Номер: US0009842765B2
Автор: Wei-Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu, CHEN WEI-TING, CHANG CHE-CHENG, LU CHEN-HSIANG, LIU YU-CHENG, Chen Wei-Ting, Chang Che-Cheng, Lu Chen-Hsiang, Liu Yu-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.

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Номер записи: 51
08-08-2023 дата публикации

Fin field effect transistor (FinFET) device and method for forming the same

Номер: US0011721762B2
Автор: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang, Chang-Yin Chen
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

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Номер записи: 52
26-12-2023 дата публикации

Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer

Номер: US0011855217B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

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Номер записи: 53
29-11-2018 дата публикации

Metal Gate Formation Through Etch Back Process

Номер: US20180342599A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит:

A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate.

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Номер записи: 54
18-01-2018 дата публикации

FIN FIELD EFFECT TRANSISTOR

Номер: US20180019342A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 55
16-05-2017 дата публикации

FinFET device and method of forming the same

Номер: US0009653364B1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang Che-Cheng, Lin Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, first and second dielectric layers, and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The first and second dielectric layer are respectively over the first and second strained layers, and the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer. The first connector is through the first dielectric layer and is electrically connected to the first strained layer. The second connector is through the second dielectric layer and is electrically connected to the second strained layer. Besides, the width of the second connector is greater than the width of the first connector.

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Номер записи: 56
30-06-2020 дата публикации

Semiconductor device and methods of manufacture

Номер: US0010700208B2
Автор: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng, CHANG CHE-CHENG, CHENG KAI-YU, LIN CHIH-HAN, YANG SIN-YI, TSENG HORNG-HUEI, Chang, Che-Cheng, Cheng, Kai-Yu, Lin, Chih-Han, Yang, Sin-Yi, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

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Номер записи: 57
14-01-2021 дата публикации

Semiconductor Device and Method

Номер: US20210013315A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит:

A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer. 1. A semiconductor device comprising:a source/drain region over a semiconductor fin;a spacer in physical contact with the source/drain region, the spacer having a first width adjacent to the source/drain region and a second width less than the first width at a location which is not adjacent to the source/drain region, wherein a portion of both the spacer and the source/drain region are embedded within an implantation region;a gate stack on an opposite side of the spacer from the source/drain region; anda capping layer over the gate stack, wherein the capping layer having a sidewall facing the spacer, the spacer covering the sidewall from a top surface of the capping layer to a bottom surface of the capping layer.2. The semiconductor device of claim 1 , further comprising a dielectric material in physical contact with the source/drain region claim 1 , wherein the dielectric material is fully embedded within the implantation region.3. The semiconductor device of claim 1 , wherein the implantation region extends into the spacer a first distance of between about 5 Å and about 50 Å.4. The semiconductor device of claim 3 , further comprising a conductive material in physical contact with both the source/drain region and the spacer.5. The semiconductor device of claim 4 , wherein the conductive material has a first width along a top surface of the conductive material of between about 3 nm and about 30 nm.6. The semiconductor device of claim 5 , wherein a ratio of the first distance to the first width may be less than 1.7. A semiconductor device comprising:a seam located within a gate stack over a semiconductor fin;an implantation region embedded within a first ...

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Номер записи: 58
19-12-2019 дата публикации

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Номер: US20190386003A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

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Номер записи: 59
17-12-2019 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0010510897B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

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Номер записи: 60
05-10-2021 дата публикации

Fin field effect transistor (FinFET) device and method

Номер: US0011139295B2
Автор: Chai-Wei Chang, Po-Chi Wu, Yi-Cheng Chao, Che-Cheng Chang, CHANG CHAI-WEI, WU PO-CHI, CHAO YI-CHENG, CHANG CHE-CHENG, Chang, Chai-Wei, Wu, Po-Chi, Chao, Yi-Cheng, Chang, Che-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.

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Номер записи: 61
22-11-2022 дата публикации

Semiconductor device and methods of manufacture

Номер: US0011508849B2
Автор: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

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Номер записи: 62
25-12-2018 дата публикации

Method for semiconductor device fabrication with improved source drain proximity

Номер: US0010163912B2
Автор: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng, LIN CHIH-HAN, CHANG CHE-CHENG, TSENG HORNG-HUEI, Lin, Chih-Han, Chang, Che-Cheng, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

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Номер записи: 63
07-08-2018 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0010043906B2
Автор: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young, YU CHENG-YEN, CHANG CHE-CHENG, CHENG TUNG-WEN, ZHANG ZHE-HAO, YOUNG BO-FENG, Yu, Cheng-Yen, Chang, Che-Cheng, Cheng, Tung-Wen, Zhang, Zhe-Hao, Young, Bo-Feng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

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Номер записи: 64
13-12-2016 дата публикации

Methods of forming a semiconductor device with a gate stack having tapered sidewalls

Номер: US0009520474B2
Автор: Che-Cheng Chang, Chang-Yin Chen, Yi-Jen Chen, Yung Jung Chang, CHANG CHE-CHENG, CHEN CHANG-YIN, CHEN YI-JEN, CHANG YUNG JUNG, Chang Che-Cheng, Chen Chang-Yin, Chen Yi-Jen, Chang Yung Jung
Принадлежит: Taiwan Semiconductor Manufacturing Company Limited, TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

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Номер записи: 65
26-06-2018 дата публикации

Etching process control in forming MIM capacitor

Номер: US0010008559B2
Автор: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng, CHEN HUNG-HAO, CHANG CHE-CHENG, CHEN WEN-TUNG, LIU YU-CHENG, TSENG HORNG-HUEI, Chen, Hung-Hao, Chang, Che-Cheng, Chen, Wen-Tung, Liu, Yu-Cheng, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

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Номер записи: 66
30-07-2019 дата публикации

Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features

Номер: US0010367079B2
Автор: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang, CHANG CHE-CHENG, LIN JR-JUNG, CHEN SHIH-HAO, LIN CHIH-HAN, LIN MU-TSANG, CHANG YUNG JUNG, Chang, Che-Cheng, Lin, Jr-Jung, Chen, Shih-Hao, Lin, Chih-Han, Lin, Mu-Tsang, Chang, Yung Jung
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.

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Номер записи: 67
18-05-2023 дата публикации

Method and Structure for FinFET Isolation

Номер: US20230154800A1
Автор: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin
Принадлежит:

A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

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Номер записи: 68
05-05-2020 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0010643947B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

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Номер записи: 69
08-02-2018 дата публикации

Semiconductor Device and Method

Номер: US20180040615A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит:

A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures. 1. A semiconductor device , comprising:a first fin and a second fin disposed over a source/drain region of a substrate;a first epitaxial regrowth region over the first fin;a second epitaxial regrowth region over the second fin, the second epitaxial regrowth region contacting the first epitaxial regrowth region;a dielectric layer over the first epitaxial regrowth region and the second epitaxial regrowth region; anda void region in the dielectric layer, the void region disposed under an upper-most surface of the first epitaxial regrowth region and under an upper-most surface of the second epitaxial regrowth region.2. The semiconductor device of claim 1 , wherein the void region is disposed under contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region.3. The semiconductor device of claim 2 , wherein contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region comprise a boundary of the void region.4. The semiconductor device of claim 2 , wherein the void region adjoins contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region.5. The semiconductor device of claim 1 , further comprising an isolation region interposed between the first fin and the second fin.6. The semiconductor device of claim 5 , ...

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Номер записи: 70
07-01-2016 дата публикации

High-K Film Apparatus and Method

Номер: US20160005832A1
Автор: Che-Cheng Chang, Yi-Ren Chen, Chang-Yin Chen, Yi-Jen Chen, Ming Zhu, Yung-Jung Chang, Harry-Hak-Lay Chuang
Принадлежит:

A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate. 1. A device , comprising:a high-k layer disposed on a substrate and over a channel region in the substrate, the high-k layer comprising a high-k dielectric material having one or more impurities therein, the one or more impurities comprising at least one of C, Cl, or N, and having a molecular concentration of less than about 50%; anda cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.2. The device of claim 1 , wherein the high-k layer comprises hafnium oxide.3. The device of claim 1 , wherein the cap layer and the high-k layer differ in composition.4. The device of claim 1 , further comprising an interfacial layer disposed between the substrate and the high-k layer.5. The device of claim 4 , wherein a thickness of the interfacial layer is in a range from about 5 Angstroms to about 25 Angstroms.6. The device of claim 1 , wherein a thickness of the high-k layer is less than about 2 nanometers.7. The device of claim 1 , wherein the high-k layer has a dielectric constant greater than 3.9.8. The device of claim 1 , wherein the high-k layer has a dielectric constant greater than 15.9. The device of claim 1 , wherein the cap layer comprises titanium nitride.10. A method claim 1 , comprising:forming a source region and a drain region in a substrate; andforming a gate stack disposed between the source region and the drain region, the gate stack comprising a high-k dielectric layer disposed over the substrate ...

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Номер записи: 71
27-09-2018 дата публикации

MECHANISMS FOR FORMING FINFET DEVICE

Номер: US20180277571A1
Автор: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang, CHANG CHE-CHENG, CHEN CHANG-YIN, LIN JR-JUNG, LIN CHIH-HAN, CHANG YUNG-JUNG, Chang, Che-Cheng, Chen, Chang-Yin, Lin, Jr-Jung, Lin, Chih-Han, Chang, Yung-Jung
Принадлежит:

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

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Номер записи: 72
02-01-2018 дата публикации

Interconnection structure with sidewall dielectric protection layer

Номер: US0009859156B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang Che-Cheng, Lin Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

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Номер записи: 73
24-05-2022 дата публикации

Semiconductor structure and fabricating method thereof

Номер: US0011342458B2
Автор: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

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Номер записи: 74
26-03-2020 дата публикации

Semiconductor Structure and Manufacturing Method Thereof

Номер: US20200098585A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer. 1. A device comprising:a substrate;a first gate structure over the substrate;a first spacer extending along a first sidewall of the first gate structure;a source/drain structure over the substrate and adjacent the first spacer;a conductive plug over the source/drain structure;a first insulating layer interposed between the first spacer and the conductive plug; anda second insulating layer interposed between the first spacer and the conductive plug, the first insulating layer being interposed between the second insulating layer and the source/drain structure, wherein the first insulating layer and the second insulating layer comprise different materials, and wherein an interface between the first insulating layer and the second insulating layer is closer to the substrate than a top surface of the first spacer.2. The device of claim 1 , wherein a width of the conductive plug decreases as the conductive plug extends from the top surface of the first spacer toward the source/drain structure.3. The device of claim 1 , further comprising a third insulating layer over the first gate structure claim 1 , wherein the first insulating layer and the third insulating layer comprise a same material.4. The device of claim 3 , wherein a portion of the second insulating layer is interposed between the third insulating layer and the conductive plug.5. The device of claim 3 , wherein a top surface of the third insulating layer ...

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Номер записи: 75
04-10-2016 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0009461043B1
Автор: Che-Cheng Chang, Chih-Han Lin, Wei-Ting Chen, CHANG CHE-CHENG, LIN CHIH-HAN, CHEN WEI-TING, Chang Che-Cheng, Lin Chih-Han, Chen Wei-Ting
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

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Номер записи: 76
28-02-2017 дата публикации

Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same

Номер: US0009583485B2
Автор: Chai-Wei Chang, Che-Cheng Chang, Po-Chi Wu, Yi-Cheng Chao, CHANG CHAI-WEI, CHANG CHE-CHENG, WU PO-CHI, CHAO YI-CHENG, Chang Chai-Wei, Chang Che-Cheng, Wu Po-Chi, Chao Yi-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.

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Номер записи: 77
23-06-2020 дата публикации

Dry etching apparatus

Номер: US0010692701B2
Автор: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Jr-Jung Lin, Chih-Han Lin, CHEN CHANG-YIN, CHENG TUNG-WEN, CHANG CHE-CHENG, LIN JR-JUNG, LIN CHIH-HAN, Chen, Chang-Yin, Cheng, Tung-Wen, Chang, Che-Cheng, Lin, Jr-Jung, Lin, Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

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Номер записи: 78
01-12-2020 дата публикации

Method of forming trenches

Номер: US0010854507B2
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.

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Номер записи: 79
26-09-2017 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US0009773696B2
Автор: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang, CHANG CHE-CHENG, CHEN CHANG-YIN, LIN JR-JUNG, LIN CHIH-HAN, CHANG YUNG JUNG, Chang Che-Cheng, Chen Chang-Yin, Lin Jr-Jung, Lin Chih-Han, Chang Yung Jung
Принадлежит: Taiwan Semiconductor Manufacturing Company Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.

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Номер записи: 80
13-11-2018 дата публикации

Method for forming fin field effect transistor (FINFET) device

Номер: US0010128355B2
Автор: Che-Cheng Chang, Yung-Jung Chang, CHANG CHE-CHENG, CHANG YUNG-JUNG, Chang, Che-Cheng, Chang, Yung-Jung
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin structure extending above a substrate and forming an isolation structure over the substrate, and the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure. The method also includes forming a first transistor and a second transistor on the first fin structure and the second fin structure, and the first transistor includes a first gate dielectric layer. The method further includes forming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, and a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure.

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Номер записи: 81
18-07-2023 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0011705519B2
Автор: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

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Номер записи: 82
03-05-2022 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US0011322618B2
Автор: Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

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Номер записи: 83
25-01-2024 дата публикации

Semiconductor Device and Method

Номер: US20240030319A1
Автор: Bo-Feng Young, Po-Chi Wu, Che-Cheng Chang
Принадлежит:

A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

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Номер записи: 84
29-11-2018 дата публикации

SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK

Номер: US20180342600A1
Автор: Che-Cheng Chang, Yi-Jen Chen, Chang-Yin Chen, Yung Jung Chang, CHANG CHE-CHENG, CHEN YI-JEN, CHEN CHANG-YIN, CHANG YUNG JUNG, Chang, Che-Cheng, Chen, Yi-Jen, Chen, Chang-Yin, Chang, Yung Jung
Принадлежит:

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

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Номер записи: 85
06-12-2018 дата публикации

Method of Forming Trenches

Номер: US20180350667A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang, Che-Cheng, Lin, Chih-Han
Принадлежит:

Methods are disclosed herein that improve contours of trenches formed when fabricating vias and conductive lines of a multi-layer interconnect (MLI) structure. An exemplary device that can result from such methods includes a via of an MLI structure and a conductive line of the MLI structure disposed over the via. A first dielectric liner layer is disposed along sidewalls of the via and sidewalls of the conductive line. A thickness of the first dielectric liner layer is substantially the same along the sidewalls of the via. A thickness of the first dielectric liner layer increases along the sidewalls of the conductive line, such that the first dielectric liner layer has a tiger-tooth shape at each bottom corner of the conductive line. A second dielectric liner layer is disposed along the first dielectric liner layer that is disposed along the sidewalls of the via.

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Номер записи: 86
10-11-2020 дата публикации

Method of adaptive weighting adjustment positioning

Номер: US0010830906B2
Автор: Wun-Sheng Yao, Che-Cheng Chang, Yi Yan, YAO WUN-SHENG, CHANG CHE-CHENG, YAN YI, Yao, Wun-Sheng, Chang, Che-Cheng, Yan, Yi
Принадлежит: AUTOMOTIVE RESEARCH & TESTING CENTER, AUTOMOTIVE RES & TESTING CT

A method of adaptive weighting adjustment positioning has the following steps: performing an initialization procedure, determining whether a first feature point is detected; when the first feature point is detected, based on multiple positioning methods, multiple positioning information will be generated, and multiple weightings will be set, and then based on the weightings and the positioning information, calculating the positioning information output; by way of adaptive weighting adjustment among the multiple positioning methods, the multiple positioning methods can be integrated. In this way, even if one of the positioning methods is temporarily unavailable, the positioning information can still be calculated by weighting adjustment between the positioning information of the remaining two available methods, and that allows users to continue to obtain accurate positioning information to confirm the current location.

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Номер записи: 87
01-11-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180315754A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

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Номер записи: 88
14-01-2020 дата публикации

Gate structure of field effect transistor with footing

Номер: US0010535758B2
Автор: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang, CHANG CHE-CHENG, CHEN CHANG-YIN, LIN JR-JUNG, LIN CHIH-HAN, CHANG YUNG JUNG, Chang, Che-Cheng, Chen, Chang-Yin, Lin, Jr-Jung, Lin, Chih-Han, Chang, Yung Jung
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

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Номер записи: 89
12-06-2018 дата публикации

Fin-type field effect transistor device and manufacturing method thereof

Номер: US0009997632B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A fin-type field effect transistor device including a substrate, at least one gate stack structure, spacers and source and drain regions is described. The gate stack structure is disposed on the substrate and the spacers are disposed on sidewalls of the gate stack structure. The source and drain regions are disposed in the substrate and located at opposite sides of the gate stack structures. A dielectric layer having contact openings is disposed over the substrate and covers the gate stack structures. Metal connectors are disposed within the contact openings and connected to the source and drain regions, and adhesion layers are sandwiched between the contact openings and the metal connectors located within the contact openings.

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Номер записи: 90
18-04-2017 дата публикации

Field effect transistor devices having interconnect structures and manufacturing method thereof

Номер: US0009627316B1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang Che-Cheng, Lin Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.

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Номер записи: 91
30-07-2019 дата публикации

Fin field effect transistor and semiconductor device

Номер: US0010366990B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

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Номер записи: 92
11-12-2018 дата публикации

Fin-type field effect transistor structure and manufacturing method thereof

Номер: US0010153370B2
Автор: Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

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Номер записи: 93
02-07-2019 дата публикации

Embedded source or drain region of transistor with downward tapered region under facet region

Номер: US0010340382B2
Автор: Che-Cheng Chang, Tung-Wen Cheng, Yung Jung Chang, Zhe-Hao Zhang, CHANG CHE-CHENG, CHENG TUNG-WEN, CHANG YUNG JUNG, ZHANG ZHE-HAO, Chang, Che-Cheng, Cheng, Tung-Wen, Chang, Yung Jung, Zhang, Zhe-Hao
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

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Номер записи: 94
20-04-2017 дата публикации

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20170110579A1
Автор: Che-Cheng Chang, Chih-Han Lin, CHANG CHE-CHENG, LIN CHIH-HAN, Chang Che-Cheng, Lin Chih-Han
Принадлежит:

A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

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Номер записи: 95
20-08-2020 дата публикации

Semiconductor Structure and Manufacturing Method Thereof

Номер: US20200266148A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

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Номер записи: 96
08-02-2018 дата публикации

Semiconductor Device and Methods of Manufacture

Номер: US20180040733A1
Автор: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
Принадлежит:

A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first contact to a source/drain region, the source/drain region being adjacent to and planar with at least a portion of a first spacer, the first spacer being adjacent to a gate electrode;forming a dielectric layer over the gate electrode;patterning the dielectric layer to form a first opening through the dielectric layer, the first opening exposing the first contact;lining sidewalls of the first opening with a dielectric material; andfilling a remainder of the first opening with a conductive material to form a second contact, the second contact extending through the dielectric material to make contact with the first contact, wherein the conductive material is electrically isolated from the gate electrode.2. The method of claim 1 , further comprising patterning the dielectric material to expose the first contact after the lining the sidewalls of the first opening.3. The method of claim 1 , wherein the lining the sidewalls of the first opening comprises performing at least in part an atomic layer deposition process.4. The method of claim 1 , wherein the dielectric material has a thickness of greater than about 0.5 nm.5. The method of claim 1 , wherein the second contact contacts the first contact at a first interface claim 1 , and wherein at the first interface the first contact has a first width and the second contact has a second width less than the first width.6. The method of claim 1 , wherein the gate electrode overlies a semiconductor fin.7. The method of claim 6 , further comprising: ...

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Номер записи: 97
18-08-2016 дата публикации

Method of Semiconductor Fabrication with Height Control Through Active Region Profile

Номер: US20160240444A1
Автор: Yi-Cheng Chao, Che-Cheng Chang, Po-Chi Wu, Jung-Jui Li, CHAO YI-CHENG, CHANG CHE-CHENG, WU PO-CHI, LI JUNG-JUI, Chao Yi-Cheng, Chang Che-Cheng, Wu Po-Chi, Li Jung-Jui
Принадлежит:

The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions.

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Номер записи: 98
02-11-2017 дата публикации

FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20170316982A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит:

A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

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Номер записи: 99
14-09-2021 дата публикации

Structure and formation method of semiconductor device with gate stacks

Номер: US0011121130B2
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, CHANG CHE-CHENG, LIN CHIH-HAN, TSENG HORNG-HUEI, Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Structures and formation methods of a semiconductor device are provided. The method includes forming a first fin structure and a second fin structure over a substrate, and forming first, second and third dummy gate stacks over the substrate. The first dummy gate stack and the second dummy gate stack partially cover the first fin structure and the second fin structure respectively. The third dummy gate stack is between the first dummy gate stack and the second dummy gate stack. The method also includes partially removing the third dummy gate stack such that a semiconductor layer of the third dummy gate stack remains over the substrate, forming a protection layer over the semiconductor layer, and replacing the first dummy gate stack and second dummy gate stack with a first gate stack and a second gate stack, respectively.

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Номер записи: 100
18-07-2013 дата публикации

Performing Treatment on Stressors

Номер: US20130181262A1
Автор: Chang Che-Cheng, Chen Chang-Yin, HUANG Yi-Chen, Wu Po-Chi, ZHANG ZHE-HAO
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region. 1. A method comprising:forming a gate stack over a semiconductor substrate, wherein the gate stack comprises a gate dielectric and a gate electrode over the gate dielectric;recessing a portion of the semiconductor substrate adjacent to the gate stack to form a recess;epitaxially growing a semiconductor region in the recess;implanting the semiconductor region with a p-type impurity or an n-type impurity; andperforming a dry treatment on the semiconductor region.2. The method of claim 1 , wherein the dry treatment is performed after the step of implanting the semiconductor region.3. The method of claim 1 , wherein the dry treatment is performed before the step of implanting the semiconductor region.4. The method of claim 1 , wherein the step of implanting results in a source/drain region to be formed in the semiconductor region claim 1 , and wherein the method further comprises claim 1 , after the dry treatment and the step of implanting claim 1 , forming a source/drain silicide region over the source/drain region.5. The method of claim 1 , wherein the dry treatment comprises a plasma treatment using a plasma generated from a process gas.6. The method of claim 5 , wherein the process gas is selected from the group consisting essentially of N claim 5 , H claim 5 , O claim 5 , NF claim 5 , CF claim 5 , CHFHCl claim 5 , Ar claim 5 , and combinations thereof.7. The method of claim 6 , wherein the process gas comprises Nand H.8. The method of further comprising claim 1 , after the step of implanting the ...

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Номер записи: 101
25-07-2013 дата публикации

Electric pencil sharpener with a replaceable cutter assembly

Номер: US20130186517A1
Автор: Che-Chang Cheng, Chien-Hsing Chang, Liang-Liang Yao
Принадлежит: SDI Corp

An electric pencil sharpener has a body, a cover and a cutter assembly. The body has a transmission device and a waste case having an opening. The cover is mounted on and closes the opening of the waste case. The cutter assembly is mounted in the waste case, is detachable from the waste case via the opening and has a connection base, a cutter bracket and a cutter. The connection base has a combining hole defined through the connection base. The cutter bracket is connected rotatably with the connection base and has a connection element connected with transmission device to make the cutter bracket driven by and rotate with the transmission device. The cutter is mounted on the cutter bracket. Accordingly, the cutter assembly is easily and conveniently replaceable when the cutter of the cutter assembly is damaged or worn off.

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Номер записи: 102
15-08-2013 дата публикации

Tape Holding Device

Номер: US20130209157A1
Автор: Che-Chang Cheng, Yenwen Hung
Принадлежит: SDI Corp

A tape holding device has a holding frame and an engaging component. The holding frame has a connecting segment and at least one elastic arm connected to the connecting component. The at least one elastic arm is elastic and can swing relative to the connecting segment. The engaging component is formed on the at least one elastic arm away from the connecting segment and has at least one engaging tab. The at least one engaging tab is formed on and protrudes from an inner surface of the at least one elastic arm that is opposite to the holding frame to abut and engage a tape supplying wheel of a dispensing unit to limit the rotation of the tape supplying wheel. The tape holding device prevents a tape from loosening, prevents a thin film on the tape from peeling and can be used to replace a new dispensing unit conveniently.

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Номер записи: 103
03-04-2014 дата публикации

CLIP ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20140092567A1
Автор: Chang Che-Cheng, Chen Kuan-Yu
Принадлежит:

A clip assembly includes a seat having a surrounding wall with a receiving hole, and a locking mechanism proximate to the surrounding wall and including a pair of movable levers. Each movable lever has an engaging portion movably inserted into the receiving hole, and a driven portion. A drive unit has a button that is moved to a pressed position, where the driven portions are pushed to move away from each other and out of the receiving hole. A clip mechanism includes a connection body received in the receiving hole and having two connecting holes to respectively engage the engaging portions. The engaging portions are disengageable from the connecting holes by pressing the button. 1. A clip assembly comprising:a base having an inner surface, an outer surface, and a surrounding wall that extends from said outer surface to said inner surface and that defines a receiving hole, said receiving hole extending through said outer surface and being closed by said inner surface, said surrounding wall having two opposite through holes that communicate with said receiving hole and that are respectively disposed at two opposite sides of said receiving hole;a locking mechanism disposed in proximity to said inner surface and said surrounding wall, said locking mechanism including a pair of movable levers, a drive unit and a restoring unit, each of said movable levers having an engaging portion that is movably inserted into said receiving hole through a corresponding one of said through holes of said surrounding wall, a pivot portion, an intermediate portion that interconnects said engaging portion and said pivot portion, and a driven portion that extends from one side of said pivot portion away from said intermediate portion, said movable levers being connected pivotally to each other in a scissor fashion at said pivot portions of said movable levers, said driven portion of one of said movable levers being opposite to and spaced-apart from said driven portion of the other of said ...

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Номер записи: 104
04-01-2018 дата публикации

Semiconductor devices, finfet devices and methods of forming the same

Номер: US20180005877A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.

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Номер записи: 105
02-01-2020 дата публикации

Notched Gate Structure Fabrication

Номер: US20200006148A1
Автор: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.

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Номер записи: 106
03-01-2019 дата публикации

Method of Forming Trenches

Номер: US20190006233A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench. 1. A method comprising:forming a first material layer over a substrate;forming a first trench in the first material layer;forming a second material layer along sidewalls of the first trench;forming a second trench in the first material layer while the second material layer is disposed along the sidewalls of the first trench, wherein the second material layer has a tapered top surface after the forming of the second trench;after the forming of the second trench, extending the first trench to expose a portion of the substrate within the first trench; andforming a conductive feature within the first trench and the second trench such that the conductive feature covers the second material layer having the tapered top surface.2. The method of claim 1 , wherein the second trench is in communication with the first trench.3. The method of claim 1 , further comprising forming an etch stop layer over the substrate claim 1 , andwherein a portion of the etch stop layer is exposed within the first trench after the forming of the first trench in the first material layer.4. The method of claim 3 , wherein the forming of the second material layer along sidewalls of the first trench includes forming a portion of the second material layer directly on the portion of the etch stop layer.5. The method of claim 3 , wherein the forming of the second trench in the first material layer includes removing the portion of the second material layer such that the portion of the etch stop layer is exposed.6. The method of claim 1 , wherein the substrate includes a semiconductor material claim ...

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Номер записи: 107
03-01-2019 дата публикации

Structure and Formation Method of Semiconductor Device Structure

Номер: US20190006243A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling. 1. A semiconductor device comprising:a fin structure;a shallow trench isolation (STI) adjacent the fin structure;a gate structure over a portion of the fin structure and the STI, wherein the gate structure comprises a gate dielectric layer, a work function layer over the gate dielectric layer, and a conductive fill material over the work function layer;spacers along opposing sidewalls of the gate structure, the spacers terminating at ends of the gate structure along a longitudinal axis of the gate structure; anda dielectric layer surrounding the gate structure and the spacers in a plan view, wherein the work function layer terminates over the STI between the fin structure and the dielectric layer along a longitudinal axis of the gate structure, wherein the gate dielectric layer completely separates the conductive fill material from the spacers and the dielectric layer.2. The semiconductor device of claim 1 , wherein the conductive fill material directly contacts the gate dielectric layer.3. The semiconductor device of claim 1 , wherein an uppermost surface of the gate dielectric layer is level with an uppermost surface of the dielectric layer.4. The semiconductor device of claim 1 , wherein a thickness of the work function layer is less than a height of the fin structure above the STI.5. The semiconductor device of claim 1 , wherein the conductive fill material is interposed between the work function layer and the dielectric layer.6. The ...

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Номер записи: 108
03-01-2019 дата публикации

Semiconductor Device and Method

Номер: US20190006493A1
Автор: Chang Che-Cheng, Wu Po-Chi, Young Bo-Feng
Принадлежит:

A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced. 1. A method of manufacturing a semiconductor device , the method comprising:forming a gate stack over a semiconductor substrate;forming a first opening in the semiconductor substrate with a first etching process; andreshaping the first opening into a second opening using a second etching process different from the first etching process, wherein the second etching process is a radical etch process.2. The method of claim 1 , wherein the first opening is formed within a fin of the semiconductor substrate.3. The method of claim 1 , wherein the radical etch process further comprises:igniting an etching precursor into a plasma; andseparating radicals from the plasma.4. The method of claim 3 , wherein the etching precursor is ammonia.5. The method of claim 1 , wherein the first etching process is a reactive ion etch.6. The method of claim 5 , wherein the radical etch process is isotropic.7. The method of claim 1 , wherein the second opening undercuts the gate stack by a distance of between about 1 nm and about 4 nm.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a dummy gate stack over a semiconductor fin of a substrate, the dummy gate stack comprising a spacer structure;removing a portion of the fin to form a first opening, wherein the first opening is formed with an anisotropic etching process; and forming a plasma from a precursor; and', 'directing radicals from the plasma to the semiconductor fin while filtering charged particles from the plasma from reaching the semiconductor fin., 'modifying the first opening into a second opening, wherein the modifying comprises9. The method of claim 8 , wherein the spacer ...

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Номер записи: 109
02-01-2020 дата публикации

Metal Gate Process for FinFET Device Improvement

Номер: US20200006513A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole. 1. A method comprising:lining sidewalls of a dummy structure with a first dielectric layer;forming a modified region of the first dielectric layer by modifying an etch selectivity of an upper portion of the first dielectric layer relative to a lower portion of the first dielectric layer;removing the dummy structure using an etch process, wherein the etch process etches the modified region at a higher rate relative to the lower portion of the first dielectric layer; andforming a metal gate in a region left by removing the dummy structure, wherein the metal gate has a first width in an upper region bounded by the modified region and a second width in a lower region bounded by the lower portion of the first dielectric layer, the first width being greater than the second width.2. The method of claim 1 , wherein lining sidewalls of a dummy structure with a first dielectric comprises depositing a dielectric layer over the dummy structure.3. The method of claim 1 , wherein forming a modified region of the first dielectric layer comprises doping the upper portion of the first dielectric layer.4. The method of ...

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Номер записи: 110
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180013001A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate. 1. A semiconductor device comprising:a substrate;an active region; the gate structure has a first sidewall and a top surface intersecting to form a top interior angle,', 'the top interior angle is an acute angle, and', 'the gate structure comprises a dielectric layer and a gate electrode; and, 'a gate structure over the active region and on the substrate, wherein the insulating structure has a first sidewall facing the active region, and', 'the dielectric layer is disposed between the first sidewall of the insulating structure and the gate electrode., 'an insulating structure over the substrate, wherein2. The semiconductor device of claim 1 , wherein the active region is a semiconductor fin.3. The semiconductor device of claim 1 , wherein the active region is an oxide defined region of the substrate.4. The semiconductor device of claim 1 , wherein the first sidewall of the insulating structure faces the first sidewall of the gate structure.5. The semiconductor device of claim 1 , wherein the first sidewall of the insulating structure is in contact with the first sidewall of the gate structure.6. The semiconductor device of claim 1 , comprising:a gate spacer facing a second sidewall of the insulating structure.7. The semiconductor device of claim 1 , comprising an interlayer dielectric disposed between the dielectric layer and the active region.8. The semiconductor device of claim 7 , wherein the insulating structure overlies the interlayer dielectric.9. A ...

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Номер записи: 111
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH FIN ISOLATION

Номер: US20210013045A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile. 1. A semiconductor device , comprising:a substrate;a first semiconductor fin and a second semiconductor fin over the substrate, wherein the second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other, the first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion of the first semiconductor fin faces and is spaced apart from an end sidewall of the second end portion of the second semiconductor fin; anda gate structure extending substantially perpendicularly to the first semiconductor fin, wherein when viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin, and when viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.2. The semiconductor device of claim 1 , wherein when viewed form above claim 1 , the gate structure further overlaps second end portion of the second ...

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Номер записи: 112
09-01-2020 дата публикации

Integrated Circuit Device Fins

Номер: US20200013881A1
Автор: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang HUNG, Wei-Hao Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

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Номер записи: 113
19-01-2017 дата публикации

METHOD FOR CLEANING VIA OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE STRUCTURE

Номер: US20170018458A1
Автор: Chang Che-Cheng, CHEN Wei-Ting, CHENG Tai-Shin, SHIAO Wei-Yin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd

A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N) and hydrogen gas (H). 1. A method for forming a semiconductor device structure , comprising:forming a metal layer in a first dielectric layer over a substrate;forming an etch stop layer over the metal layer, wherein the etch stop layer is made of metal-containing material;forming a second dielectric layer over the etch stop layer removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process; and{'sub': 2', '2, 'performing a plasma cleaning process on the via and the second dielectric layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N) and hydrogen gas (H).'}2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein a ratio of the flow rate of nitrogen gas (N) to the flow rate of hydrogen gas (H) is in a range from about 2/1 to about 4/1.3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:after the plasma cleaning process, performing a wet cleaning process on the second dielectric layer.4. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the etching process is performed by using an etch gas comprising fluorine-containing gas.5. The method for forming the semiconductor device ...

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Номер записи: 114
18-01-2018 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

Номер: US20180019128A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei, Wu Po-Chi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin. 1. A method for manufacturing a semiconductor structure comprising:forming at least one first active semiconductor fin and at least one second active semiconductor fin on a substrate, wherein the substrate has a first region and a second region, the first active semiconductor fin is formed on the first region of the substrate, and the second active semiconductor fin is formed on the second region of the substrate;forming a dielectric layer on the first region and the second region of the substrate;doping a first portion of the dielectric layer on the first region of the substrate with first dopants to form a first insulating structure;doping a second portion of the dielectric layer on the second region of the substrate with second dopants to form a second insulating structure, wherein the second dopants are different from the first dopants;converting a portion of the first insulating structure and a portion of the second insulating structure into at least one sacrificial layer; andremoving the at least one sacrificial layer.2. The method of claim 1 , wherein converting the portion of the first insulating structure and the portion of the second insulating structure into the at least one sacrificial layer comprises introducing at least one etchant to react with the portion of the first insulating structure and the portion of the second insulating structure.3. The method of ...

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Номер записи: 115
18-01-2018 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20180019161A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, Chen Chang-Yin, LIN Chih-Han, Lin Jr-Jung
Принадлежит:

The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure. 1. A semiconductor structure , comprising:a semiconductor layer;a gate comprising a conductive portion and a sidewall spacer, wherein a top surface of the conductive portion and a top surface of the side-wall spacer are substantially coplanar, and the gate is positioned over the semiconductor layer;an interlayer dielectric (ILD) surrounding a sidewall surface of the sidewall spacer, positioning over the semiconductor layer; anda protection layer, positioning on the top surface of the conductive portion and the top surface of the sidewall spacer, the protection layer comprising a tapered sidewall.2. The semiconductor structure in claim 1 , wherein the protection layer comprises at least one of sulfur nitride claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , silicon carbonitride claim 1 , or combinations thereof.3. The semiconductor structure in claim 1 , wherein the protection layer is further extending to a top surface of the ILD.4. The semiconductor structure in claim 1 , further comprisinga ...

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Номер записи: 116
18-01-2018 дата публикации

Fin-type field effect transistor structure and manufacturing method thereof

Номер: US20180019240A1
Автор: Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

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Номер записи: 117
21-01-2021 дата публикации

Fin Field Effect Transistor (FinFET) Device Structure with Interconnect Structure

Номер: US20210020496A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction. 1. A semiconductor device structure , comprising:a first metal layer over a substrate;an etch stop layer over the first metal layer;a dielectric layer over the etch stop layer, the dielectric layer having a single continuous composition, the dielectric layer having a trench opening and a via opening, wherein the trench opening has an extending portion, a bottom surface of the extending portion extends toward the etch stop layer as the bottom surface extends from the via opening toward a sidewall of the trench opening;an adhesion layer on sidewalls and bottom surfaces of the trench opening and the via opening, wherein the adhesion layer is discontinuous such that an exposed portion of the dielectric layer is exposed adjacent the extending portion; anda second metal layer in the via opening and the trench opening, wherein the second metal layer is electrically connected to the first metal layer.2. The device of claim 1 , wherein the adhesion layer completely fills the extending portion.3. The device of claim 1 , wherein the second metal layer directly contacts the dielectric layer.4. The device of claim 1 , wherein a surface of the adhesion layer and a surface of the dielectric layer along a corner between the trench ...

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Номер записи: 118
22-01-2015 дата публикации

METHOD OF FORMING A SELECTIVELY ADJUSTABLE GATE STRUCTURE

Номер: US20150024518A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, Chen Yi-Jen, Liao Young
Принадлежит:

The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost. 1. A method of forming a selectively adjustable gate structure ,forming a gate structure having a first length over a semiconductor substrate;measuring the first length of the gate structure;comparing the first length to a target length; andadjusting the first length of the gate structure if the first length differs from the target length by an amount that is greater than a predetermined threshold value, to converge the length of the gate structure upon the target length to reduce critical-dimension (CD) variations.2. The method of claim 1 , wherein adjusting the length of the gate structure comprises:performing a deposition process to deposit additional gate material to increase the first length of the gate structure; andperforming an etching process to selectively remove a portion of the additional gate material.3. The method of claim 2 , wherein the deposition process and the etching process are performed in-situ.4. The method of claim 2 , wherein the deposition process is performed within a processing chamber held at pressure having a range of between approximately 1 mT (millitorr) and approximately 30 mT.5. The method of claim 2 , wherein the deposition process is performed within a processing chamber using a deposition chemistry comprising one or more of: silicon tetrachloride (SiCl) claim ...

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Номер записи: 119
28-01-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20160027684A1
Автор: Chang Che-Cheng, CHENG Tung-Wen, HSEIH JUI FU, LIN MU-TSANG
Принадлежит:

A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface. 1. A semiconductor structure , comprising:a semiconductor substrate; and a bottom surface contacting the bottom portion of the semiconductor substrate;', 'a top surface opposite to the bottom surface; and', 'a turning point whereby the STI is divided into an upper portion and a lower portion,', 'wherein the bottom surface comprises a width greater than a width of the top surface, and the sidewall has an inclined or curved surface along the upper portion., 'a shallow trench isolation (STI) including a sidewall interfacing with the semiconductor substrate, wherein the STI extrudes from a bottom portion of the semiconductor substrate, and the STI comprises2. The semiconductor structure of claim 1 , wherein a width of the STI gradually becomes greater from the top surface to the bottom surface.3. (canceled)4. The semiconductor structure of claim 2 , wherein the sidewall of the STI is a curved surface.5. The semiconductor structure of claim 1 , wherein a width of the lower portion becomes greater from the turning point to the bottom surface.6. (canceled)7. The semiconductor structure of claim 5 , wherein the sidewall of the lower portion is a curved surface.8. The semiconductor structure of claim 1 , wherein a width at the turning point is greater than the width of the top surface claim 1 , and the width of the bottom surface is greater than the width at the turning point.9. The semiconductor structure of claim 1 , wherein the sidewall comprises a protrusion adjacent to the bottom surface.10. The semiconductor ...

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Номер записи: 120
25-01-2018 дата публикации

INTERCONNECTION STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20180025975A1
Автор: Chang Che-Cheng, LIN Chih-Han, TSENG Homg-Huei
Принадлежит:

An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. At least a portion of the conductive structure tapers along a direction from the non-insulator structure to the dielectric structure. 1. An interconnection structure , comprising:a dielectric structure;an anti-adhesion layer; anda conductive structure, wherein a central portion of the conductive structure is surrounded by the anti-adhesion layer such that the central portion of the conductive structure is separated from a first portion of the dielectric structure by the anti-adhesion layer.2. The interconnection structure of claim 1 , wherein the conductive structure is in contact with a second portion of the dielectric structure above the anti-adhesion layer and a third portion of the dielectric structure below the anti-adhesion layer.3. The interconnection structure of claim 1 , wherein the dielectric structure is in contact with a bottom surface of the anti-adhesion layer.4. The interconnection structure of claim 1 , wherein:a first sidewall of the anti-adhesion layer is in contact with the first portion of the dielectric structure,a second sidewall of the anti-adhesion layer is in contact with the central portion of the conductive structure, andthe first sidewall of the anti-adhesion layer is disposed on a diametrically opposite side of the anti-adhesion layer relative to the second sidewall of the anti-adhesion layer.5. The interconnection structure of claim 1 , wherein:a second portion of the conductive structure extends is below the central portion of the ...

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Номер записи: 121
25-01-2018 дата публикации

METHODS FOR FABRICATING FIN FIELD EFFECT TRANSISTORS

Номер: US20180026033A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein. 1. A method for fabricating a fin field effect transistor (FinFET) , comprising:forming a first semiconductor fin, a second semiconductor fin and an insulator between the first and second semiconductor fins;forming a first dummy gate, a second dummy gate and an opening between the first and second dummy gates over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively;forming a dielectric layer in the opening, wherein the dielectric layer comprises an air gap therein; andreplacing the first dummy gate and the second dummy gate with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.2. The method of claim 1 , wherein the insulator is formed between lower portions of the first and second semiconductor fins claim 1 , and the first gate and the second gate surround upper portions of the first semiconductor fin and the second semiconductor fin respectively.3. The method of claim 1 , ...

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Номер записи: 122
25-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF

Номер: US20180026039A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor. 1. A semiconductor device , comprising: a first work function conductor; and', the plug portion of the first filling conductor is disposed between a first sidewall of the first work function conductor and a second sidewall of the first work function conductor, and', 'the cap portion of the first filling conductor overlies an uppermost surface of the first work function conductor; and, 'a first filling conductor comprising a plug portion and a cap portion, wherein], 'a first gate stack comprising 'a sidewall of the cap portion and the first sidewall of the first work function conductor are in direct contact with a sidewall of the first gate spacer.', 'a first gate spacer disposed on a first side of the first gate stack and a second gate spacer disposed on a second side of the first gate stack opposite the first side, wherein2. The semiconductor device of claim 1 , the first gate stack comprising a second work function conductor disposed between the plug portion of the first filling conductor and the first sidewall of the first work function conductor and between the plug portion of the first filling conductor and the second sidewall of the first work function conductor.3. The semiconductor device of claim 2 , wherein the first work function conductor is a p-type work function conductor and the second work function conductor is an n-type work function conductor.4. The semiconductor device of claim 1 , comprising a dielectric cap claim 1 , wherein the dielectric cap is separated from the first work ...

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Номер записи: 123
23-01-2020 дата публикации

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE

Номер: US20200027988A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion. 1. A device comprising:a fin structure disposed over a substrate, the fin structure extending along a first direction;a gate stack disposed over the fin structure, wherein the gate stack includes a first portion and a second portion extending along a second direction adjacent to the fin structure, the second direction being perpendicular to the first direction, wherein the first portion is wider than the second portion, wherein the second portion of the gate stack includes a sidewall surface extending towards the fin structure at a third direction, the third direction being different than the first direction and the second direction; anda source/drain feature disposed on the fin structure.2. The device of claim 1 , wherein the first portion of the gate stack interfaces with the second portion of the gate stack.3. The device of claim 1 , wherein the first portion of the gate stack includes a gate electrode layer and the second portion of the gate stack includes the gate electrode layer.4. The device of claim 1 , wherein the sidewall surface is a curved sidewall surface claim 1 , andwherein a center of curvature of the curved sidewall surface is positioned outside of the gate stack.5. The device of claim 1 , wherein the gate stack includes a gate electrode and a gate dielectric layer claim 1 , andwherein the sidewall surface is defined by the gate electrode, andwherein the gate dielectric layer is disposed over the fin structure between the gate electrode and the fin structure.6. The device of claim 5 , wherein the sidewall surface of the gate ...

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Номер записи: 124
28-01-2021 дата публикации

Structure and Formation Method of Semiconductor Device with Gate Stack

Номер: US20210028296A1
Автор: Chang Che-Cheng, Chen Yi-Jen, Shih Sheng-Chi
Принадлежит:

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate. 1. A device comprising:a first gate dielectric over a substrate;a first gate electrode over the first gate dielectric, the first gate electrode having a first sidewall forming a first angle with a first plane and a second sidewall forming the first angle with the first plane, the first plane parallel to a top surface of the substrate;a second gate dielectric over the substrate;a second gate electrode over the second gate dielectric, the second gate electrode having a third sidewall forming the first angle with the first plane and a fourth sidewall forming a second angle with the first plane, the second angle different from the first angle;a third gate dielectric over the substrate;a third gate electrode over the third gate dielectric, the third gate electrode having a fifth sidewall forming the second angle with the first plane and a sixth sidewall forming the second angle with the first plane; anda dielectric layer surrounding the first gate electrode, the second gate electrode, and the third gate electrode.2. The device of claim 1 , wherein the first gate electrode is separated from the second gate electrode by a first distance claim 1 , and the second gate electrode is separated from the third gate electrode by a second ...

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Номер записи: 125
02-02-2017 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20170033112A1
Автор: Chang Che-Cheng, CHENG Tai-Shin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure in or over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the conductive structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The second dielectric layer has a second opening connected to the first opening and exposing the conductive structure. The semiconductor device structure includes a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure. The capacitor is electrically connected to the conductive structure. 1. A semiconductor device structure , comprising:a substrate;a conductive structure in or over the substrate;a first dielectric layer over the substrate, wherein the first dielectric layer has a first opening exposing the conductive structure;a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second opening connected to the first opening and exposing the conductive structure; anda capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure, wherein the capacitor is electrically connected to the conductive structure.2. The semiconductor device structure as claimed in claim 1 , wherein the capacitor conformally covers the first inner wall of the first opening claim 1 , the second inner wall of the second opening claim 1 , and the top surface of the conductive structure.3. The semiconductor device structure as claimed in claim 1 , wherein a first portion of a bottom surface of the second dielectric layer is over the first opening claim 1 , and a second portion of the capacitor covering the first ...

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Номер записи: 126
01-02-2018 дата публикации

Semiconductor device

Номер: US20180033698A1
Автор: Che-Cheng Chang, Chih-Han Lin, Wei-Ting Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

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Номер записи: 127
30-01-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200035804A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han
Принадлежит:

A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap. 1. A semiconductor structure , comprising:a gate structure disposed over a semiconductor substrate;a first gate spacer covering a first sidewall of the gate structure;an interlayer dielectric (ILD) layer adjacent to the first gate spacer; anda contact stop layer positioned over the first gate spacer and the interlayer dielectric layer,wherein an air gap is between the first gate spacer and the interlayer dielectric layer, and the contact stop layer comprises a capping portion that seals a top of the air gap.2. The semiconductor structure of claim 1 , wherein the contact stop layer further comprises a horizontal layer claim 1 , and the capping portion extends downwards from the horizontal layer and to a position between the first gate spacer and the interlayer dielectric layer.3. The semiconductor structure of claim 1 , wherein the first gate spacer has a L-shape cross-section.4. The semiconductor structure of claim 1 , wherein the first gate spacer has a vertical portion on the first sidewall of the gate structure and a lateral portion that extends from a bottom of the vertical portion away from the gate structure.5. The semiconductor structure of claim 4 , further comprising a contact etch stop layer disposed between the lateral portion of the first gate spacer and the interlayer dielectric layer.6. The semiconductor structure of claim ...

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Номер записи: 128
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200035832A1
Автор: Chang Che-Cheng, CHENG Tung-Wen, Young Bo-Feng, Yu Cheng-Yen, ZHANG ZHE-HAO
Принадлежит:

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate. 1. A semiconductor device , comprising:a Fin FET device including:a first fin structure disposed over a substrate;an isolation insulating layer disposed over the substrate; anda first source/drain stressor layer made of semiconductor material and disposed over the first fin structure, wherein:the first source/drain stressor layer is in contact with the isolation insulating layer and the first fin structure, anda bottom of the first source/drain stressor layer in contact with the isolation insulating layer and the first fin structure has an U-shape.2. The semiconductor device of claim 1 , wherein:the Fin FET device further includes:a second fin structure disposed adjacent to the first fin structure; anda second source/drain stressor layer disposed over the second fin structure, anda surface of the isolation insulating layer between the first fin structure and the second fin structure has an U-shape.3. The semiconductor device of claim 2 , wherein a bottom of the U-shape of the first source/drain stressor layer is located above a bottom of the U-shape of the isolation insulating layer.4. The semiconductor device of claim 2 , wherein a bottom of the U-shape ...

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Номер записи: 129
04-02-2021 дата публикации

Structure and Formation Method of Semiconductor Device Structure with Gate Stack

Номер: US20210036128A1
Автор: Chang Che-Cheng, CHENG Tung-Wen, LIN MU-TSANG, Young Bo-Feng, ZHANG ZHE-HAO
Принадлежит:

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate. 1. A semiconductor device comprising:a substrate;a gate electrode over an upper surface of the substrate;a source/drain structure adjacent to the gate electrode, wherein the source/drain structure has a first width measured at the upper surface of the substrate, a second width measured at a lower surface of the source/drain structure in the substrate, and a third width measured between the upper surface of the substrate and the lower surface of the source/drain structure, wherein the third width is larger than the first width and the second width; anda spacer element extending along a sidewall of the gate electrode from a top surface of the gate electrode to the substrate, the spacer element has an upper portion and a lower portion between the upper portion and the substrate, wherein a thickness of the upper portion of the spacer element is substantially uniform, and a thickness of the lower portion of the spacer element gradually increases as the lower portion of the spacer element extends towards the substrate.2. The semiconductor device of claim 1 , wherein a lower surface of the spacer element extends along the upper ...

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Номер записи: 130
04-02-2021 дата публикации

FinFET Device and Method of Forming and Monitoring Quality of the Same

Номер: US20210036148A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features. 1. A method of forming a FinFET device , the method comprising:forming a plurality of fins supported by a substrate having a center area and a periphery area;depositing a gate layer on the fins; andetching the gate layer with an etching gas to form a first gate having a first profile in a first portion over a first fin and a second profile in a second portion overlapped with sidewalls of the first fin, wherein the etching gas is applied at a ratio in a range from 0.2 to 1 of a flow rate at the center area relative to a flow rate at the periphery area.2. The method of claim 1 , wherein the etching rate of the gate layer in the peripheral area is similar to the etching rate of the gate layer in the center area.3. The method of claim 1 , wherein the step of etching the gate layer employs an etching gas selected from the group consisting of HBr claim 1 , CF claim 1 , CHF claim 1 , CH claim 1 , CHF claim 1 , NH claim 1 , BCl claim 1 , Cl claim 1 , N claim 1 , H claim 1 , O claim 1 , He claim 1 , Ar claim 1 , and combinations thereof.4. The method of claim 1 , wherein the plurality of fins is formed with a higher density in the center area relative to the peripheral area.5. The method of claim 1 , wherein the step of etching the gate layer forms respective gate structures claim 1 , each having a first notch feature in a first portion over a respective fin and a second notch feature in a second ...

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Номер записи: 131
04-02-2021 дата публикации

EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION

Номер: US20210036155A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, CHENG Tung-Wen, ZHANG ZHE-HAO
Принадлежит:

In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures. 1. A method , comprising:providing a semiconductor structure comprising a body structure;forming a gate structure over the body structure;forming a pair of dielectric structures abutting the body structure;removing a portion of the body structure;removing the pair of dielectric structures; andgrowing stressor material with a lattice constant different from that of the body structure in the source or drain recess to form a source or drain region.2. The method of claim 1 , wherein the body structure is a fin structure.3. The method of claim 2 , wherein forming the gate structure over the body structure comprises:forming the gate structure to wrap around a channel region of the body structure, wherein a first surface is leveled with a bottom of the gate structure.4. The method of claim 3 , wherein forming the pair of dielectric structures abutting the body structure comprises:forming the pair of dielectric structures above the first surface, wherein the pair of dielectric structures are thicker towards the first surface and thinner away from the first surface.5. The method of claim 1 , wherein the removal of the portion of the body structure comprises:removing the body structure above the first surface; andremoving a portion of the body ...

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Номер записи: 132
04-02-2021 дата публикации

SEMICONDUCTOR DEVICE WITH GATE STACK

Номер: US20210036157A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a conductive structure and a gate dielectric layer, and a top of the gate dielectric layer is higher than a top of the conductive structure. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack. 1. A semiconductor device , comprising:a gate stack over a semiconductor substrate, wherein the gate stack has a conductive structure and a gate dielectric layer, and a top of the gate dielectric layer is higher than a top of the conductive structure;a protection element over the gate stack; anda spacer extending along a side surface of the protection element and a sidewall of the gate stack.2. The semiconductor device as claimed in claim 1 , further comprising:a source/drain structure over the semiconductor substrate;a dielectric layer over the source/drain structure and surrounding the gate stack and the spacer; anda conductive contact electrically connected to the source/drain structure.3. The semiconductor device as claimed in claim 2 , wherein the conductive contact is in direct contact with the protection element.4. The semiconductor device as claimed in claim 2 , wherein the conductive contact is separated from the protection element.5. The semiconductor device as claimed in claim 1 , wherein the spacer has an inner sidewall and an outer sidewall claim 1 , the inner sidewall is between the outer sidewall and the gate stack claim 1 , and an upper portion of the inner sidewall inclines towards the outer sidewall.6. The semiconductor device as claimed in claim 5 , wherein the outer sidewall of the spacer is a substantially vertical sidewall.7. The semiconductor device as claimed in claim 1 , wherein an upper portion of the protection element is wider than a lower portion of ...

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Номер записи: 133
11-02-2016 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20160043079A1
Автор: CHANG Chai-Wei, Chang Che-Cheng, Wu Po-Chi
Принадлежит:

In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged. 1. A semiconductor device comprising:a semiconductor substrate with a first region and a second region, wherein the first region comprises first fins for a short gate length device and the second region comprises second fins for a large gate length device;a first dummy material over the first region, the first dummy material extending a first distance away from the semiconductor substrate; anda second dummy material over the second region, the second dummy material extending a second distance away from the semiconductor substrate, the second distance being greater than the first distance.2. The semiconductor device of claim 1 , further comprising a first isolation region at least partially defining the first region claim 1 , the first dummy material being recessed below the first isolation region.3. The semiconductor device of claim 2 , further comprising a first spacer in physical contact with both the first isolation region and the first dummy material.4. The semiconductor device of claim 3 , further comprising a second isolation region at least partially defining the second region.5. The semiconductor device of claim 4 , further comprising a second spacer in physical contact with both the second isolation region and the second dummy ...

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Номер записи: 134
09-02-2017 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR FIN STRUCTURE WITH EXTENDING GATE STRUCTURE

Номер: US20170040439A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure. 114-. (canceled)15. A method for manufacturing a semiconductor structure , comprising:forming a fin structure over a substrate;forming an isolation structure around the fin structure over the substrate;forming a dielectric layer;after the dielectric layer is formed, forming a dummy gate structure across the fin structure;forming spacers on sidewalls of the dummy gate structure;removing the dummy gate structure to form a trench between the spacers;removing a portion of the isolation structure to form an extended trench extending into the isolation structure; andforming a gate structure in the extended trench,wherein the dielectric layer is disposed between the spacers and the isolation structure.16. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein the spacer positioned over the isolation structure has a first height and the gate structure positioned over the isolation structure has a second height which is greater than the first height.17. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein:after the spacer layers are formed and before the dummy gate is removed, the dummy gate structure is formed on a first portion of the dielectric layer and the spacers are formed on a second portion of the dielectric layer,the first portion of the dielectric layer is removed after the dummy gate structure is removed, andthe second ...

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Номер записи: 135
08-02-2018 дата публикации

Semiconductor Device and Method

Номер: US20180040559A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating material over a substrate, and forming a first conductive contact in the first insulating material. The first conductive contact has a protruding uppermost surface, with a first height along a central portion of the first conductive contact, and a second height along a vertical vector projection of a sidewall of the first conductive contact. The first height is larger than the second height. A second insulating material is deposited over the first insulating material, and a second conductive contact is formed in the second insulating material. The second conductive contact is disposed over and at least partially within the first conductive contact. A distance between a bottommost surface of the second conductive contact and the protruding uppermost surface of the first conductive contact is less than about 1.0 nm. 1. A semiconductor device comprising:a first conductive contact disposed over a substrate, the first conductive contact comprising an uppermost surface having a first lateral width; anda second conductive contact over the first conductive contact, the second conductive contact comprising a lower portion having a second lateral width, wherein the first lateral width is larger than the second lateral width.2. The semiconductor device of claim 1 , wherein the first conductive contact is disposed laterally adjacent a gate structure claim 1 , and the second conductive contact is disposed at a level above the gate structure.3. The semiconductor device of claim 2 , further comprising a void located within the gate structure.4. The semiconductor device of claim 2 , further comprising an etch stop layer (ESL) disposed at a level above the gate structure claim 2 , wherein the second conductive contact penetrates the ESL.5. The semiconductor device of claim 1 , wherein the first conductive contact and the second ...

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Номер записи: 136
08-02-2018 дата публикации

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACKS

Номер: US20180040613A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a substrate and a first fin structure and a second fin structure over the substrate. The semiconductor device also includes a first gate stack and a second gate stack partially covering the first fin structure and the second fin structure, respectively, and a stack structure over the substrate. The stack structure is between the first gate stack and the second gate stack. The stack structure includes a semiconductor layer over the substrate and a protection layer over the semiconductor layer. 1. A semiconductor device , comprising:a substrate;a first fin structure and a second fin structure over the substrate;a first gate stack and a second gate stack partially covering the first fin structure and the second fin structure, respectively; and a semiconductor layer over the substrate; and', 'a protection layer over the semiconductor layer., 'a stack structure over the substrate, wherein the stack structure is between the first gate stack and the second gate stack, wherein the stack structure comprises2. The semiconductor device as claimed in claim 1 , wherein the stack structure is over the first fin structure and the second fin structure.3. The semiconductor device as claimed in claim 1 , further comprising:a conductive layer over the semiconductor layer, wherein a top surface of the conductive layer is substantially coplanar with a top surface of the first gate stack.4. The semiconductor device as claimed in claim 1 , wherein the semiconductor layer comprises polysilicon.5. The semiconductor device as claimed in claim 3 , wherein the conductive layer comprises a work function layer and a conductive filling layer over the work function layer.6. The semiconductor device as claimed in claim 3 , wherein the stack structure further comprises:a dielectric layer between the protection layer and the conductive layer.7. The semiconductor device as claimed in claim 1 , ...

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Номер записи: 137
08-02-2018 дата публикации

Fin Structure and Method of Forming Same

Номер: US20180040614A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively. 1. A method comprising:in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device region simultaneously, wherein a first semiconductor strip is formed between the first recesses, and a second semiconductor strip is formed between the second recesses;in a second etching step, etching the semiconductor substrate in the second device region to extend the second recesses lower than the first recesses;filling the first recesses and the second recesses with a dielectric material to form first isolation regions in the first recesses and second isolation regions in the second recesses; andrecessing the first isolation regions and the second isolation regions, wherein portions of the semiconductor substrate in the first device region protrude higher than top surfaces of the first isolation regions to form a first semiconductor fin, and portions of the semiconductor substrate in the second device region protrude higher than top surfaces of the second isolation regions to form a ...

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Номер записи: 138
08-02-2018 дата публикации

Semiconductor Device and Method

Номер: US20180040702A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer. 1. A method of manufacturing a semiconductor device , the method comprising:manufacturing a first source/drain region adjacent to a first spacer, the first spacer adjacent to a gate electrode;forming an opening exposing the first source/drain region; andimplanting dopants into the first source/drain region and the first spacer after the forming the opening, wherein the implanting the dopants forms a first implantation region within the first spacer.2. The method of claim 1 , wherein the dopants are n-type dopants or p-type dopants.3. The method of claim 1 , wherein the forming the opening exposing the first source/drain region also removes a portion of the first spacer to form a first slanted sidewall.4. The method of claim 3 , wherein the first slanted sidewall has an angle of between about 10° and about 85°.5. The method of claim 3 , wherein the first implantation region has a thickness from a surface of the first slanted sidewall of between about 10 Å and about 50 Å.6. The method of claim 1 , further comprising annealing the first source/drain region to activate the dopants claim 1 , wherein the annealing the first source/drain region forms a second implantation region within the first spacer that at least partially overlaps the first implantation region.7. The method of claim 1 , further comprising forming a conductive material within the opening.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a gate stack over a semiconductor fin, the gate stack comprising a gate electrode;forming a first spacer over the semiconductor fin and adjacent to the gate stack;removing a portion of the semiconductor fin exposed by ...

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Номер записи: 139
08-02-2018 дата публикации

FinFET and Method of Forming Same

Номер: US20180040703A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins. 1. A method comprising:forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width;removing unprotected portions of the substrate exposed by the patterned mask stack to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins; andremoving portions of the plurality of fins, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.2. The method of claim 1 , further comprising reducing a height of the first fin and a height of the second fin claim 1 , wherein the height of the first fin is reduced by a greater amount than the height of the second fin.3. The method of claim 1 , wherein removing the unprotected portions of the substrate comprises performing a first etch process on the substrate using the patterned mask stack as an etch mask claim 1 , and wherein removing the portions of the plurality of fins comprises performing a second etch process on the plurality of fins using the patterned mask stack as an etch mask claim 1 , the second etch process being different from the first etch process.4. The method of claim 3 , wherein the first etch process is performed for a first time interval claim 3 , wherein the second etch process is performed for ...

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Номер записи: 140
08-02-2018 дата публикации

FINFET AND METHOD OF FORMING SAME

Номер: US20180040713A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei, Wu Po-Chi
Принадлежит:

A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region. 1. A method comprising:forming a first active fin structure and a second active fin structure on a substrate;forming a dummy fin structure on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure;removing the dummy fin structure to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure;forming a plurality of protruding features on the first portion of the substrate; andforming a shallow trench isolation (STI) region over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.2. The method of claim 1 , wherein removing the dummy fin structure comprises:protecting the first active fin structure and the second active fin structure; andetching the dummy fin structure for a first time interval.3. The method of claim 2 , wherein forming the plurality of protruding features comprises etching the ...

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Номер записи: 141
08-02-2018 дата публикации

Metal Gate Formation Through Etch Back Process

Номер: US20180040715A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate. 1. A method comprising:forming a dummy gate stack over a semiconductor region;forming a dielectric layer at a same level as the dummy gate stack;removing the dummy gate stack to form an opening in the dielectric layer;forming a plurality of metal layers extending into the opening, wherein the plurality of metal layers is formed of different materials;forming a sacrificial layer over the plurality of metal layers, wherein the sacrificial layer is filled into the opening; andetching back the plurality of metal layers, wherein remaining portions of the metal layer plurality of metal layers have edges lower than a top surface of the dielectric layer, wherein after the etching back, the plurality of metal layers have slanted top surfaces, and upper layers in the plurality of metal layers have top surfaces lower than top surfaces of respective underlying layers in the plurality of metal layers;filling the opening with a conductive material, wherein the conductive material is over the plurality of metal layers, wherein the metal layer and the conductive material in combination form a replacement gate; andforming a source region and a drain region, wherein the source region and the drain region are on opposite sides of the replacement gate.2. (canceled)3. The method of claim 1 , wherein the filling the ...

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Номер записи: 142
08-02-2018 дата публикации

Semiconductor Device and Method

Номер: US20180040734A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

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Номер записи: 143
08-02-2018 дата публикации

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

Номер: US20180040735A1
Автор: Chang Che-Cheng, Chen Chang-Yin, CHENG Tung-Wen, LIN MU-TSANG
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer. 1. A method of fabricating a semiconductor structure , comprising:forming a gate dielectric layer and a dummy gate stack on a substrate;etching the dummy gate stack to form a dummy gate structure;etching the gate dielectric layer to form a recess that extends into the gate dielectric layer under the dummy gate structure;forming a protection layer surrounding the dummy gate structure and filling the recess;forming a cavity adjacent to the dummy gate structure by etching the substrate and a portion of the protection layer such that the protection layer has an inner-beveled part;forming an epitaxy in the cavity next to the protection layer;forming a spacer from the protection layer, wherein the spacer includes a skirting part beneath the dummy gate structure and the inner-beveled part contacting the epitaxy;removing the dummy gate structure on the gate dielectric layer; andforming a metal gate structure adjacent to the spacer.2. The method of claim 1 , further comprising forming an inter-layer dielectric layer in contact with the epitaxy and the protection layer.3. The method of claim 1 , wherein etching the gate dielectric layer to form the recess comprises removing a portion of the gate dielectric layer exposed from the dummy gate structure and a portion of the gate dielectric layer underneath the dummy gate structure by performing an etching process.4. The method of claim 3 , wherein the etching process is a dry etching process.5. The method of claim 1 , wherein forming the spacer from the protection layer comprises removing a ...

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Номер записи: 144
18-02-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACUTING METHOD OF THE SAME

Номер: US20160049483A1
Автор: Chang Che-Cheng, CHANG KUO HUI, Chen Chang-Yin, CHENG Tung-Wen, LIN MU-TSANG, ZHANG ZHE-HAO
Принадлежит:

The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length. 1. A semiconductor structure , comprising:a substrate having a top surface;{'b': '10', 'a gate over the substrate, the gate comprising a footing region in proximity to the top surface, the footing region comprising a footing length laterally measured at a height under nm above the top surface; and'}a spacer surrounding a sidewall of a gate body, comprising a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface,wherein the footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between the gate body and the spacer, andwherein the spacer width is substantially equal to or greater than the footing length.2. The semiconductor structure of claim 1 , wherein the gate comprises a high-K dielectric layer over the top surface.3. The semiconductor structure of claim 2 , wherein the gate comprises the high-K dielectric layer at the sidewall of the gate.4. The semiconductor structure of claim 1 , wherein the spacer width is in a range of from about 2 nm to about 20 nm.5. The semiconductor structure of claim 2 , wherein the gate further comprises at least one of an N-work function layer and a P-work ...

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Номер записи: 145
18-02-2021 дата публикации

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH STOP LAYER AND METHOD FOR FORMING THE SAME

Номер: US20210050447A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer. 120.-. (canceled)21. A fin field effect transistor (FinFET) device structure , comprising:a stop layer formed over a substrate, wherein the stop layer is made of a first composition including silicon and oxygen, wherein the first composition extends from a top surface of the stop layer to a bottom surface of the stop layer, the bottom surface of the stop layer over and interfacing a portion of a fin structure extending from the substrate;an isolation structure formed over the substrate, wherein the isolation structure is laterally adjacent to the stop layer;a gate structure formed over a channel region of the fin structure and directly above the isolation structure; anda source/drain (S/D) structure adjacent to the gate structure, wherein the stop layer contiguously extends from under the gate structure to under the S/D structure, and wherein the stop layer has a first thickness under the gate structure and a second thickness under the S/D structure, the second thickness different than the first thickness.22. The FinFET device structure of claim 21 , wherein the second thickness is less than the first thickness.23. The FinFET device structure of claim 21 , wherein the first thickness is disposed below spacer elements abutting the gate structure.24. The FinFET device structure of claim 21 , wherein an entirety of a bottommost surface of the S/D structure is in direct contact with the top surface of the stop layer.25. The FinFET device structure of claim 21 , wherein a top surface of the stop layer ...

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Номер записи: 146
18-02-2016 дата публикации

FIELD EFFECT TRANSISTOR WITH NON-DOPED CHANNEL

Номер: US20160049498A1
Автор: Chang Che-Cheng, Chen Chang-Yin, CHENG Tung-Wen, LIN MU-TSANG
Принадлежит:

Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate. 1. A semiconductor structure , comprising:a substrate having a top surface;a first doped region in proximity to the top surface;a non-doped region, positioned in proximity to the top surface and adjacent to the first doped region, having a first width; anda metal gate, positioned over the non-doped region and over a portion of the first doped region, having a second width;wherein the first width is smaller than the second width,wherein material constituting the non-doped region is different from material constituting the substrate, andwherein the first doped region has a plateau region under the metal gate and the plateau region being an epitaxially-regrown region.2. The semiconductor structure of claim 1 , wherein the non-doped region is an epitaxially-grown region.3. The semiconductor structure of claim 1 , further comprising a second doped region claim 1 , a thickness measured from the top surface to a bottom of the second doped region being from about 10 to about 20 times of a thickness measured from the top surface to a bottom of the non-doped region.4. The semiconductor structure of claim 1 , wherein the material constitutes the non-doped region comprises Si claim 1 , SiC claim 1 , SiN claim 1 , SiON claim 1 , SiGe claim 1 , SiP claim 1 , or the combinations thereof.5. The semiconductor structure of claim 1 , further comprising a high-K dielectric layer between the non-doped region and the metal gate ...

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Номер записи: 147
22-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180053762A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin. 1. A method for manufacturing a semiconductor device comprising:forming a semiconductor fin on a substrate;forming a gate dielectric to cover the semiconductor fin;forming a dummy gate on the gate dielectric and the semiconductor fin;forming at least one gate spacer on at least one sidewall of the dummy gate;removing at least a portion of the semiconductor fin and at least a portion of the gate dielectric uncovered by the dummy gate and the gate spacer and forming a first recess between the gate spacer and the semiconductor fin; andremoving at least another portion of the semiconductor fin covered by the gate dielectric to form a second recess between the gate dielectric and the semiconductor fin.2. The method of claim 1 , wherein the first recess is defined in part by a bottom surface of the gate spacer.3. The method of claim 1 , wherein the second recess is defined in part by a bottom surface and a sidewall of the gate dielectric.4. The method of claim 1 , wherein the second recess underlies the dummy gate.5. The method of claim 1 , comprising forming an epitaxy structure in the first recess and the second recess.6. The method of claim 1 , comprising replacing the dummy gate with a gate electrode after forming the second recess.7. The method of claim 1 , wherein the first recess is defined in part by an end surface of the gate dielectric and an end ...

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Номер записи: 148
22-02-2018 дата публикации

Semiconductor Device and Manufacturing Method Thereof

Номер: US20180053855A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer. 1. A semiconductor device , comprising:a substrate having at least one semiconductor fin;a region defined by gate spacers on two opposed sides of the region and insulating structures on two other opposed sides of the region; anda high-k dielectric layer on the gate insulating film and within the region; anda metal layer within the region and directly contacting the gate spacers.2. The semiconductor device of claim 1 , further comprising a gate electrode filling the region.3. The semiconductor device of claim 1 , wherein the metal layer includes a work function layer contacting a sidewall of at least one gate spacer.4. The semiconductor device of claim 1 , further comprising a gate dielectric layer that extends under respective gate spacers.5. The semiconductor device of claim 2 , wherein at least one of the insulating structures has a sidewall facing the gate electrode claim 2 , and the high-k dielectric layer leaves a sidewall of the at least one of the insulating structures uncovered.6. The semiconductor device of claim 1 , wherein the gate spacers are formed from a material selected from the group consisting of silicon nitride claim 1 , oxynitride claim 1 , silicon carbon claim 1 , silicon oxynitride claim 1 , and silicon oxide.7. The semiconductor device of claim 1 , wherein the insulating structures are formed of a material ...

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Номер записи: 149
13-02-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200052080A1
Автор: Chang Che-Cheng, LIN Chih-Han Cheng, Tseng Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure. 1. A semiconductor structure , comprising:a first dielectric layer;a second dielectric layer;a protection layer over the second dielectric layer;a third dielectric layer over the protection layer; anda conductor extending through the third dielectric layer, the protection layer, and the second dielectric layer, wherein a first portion of the protection layer and a first portion of the second dielectric layer are between the conductor and the first dielectric layer.2. The semiconductor structure of claim 1 , wherein a second portion of the protection layer is over the first dielectric layer.3. The semiconductor structure of claim 1 , wherein a sidewall of the first portion of the second dielectric layer is in contact with a sidewall of the first dielectric layer.4. The semiconductor structure of claim 1 , wherein a sidewall of the first portion of the protection layer is in contact with a sidewall of the first dielectric layer.5. The semiconductor structure of claim 1 , comprising:a gate structure; anda source/drain structure, wherein the third dielectric layer is over the gate structure and the source/drain structure.6. The semiconductor structure of claim 5 , wherein:a second portion of the protection layer is over the gate structure, andthe conductor is over the source/drain structure.7. The semiconductor structure of claim 1 , wherein the protection layer is made of ...

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Номер записи: 150
21-02-2019 дата публикации

Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric

Номер: US20190057964A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region. 1. A semiconductor device comprising:a first transistor that includes:a source/drain region;a gate structure;a gate spacer disposed on a sidewall of the gate structure;a first dielectric material disposed adjacent to an upper portion of the gate spacer; anda second dielectric material disposed adjacent to a lower portion of the gate spacer, wherein the second dielectric material and the first dielectric material have different material compositions.2. The semiconductor device of claim 1 , wherein the first dielectric material has a recessed upper surface.3. The semiconductor device of claim 2 , wherein:the first transistor is a non-Input/Output (non-I/O) device;the semiconductor device further comprises a second transistor that is an Input/Output (I/O) device, the I/O device including a source/drain region, a gate structure, a gate spacer, and a first dielectric material disposed adjacent to an upper portion of the gate spacer; andthe first dielectric material of the I/O device has a more recessed upper surface than the first dielectric material of the non-I/O device.4. ...

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Номер записи: 151
01-03-2018 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20180061831A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer. 1. A method for manufacturing a semiconductor structure , the method comprising:forming a dielectric layer on a source/drain structure adjacent to a first spacer of a gate structure;removing an upper portion of the dielectric layer, such that the dielectric layer and the first spacer of the gate structure form a recess;rounding a top portion of the first spacer adjacent to the recess to have a rounded top corner;forming a protection layer at least on the rounded top corner; andforming a conductive via at least through the dielectric layer to be electrically connected to the source/drain structure.2. The method of claim 1 , further comprising:forming a contact etch stop layer at least on a sidewall of the top portion of the first spacer before the forming the dielectric layer.3. The method of claim 2 , wherein the forming a contact etch stop layer comprises forming a portion of the contact etch stop layer on the source/drain structure.4. The method of claim 2 , wherein the rounding removes at least a portion of the contact etch stop layer from the sidewall of the top portion of the first spacer.5. The method of ...

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Номер записи: 152
20-02-2020 дата публикации

Semiconductor Structure and Manufacturing Method Thereof

Номер: US20200058755A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess. 1. A semiconductor structure , comprising:a gate structure;a source/drain structure;a dielectric layer adjacent to the gate structure and directly contacting the source/drain structure, wherein a top surface of the dielectric layer is below a top surface of the gate structure;a first conductor directly contacting the source/drain structure; anda gap over the source/drain structure, wherein a bottom of the gap is above a bottom of first conductor.2. The semiconductor structure of claim 1 , wherein the dielectric layer and the first conductor directly contact a top surface of the source/drain structure.3. The semiconductor structure of claim 1 , wherein the first conductor directly contacts a sidewall of the dielectric layer.4. The semiconductor structure of claim 1 , wherein the gap is defined by the dielectric layer and the first conductor.5. The semiconductor structure of claim 4 , comprising:a spacer between the gate structure and the dielectric layer, wherein the gap is further defined by the spacer.6. The semiconductor structure of claim 1 , comprising:a spacer between the gate structure and the dielectric layer.7. The semiconductor structure of claim 1 , wherein the first conductor comprises a first portion having a substantially uniform width and a second portion having a tapered width.8. The semiconductor structure of claim 1 , comprising a second conductor over the first conductor and over the gap.9. The ...

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Номер записи: 153
04-03-2021 дата публикации

Fin Structure and Method of Forming Same Through Two-Step Etching Processes

Номер: US20210066290A1
Автор: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

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Номер записи: 154
04-03-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210066501A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and in which the high-k dielectric layer is in contact with the top surface of the STI structure. 1. A device , comprising:a substrate having a semiconductor fin;a shallow trench isolation (STI) structure over the substrate and laterally surrounding the semiconductor fin;an isolation structure disposed on a top surface of the STI structure; anda gate stack crossing the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, wherein the gate stack comprises a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and wherein the high-k dielectric layer is in contact with the top surface of the STI structure.2. The device of claim 1 , further comprising a gate insulating film between the high-k dielectric layer and the semiconductor fin.3. The device of claim 1 , wherein the gate stack further comprises a metal layer extending over the high-k dielectric layer and terminating prior to reaching the sidewall of the isolation structure.4. The device of claim 3 , wherein the gate stack further comprises a gate electrode over the metal layer and in contact with the sidewall of the isolation structure.5. The device ...

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Номер записи: 155
12-03-2015 дата публикации

STRAINED SOURCE AND DRAIN (SSD) STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20150069466A1
Автор: Chang Che-Cheng, Chang Yung-Jung, Chen Yi-Jen, CHENG Tung-Wen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers. 1. A semiconductor device structure , comprising:a substrate;a gate stack structure formed on the substrate;gate spacers formed on sidewalls of the gate stacks; anddoped regions formed in the substrate;a strained source and drain (SSD) structure adjacent to the gate spacers, wherein the doped regions are adjacent to the SSD structure, and SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.2. The semiconductor device structure as claimed in claim 1 , wherein an inner border of the SSD structure on a top surface of substrate is not aligned with an outer side of the gate spacers.3. The semiconductor device structure as claimed in claim 1 , wherein the doped regions are doped with arsenic (As) claim 1 , phosphorous (P) claim 1 , antimony (Sb) claim 1 , boron (B) or boron fluorine (BF).4. The semiconductor device structure as claimed in claim 1 , wherein the doped regions have a depth in a range from about 1 A to about 100 A.5. The semiconductor device structure as claimed in claim 1 , wherein the doped regions have a doping concentration in a range from about 1E13 to about 2E18 atom/cm.6. The semiconductor device structure as claimed in claim 1 , wherein a surface ...

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Номер записи: 156
12-03-2015 дата публикации

SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK

Номер: US20150069535A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, Chen Chang-Yin, Chen Yi - Jen
Принадлежит:

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided. 1. A semiconductor device , comprising:a metal gate stack comprising a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric, the metal gate electrode comprising a first top surface and a second bottom surface substantially diametrically opposite the first top surface, the first top surface comprising a first surface length and the second bottom surface comprising a second surface length, wherein the first surface length is larger than the second surface length.2. The semiconductor device of claim 1 , wherein the metal gate electrode comprises a third surface and a fourth surface substantially diametrically opposite the third surface.3. The semiconductor device of claim 2 , wherein the second bottom surface is at a first angle with respect to the third surface that is greater than about 90 degrees and a second angle with respect to the fourth surface that is greater than about 90 degrees.4. The semiconductor device of claim 2 , wherein the first top surface is at a third angle with respect to the third surface that is less than about 90 degrees and a fourth angle with respect to the fourth surface that is less than about 90 degrees.5. The semiconductor device of claim 2 , wherein the third surface is not parallel with respect to the fourth surface.6. A method of forming a semiconductor device claim 2 , comprising:forming a gate dielectric;forming a silicon dummy layer over the gate dielectric such ...

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Номер записи: 157
17-03-2022 дата публикации

Method of manufacturing a semiconductor and a semiconductor device

Номер: US20220085203A1
Автор: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

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Номер записи: 158
10-03-2016 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE

Номер: US20160071976A1
Автор: Chang Che-Cheng, Chang Yung-Jung, Chen Yi-Jen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack , and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure . The etch stop layer is in contact with the sealing structure. 1. A semiconductor device structure , comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;a sealing structure over a sidewall of the gate stack, wherein a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7; andan etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure, wherein the etch stop layer is in contact with the sealing structure.2. The semiconductor device structure as claimed in claim 1 , wherein there is no intermediate layer between the sealing structure and the etch stop layer.3. The semiconductor device structure as claimed in claim 1 , wherein the sealing structure comprises silicon nitride.4. The semiconductor device structure as claimed in claim 1 , wherein the gate stack comprises a metal gate electrode and a gate dielectric layer.5. The semiconductor device structure as claimed in claim 4 , wherein the sealing structure is in contact with the metal gate electrode.6. The semiconductor device structure as claimed in claim 4 , wherein the sealing structure is in contact with the gate dielectric layer.7. The semiconductor device structure as claimed in claim 1 , further comprising:a lightly-doped source/drain region in the semiconductor substrate and adjacent to the gate stack; anda heavily-doped source/drain region in the semiconductor substrate and adjacent to ...

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Номер записи: 159
10-03-2016 дата публикации

Semiconductor structure and fabricating method thereof

Номер: US20160071980A1
Автор: Chang-Yin Chen, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen CHENG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

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Номер записи: 160
08-03-2018 дата публикации

Method and Structure for FinFET Isolation

Номер: US20180068900A1
Автор: Chang Che-Cheng, LIN Chih-Han, Lin Jr-Jung
Принадлежит:

A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin. 1. A semiconductor device , comprising:a substrate;first and second fins over the substrate and extending lengthwise generally along a first direction;a first gate stack over the substrate and the first fin;a second gate stack over the substrate and the second fin; anda first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin.2. The semiconductor device of claim 1 , further comprising one or more dielectric layers over the first fin and laterally between the first gate stack and the first isolation structure.3. The semiconductor device of claim 1 , further comprising:spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.4. The semiconductor device of claim 3 , wherein the spacer features completely surround the first isolation structure from a top view.5. The semiconductor device of claim 1 , wherein a bottom surface of the first isolation structure is below a bottom surface of the first gate stack.6. The semiconductor device of claim 1 , wherein the first isolation structure includes a first portion above the first and second fins and a second portion between the ...

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Номер записи: 161
08-03-2018 дата публикации

Semiconductor structure with unleveled gate structure

Номер: US20180069095A1
Автор: Chai-Wei Chang, Che-Cheng Chang, Po-Chi WU, Yi-Cheng Chao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over a portion of the gate dielectric layer. The gate structure further includes a gate electrode layer formed over a portion of the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

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Номер записи: 162
08-03-2018 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR FIN STRUCTURE WITH EXTENDING GATE STRUCTURE

Номер: US20180069101A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure. 120-. (canceled)21. A method for manufacturing a semiconductor structure , comprising:forming a fin structure protruding from a substrate;forming an isolation structure around the fin structure over the substrate;forming a dummy gate structure across the fin structure, the dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode layer, and sidewall spacers;removing the dummy gate dielectric layer and the dummy gate electrode layer to form a trench between the sidewall spacers;removing a portion of the isolation structure to form an extended trench extending into the isolation structure; andforming a gate structure in the extended trench, wherein:a portion of the extended trench further extends to a position below the sidewall spacers, andafter the gate structure is formed, a part of the dummy gate dielectric layer is disposed between one of the sidewall spacers and the isolation structure, and the gate structure is in contact with the part of the dummy gate dielectric layer and the sidewall spacers.22. The method of claim 21 , wherein a portion of the sidewall spacers is positioned over the isolation structure and has a first height and a portion of the gate structure is positioned over the isolation structure and has a second height which is greater than the first height.23. The method of claim 21 , wherein:the dummy gate electrode is formed on a first portion ...

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Номер записи: 163
27-02-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200066530A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei, Wu Po-Chi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure. 1. A semiconductor device comprising:a substrate; a fin over the substrate;', 'a gate electrode over the fin; and', 'a gate dielectric layer between the gate electrode and the fin; and, 'a fin field-effect transistor (FinFET) comprisingan insulating structure over the substrate, adjacent the fin, and having a top surface lower than a top surface of the fin, wherein the top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions and the first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.2. The semiconductor device of claim 1 , wherein the second edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.3. The semiconductor device of claim 1 , wherein the first edge portion of the top surface of the insulating structure extends downwards form the intermediate portion of the top surface of the insulating structure toward a first sidewall of the insulating structure.4. The semiconductor device of claim 3 , wherein the second edge portion of the top surface of the ...

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Номер записи: 164
27-02-2020 дата публикации

Fin Field Effect Transistor (FinFET) Device and Method

Номер: US20200066719A1
Автор: CHANG Chai-Wei, Chang Che-Cheng, CHAO Yi-Cheng, Wu Po-Chi
Принадлежит:

A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm. 1. A method comprising:forming a fin structure over a substrate;forming a first dummy gate structure and a second dummy gate structure over the fin structure;forming an inter-layer dielectric (ILD) structure over the substrate and adjacent to the first dummy gate structure and the second dummy gate structure;removing the first dummy gate structure to form a first trench in the ILD structure;removing the second dummy gate structure to form a second trench in the ILD structure;forming a first gate structure in the first trench and a second gate structure in the second trench, the first gate structure comprising a first work function layer and a first gate electrode layer, and the second gate structure comprising a second work function layer and a second gate electrode layer;removing portions of the first gate structure and the second gate structure outside of the first and second trenches;performing a first etch process on the first work function layer and the second work function layer, wherein after the first etch process the first work function layer has a top surface lower than a top surface of the first gate electrode layer, and wherein after the first etch process the second ...

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Номер записи: 165
27-02-2020 дата публикации

Semiconductor Structure and Manufacturing Method Thereof

Номер: US20200066853A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer. 1. A structure comprising:a first gate structure over a substrate;a source drain structure on the substrate adjacent the first gate structure;a dielectric layer over the source drain structure and the first gate structure; anda conductive plug extending through the dielectric layer and electrically connected to the source drain structure, a gap being between the conductive plug and the first gate structure, the gap extending to the source drain structure, a top portion of the source drain structure being above a top surface of the substrate.2. The structure of claim 1 , wherein the gap is gas filled.3. The structure of claim 1 , wherein a top surface of the conductive plug is higher than a top surface of the dielectric layer.4. The structure of further comprising:a mask layer between the first gate structure and the dielectric layer.5. The structure of further comprising:a second gate structure adjacent the source drain structure, the source drain structure being between the first and second gate structures, the gap being between the conductive plug and the second gate structure.6. The structure of claim 5 , wherein the first gate structure is spaced apart from the second gate structure by a first distance claim 5 , the conductive plug having an upper portion having a first width claim 5 , the first width being greater than the first distance.7. The structure of further comprising:spacers on opposing sidewalls of the first gate structure, at least one of the ...

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Номер записи: 166
27-02-2020 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH UNLEVELED GATE STRUCTURE

Номер: US20200066880A1
Автор: CHANG Chai-Wei, Chang Che-Cheng, CHAO Yi-Cheng, Wu Po-Chi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion. 1. A method for manufacturing a semiconductor structure , comprising:forming a fin structure from a substrate;forming a gate dielectric layer across the fin structure;forming a work function metal layer over the gate dielectric layer;forming a gate electrode layer over the work function metal layer;etching the work function metal layer to form a gap between the gate dielectric layer and the gate electrode layer;etching the gate dielectric layer to enlarge the gap;etching the gate electrode layer from the enlarged gap; andforming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer,wherein the dielectric layer comprises a first portion directly above the work function metal layer, a second portion directly above the gate dielectric layer, and a third portion directly above the gate electrode layer, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.2. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the dielectric layer has a ...

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Номер записи: 167
11-03-2021 дата публикации

Notched Gate Structure Fabrication

Номер: US20210074591A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han
Принадлежит:

A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack. 1. A method , comprising:providing a structure having a substrate and a fin protruding from the substrate;forming a gate stack layer over the fin;patterning the gate stack layer, thereby forming a gate stack, wherein the patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack;removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, wherein a top portion of the passivation layer remains; andlaterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.2. The method of claim 1 , wherein the bottom portion of the passivation layer is thinner than the top portion of the passivation layer.3. The method of claim 1 , wherein the passivation layer is formed on the sidewall surfaces of the gate stack but not on a top surface of the gate stack.4. The method of claim 1 , wherein the passivation layer is an oxide layer or a nitride layer.5. The method of claim 1 , wherein after the laterally etching of the bottom portion of the gate stack claim 1 , the bottom portion of the gate stack has a curvature surface.6. The method of claim 1 , wherein the patterning of the gate stack layer includes applying a mixture of an etchant and a passivation gas.7. The method of claim 6 , ...

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Номер записи: 168
11-03-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20210074840A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han
Принадлежит:

A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer. 1. A semiconductor device , comprising:an isolation insulating layer disposed over a substrate;a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer;a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer;gate sidewall spacers disposed over opposing side faces of the gate structure; anda source/drain epitaxial layer, wherein:the upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin,the first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer, andthe gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.2. ...

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Номер записи: 169
11-03-2021 дата публикации

Fin Field Effect Transistor (FinFET) Device and Method for Forming the Same

Номер: US20210074859A1
Автор: Chang Che-Cheng, Chang Yung-Jung, Chen Chang-Yin, CHENG Tung-Wen, ZHANG ZHE-HAO
Принадлежит:

A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure. 1. A semiconductor device comprising:a fin structure embedded in an isolation structure, wherein a top surface of the fin structure intersects a top surface of the isolation structure at an angle of greater than 90° and less than about 175°, wherein the angle is measured from a portion of the fin structure that is embedded in the isolation structure to a sidewall of the isolation structure; andan epitaxial structure formed on a surface of the fin structure, wherein a cross section of the epitaxial structure has a pentagon-like shape, and wherein an interface between the epitaxial structure and a first portion of the fin structure is lower than a top surface of the isolation structure.2. The semiconductor device of claim 1 , wherein the epitaxial structure extends above the isolation structure between about 1 nm and about 100 nm.3. The semiconductor device of claim 2 , wherein the epitaxial structure has a width of between about 1 nm and about 100 nm.4. The semiconductor device of claim 1 , wherein a ratio of a height of the epitaxial structure and a width of the epitaxial structure is between about 1 and about 100.5. The semiconductor device of claim 1 , wherein the epitaxial structure extends into the isolation structure a distance of between about 0.1 nm and about 50 nm.6. The semiconductor device of claim 1 , wherein the epitaxial structure comprises ...

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Номер записи: 170
17-03-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACUTING METHOD OF THE SAME

Номер: US20160079353A1
Автор: Chang Che-Cheng, Chen Chang-Yin, CHENG Tung-Wen, LIN Chih-Han, Lin Jr-Jung, Wu Po-Chi
Принадлежит:

Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin. 1. A semiconductor structure , comprising:a substrate having a center portion and an edge portion;an isolation layer over the substrate;a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer;a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate; anda second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate,wherein a lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.2. The semiconductor structure of claim 1 , wherein the substrate further comprises a dense gate region and an isolated gate region at the center portion and at the edge portion of the substrate.3. The semiconductor structure of claim 1 , a difference between the lower width and the upper width is below 15 nm.4. The semiconductor structure of claim 3 , a 3-sigma value of the difference between the lower width and the upper width measured by a spectroscopic critical ...

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Номер записи: 171
16-03-2017 дата публикации

Method and Structure for FinFET Isolation

Номер: US20170076989A1
Автор: Che-Cheng Chang, Chih-Han Lin, Jr-Jung LIN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a substrate having first and second fins extending lengthwise generally along a same line; a first gate stack over the substrate and engaging the first fin; a second gate stack over the substrate and engaging the second fin; a first isolation structure disposed between the first and second fins; and spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.

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Номер записи: 172
16-03-2017 дата публикации

ENHANCED VOLUME CONTROL BY RECESS PROFILE CONTROL

Номер: US20170077302A1
Автор: Chang Che-Cheng, CHENG Tung-Wen, LIN MU-TSANG, Young Bo-Feng, Yu Cheng-Yen
Принадлежит:

The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses. 1. A semiconductor device , comprising:epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region;a gate structure arranged onto the semiconductor body over the channel region; anda dielectric material arranged laterally between the epitaxial source/drain regions and the channel region.2. The semiconductor device of claim 1 ,wherein the semiconductor body comprises a three-dimensional fin of semiconductor material extending outward from a semiconductor substrate,wherein the epitaxial source/drain regions are arranged within the three-dimensional fin of semiconductor material; andwherein the gate structure straddles the three-dimensional fin of semiconductor material.3. The semiconductor device of claim 2 , wherein the gate structure comprises:a gate electrode disposed over a gate dielectric layer;a gate protection layer disposed over the gate electrode; anda hard mask disposed over the gate protection layer.4. The semiconductor device of claim 3 , further comprising:a sealant layer disposed along sidewalls of the gate electrode, sidewalls of the gate ...

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Номер записи: 173
05-03-2020 дата публикации

Semiconductor device with gate stack

Номер: US20200075766A1
Автор: Che-Cheng Chang, Chih-Han Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a work function layer and a gate dielectric layer, and tops of the work function layer and the gate dielectric layer are at different height levels. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.

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Номер записи: 174
18-03-2021 дата публикации

Method of Forming Trenches

Номер: US20210082748A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench. 1. A device comprising:an interlayer dielectric layer disposed on a substrate, the interlayer dielectric layer having a first sidewall segment and an opposing second sidewall segment;a capping layer including a first portion disposed along an interfacing with the first sidewall segment of the interlayer dielectric layer and a second portion disposed along an interfacing with the second sidewall segment of the interlayer dielectric layer, the first portion of the capping layer having a first top surface tapering toward the substrate and the second portion of the capping layer having a second top surface tapering toward the substrate; anda conductive feature extending through the interlayer dielectric layer and the capping layer such that the conductive feature interfaces with the capping layer and the interlayer dielectric layer.2. The device of claim 1 , wherein the first portion of the capping layer further includes a first sidewall surface and an opposing second sidewall surface and the first top surface tapers from the first sidewall surface to the second sidewall surface claim 1 , the first sidewall surface interfacing with the first sidewall segment of the interlayer dielectric layer and the second sidewall surface interfacing with the conductive feature and the first top surface interfacing with the conductive feature.3. The device of claim 1 , wherein the interlayer dielectric layer includes a third sidewall segment directly connected to the first sidewall segment and a fourth sidewall segment directly connected to the second sidewall segment claim 1 , ...

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Номер записи: 175
24-03-2016 дата публикации

SEMICONDUCTOR STRUCTURE WITH STRAINED SOURCE AND DRAIN STRUCTURES AND METHOD FOR FORMING THE SAME

Номер: US20160087037A1
Автор: Chang Che-Cheng, Chen Chang-Yin, CHENG Tung-Wen, LIN MU-TSANG
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid. 1. A semiconductor structure , comprising:a substrate;a first gate structure and a second gate structure formed over the substrate;first recesses formed in the substrate adjacent to the first gate structure;first strained source and drain structures formed in the first recesses;second recesses formed in the substrate adjacent to the second gate structure; andsecond strained source and drain structures formed in the second recesses,wherein each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid.2. The semiconductor structure as claimed in claim 1 , wherein each of the first recesses has a first top width and a first bottom width greater than the first top width claim 1 , and each of the second recesses has a second top width and a second bottom width less than the second top width.3. The semiconductor structure as claimed in claim 2 , wherein a ratio of the first top width to the first bottom width is in a range from about 1 to about 0.3 claim 2 , and a ratio of the second top width to the second bottom width is in a range from about 3 to about 1.4. The semiconductor structure as claimed in claim 1 , wherein each of the first strained source and drain structures has a ...

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Номер записи: 176
23-03-2017 дата публикации

Structure and Formation Method of Semiconductor Device Structure

Номер: US20170084499A1
Автор: Che-Cheng Chang, Chen-Hsiang LU, Jui-Ping Chuang, Wei-Ting Chen, Yu-Cheng Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element

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Номер записи: 177
12-03-2020 дата публикации

Semiconductor Device and Manufacturing Method Thereof

Номер: US20200083378A1
Автор: Chang Che-Cheng, LIN Chih-Han
Принадлежит:

A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer. 1. A semiconductor device , comprising:a gate stack over a fin, the gate stack including one or more metal layers;first insulating structures over the fin on opposing first sides of the gate stack; andsecond insulating structures on opposing second sides of the gate stack, wherein the second insulating structures are interposed between the first insulating structures, wherein an upper surface of the first insulating structures is level with an upper surface of the second insulating structures.2. The device of claim 1 , wherein the gate stack further comprises:a high-k dielectric layer interposed between the one or more metal layers and the fin, wherein a lower surface of the high-k dielectric layer is level with a bottom surface of the first insulating structures.3. The device of claim 2 , wherein the bottom surface of the high-k dielectric layer is level with a bottom surface of the second insulating structures.4. The device of claim 1 , wherein the gate stack comprises a first metal layer claim 1 , wherein the first metal layer is in direct contact with the second insulating structures.5. The device of claim 4 , wherein the first metal layer is in direct contact with the first insulating structures.6. The device of claim 1 , wherein the first insulating structures comprise silicon nitride claim 1 , oxynitride claim 1 , silicon ...

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Номер записи: 178
12-03-2020 дата публикации

Semiconductor Device and Method

Номер: US20200083379A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure. 1. A method comprising:forming a gate structure, wherein the gate structure comprises a first metal layer and a second metal layer over the first metal layer, wherein the first metal layer extends above the second metal layer;depositing a first dielectric material over the gate structure;forming a first via opening disposed over the gate structure and through the first dielectric material, the first via opening exposing an upper surface and sidewall of the first metal layer; andforming a conductive contact in the first via opening, wherein the conductive contact physically contacts the first metal layer and the second metal layer.2. The method of claim 1 , wherein forming the gate structure comprises forming a third metal layer claim 1 , wherein the first metal layer is over the third metal layer claim 1 , wherein an upper surface of the first metal layer and an upper surface of the third metal layer form a curved surface.3. The method of claim 2 , wherein forming the gate structure comprises forming a gate dielectric prior to forming the third metal layer claim 2 , wherein the third metal layer is formed over the gate dielectric claim 2 , wherein the ...

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Номер записи: 179
31-03-2016 дата публикации

APPARATUS AND METHOD OF MANUFACTURING FIN-FET DEVICES

Номер: US20160093537A1
Автор: Chang Che-Cheng, Chen Chang-Yin, CHENG Tung-Wen, LIN Chih-Han, Lin Jr-Jung
Принадлежит:

A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3. 1. A method of manufacturing a Fin-FET device , comprising:forming a plurality of fins in a substrate, wherein the substrate comprises a center region and a periphery region surrounding the center region;depositing a gate material layer over the fins; andetching the gate material layer with an etching gas to form gates, wherein the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.2. The method of claim 1 , wherein the gate formed at the center region and the gate formed at the periphery region both have a notched feature.3. The method of claim 1 , wherein the gate has a first portion disposed above the fin and a second portion overlapped with the sidewalls of the fin.4. The method of claim 3 , wherein the second portion comprises:a first width at a boundary of the first portion and the second portion; anda second width at a bottom of the gate, wherein the second width is smaller than the first width.5. The method of claim 4 , further comprising a third width between the first width and the second width claim 4 , wherein the third with is smaller than the second width.6. The method of claim 1 , wherein the etching gas is hydrogen bromide or oxygen.7. The method of claim 1 , further comprising growing an epitaxial structure in the fin.8. The method of claim 7 , wherein the epitaxial structure is formed of SiGe.9. The method of claim 7 , wherein a proximity distance between the epitaxial structure and the gate is in a range ...

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Номер записи: 180
29-03-2018 дата публикации

Metal Gate Process for FinFET Device Improvement

Номер: US20180090590A1
Автор: Chang Che-Cheng, LIN Chih-Han, Tseng Horng-Huei
Принадлежит:

In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole. 1. A semiconductor device , comprising: 'a metal gate on a portion of the substrate, wherein the metal gate has a first width and a second width which is greater than the first width, wherein the first width is measured at a first height above the substrate, and the second width is measured at a second height above the substrate which is higher than the first height;', 'a substrate;'}a first dielectric layer, wherein the first dielectric layer comprises a doped portion surrounding an upper portion of the metal gate and an undoped portion surrounding a lower portion of the metal gate; anda second dielectric layer surrounding the first dielectric layer.2. The semiconductor device of claim 1 , wherein the first dielectric layer is silicon nitride or silicon oxynitride claim 1 , and the second dielectric layer is silicon oxide.3. The semiconductor device of claim 1 , wherein the doped portion is doped with phosphorous or boron.4. The semiconductor device of claim 1 , wherein the second dielectric layer includes a doped region overlying an undoped region.5. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 181
30-03-2017 дата публикации

SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK

Номер: US20170092741A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, Chen Yi-Jen
Принадлежит:

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided. 1. A method of forming a semiconductor device , comprising:forming a silicon dummy layer;etching the silicon dummy layer to define a first tapered sidewall and a second tapered sidewall;forming a first spacer adjacent the first tapered sidewall of the silicon dummy layer and forming a second spacer adjacent the second tapered sidewall of the silicon dummy layer;removing the silicon dummy layer to form an opening, wherein the opening is defined by a first tapered sidewall of the first spacer previously in contact with the first tapered sidewall of the silicon dummy layer and a first tapered sidewall of the second spacer previously in contact with the second tapered sidewall of the silicon dummy layer; andforming a gate electrode in the opening.2. The method of claim 1 , wherein etching the silicon dummy layer comprises:performing a first etch using a first etch process to etch through a first portion of the silicon dummy layer; andperforming a second etch using a second etch process to etch through a second portion of the silicon dummy layer, the second etch process different than the first etch process.3. The method of claim 2 , wherein etching the silicon dummy layer comprises:performing a third etch using a third etch process to etch through a third portion of the silicon dummy layer.4. The method of claim 3 , wherein the third etch exposes a top surface of a substrate underlying the silicon dummy layer.5. The method of ...

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Номер записи: 182
07-04-2016 дата публикации

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK

Номер: US20160099324A1
Автор: Chang Che-Cheng, Chen Yi-Jen, Shih Sheng-Chi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate. 1. A semiconductor device , comprising:a semiconductor substrate;a first gate electrode over the semiconductor substrate, wherein the first gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate;a first gate dielectric layer between the first gate electrode and the semiconductor substrate;a second gate electrode over the semiconductor substrate, wherein the second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion of the second gate electrode is wider than the lower portion of the second gate electrode;a second gate dielectric layer between the second gate electrode and the semiconductor substrate; anda third gate electrode over the semiconductor substrate and between the first gate electrode and the second gate electrode and are immediately adjacent to the first gate electrode and the second gate electrode, wherein the third gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate,wherein the lower portion of the third gate electrode is wider than the lower portion of the second gate electrode and is narrower than the lower ...

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Номер записи: 183
07-04-2016 дата публикации

GATE STRUCTURE HAVING DESIGNED PROFILE AND METHOD FOR FORMING THE SAME

Номер: US20160099337A1
Автор: Chang Che-Cheng, CHENG Kai-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C. 112-. (canceled)13. A method for forming a semiconductor structure , comprising:forming a polysilicon layer over a substrate;forming a hard mask structure over the polysilicon layer;etching the polysilicon layer to form a dummy gate structure below the hard mask structure;forming spacers over sidewalls of the dummy gate structure; andreplacing the dummy gate structure by a metal gate structure,wherein the dummy gate structure has a top width, a neck width, and a bottom width, and the neck width is larger than both the top width and the bottom width.14. The method for forming a semiconductor structure as claimed in claim 13 , wherein the step of etching the polysilicon layer to form the dummy gate structure further comprises:etching the polysilicon layer to form an upper portion of the dummy gate structure by a first etching process; andetching the polysilicon layer to form a bottom portion of the dummy gate structure by a second etching process,wherein a first etching gas and a second gas are used in both the first etching process and the second etching process, and a volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than a volume ratio of the first etching gas to the second etching gas used in the second etching process.15. The method for forming a semiconductor structure as claimed in claim 14 , wherein the first etching gas is CF claim 14 , and the second ...

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Номер записи: 184
28-03-2019 дата публикации

Removing Polymer Through Treatment

Номер: US20190096747A1
Автор: Chang Che-Cheng, CHEN HUNG-HAO, Chen Wen-Tung, LIU YU-CHENG, Tseng Horng-Huei
Принадлежит:

A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively. 1. A method of forming integrated circuits , the method comprising:performing a first photo lithography process to form a first trench in a dielectric layer;performing a second photo lithography process to form a second trench in the dielectric layer;using the dielectric layer as a first etching mask to etch a hard mask layer and to extend the first trench and the second trench into the hard mask layer;performing a third photo lithography process to form a first via opening in an upper portion of a low-k dielectric layer underlying the hard mask layer;performing a fourth photo lithography process to form a second via opening in the upper portion of the low-k dielectric layer;etching the low-k dielectric layer using the hard mask layer as a second etching mask to extend the first trench and the second trench into the low-k dielectric layer, wherein the first via opening and the second via opening extend into a bottom portion of the low-k dielectric layer; andperforming a treatment using a process gas including nitrogen and argon to remove a polymer in the first trench, the second trench, the first via opening and the second via opening.2. The method of claim 1 , wherein the ...

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Номер записи: 185
13-04-2017 дата публикации

METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Номер: US20170104087A1
Автор: Chang Che-Cheng, Chang Yung-Jung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin structure extending above a substrate and forming an isolation structure over the substrate, and the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure. The method also includes forming a first transistor and a second transistor on the first fin structure and the second fin structure, and the first transistor includes a first gate dielectric layer. The method further includes forming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, and a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure. 1. A method for forming a fin field effect transistor (FinFET) device structure , comprising:providing a first fin structure and a second fin structure extending above a substrate;forming an isolation structure over the substrate, wherein the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure;forming a first transistor and a second transistor on the first fin structure and the second fin structure, wherein the first transistor comprises a first gate dielectric layer; andforming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, wherein a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure.2. The method for forming the FinFET device structure as claimed in claim 1 , further comprising:forming a polysilicon layer on the first fin structure and the second fin structure before forming the first transistor and the second transistor on the first fin structure and the second fin structure.3. The method for forming the ...

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Номер записи: 186
26-03-2020 дата публикации

Methods of Forming Isolation Features in Metal Gates

Номер: US20200098646A1
Автор: Chang Che-Cheng, Chen Chang-Yin, LIN Chih-Han
Принадлежит:

A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins. 1. A method , comprising:providing a structure having a first fin and a second fin over a substrate, lower portions of the first fin and the second fin being separated by an isolation structure, a dummy gate structure over the first fin and the second fin, and source/drain features over the first fin and the second fin on both sides of the dummy gate structure;forming a trench in the dummy gate structure between the first fin and the second fin, wherein the forming of the trench removes a portion of the isolation structure;forming a dielectric layer in the trench, wherein a bottom surface of the dielectric layer extends below a top surface of the isolation structure; andreplacing the dummy gate structure with a first high-k metal gate structure formed over the first fin and a second high-k metal gate structure formed over the second fin.2. The method of claim 1 , wherein the forming of the trench includes:removing a top portion of the dummy gate structure in a first etching process, wherein the first etching process is implemented at a first etching power and a first etching bias; andremoving a bottom portion of the dummy gate structure in a second etching process, wherein the second etching process is implemented ...

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Номер записи: 187
21-04-2016 дата публикации

Method and Structure for FinFET Isolation

Номер: US20160111336A1
Автор: Chang Che-Cheng, LIN Chih-Han, Lin Jr-Jung
Принадлежит:

A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and separating the dummy gate stacks. The method further includes removing the dummy gate stacks thereby forming a first trench and a second trench that expose first and second portions of the active fin respectively. The method further includes removing the first portion of the active fin and forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin. The method further includes filling the first trench with a second dielectric material that effectively isolates the second portion of the active fin. 1. A method of forming a semiconductor device , comprising:receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and between the dummy gate stacks;removing the dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose first and second portions of the active fin respectively;removing the first portion of the active fin; andforming a gate stack in the second trench, the gate stack engaging the second portion of the active fin.2. The method of claim 1 , wherein the dummy gate stacks and the first dielectric features are separated by spacer features.3. The method of claim 1 , further comprising:filling the first trench with a second dielectric material.4. The method of claim 1 , wherein the dummy gate stacks are over a first surface of an isolation structure over the substrate claim 1 , and the removing of the first portion of the active fin includes:expanding the first trench below the first surface.5. The method of claim 1 , wherein the removing of the first portion of the ...

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Номер записи: 188
21-04-2016 дата публикации

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME

Номер: US20160111420A1
Автор: Chang Che-Cheng, Chang Yung-Jung, CHENG Tung-Wen, ZHANG ZHE-HAO
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure. 112-. (canceled)13. A method for forming a fin field effect transistor (FinFET) device structure , comprising:providing a substrate, wherein the substrate comprises a core region and an I/O region;forming a fin structure above the substrate;forming a plurality of gate stack structures over the fin structure;performing a deposition process to form a film on the fin structure and the gate stack structures; andetching the film and a portion of the fin structure to form a plurality of first trenches in the core region and a plurality of second trenches in the I/O region.14. The method for forming the FinFET device structure as claimed in claim 13 , wherein a first etched fin structure directly below the gate stack structure is formed between two adjacent first trenches claim 13 , and a second fin etched fin structure directly below the gate stack structure is formed between two adjacent second trenches claim 13 , and the a width of the first etched fin structure is smaller than a width of the second etched fin structure.15. The method for forming the FinFET device structure as claimed in claim 13 , further comprising:epitaxially growing an epitaxial structure in the first trenches and the second trenches, wherein an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.16. The method for ...

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Номер записи: 189
21-04-2016 дата публикации

Method and Structure for FinFET

Номер: US20160111518A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, CHEN Shih-Hao, LIN Chih-Han, Lin Jr-Jung, LIN MU-TSANG
Принадлежит:

A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity. 1. A method of forming a semiconductor device , comprising:receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack;removing the dummy gate stack, resulting in a first trench;etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature;depositing a dielectric material in the first trench and in the cavity; andetching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.2. The method of claim 1 , wherein the etching of the oxide layer exposes the active fin.3. The method of claim 1 , wherein the etching of the oxide layer partially removes the oxide layer claim 1 , leaving a portion of the oxide layer over the active fin in the first trench.4. The method of claim 3 , wherein the etching in the first trench includes first and second etching processes claim 3 , the first etching process is tuned to etch the dielectric material claim 3 , and the second etching process is tuned to etch the portion of the oxide layer.5. The method of claim 1 , wherein the depositing of the dielectric material uses one of: atomic layer deposition and chemical vapor deposition.6. ...

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Номер записи: 190
21-04-2016 дата публикации

Fin field effect transistor (finfet) device and method for forming the same

Номер: US20160111540A1
Автор: Chang-Yin Chen, Che-Cheng Chang, Tung-Wen CHENG, Yung-Jung Chang, Zhe-Hao Zhang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

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Номер записи: 191
21-04-2016 дата публикации

GATE LAST SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20160111541A1
Автор: Chang Che-Cheng, LIN Chih-Han, Lin Jr-Jung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure. 1. A semiconductor structure , comprising:a substrate;a metal gate structure formed over a fin structure of the substrate;a spacer formed on a sidewall of the metal gate structure; anda source/drain structure formed in the fin structure,wherein the source/drain structure has an extending portion extending into a recess of the spacer.2. (canceled)3. The semiconductor structure as claimed in claim 1 , wherein the spacer has a first width and the extending portion of the source/drain structure has a second width smaller than the first width.4. The semiconductor structure as claimed in claim 1 , wherein the spacer has a first width and the extending portion of the source/drain structure has a second width claim 1 , and a ratio of the first width to the second width is in a range from 1:1 to about 30:1.5. The semiconductor structure as claimed in claim 1 , wherein the spacer is made of silicon nitride claim 1 , silicon carbide claim 1 , silicon oxynitride claim 1 , silicon carbon claim 1 , silicon oxide claim 1 , silicon hydrogen claim 1 , or a combination thereof.6. The semiconductor structure as claimed in claim 1 , wherein the source/drain structure is a strained source/drain structure.7. The semiconductor structure as claimed in claim 1 , wherein the metal gate structure comprises a high-k dielectric layer claim 1 , a work function layer claim 1 , and metal gate electrode layer.8. A semiconductor structure claim 1 , comprising:a substrate;a gate structure formed over the substrate;a spacer formed on a sidewall of the gate structure;a source/drain ...

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Номер записи: 192
21-04-2016 дата публикации

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME

Номер: US20160111542A1
Автор: Chang Che-Cheng, Chang Yung-Jung, Chen Chang-Yin, CHENG Tung-Wen, ZHANG ZHE-HAO
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure. 1. A fin field effect transistor (FinFET) device structure , comprising:a substrate;a fin structure extending above the substrate;an epitaxial structure formed on the fin structure, wherein the epitaxial structure has a first height, and the epitaxial structure comprises a rhombus-like upper portion and a column-like lower portion;fin sidewall spacers formed adjacent to the epitaxial structure, wherein the sidewall spacers have a second height and the first height is greater than the second height, and wherein the rhombus-like upper portion is entirely above a top of the fin sidewall spacers.2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:a gate stack structure is formed over a central portion of the fin structure, wherein the epitaxial structure formed adjacent to the central portion of the fin structure.3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the second height is in a range from about 0.1 nm to about 100 nm.4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:an isolation structure, wherein the fin structure is embedded in the isolation structure.5. The fin field effect transistor (FinFET) device structure as claimed in claim 4 , wherein a bottom surface of the ...

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Номер записи: 193