Method of correcting overlay error

A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Input apparatus and method

An input apparatus and method for use in an information input unit. The information input unit is coupled to an information device having a display. The input apparatus includes an operational selection module, which is coupled to the information input unit, for generating a press signal in response to a pressing operation detected by the operational selection module and for generating a shift signal in response to a shifting operation detected by the operational selection module. A control chip of the information input unit activates the information device to display a graphical interface indicative of a set of options on the display when the information input unit receives the shift signal. Selection of the set of options on the graphical interface is made according to the press signal and the shift signal.

Global positioning system receiver and correlating circuit thereof

A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.

MRAM structure and method of fabricating the same

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

CURRENT SENSING DEVICE AND METHOD

Disclosures of the present invention describe a current sensing device and method, wherein the current sensing device comprises: at least one magnetic sensor, a signal receiving unit and a microprocessor. Particularly, the present invention provides an environmental magnetic field filtering unit and an effective current calculation unit in the microprocessor, such that the microprocessor is able to calculate the value of a current flowing in a specific electrical cable with high accuracy based on a sensing magnetic field outputted from the magnetic sensor.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

Shell and signal transmission apparatus using the shell

A signal transmission apparatus comprises a base and a shell, wherein a top portion of the base has a signal transmission device. The shell is covered above the base. A cavity is formed inside the shell. The cavity is in communication with an opening of a bottom portion of the shell. And the shell comprises a ceramic shell body and an inner covering layer. The inner covering layer is fully attached to an inner surface of the ceramic shell body. Therefore, the signals of the signal transmission device can pass through the shell so that the signal transmission device can receive or transmit signals. And through the strong adhesion of the inner covering layer, the ceramic shell body can be kept intact without being broken into a lot of debris when the ceramic shell body is impacted by external force or suddenly dropped.

Switch device capable of automatically detecting and adjusting zero cross point

Disclosures of the present invention describe a switch device has a controlling and processing unit comprising a first zero point detector, a second zero point detector, an arc detector, and a microcontroller. According to zero crossing point of input voltage signal, zero crossing point of output voltage signal, relay's delay time, and arc-spark-induced signal, the microcontroller is capable of adaptively generating a relay controlling signal to control the relay, such that the relay achieves a short-circuit switching at the zero cross point of output voltage signal for making the output voltage signal be transmitted to at least one load device. Moreover, the microcontroller is also able to control the relay to finish a short-circuit switching at the zero cross point of input voltage signal, so as to stop the output voltage signal from being transmitted to the load device.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

Global positioning system receiver and correlating circuit thereof

A global positioning system receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the products therefrom for generating the total summation value. Therefore, the correlating circuit having portable process is formed. Moreover, an external memory is used to store the sample digital data for reducing costs.

Semiconductor process

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Correlator for spread spectrum receiver

The present invention discloses correlation architecture in the application of full-digital GPS (Global Positioning System) receivers. According to the present invention, a satellite C/A code generator is employed to generate N-bit parallel code data at a time, and a Doppler frequency generator is used to generate N-bit parallel Doppler frequency data at a time. Signals received by the receiver can be temporarily stored in a buffer that provides N-bit parallel reception data to a correlation circuit. In the correlation circuit, a N-bit multiplier is used to multiply the N-bit reception data by the N-bit C/A code data and the N-bit Doppler frequency data to generate multiplication results. The N-bit multiplication results are thereafter summed up in parallel by a digital summator. Accordingly, the correlator of the present invention can improve circuit performance and save the required cost.

MEASUREMENT MARK STRUCTURE AND MANUFACTURING METHOD THEREOF

The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped. 1. A measurement mark structure comprising:a plurality of inner patterns, the inner patterns being arranged along a first direction; andan outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.2. The measurement mark structure according to claim 1 , wherein the outer pattern does not contact each inner pattern directly.3. The measurement mark structure according to claim 1 , wherein each inner pattern is rectangular frame shaped claim 1 , and has two long edges and two short edges.4. The measurement mark structure according to claim 3 , wherein each long edge of each inner pattern is parallel to a second direction claim 3 , wherein the second direction and the first direction are perpendicular to each other.5. The measurement mark structure according to further comprising:a plurality of second inner patterns, and the second inner patterns being arranged along the second direction; anda second outer pattern, positioned surrounding the second inner patterns, and the second outer pattern is rectangular frame shaped.6. The measurement mark structure according to claim 5 , wherein the second outer pattern does not contact each second inner pattern directly.7. The measurement mark structure according to claim 1 , wherein each outer pattern has two long edges and two short edges.8. The measurement mark structure according to claim 7 , wherein each long edge of each outer pattern is parallel to the first direction.9. The measurement mark structure according to claim 1 , further comprising a substrate claim 1 , the inner patterns and the outer pattern being disposed on the substrate.10. A method for forming a measurement mark structure claim 1 , at ...

Power protection

A circuit for power protection comprising a power supply switching unit for switching a power supply off according to a switching-off signal, a surge voltage protective unit for outputting the switching-off signal while a surge voltage is occurred, a leakage current protective unit for outputting the switching-off signal while a leakage current is occurred, an overload current protective unit for outputting the switching-off signal while an overload current is occurred, an over/under voltage protective unit for outputting the switching-off signal while an over/under voltage is occurred, and a temperature protective unit for outputting the switching-off signal while an over-temperature is occurred. The present invention has the effects of the surge voltage protection, the leakage current protection, the overload current protection, the over/under voltage protection, and the over-temperature protection at the same time, and, in comparison with a conventional circuit for power protection, ...

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Semiconductor process and semiconductor device

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Apparatus for controlling rotational speed of motor

An apparatus for controlling a rotational speed of a motor, coupled to a sensing unit capable of outputting a sensing signal. The apparatus comprises a controlling unit, coupled to the sensing unit, for outputting a controlling signal according to the sensing signal, wherein the controlling signal is a square wave and has a duty ratio that is determined by the sensing signal; and a driving unit, coupled to the controlling unit, for outputting a driving signal to a motor rotor according to the duty ratio of the controlling signal, wherein the driving signal is a square wave, and the rotational speed of the motor rotor is determined by the duty ratio of the driving signal.

Semiconductor memory device

The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

PATTERNING METHOD AND OVERLAY MESUREMENT METHOD

The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Floor types identifying device, dust suction device having the same, and vacuum cleaner having the same

A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.

Method for cleaning contact hole and forming contact plug therein

The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.

METHOD OF CORRECTING OVERLAY ERROR

A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Power supply with duty cycle limiting circuit, duty cycle limiting circuit, and method of operating the same

A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

Power source protecting device

A power source protecting device comprises a power source switching unit for shutting off the power supply from an AC power source according to an open control signal, a surge voltage protecting unit for outputting the open control signal when a surge voltage occurs, a leakage current protecting unit for outputting the open control signal when a leakage current occurs, and an over-current protecting unit for outputting the open control signal according to a current value when an over-current occurs. The present invention can provides the surge voltage protection, the leakage current protection and the over current protection at the same time. In comparison with the conventional power source protecting device, the invention can provide a more compact and low cost device, and is able to provide an accurate and safe protection according to the current detection based on an energy.

MRAM structure and method of fabricating the same

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Global positioning system receiver and correlating circuit thereof

A global positioning system receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the products therefrom for generating the total summation value. Therefore, the correlating circuit having portable process is formed. Moreover, an external memory is used to store the sample digital data for reducing costs.

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Semiconductor structure and method for forming the same

A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

Current sensing device and method

Disclosures of the present invention describe a current sensing device and method, wherein the current sensing device comprises: at least one magnetic sensor, a signal receiving unit and a microprocessor. Particularly, the present invention provides an environmental magnetic field filtering unit and an effective current calculation unit in the microprocessor, such that the microprocessor is able to calculate the value of a current flowing in a specific electrical cable with high accuracy based on a sensing magnetic field outputted from the magnetic sensor.

Motor drive circuit and method with frequency setting and correcting functions

A motor drive circuit and method with frequency setting and correcting functions. The drive circuit includes a speed control device, which simultaneously receives a sense signal and a rotation frequency signal. A pulse width modulation signal capable of modulating a duty ratio may be generated by a pulse width modulation method. The pulse width modulation signal is then transferred to a drive timing controller that generates a timing control signal to control output timing of a power drive signal for the drive circuit. Meanwhile, a sensor is used to detect a motor and to generate a correction sense signal, which is immediately fed back to the speed control device to form a closed loop control, so that the rotation frequency of the motor may be automatically corrected and set.

Global positioning system receiver and correlating circuit thereof

A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.

Overlap mark set and method for selecting recipe of measuring overlap error

An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

METHOD FOR DRIVING A BRUSHLESS DC MOTOR

A method for driving a brushless DC motor is disclosed in accordance with the present invention. Firstly, a driving control signal is generated based on sensed information of a motor rotor's magnetic field distribution. The driving control signal is inactive in the case that four rotor magnetic arcs are rotated more or less than critical positions of the rotor corresponding a stator. At that time, no magnetic fields are produced from the motor's stator, and thus the rotor rotates by inertial force. In another case, the driving control signal is issued in a conventional manner.

Semiconductor structure and method for forming the same

A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

System for controlling rotational speed of fan according to reference clock frequency

A system for controlling the rotational speed of a fan, according to a reference clock having a reference frequency, is disclosed. The rotational speed corresponds to a fan rotational speed signal. The fan rotational speed controlling unit compares the reference clock with the fan rotational speed signal, to output a speed controlling signal. The Voltage generating circuit generates a level signal corresponding to the speed controlling signal. The driving unit generates a driving signal to control the rotational speed of the fan according to the level signal. When the fan is assembled with the controlling system, only coils with the same number of turns need to be use to obtain various rated rotational speeds of fans of different specifications by altering the reference frequency of the controlling system. Because coils with different number of turns are not required in stock at the same time, the time cost and the manufacturing cost can be reduced.

SPARK DETECTION DEVICE CAPABLE OF DETECTING CHARACTERISTICS OF A SPARK SIGNAL

A spark detection device includes a sensing element and a comparing element. The sensing element is for sensing a spark signal to generate a sensing signal. A first end of the comparing element is coupled to the sensing element, and a second end of the comparing element is for receiving a threshold signal. The comparing element is for generating an output signal at an output end of the comparing element by performing a comparing operation according to the sensing signal and the threshold signal. 1. A spark detection device capable of detecting characteristics of a spark signal , comprising:a sensing element for sensing a spark signal to generate a sensing signal; anda comparing element, a first end of the comparing element being coupled to the sensing element, a second end of the comparing element being for receiving a threshold signal, the comparing element being for generating an output signal at an output end of the comparing element by performing a comparing operation according to the sensing signal and the threshold signal.2. The spark detection device of further comprising a signal adjusting element coupled to the output end of the comparing element claim 1 , for detecting or adjusting pulse width of the output signal.3. The spark detection device of claim 1 , wherein the comparing element comprises a comparator for comparing the sensing signal with the threshold signal to generate the output signal when the sensing signal is greater than the threshold signal.4. The spark detection device of claim 1 , wherein the comparing element comprises:an integrator circuit for performing an integration operation to the sensing signal to generate a corresponding energy level signal; anda comparator coupled to the integrator circuit for comparing the energy level signal with the threshold signal to generate the output signal when the energy level signal is greater than the threshold signal.5. The spark detection device of claim 1 , wherein the sensing element comprises:a ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench. 1. A semiconductor structure , comprising:a substrate having a device region and an alignment mark region;a dielectric layer disposed on the substrate;a conductive via formed in the dielectric layer on the device region;a first trench formed in the dielectric layer on the alignment mark region;a plurality of second trenches formed in the dielectric layer under the first trench and exposed from a bottom surface of the first trench; anda memory stack structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the plurality of second trenches.2. The semiconductor structure according to claim 1 , wherein the memory stack structure comprises a magnetoresistive random access memory (MRAM) structure claim 1 , comprising:a bottom electrode layer;a magnetic tunneling junction (MTJ) layer;a cap layer; anda top electrode layer.3. The semiconductor structure according to claim 1 , wherein the second trenches form an alignment mark feature claim 1 , wherein the memory stack structure is patterned by a patterning process aligned to the alignment mark feature.4. The semiconductor structure according to claim 1 , wherein the dielectric layer is not penetrated by the first trench and the second trenches.5. The semiconductor structure according to claim 1 , ...

NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Power saving device capable of automatically sensing standby current

The invention discloses a power saving device capable of automatically sensing standby current, which is used in a power device such as a power outlet or other power supply devices for giving the power device ability of electricity saving. When the power saving device normally works, a threshold current setting unit of a controlling and processing module is configured to automatically calculate a threshold current based on current signals sensed by a current detecting unit under different operation modes of at least one electrical device electrically connected to the power device. Moreover, when at least one standby current sensed from the electrical device is determined to be lower than the threshold current, the controlling and processing module immediately switches a switch unit to an open-circuit state, thereby causing the electrical device unable to receive electricity from the power device. Consequently, the power device exhibits the ability of power saving.

Semiconductor structure and method for forming the same

A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

Salicide process

A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.

Motor monitoring system

A motor monitoring system including a control chip and a motor is disclosed. The control chip could be a chipset or a monitoring chip able to control the rotational speed of the motor. The control chip is used to receive a temperature reading and output a control signal according to the temperature reading. The motor receives the control signal and automatically adjusts the speed of its own accordingly. Hence, the configuration of the monitoring system is simplified, the R&D flow is shortened, and the cost of R&D and manufacturing are greatly reduced.

Semiconductor device

A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

SALICIDE PROCESS

A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a dielectric layer, a stop layer, a via and a memory device. The dielectric layer is located on a substrate. The stop layer is located on the dielectric layer. The via extends in the stop layer and the dielectric layer. The memory device is disposed on the via and electrically connected to the via.

Voltage independent PWM base frequency generating method

A DC brushless motor operation speed control method is disclosed. First, a linearly voltage dependent current source is used to charge a capacitor and the terminal voltage of the capacitor is coupled to a linearly voltage dependent base frequency level detector. When the output voltage of the capacitor reaches the base frequency reference voltage, the signal output from the base frequency level detector will make the capacitor discharge, outputting a series of base frequency triangular waves. Under different supply voltages, all the generated base frequency triangular waves have the same cycle time. The base frequency triangular waves are transmitted to a speed control comparator. Through pulse width modulation, the speed control reference voltage adjusts the output pulse width of the comparator and thereby controls the speed of the motor.

Voltage independent PWM base frequency generating method

A DC brushless motor operation speed control method is disclosed. First, a linearly voltage dependent current source is used to charge a capacitor and the terminal voltage of the capacitor is coupled to a linearly voltage dependent base frequency level detector. When the output voltage of the capacitor reaches the base frequency reference voltage, the signal output from the base frequency level detector will make the capacitor discharge, outputting a series of base frequency triangular waves. Under different supply voltages, all the generated base frequency triangular waves have the same cycle time. The base frequency triangular waves are transmitted to a speed control comparator. Through pulse width modulation, the speed control reference voltage adjusts the output pulse width of the comparator and thereby controls the speed of the motor.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

SEMICONDUCTOR DEVICE INCLUDING MAGNETIC TUNNEL JUNCTION STRUCTURE

A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.

MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

SEMICONDUCTOR PROCESS

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Security certificate management method for a vehicular network node and vehicular network node applying the same

A security certificate management method for a vehicular network node is applied in a vehicular network. A message is received. Whether a certificate in the message is revoked is determined. If the certificate in the message is revoked, a regional certificate revocation list (RCRL) is generated or updated based on the revoked certificate by the vehicular network node, and the RCRL is transmitted into a communication range of the vehicular network node.

SYSTEM FOR ACTIVELY DETECTING ALTERNATING CURRENT LOAD

A system for actively detecting an alternating current (AC) load includes a first power interface, a second power interface, a switch unit, and a control unit. The first power interface is coupled to an AC source to receive and provide an AC voltage. The second power interface is configured to be coupled to an electronic equipment to provide the AC source to the electronic equipment and provide a connection signal according to whether the electronic equipment is coupled to the second power interface. The switch unit is coupled between the first power interface and the second power interface and receives a switch signal to determine whether the AC voltage is transmitted to the second power interface. The control unit is coupled to the second power interface and the switch unit to provide the switch signal according to the connection signal. 1. A system for actively detecting an alternating current load , the system comprising:a first power interface coupled to an alternating current source to receive and provide an alternating current voltage;a second power interface configured to be coupled to an electronic equipment to provide the alternating current source to the electronic equipment and provide a connection signal according to whether the electronic equipment is coupled to the second power interface;a switch unit coupled between the first power interface and the second power interface, the switch unit receiving a switch signal to determine whether the alternating current voltage is transmitted to the second power interface; anda control unit coupled to the second power interface and the switch unit to provide the switch signal according to the connection signal.2. The system as recited in claim 1 , wherein when the electronic equipment is not coupled to the second power interface claim 1 , the control unit sets the switch signal according to the connection signal to switch off the switch unit.3. The system as recited in claim 1 , wherein when the electronic ...

OVERLAP MARK SET AND METHOD FOR SELECTING RECIPE OF MEASURING OVERLAP ERROR

An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b therebetween. The preset offsets a and b are not equal. 1. An overlap mark set , comprising at least one first overlap mark and a second overlap mark disposed in the same pattern layer , wherein: [{'b': '1', 'at least two sets of X-directional linear patterns having a preset offset a therebetween; and'}, {'b': '1', 'at least two sets of Y-directional linear patterns having the preset offset a therebetween; and'}], 'the first overlap mark comprises [{'b': '1', 'at least two sets of X-directional linear patterns having a preset offset b therebetween; and'}, {'b': '1', 'at least two sets of Y-directional linear patterns having the preset offset b therebetween,'}], 'the second overlap mark comprises{'b': 1', '1, 'wherein the preset offset a is not equal to the preset offset b.'}2. The overlap mark set as claimed in claim 1 , wherein the same pattern layer is a pre-layer.3. The overlap mark set as claimed in claim 1 , wherein the same pattern layer is a current layer.411. The overlap mark set as claimed in claim 1 , wherein one of the preset offset a and the preset offset b is zero.511111. The overlap mark set as claimed in claim 1 , further comprising a third overlap mark disposed in the same pattern layer claim 1 , wherein the third overlap mark comprises two sets of X-directional linear patterns having a preset offset c therebetween and two sets of Y-directional linear patterns having the preset offset c ...

Non-contact intelligent battery sensing system and method

In view of drivers cannot equip their vehicles with conventional intelligent battery monitoring system by themselves because the wire connections of the intelligent battery monitoring system are complex, the present invention particularly discloses a non-contact intelligent battery sensing system showing the advantages of simple circuit framework and low manufacturing cost. Since the non-contact intelligent battery sensing system only comprises a magnetic field sensor and a sensor controlling module, it is very easy for the drivers to equip their vehicles with this non-contact intelligent battery sensing system by themselves. To apply the non-contact intelligent battery sensing system, the driver just needs to firstly dispose the magnetic field sensor at one position near to a power line of a battery to be sensed, and then install a sensor controlling application program in his smart phones. Apparently, the non-contact intelligent battery sensing system further shows the advantage of easy ...

MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Electrical energy transferring device showing power consumption/charging status

An electrical energy transferring device coupled to an electrical energy receiving device is provided. The electrical energy transferring device includes an electrical source measuring unit and a power indicating unit. The electrical source measuring unit detects a power consumption and/or a charging status of the electrical energy receiving device. The power indicating unit is coupled to the electrical source measuring unit for showing the power consumption and/or the charging status of the electrical energy receiving device by a color signal and/or an audio signal.

Semiconductor device including magnetic tunnel junction structure

A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (PO-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component. 1. A method for fabricating a semiconductor device , the method comprising steps of:providing a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer; andin situ removing the nitride layer and the platinum (Pt) with a chemical solution including a sulfuric acid component and a phosphoric acid component.2. The method according to claim 1 , wherein a ratio of the sulfuric acid component to the phosphoric acid component is in a range of 1:1 to 10:1.3. The method according to claim 1 , wherein a ratio of the sulfuric acid component to the phosphoric acid component is in a range of 3:1 to 4:1.4. The method according to claim 1 , wherein the chemical solution further includes a hydrogen peroxide component.5. The method according to claim 4 , wherein a ratio of the sulfuric acid component to the hydrogen peroxide component is 7:1.6. The method according to claim 4 , wherein removing rate of the nitride layer with the chemical solution is at 220 angstroms per minute.7. The method according to claim 1 , wherein the step of providing the substrate having the nitride layer and the Pt-containing Ni-semiconductor compound layer comprises:forming the nitride layer as being a patterned hard mask to expose a source/drain region on the substrate; andforming the Pt-containing Ni-semiconductor compound layer on the source/drain region.8. The method according to claim 7 , further comprising a step of:removing a first gate hard mask over a first gate structure as being adjacent to the source/drain region so that the Pt-containing Ni-semiconductor compound layer is ...

Method for driving a brushless DC motor

A method for driving a brushless DC motor is disclosed in accordance with the present invention. Firstly, a driving control signal is generated based on sensed information of a motor rotor's magnetic field distribution. The driving control signal is inactive in the case that four rotor magnetic arcs are rotated more or less than critical positions of the rotor corresponding a stator. At that time, no magnetic fields are produced from the motor's stator, and thus the rotor rotates by inertial force. In another case, the driving control signal is issued in a conventional manner.

METHOD OF FORMING CONTACT STRUCUTRE

A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

SEMICONDUCTOR MEMORY DEVICE

The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer. 1. A semiconductor memory device , comprising:a substrate having thereon a memory cell region and an alignment mark region;a dielectric layer on the substrate, the dielectric layer covering the memory cell region and the alignment mark region;a plurality of conductive vias in the dielectric layer within the memory cell region;an alignment mark trench in the dielectric layer within the alignment mark region;a plurality of storage structures disposed on the plurality of conductive vias, respectively, wherein each of the plurality of storage structures comprises a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode defined from a top electrode metal layer; anda residual metal stack in the alignment mark trench, wherein the residual metal stack comprises a portion of the bottom electrode metal layer and a portion of the MTJ layer.2. The semiconductor memory device according to claim 1 , wherein the bottom electrode is in direct contact with each of the plurality of conductive vias.3. The semiconductor memory device according to claim 1 , wherein the alignment mark trench is not ...

SECURITY CERTIFICATE MANAGEMENT METHOD FOR A VEHICULAR NETWORK NODE AND VEHICULAR NETWORK NODE APPLYING THE SAME

A security certificate management method for a vehicular network node is applied in a vehicular network. A message is received. Whether a certificate in the message is revoked is determined. If the certificate in the message is revoked, a regional certificate revocation list (RCRL) is generated or updated based on the revoked certificate by the vehicular network node, and the RCRL is transmitted into a communication range of the vehicular network node.

Motor drive circuit and method with frequency setting and correcting functions

A motor drive circuit and method with frequency setting and correcting functions. The drive circuit includes a speed control device, which simultaneously receives a sense signal and a rotation frequency signal. A pulse width modulation signal capable of modulating a duty ratio may be generated by a pulse width modulation method. The pulse width modulation signal is then transferred to a drive timing controller that generates a timing control signal to control output timing of a power drive signal for the drive circuit. Meanwhile, a sensor is used to detect a motor and to generate a correction sense signal, which is immediately fed back to the speed control device to form a closed loop control, so that the rotation frequency of the motor may be automatically corrected and set.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench. 1. A semiconductor structure , comprising:a substrate having a device region and an alignment mark region;a dielectric layer disposed on the substrate;a conductive via formed in the dielectric layer on the device region;a first trench formed in the dielectric layer on the alignment mark region;a plurality of second trenches formed in the dielectric layer under the first trench and exposed from a bottom surface of the first trench; anda memory stack structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trenches.2. The semiconductor structure according to claim 1 ,wherein the memory stack structure comprises a magnetoresistive random access memory (MRAM) structure comprising:a bottom electrode layer;a magnetic tunneling junction (MTJ) layer;a cap layer; anda top electrode layer.3. The semiconductor structure according to claim 1 , wherein the second trenches form an alignment mark feature claim 1 , wherein the memory stack structure is patterned by a patterning process aligned to the alignment mark feature.4. The semiconductor structure according to claim 1 , wherein the dielectric layer is not penetrated by the first trench and the second trenches.5. The semiconductor structure according to claim 1 , wherein the bottom ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the t op electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ). 1. A method for fabricating semiconductor device , comprising:forming an inter-metal dielectric (IMD) layer on a substrate;forming a metal interconnection in the IMD layer;forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration;forming a free layer on the bottom electrode layer;forming a top electrode layer on the free layer; andpatterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).2. The method of claim 1 , further comprising:forming a patterned mask on the bottom electrode layer;removing part of the bottom electrode layer and part of the IMD layer to form a trench;forming the free layer on the bottom electrode layer and into the trench;forming the top electrode layer on the free layer; andpatterning the top electrode layer, the free layer, and the bottom electrode layer to form the MTJ and an alignment mark adjacent to the MTJ.3. The method of claim 1 , further comprising:forming a pinned layer on the bottom electrode layer; andforming a barrier layer on the pinned layer before forming the free layer.4. The method of claim 1 , wherein the bottom electrode layer comprises tantalum nitride (TaN).5. The method of claim 4 , wherein a concentration of nitrogen increases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.6. The method of claim 4 , wherein a ...

SWITCH DEVICE CAPABLE OF AUTOMATICALLY DETECTING AND ADJUSTING ZERO CROSS POINT

Disclosures of the present invention describe a switch device has a controlling and processing unit comprising a first zero point detector, a second zero point detector, an arc detector, and a microcontroller. According to zero crossing point of input voltage signal, zero crossing point of output voltage signal, relay's delay time, and arc-spark-induced signal, the microcontroller is capable of adaptively generating a relay controlling signal to control the relay, such that the relay achieves a short-circuit switching at the zero cross point of output voltage signal for making the output voltage signal be transmitted to at least one load device. Moreover, the microcontroller is also able to control the relay to finish a short-circuit switching at the zero cross point of input voltage signal, so as to stop the output voltage signal from being transmitted to the load device. 1. A switch device capable of automatically detecting and adjusting zero crossing point , comprising:an input voltage detecting unit, being coupled to an AC power source for detecting an input voltage signal supplied by the AC power source;an output voltage detecting unit, being electrically connected to a load connecting terminal of a relay, so as to detect an output voltage signal from the load connecting terminal; wherein an input terminal of the relay is coupled to the AC power source; and a first detector, being configured for detecting a zero crossing point of the input voltage signal;', 'a second detector, being configured for detecting a zero crossing point of the output voltage signal;', 'an arc detector, being configured for detecting an arc-spark-induced signal from the output voltage signal; and', 'a microcontroller, being coupled to the first detector, the second detector and the arc detector;, 'a controlling and processing unit, being electrically connected to the input voltage detecting unit, the output voltage detecting unit, and the relay, and comprisingwherein the microcontroller ...

Semiconductor memory device and fabrication method thereof

A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Global positioning system receiver and correlating circuit thereof

A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.

Apparatus for controlling rotational speed of motor

An apparatus for controlling a rotational speed of a motor, coupled to a sensing unit capable of outputting a sensing signal. The apparatus includes a controlling unit, coupled to the sensing unit, for outputting a controlling signal according to the sensing signal and independently of the rotational speed of the motor. The controlling signal is a square wave and has a duty ratio that is determined by the sensing signal. The apparatus also includes a driving unit, coupled to the controlling unit, for outputting a driving signal to a motor rotor according to the duty ratio of the controlling signal. The driving signal also is a square wave. The rotational speed of the motor rotor is determined by the duty ratio of the driving signal.

SEMICONDUCTOR PROCESS AND SEMICONDUCTOR DEVICE

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer. 1. A semiconductor process , comprising:forming a silicon-phosphorus (SiP) epitaxial layer serving as a source/drain region;forming, directly on the SiP epitaxial layer, a crystalline metal silicide layer that prevents oxidation of the SiP epitaxial layer; andforming a contact plug over the crystalline metal silicide layer.2. The semiconductor process of claim 1 , wherein forming the crystalline metal silicide layer comprises:forming a metal layer in contact with the SiP epitaxial layer;performing a first metal silicidation reaction by heating; andremoving the remaining metal layer.3. The semiconductor process of claim 2 , wherein the metal layer comprises Ti/TiN claim 2 , cobalt claim 2 , or nickel.4. The semiconductor process of claim 3 , wherein the metal layer comprises Ti/TiN claim 3 , and the crystalline metal silicide layer comprises CM TiSi.5. The semiconductor process of claim 2 , wherein the first metal silicidation reaction is conducted at a temperature between 700° C. and 800° C.6. The semiconductor process of claim 1 , wherein forming the contact plug comprises:forming a contact hole over the crystalline metal silicide layer;forming a barrier metal layer in the contact hole;performing a second metal silicidation reaction between the barrier metal layer and the SiP epitaxial layer by heating to form an amorphous metal silicide layer on the crystalline metal silicide layer; andfilling the contact hole with a metal material.7. The semiconductor process of claim 6 , wherein the barrier metal layer comprises Ti/TiN claim 6 , Ni/Co/TiN claim 6 , Ti/WN claim 6 , or Ni/Co/WN.8. The semiconductor process of claim 7 , wherein the ...

Non-volatile memory device and manufacturing method thereof

Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

System for controlling rotational speed of fan

A system for controlling the rotational speed of a fan, according to a reference clock having a reference frequency, is disclosed. The rotational speed corresponds to a fan rotational speed signal. The fan rotational speed controlling unit compares the reference clock with the fan rotational speed signal, to output a speed controlling signal. The voltage generating circuit generates a level signal corresponding to the speed controlling signal. The driving unit generates a driving signal to control the rotational speed of the fan according to the level signal. When the fan is assembled with the controlling system, only coils with the same turns need to be use to obtain various rated rotational speeds of fans of different specifications by altering the reference frequency of the controlling system. Because coils with different turns are not required in stock at the same time, the time cost and the manufacturing cost can be reduced.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

DC uninterruptible power supply apparatus with bidirectional protection function

A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

Semiconductor device including magnetic tunnel junction structure

A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.

Battery internal resistance measuring device having a differential value calculating unit to treat two adjacent first voltage sampling values with first slope value calculation

The present invention discloses a battery internal resistance measuring device and a method thereof, wherein the battery internal resistance measuring device comprises a voltage detecting unit, at least one measurement resistor, at least one switch, and a measurement controller. By means of further explanation, the measurement controller at least comprises a differential value calculating unit for treating a differential value calculation or a slope calculation to each two of adjacent voltage sampling values on a waveform of a discharge voltage signal of the battery, such that the measurement controller can subsequently find out a discharge starting point and a discharge ending point according to data of the differential value calculations or the slope calculations. Eventually, the measurement controller calculates an internal resistance of the battery after picking up an open-circuit voltage and a short-circuit voltage from the discharge starting point and the discharge ending point.

Correlator for spread spectrum receiver

The present invention discloses correlation architecture in the application of full-digital GPS (Global Positioning System) receivers. According to the present invention, a satellite C/A code generator is employed to generate N-bit parallel code data at a time, and a Doppler frequency generator is used to generate N-bit parallel Doppler frequency data at a time. Signals received by the receiver can be temporarily stored in a buffer that provides N-bit parallel reception data to a correlation circuit. In the correlation circuit, a N-bit multiplier is used to multiply the N-bit reception data by the N-bit C/A code data and the N-bit Doppler frequency data to generate multiplication results. The N-bit multiplication results are thereafter summed up in parallel by a digital summator. Accordingly, the correlator of the present invention can improve circuit performance and save the required cost.

Semiconductor memory device and fabrication method thereof

The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ). 1. A method for fabricating semiconductor device , comprising:forming an inter-metal dielectric (IMD) layer on a substrate;forming a metal interconnection in the IMD layer;forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration;forming a free layer on the bottom electrode layer;forming a top electrode layer on the free layer; andpatterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).2. The method of claim 1 , further comprising:forming a patterned mask on the bottom electrode layer;removing part of the bottom electrode layer and part of the IMD layer to form a trench;forming the free layer on the bottom electrode layer and into the trench;forming the top electrode layer on the free layer; andpatterning the top electrode layer, the free layer, and the bottom electrode layer to form the MTJ and an alignment mark adjacent to the MTJ.3. The method of claim 1 , further comprising:forming a pinned layer on the bottom electrode layer; andforming a barrier layer on the pinned layer before forming the free layer.4. The method of claim 1 , wherein the bottom electrode layer comprises tantalum nitride (TaN).5. The method of claim 4 , wherein a concentration of nitrogen increases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.6. The method of claim 4 , wherein a ...

DATA TRANSMISSION METHOD

A data transmission method, applied to a data transmission device connected to a first host and a second host, comprising: (a) activating a console of the first host via a trigger operation and acquiring a source path of target data in the first host; (b) acquiring the target data from the source path and copying the target data to a storage circuit inside or outside the data transmission device; and (c) copying the target data from the storage circuit to the second host.

Power protection device

A power protection device includes a power source switching unit for shutting off the power supply from an AC power source according to an open control signal, a surge voltage protecting unit for outputting the open control signal when a surge voltage occurs, a leakage current protecting unit for outputting the open control signal when a leakage current occurs, and an over-current protecting unit for outputting an open control signal according to a current value when an over-current occurs. The power protection device provides the surge voltage protection, the leakage current protection and the over current protection at the same time.

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

SEMICONDUCTOR DEVICE

A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection. 1. A semiconductor device , comprising:a substrate;a first magnetic tunnel junction (MTJ) structure disposed on the substrate;a second MTJ structure disposed on the substrate; and a first metal interconnection; and', 'a second metal interconnection disposed on and contacting the first metal interconnection, wherein a material composition of the second metal interconnection is different from a material composition of the first metal interconnection., 'an interconnection structure disposed on the substrate and located between the first MTJ structure and the second MTJ structure in a first horizontal direction, wherein the interconnection structure comprises2. The semiconductor device according to claim 1 , further comprising:a third metal interconnection disposed on and contacting the first MTJ structure; anda fourth metal interconnection disposed on and contacting the second MTJ structure, wherein the material composition of the second metal interconnection, a material composition of the third metal interconnection, and a material composition of the fourth metal interconnection are identical to one another.3. The semiconductor device according to claim 2 , wherein the second metal interconnection is elongated in the first horizontal ...

NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Mosquito Trap

A mosquito trap includes: a container defining an inner space therein and having a top opening in fluid communication with the inner space and adapted for entrance of mosquito therethrough and into the inner space; a perforated plate mounted in the container, dividing the inner space into first and second chambers, and formed with a plurality of apertures in fluid communication with the first and second chambers; and a carbon dioxide generating attractant disposed in the second chamber of the container.

SEMICONDUCTOR DEVICE

A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

Input power control device

An input power control device for controlling the electrical power fed into the driven device from the power supply is provided. The power control device includes a driving device, a voltage detector, a current detector, a multiplier, and a power controller. The voltage detector detects the output voltage of the power supply, while the current detector detects the drive current fed into the driven device from the driving device. The multiplier multiplies the voltage signal and the current signal together to obtain the present electrical power input to the driven device. If the present input power of the driven device is too high, the power controller outputs an adjustment signal to the driving device to decrease the drive current of the driven device until the input power is equal to the rated value.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. 1. A semiconductor device , comprising:a substrate;a first magnetic tunnel junction (MTJ) structure disposed on the substrate;a second MTJ structure disposed on the substrate; and a first metal interconnection; and', 'a second metal interconnection disposed on and contacting the first metal interconnection., 'an interconnection structure disposed on the substrate and located between the first MTJ structure and the second MTJ structure in a first horizontal direction, wherein the interconnection structure comprises2. The semiconductor device according to claim 1 , further comprising:a third metal interconnection disposed on and contacting the first MTJ structure; anda fourth metal interconnection disposed on and contacting the second MTJ structure.3. The semiconductor device according to claim 2 , wherein the material composition of the second metal interconnection claim 2 , a material composition of the third metal interconnection claim 2 , and a material composition of the fourth metal interconnection are identical to one another.4. The semiconductor device according to claim 2 , wherein the second metal interconnection is elongated in the first horizontal direction claim 2 , and the third metal interconnection and the fourth metal interconnection are elongated in a second horizontal direction claim 2 , respectively.5. The semiconductor device according to claim 4 , ...

DEVICE AND METHOD FOR ACHIEVING DYNAMIC CHARGING AND BALANCE OF BATTERY CELLS AND RECHARGEABLE BATTERY DEVICE

A device for achieving dynamic charging and balance of battery cells is disclosed. The device is configured for monitoring a plurality of battery voltages from a plurality of battery cells in a multi-cell battery pack. In case of a battery voltage difference between two of the battery cells being greater than a pre-determined voltage difference, the device generates a plurality of balance charging currents for charging the battery cells. In which, each of the balance charging currents is calculated based on remaining charge time, measured battery voltage, and rated battery capacity. Thus, in a charge cycle, one balance charging current for charging the battery cell with low battery voltage is designed to be greater than another one balance charging current for charging the battery cell with high battery voltage. Consequently, elimination of the battery voltage difference existing between any two of the battery cells is achieved.

Semiconductor structure and method for manufacturing the same

A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

METHOD FOR FABRICATING MOS TRANSISTOR

A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process. 1. A method for fabricating metal-oxide semiconductor (MOS) transistor , comprising:providing a semiconductor substrate having a silicide thereon;performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; andremoving un-reacted platinum in the first rapid thermal process.2. The method of claim 1 , wherein the semiconductor substrate comprises a source/drain region thereon claim 1 , the silicide being formed on the source/drain region claim 1 , comprising:forming a Ni—Pt layer on the surface of the source/drain region;forming a barrier layer on the Ni-Pt layer; andperforming a second rapid thermal process to transform part of the source/drain region into the silicide.3. The method of claim 2 , wherein the temperature of the first rapid thermal process and the second thermal process is between 240° C. to 290° C.4. The method of claim 2 , wherein the duration of the first rapid thermal process and the second rapid thermal process is between 30 seconds to 120 seconds.5. The method of claim 1 , further comprising performing a third rapid thermal process after removing un-reacted platinum for reducing resistance of the silicide.6. The method of claim 5 , wherein the temperature of the third rapid thermal process is higher than 300° C.7. The method of claim 1 , wherein the barrier layer comprises TiN.8. The method of claim 2 , further comprising:using a sulfuric acid-hydrogen peroxide mixture (SPM) for removing un-reacted nickel and the barrier layer from the second rapid thermal process; andusing a hydrochloric acid-hydrogen peroxide mixture (HPM) for removing un- ...

METHOD FOR FABRICATING MOS TRANSISTOR

A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process. 1. A method for fabricating metal-oxide semiconductor (MOS) transistor , comprising:providing a semiconductor substrate having a silicide thereon;performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; andremoving un-reacted platinum in the first rapid thermal process.2. The method of claim 1 , wherein the semiconductor substrate comprises a source/drain region thereon claim 1 , the silicide being formed on the source/drain region claim 1 , comprising:forming a Ni—Pt layer on the surface of the source/drain region;forming a barrier layer on the Ni—Pt layer; andperforming a second rapid thermal process to transform part of the source/drain region into the silicide.3. The method of claim 2 , wherein the temperature of the first rapid thermal process and the second thermal process is between 240° C. to 290° C.4. The method of claim 2 , wherein the duration of the first rapid thermal process and the second rapid thermal process is between 30 seconds to 120 seconds.5. The method of claim 1 , further comprising performing a third rapid thermal process after removing un-reacted platinum for reducing resistance of the silicide.6. The method of claim 5 , wherein the temperature of the third rapid thermal process is higher than 300° C.7. The method of claim 1 , wherein the barrier layer comprises TiN.8. The method of claim 2 , further comprising:using a sulfuric acid-hydrogen peroxide mixture (SPM) for removing un-reacted nickel and the barrier layer from the second rapid thermal process; andusing a hydrochloric acid-hydrogen peroxide mixture (HPM) for removing un- ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. 1. A manufacturing method of a semiconductor device , comprising:providing a substrate, with at least one fin structure on the substrate;depositing a metal layer on the fin structure to form a silicide layer;removing the metal layer, wherein no RTP (Rapid Thermal Process) is performed before the metal layer is removed, and;performing a RTP after the metal layer is removed.2. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a STI surrounding the fin structure.3. The manufacturing method of a semiconductor device of claim 1 , further comprising forming an epitaxy layer on the fin structure before depositing the metal layer.4. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a gate on parts of the fin structure.5. The manufacturing method of a semiconductor device of claim 4 , wherein the gate comprises a polysilicon gate or a metal gate.6. The manufacturing method of a semiconductor device of claim 1 , wherein the temperature of the RTP is between 400° C. and 600° C. .7. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a plurality of contacts on the silicide layer.8. The manufacturing method of a semiconductor device of claim 1 , wherein the contacts comprise slot contacts or pole contacts.9. A manufacturing method of a semiconductor device claim 1 , comprising:providing a substrate, with at least one fin structure on the substrate;depositing a metal layer on the fin structure to form a silicide layer;performing a low ...

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.

SHELL AND SIGNAL TRANSMISSION APPARATUS USING THE SHELL

A signal transmission apparatus comprises a base and a shell, wherein a top portion of the base has a signal transmission device. The shell is covered above the base. A cavity is formed inside the shell. The cavity is in communication with an opening of a bottom portion of the shell. And the shell comprises a ceramic shell body and an inner covering layer. The inner covering layer is fully attached to an inner surface of the ceramic shell body. Therefore, the signals of the signal transmission device can pass through the shell so that the signal transmission device can receive or transmit signals. And through the strong adhesion of the inner covering layer, the ceramic shell body can be kept intact without being broken into a lot of debris when the ceramic shell body is impacted by external force or suddenly dropped. 1. A shell , wherein a cavity is formed inside said shell , said cavity is in communication with an opening of a bottom portion of said shell , and said shell comprises a ceramic shell body and an inner covering layer , said inner covering layer is formed by hardening a liquid resin and fully attached to an inner surface of said ceramic shell body , wherein a thickness of said inner covering layer is greater than or equal to 0.3 mm and less than or equal to 10 mm.2. The shell according to claim 1 , further comprising a plurality of through holes claim 1 , wherein said plurality of through holes is in communication with said cavity.3. (canceled)4. (canceled)5. The shell according to claim 1 , further comprising an outer covering layer claim 1 ,wherein said outer covering layer is covered on an outer surface of said ceramic shell body, andwherein said outer covering layer is a glaze layer.6. A signal transmission apparatus claim 1 , comprising:a base, wherein a top portion of said base has a signal transmission device; anda shell covering above said base, wherein a cavity is formed inside said shell, said cavity is in communication with an opening of a ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer. 1. A semiconductor device , comprising:a substrate;a first gate structure on the substrate;a first spacer adjacent to the first gate structure;a lower contact plug adjacent to the first gate structure and contact the first spacer; anda first overhang feature only disposed on an upper end of the first spacer.2. The semiconductor device according to claim 1 , wherein the lower contact plug comprises a first tungsten layer and a first glue layer.3. The semiconductor device according to claim 2 , wherein the first glue layer is disposed between the first tungsten layer and the first spacer.4. The semiconductor device according to claim 2 , wherein the first glue layer is disposed between the first tungsten layer and the first overhang feature.5. The semiconductor device according to claim 2 , wherein the first glue layer comprise Ti or TiN.6. The semiconductor device according to claim 1 , wherein the first overhang feature comprises silicon oxide.7. The semiconductor device according to claim 1 , wherein a top surface of the first overhang feature is coplanar with a top surface of the first gate structure.8. The semiconductor device according to claim 1 , wherein the lower contact plug comprises a narrower top portion and a wider bottom portion.9. The semiconductor device according to claim 8 , further comprising an undercut between the first overhang feature and the first spacer claim 8 , wherein the wider bottom portion is disposed within the undercut.10. The semiconductor device according to further comprising:a second gate structure on the substrate;a second spacer adjacent to the second gate structure; anda second overhang feature only disposed on an upper end of the ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate. 1. A method for fabricating semiconductor device , comprising:providing a substrate having a gate structure thereon;forming a silicon layer on the substrate to cover the gate structure entirely;planarizing the silicon layer; andperforming a replacement metal gate (RMG) process to transform the gate structure into a metal gate.2. The method of claim 1 , wherein the silicon layer comprises an amorphous silicon layer.3. The method of claim 1 , further comprising forming a liner on the substrate and the gate structure before forming the silicon layer.4. The method of claim 3 , wherein the liner comprises silicon oxide or silicon nitride.5. The method of claim 1 , further comprising:forming a spacer adjacent to the gate structure;forming a source/drain region in the substrate adjacent to the spacer; andforming the silicon layer to cover the gate structure and the spacer.6. The method of claim 5 , further comprising:removing part of the silicon layer adjacent to the gate structure after planarizing the silicon layer to form a contact hole; andforming a first contact plug in the contact hole.7. The method of claim 6 , wherein the first contact plug contacts the spacer directly.8. The method of claim 6 , further comprising:forming an interlayer dielectric (ILD) layer on the silicon layer, the gate structure, and the first contact plug; andforming a second contact plug in the ILD layer and electrically connect to the first contact plug.9. A semiconductor device claim 6 , comprising:a substrate;a first gate structure on the substrate;a first spacer adjacent to the first gate structure;a first contact plug adjacent to ...

SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF

A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via. 1. A semiconductor structure , comprising:a dielectric layer disposed on a substrate, wherein the dielectric layer has a via;a titanium layer covering the via, wherein the titanium layer has tensile stress lower than 1500 Mpa;a titanium nitride layer conformally covering the titanium layer; anda metal filling the via.2. The semiconductor structure according to claim 1 , wherein the via comprises a contact hole claim 1 , and the titanium layer claim 1 , the titanium nitride layer and the metal constitute a contact plug.3. The semiconductor structure according to claim 1 , further comprising:a silicide disposed between the titanium nitride layer and the substrate.4. The semiconductor structure according to claim 3 , wherein the silicide comprises a silicon titanium silicide.5. The semiconductor structure according to claim 3 , further comprising:a gate disposed on the substrate beside the via; anda source/drain disposed in the substrate below the titanium layer, and the silicide disposed on the source/drain.6. The semiconductor structure according to claim 1 , further comprising:a gate disposed directly below the titanium layer ...

METHOD FOR CLEANING CONTACT HOLE AND FORMING CONTACT PLUG THEREIN

The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process. 1. A method for cleaning a contact hole and forming a contact plug therein , the method comprising:providing a silicon substrate;forming a contact hole in the silicon substrate;performing a pre-cleaning process to clean the contact hole, the pre-cleaning process including:performing an oxide dry etching process;performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.;performing a degassing process for removing water and gas with a temperature ranging from 300° C.˜500° C.; andperforming an Ar-plasma etching process; andforming a contact plug in the contact hole.2. The method for cleaning the contact hole and forming the contact plug therein according to claim 1 , wherein a method of forming the contact plug in the contact hole while performing the Ar-plasma etching process includes steps of:depositing a barrier metal layer in the contact hole;performing a second thermal annealing process with a temperature which is equal to or greater than 450° C.; andforming a contact metal layer in the contact hole, wherein the contact metal layer is disposed on the barrier metal layer.3. The method for cleaning the contact hole and forming the contact plug therein according to claim 2 , wherein the step of depositing the barrier metal layer in the contact hole includes:stacking sequentially a Titanium (Ti) ...

DC UNINTERRUPTIBLE POWER SUPPLY APPARATUS WITH BIDIRECTIONAL PROTECTION FUNCTION

A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism. 1. A DC uninterruptible power supply apparatus with bidirectional protection function configured to receive a DC power source and supply power to a DC load , the DC uninterruptible power supply apparatus comprising:a first loop configured to receive the DC power source and supply power to the DC load,a second loop configured to receive the DC power source and convert the DC power source into an energy-storing power source to charge an energy-storing unit,a third loop coupled to the first loop and the energy-storing unit, and the energy-storing unit configured to provide a backup power source to the DC load through the third loop and the first loop, anda control unit configured to control the first loop, the second loop, and the third loop to be connected or disconnected for correspondingly providing a first protection mechanism, a second protection mechanism, and a third protection mechanism,wherein the first protection mechanism provides protection when the DC power source is reversely connected, the DC load is reversely connected, the DC power source is short circuit to ground, or the DC load is short circuit to ground, the second protection mechanism provides protection when the second loop occurs a first ...

Floor types identifying device, dust suction device having the same, and vacuum cleaner having the same

A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.

Power supply with duty cycle limiting circuit, duty cycle limiting circuit, and method of operating the same

A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C. 1. A semiconductor process , comprising:providing a wafer on a pedestal;lifting the pedestal to approach a heating source and performing an etching process on the wafer; andperforming an annealing process on the wafer by the heating source.2. The semiconductor process according to claim 1 , wherein the annealing process is performed without moving the pedestal.3. The semiconductor process according to claim 1 , further comprising:a plurality of pins located on the pedestal.4. The semiconductor process according to claim 3 , wherein the wafer is lifted by the pins during the annealing process.5. The semiconductor process according to claim 1 , wherein the temperature difference between the heating source and the pedestal is larger than 180° C. during the etching process.6. The semiconductor process according to claim 1 , wherein the temperature of the heating source is higher than or equal to 200° C. during the etching process.7. The semiconductor process according to claim 1 , wherein the temperature of the pedestal is lower than or equal to 20° C. during the etching process.8. The semiconductor process according to claim 1 , wherein the etching process is a plasma etching process.9. The semiconductor process according to claim 1 , wherein argon or hydrogen gases are imported during the annealing process.10. The semiconductor process according to claim 1 , wherein the semiconductor process comprises a cleaning process.11. The semiconductor process ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. 1. A manufacturing method of a semiconductor device , comprising:providing a substrate, with at least one fin structure on the substrate;depositing a metal layer on the fin structure to form a silicide layer;removing the metal layer, wherein no RTP (Rapid Thermal Process) is performed before the metal layer is removed, and;performing a RTP after the metal layer is removed.2. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a STI surrounding the fin structure.3. The manufacturing method of a semiconductor device of claim 1 , further comprising forming an epitaxy layer on the fin structure before depositing the metal layer.4. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a gate on parts of the fin structure.5. The manufacturing method of a semiconductor device of claim 4 , wherein the gate comprises a polysilicon gate or a metal gate.6. The manufacturing method of a semiconductor device of claim 1 , wherein the temperature of the RTP is between 400° C. and 600° C.7. The manufacturing method of a semiconductor device of claim 1 , further comprising forming a plurality of contacts on the silicide layer.8. The manufacturing method of a semiconductor device of claim 1 , wherein the contacts comprise slot contacts or pole contacts.9. A manufacturing method of a semiconductor device claim 1 , comprising:providing a substrate, with at least one fin structure on the substrate;depositing a metal layer on the fin structure to form a silicide layer.performing a low ...

NON-CONTACT INTELLIGENT BATTERY SENSING SYSTEM AND METHOD

In view of drivers cannot equip their vehicles with conventional intelligent battery monitoring system by themselves because the wire connections of the intelligent battery monitoring system are complex, the present invention particularly discloses a non-contact intelligent battery sensing system showing the advantages of simple circuit framework and low manufacturing cost. Since the non-contact intelligent battery sensing system only comprises a magnetic field sensor and a sensor controlling module, it is very easy for the drivers to equip their vehicles with this non-contact intelligent battery sensing system by themselves. To apply the non-contact intelligent battery sensing system, the driver just needs to firstly dispose the magnetic field sensor at one position near to a power line of a battery to be sensed, and then install a sensor controlling application program in his smart phones. Apparently, the non-contact intelligent battery sensing system further shows the advantage of easy to be installed. 1. A non-contact intelligent battery sensing system , comprising:a first magnetic field sensor, being disposed near a power line of a battery, and used for sensing a magnetic field formed around the power line so as to correspondingly output a magnetic field sensing signal; and a storage unit for storing the received magnetic field sensing signal;', 'a microprocessor, being coupled to the storage unit and comprising a feature parameter verifying unit and a battery state estimation unit; wherein the feature parameter verifying unit is configured to find out a plurality of feature parameters from a waveform characteristic of the magnetic field sensing signal, such that the battery state estimation unit is able to estimate a battery state according to the feature parameters; and', 'an output unit, being coupled to the microprocessor for outputting the battery state to an external electronic device., 'a sensor controlling module, being coupled to the first magnetic ...

ELECTRICAL ENERGY TRANSFERRING DEVICE SHOWING POWER CONSUMPTION/CHARGING STATUS

An electrical energy transferring device coupled to an electrical energy receiving device is provided. The electrical energy transferring device includes an electrical source measuring unit and a power indicating unit. The electrical source measuring unit detects a power consumption and/or a charging status of the electrical energy receiving device. The power indicating unit is coupled to the electrical source measuring unit for showing the power consumption and/or the charging status of the electrical energy receiving device by a color signal and/or an audio signal. 1. An electrical energy transferring device coupled to an electrical energy receiving device , comprising:an electrical source measuring unit for detecting a power consumption and/or a charging status of the electrical energy receiving device; anda power indicating unit coupled to the electrical source measuring unit for showing the power consumption and/or the charging status of the electrical energy receiving device by a color signal and/or an audio signal.2. The electrical energy transferring device according to claim 1 , further comprising:an upper power limit selection unit for setting an upper power limit of the electrical energy transferring device; and/ora protection unit for breaking off a power input path of the electrical energy transferring device if the electrical energy transferring device detects that the power consumption and/or the charging status of the electrical energy receiving device is over a threshold.3. The electrical energy transferring device according to claim 1 , wherein claim 1 , the power indicating unit comprises a full-color display element and/or a plurality of single-color display elements claim 1 , and/or an audio warning device.4. The electrical energy transferring device according to claim 1 , wherein claim 1 ,the power indicating unit shows the power consumption and/or the charging status of the electrical energy receiving device by a full-color blend display; ...

BATTERY INTERNAL RESISTANCE MEASURING DEVICE AND METHOD THEREOF

The present invention discloses a battery internal resistance measuring device and a method thereof, wherein the battery internal resistance measuring device comprises a voltage detecting unit, at least one measurement resistor, at least one switch, and a measurement controller. By means of further explanation, the measurement controller at least comprises a differential value calculating unit for treating a differential value calculation or a slope calculation to each two of adjacent voltage sampling values on a waveform of a discharge voltage signal of the battery, such that the measurement controller can subsequently find out a discharge starting point and a discharge ending point according to data of the differential value calculations or the slope calculations. Eventually, the measurement controller calculates an internal resistance of the battery after picking up an open-circuit voltage and a short-circuit voltage from the discharge starting point and the discharge ending point. 1. A battery internal resistance measuring device , comprising:a voltage detecting unit, being electrically connected to a battery;at least one measurement resistor, being electrically connected to the voltage detecting unit in parallel;at least one switch, being electrically connected to the measurement resistor in series; anda measurement controller, being electrically connected to the voltage detecting unit, and comprising a differential value calculating unit;wherein the voltage detecting unit is able to be electrically connected with a load in parallel, such that the voltage detecting unit correspondingly provides a discharge voltage signal of the battery to the measurement controller as the measurement controller generates a switch controlling signal to the switch;wherein the measurement controller picks up a plurality of first voltage sampling values from a waveform of the discharge voltage signal based on a first sampling rate during a switching-off period of the switch; ...

SEMICONDUCTOR PROCESS FOR FORMING PLUG

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided. 1. A semiconductor process for forming a plug , comprising:forming a dielectric layer having a recess on a substrate;forming a titanium layer conformally covering the recess;forming a first titanium nitride layer conformally covering the titanium layer, thereby the first titanium nitride layer having first sidewall parts;pulling back the first sidewall parts of the first titanium nitride layer, thereby second sidewall parts being formed; andforming a second titanium nitride layer covering the recess.2. The semiconductor process for forming a plug according to claim 1 , wherein the titanium layer is formed by a physical vapor deposition (PVD) process claim 1 , wherein the titanium layer has a bottom part and the sidewall parts claim 1 , and the bottom part has a thickness 4-8 times thicknesses of the sidewall parts.3. The semiconductor process for forming a plug according to claim 1 , wherein the first titanium nitride layer is formed by a chemical vapor deposition (CVD) process.4. The semiconductor process for forming a plug according to claim 1 , further comprising:performing an annealing process to form a metal silicide in the substrate at a bottom of the recess after the first titanium nitride layer is formed.5. The semiconductor process for forming a plug according to claim 4 , wherein the annealing process is performed before the first titanium ...

POWER SAVING DEVICE CAPABLE OF AUTOMATICALLY SENSING STANDBY CURRENT

The invention discloses a power saving device capable of automatically sensing standby current, which is used in a power device such as a power outlet or other power supply devices for giving the power device ability of electricity saving. When the power saving device normally works, a threshold current setting unit of a controlling and processing module is configured to automatically calculate a threshold current based on current signals sensed by a current detecting unit under different operation modes of at least one electrical device electrically connected to the power device. Moreover, when at least one standby current sensed from the electrical device is determined to be lower than the threshold current, the controlling and processing module immediately switches a switch unit to an open-circuit state, thereby causing the electrical device unable to receive electricity from the power device. Consequently, the power device exhibits the ability of power saving. 1. A power saving device capable of automatically sensing standby current , being for use in a power device electrically connected between an electricity inputting port and a power supplying port , and comprising:a current detecting unit, being coupled between the power supplying port and the power device; wherein an external electrical device can be electrically connected to the power supplying port for receiving a power outputted by the power device, and the current detecting unit being used for measuring a current signal from the power;a switch unit, being coupled between the power supplying port and the current detecting unit;a controlling and processing module, being electrically connected to the power device, the current detecting unit and the switch unit, and comprising a threshold current setting unit, a comparison unit and a microprocessor; andan activation unit, being configured for activating the controlling and processing module to switch the switch unit to a short-circuit state;wherein the ...

Device for real-time self diagnosis of a fan and the method using the same

A device for real-time self-diagnosis of a fan and a method are disclosed for detecting whether a fan body encounters an environment abnormal situation. The fan body includes a motor, a fan and a tachometer. The fan body further includes a microcontroller for receiving a speed signal of the tachometer and calculating a speed value of the fan, and detecting a current value of the motor during operation. The microcontroller can control the motor to drive the fan according to a monitoring period and a control signal transmitted from the control board, and can calculate a speed change amount according to the monitoring period, and can calculate a current change amount. When the speed change amount exceeds a speed change threshold and the current change amount exceeds a current change threshold for a period of time, the microcontroller generates an environmental anomaly signal.

Intelligent fan with interface compatibility

An intelligent fan with interface compatibility is provided. The intelligent fan includes a fan body having a fan and a motor, a driving circuit, a tachometer, an output connector including a first pin, a second pin, a third pin and a fourth pin connected to a fan connector of a motherboard, and a microcontroller connected to the driving circuit and the tachometer, and connected to the motherboard via the first, second, third and fourth pins. When the intelligent fan is powered on, the microcontroller sets the third and fourth pins as input pins for receiving an output signal of the fan connector of the motherboard, and the microcontroller performs an I2C signal analysis on the output signal. When the I2C signal analysis succeeds, the intelligent fan is set in an I2C mode, and when the I2C signal analysis fails, the intelligent fan is set in a PWM mode.

Intelligent fan control system with interface compatibility

An intelligent fan control system with interface compatibility is provided. The intelligent fan control system can identify and control fans one-to-one connected to fan slots, and each fan slot includes four pins. The intelligent fan control system includes a bus; an I2C signal switching unit including SDA outputs one-to-one connected to third pin of the fan slots via the bus; an I2C signal switching unit including SCL outputs one-to-one connected to fourth pins of the fan slots via the bus; voltage control units one-to-one corresponding to the fan slots, and having output terminals one-to-one connected to second pins of the fan slots; connection line sets, and each connection line set including four connection lines and connected to the corresponding fan slot; a control board comprising port sets, and can control and switch the I2C signal switching unit to the fan slots in sequence, to transmit the corresponding I2C signal.

ACCESS POINT IN GEOGRAPHIC ROUTING SYSTEM AND CONTROLLING METHOD THEREOF

An access point in a geographic routing system and a controlling method thereof are provided. The controlling method of the access point in the geographic routing includes the following steps. A traffic event packet is received by the access point. A back-off timer of the access point is set to be a first back-off time value. The first back-off time value is less than a second back-off time value of any on board unit (OBU) which receives the traffic event packet. The traffic event packet is broadcasted by the access point when the back-off timer is counted down to be zero. 1. A controlling method of an access point in a geographic routing system , comprising:receiving a traffic event packet by the access point; andsetting a back-off timer of the access point to be a first back-off time value, wherein the first back-off time value is less than a second back-off time value of any on board unit (OBU) which receives the traffic event packet; andbroadcasting the traffic event packet by the access point when the back-off timer is counted down to be zero.2. The controlling method of the access point in the geographic routing system according to claim 1 , wherein the first back-off time value is zero.3. The controlling method of the access point in the geographic routing system according to claim 1 , further comprising:setting a transmitting power of the access point to be a first transmitting power value, wherein the first transmitting power value is larger than a second transmitting power value of any OBU.4. A controlling method of an access point in a geographic routing system claim 1 , comprising:receiving a traffic event packet by the access point; anddetermining whether there is another access point which is closer to a destination area than the access point;forwarding the traffic event packet to the another access point, if there is the another access point which is closer to the destination area than the access point; andbroadcasting the traffic event packet by the ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate. 1. A method for fabricating semiconductor device , comprising:providing a substrate having a gate structure thereon;forming a silicon layer on the substrate to cover the gate structure entirely;planarizing the silicon layer; andperforming a replacement metal gate (RMG) process to transform the gate structure into a metal gate.2. The method of claim 1 , wherein the silicon layer comprises an amorphous silicon layer.3. The method of claim 1 , further comprising forming a liner on the substrate and the gate structure before forming the silicon layer.4. The method of claim 3 , wherein the liner comprises silicon oxide or silicon nitride.5. The method of claim 1 , further comprising:forming a spacer adjacent to the gate structure;forming a source/drain region in the substrate adjacent to the spacer; andforming the silicon layer to cover the gate structure and the spacer.6. The method of claim 5 , further comprising:removing part of the silicon layer adjacent to the gate structure after planarizing the silicon layer to form a contact hole; andforming a first contact plug in the contact hole.7. The method of claim 6 , wherein the first contact plug contacts the spacer directly.8. The method of claim 6 , further comprising:forming an interlayer dielectric (ILD) layer on the silicon layer, the gate structure, and the first contact plug; andforming a second contact plug in the ILD layer and electrically connect to the first contact plug. This application is a division of U.S. application Ser. No. 14/873,223 filed Oct. 2, 2015, and incorporated herein by reference in its entirety.The invention relates to a method for fabricating semiconductor ...

Game recording apparatus and game recording method

A game recording apparatus includes a video processing module, a video buffering module, an information converting module, a subtitle buffering module, and a video integrating module. The video processing module is coupled between a game console and video buffering module. The information converting module is coupled between a game controller and subtitle buffering module. The video processing module receives a video signal from game console and codes it, and coded video signal is stored in video buffering module. The information converting module receives an operation information from game controller and converts operation information into a subtitle information and saves it into subtitle buffering module. The video integrating module integrates coded video signal and subtitle information into a game video information with a specific video format. Therefore, requirements of time constraint and computing power can be reduced and operation load and cost of game recording apparatus can be lowered.

SEMICONDUCTOR STRUCTURE AND PROCESS FOR FORMING PLUG

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided. 1. A semiconductor process for forming a plug , comprising:forming a dielectric layer having a recess on a substrate;forming a titanium layer conformally covering the recess;forming a first titanium nitride layer conformally covering the titanium layer, thereby the first titanium nitride layer having first sidewall parts;pulling back the first sidewall parts of the first titanium nitride layer, thereby second sidewall parts being formed; andforming a second titanium nitride layer covering the recess.2. The semiconductor process for forming a plug according to claim 1 , wherein the titanium layer is formed by a physical vapor deposition (PVD) process claim 1 , wherein the titanium layer has a bottom part and the sidewall parts claim 1 , and the bottom part has a thickness 4-8 times thicknesses of the sidewall parts.3. The semiconductor process for forming a plug according to claim 1 , wherein the first titanium nitride layer is formed by a chemical vapor deposition (CVD) process.4. The semiconductor process for forming a plug according to claim 1 , further comprising:performing an annealing process to form a metal silicide in the substrate at a bottom of the recess after the first titanium nitride layer is formed.5. The semiconductor process for forming a plug according to claim 4 , wherein the annealing process is performed before the first titanium ...

Input device and input method thereof

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Access point in geographic routing system and controlling method thereof

An access point in a geographic routing system and a controlling method thereof are provided. The controlling method of the access point in the geographic routing includes the following steps. A traffic event packet is received by the access point. A back-off timer of the access point is set to be a first back-off time value. The first back-off time value is less than a second back-off time value of any on board unit (OBU) which receives the traffic event packet. The traffic event packet is broadcasted by the access point when the back-off timer is counted down to be zero.

Semiconductor device

Controlling device for flame outlets of propane gas water heater

Semiconductor device

A semiconductor device comprising: a substrate; a first magnetic tunnel junction (MTJ) structure disposed on the substrate; a second MTJ structure disposed on the substrate; and an interconnection structure disposed on the substrate and located between the first MTJ structure and the second MTJ structure in a first horizontal direction, wherein the interconnection structure comprises: a first metal interconnection; and a second metal interconnection disposed on and contacting the first metal interconnection.

Method of monitoring network connections of semiconductor tools

可偵測突波訊號特性之突波偵測裝置

突波偵測裝置包含一感應單元，及一比較單元。該感應單元係用以感應一突波訊號以產生一感應訊號。該比較單元之第一輸入端係耦接於該感應單元，該比較單元之第二輸入端係用以接收一門檻值訊號，該比較單元係用以根據該感應訊號及該門檻值訊號進行比較運算以產生一輸出訊號。

Device for conducting motor recognition and protection and vacuum cleaner using the same

A device for conducting motor recognition and protection is disclosed. The device comprises a current detection circuit and a microprocessor, of which the current detection circuit is used for detecting an operation current from a roller brush driving motor that is integrated in a suction head of a vacuum cleaner. Moreover, the microprocessor is configured for determining a product model of the roller brush driving motor based on the operation current, deciding a protection parameter set according to the product model, and conducting a motor protection for the roller brush driving motor after loading at least one motor protection parameter contained by the protection parameter set.

Controlling apparatus for compounded flame outlets of gas water heater

Semiconductor device

A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

網路服務推薦方法與其電腦程式產品

一種網路服務推薦方法與其電腦程式產品。在此網路服務推薦方法中，首先提供複數個網路服務之原始服務信任值。這些網路服務係由複數個服務提供者所提供。接著，根據歷史需求者回饋參數和網路服務之原始服務信任值來計算網路服務之修正後服務信任值。然後，根據網路服務之修正後服務信任值以及原始提供者誠信度來計算目標提供者之修正後提供者誠信度。接著，根據網路服務之修正後服務信任值與服務提供者之修正後提供者誠信度來從網路服務中選擇出可信賴的網路服務。當電腦載入此電腦程式產品後，此電腦可執行上述之網路服務推薦方法。

Cock valve assembly of gas water heater