Embedded JFETs for High Voltage Applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. 1. A device comprising:a buried well region of a first conductivity type over a substrate layer;a first High Voltage Well (HVW) region of the first conductivity type over the buried well region;an insulation region over the first HVW region;a drain region of the first conductivity type on a first side of the insulation region;a gate electrode on a second side of the insulation region;a well region in a region adjacent to the insulation region, wherein the well region is of a second conductivity type opposite to the first conductivity type;a second HVW region of the first conductivity type in the well region, wherein the second HVW region overlaps a portion of the buried well region; anda source region of the first conductivity type in a top region of the second HVW region.2. The device of claim 1 , wherein the first conductivity type is n-type.3. The device of claim 1 , wherein the well region comprises a first portion and a second portion on opposite sides of the second HVW region.4. The device of claim 3 , wherein the well region encircles the second HVW region.5. The device of claim 1 , wherein the well region is configured to pinch off a current flowing ...

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Bootstrap MOS for high voltage applications

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.

High voltage resistor with high voltage junction termination

Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Triple well isolated diode and method of making

A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.

PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Plate design to decrease noise in semiconductor devices

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

High side gate driver device

The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

Ultrahigh-voltage semiconductor structure and method for manufacturing the same

The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

HIGH SIDE GATE DRIVER DEVICE

The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

A NOVEL LAYOUT TO REDUCE NOISE IN SEMICONDUCTOR DEVICES

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Plate design to decrease noise in semiconductor devices

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Field effect transistor structure and manufacturing method thereof

The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

Power MOSFETs and methods for forming the same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Power MOSFETs and Methods for Forming the Same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. 1. A device comprising:a substrate;a well of a first impurity type in the substrate;a gate structure over the well;a region of a first conductivity type, formed at a first side of the gate structure;a drift region of a second conductivity type opposite to the first conductivity type, formed at a second side of the gate structure and including a first part extending from a top surface of the substrate to a first depth into the well, a second part underlying the gate structure and extending a second depth less than the first depth from the top surface of the substrate into the well;a source region of the second conductivity type within the region; anda drain region of the second conductivity type within the first part of the drift region, extending a third depth less than the first depth from the top surface of the substrate into the well.2. The device of claim 1 , wherein the gate structure includes a gate dielectric on the top surface of the substrate and a gate electrode on the gate dielectric.3. The device of claim 2 , wherein the first part of the drift region and the second part of the drift region form an interface claim 2 , the interface being substantially aligned with an edge of the gate electrode.4. The ...

Semiconductor structure having field plate and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMATION

The present disclosure relates an integrated chip structure. The integrated chip structure includes a first chiplet predominantly having a first plurality of integrated chip devices coupled to a first plurality of interconnects over a first substrate. The first plurality of integrated chip devices are a first type of integrated chip device. The integrated chip structure further includes a second chiplet predominantly having a second plurality of integrated chip devices coupled to a second plurality of interconnects over a second substrate. The second plurality of integrated chip devices are a second type of integrated chip device different than the first type of integrated chip device. One or more inter-chiplet connectors are between the first and second chiplets and are configured to electrically couple the first and second chiplets. The first plurality of interconnects have a first minimum width different than a second minimum width of the second plurality of interconnects.

Semiconductor isolation structure and method for making the semiconductor isolation structure

A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall. 1. A semiconductor device comprising:a semiconductor substrate comprising a device region;an isolation structure extending laterally in a closed path to demarcate the device region;a first source/drain region and a second source/drain region in the device region and laterally spaced, wherein a sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and wherein remaining sidewalls of the first source/drain region are spaced from the isolation structure;a selectively-conductive channel in the device region, wherein the selectively-conductive channel extends laterally from the first source/drain region to the second source/drain region; anda plate comprising a central portion and a first peripheral portion, wherein the central portion overlies the selectively-conductive channel, and wherein the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.2. The semiconductor device of claim 1 , ...

HV interconnection solution using floating conductors

A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

Method of forming high voltage device

A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

POWER MOSFETS AND METHODS FOR FORMING THE SAME

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. 1. A device comprising:a substrate;a well in the substrate, the well being of a first conductivity type and having a first impurity concentration;a gate stack over the well; a first part adjacent the gate stack and extending from a top surface of the well to a first depth into the well; and', 'a second part underlying the gate stack and extending from the top surface of the well to a second depth into the well, the first depth being greater than the second depth; and, 'a drift region of a second conductivity type within the well, the drift region having a second impurity concentration, the second conductivity type being opposite the first conductivity type, the drift region comprisinga drain region of the second conductivity type within the first part of the drift region, the drain region having a third impurity concentration different from the second impurity concentration.2. The device of claim 1 , further comprising a first region of the first conductivity type within the well claim 1 , the first region having a fourth impurity concentration different from the first impurity concentration claim 1 , a portion of the well disposed below the gate stack being interposed between the first region and the drift region. ...

High voltage resistor

Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

Metal oxide semiconductor field effect transistor having variable thickness gate dielectric

A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. The gate structure includes a variable thickness gate dielectric layer. The variable thickness gate dielectric layer includes a first portion closest to the drain, the first portion having a first thickness. The variable thickness gate dielectric layer further includes a second portion distal from the drain, the second portion having a second thickness less than the first thickness.

Embedded JFETs for high voltage applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

High Side Gate Driver Device

The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. 1. A semiconductor device , comprising:a drift region having a first doping polarity formed in a substrate;a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component;a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region;a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; anda doped isolation region having the second doping polarity, wherein the doped isolation region at least partially surrounds the drift region and the doped extension region in a top view.2. The semiconductor device of claim 1 , wherein the laterally-extending component of the doped extension region is located substantially away from a surface of the drift region.3. The semiconductor device of claim 1 , further including:a drain region formed in the drift region, the drain region having the first doping polarity and being more doped than the drift region; anda source region formed in the doped extension region, the source ...

NOVEL LAYOUT TO REDUCE NOISE IN SEMICONDUCTOR DEVICES

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate. 1. A semiconductor device , comprising:an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate;a gate disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure;a first source/drain region disposed in the device region and on a first side of the gate;a second source/drain region disposed in the device region and on a second side of the gate opposite the first side of the gate; anda silicide blocking structure at least partially overlying the gate and at least partially overlying the isolation structure.2. The semiconductor device of claim 1 , wherein the silicide blocking structure at least partially overlies the first source/drain region.3. The semiconductor device of claim 1 , further comprising:a silicide layer disposed over the gate, wherein the silicide layer covers some, but not all, of an upper surface of the gate.4. The semiconductor device of claim 1 , wherein a first sidewall of the ...

Power MOSFETs and Methods for Forming the Same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. 1. A power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) comprising:a substrate;a first region extending from a top surface of the substrate into the substrate, wherein the first region is of a first conductivity type with a first impurity concentration;a gate dielectric over and in contact with the first region;a gate electrode over and in contact with the gate dielectric;a second region of the first conductivity type, formed within the first region at a first side of the gate electrode, wherein the second region has a second impurity concentration;a stepped drift region of a second conductivity type opposite to the first conductivity type, of a third impurity concentration, and within the first region, wherein the stepped drift region comprises a first part formed at a second side of the gate electrode, and a second part beneath the gate electrode, adjacent to the first part, with a depth less than a depth of the first part;a source region of the second conductivity type within the second region; anda drain region of the second conductivity type within the first part of the stepped drift region.2. The power MOSFET of claim 1 , wherein a sum of the depth of the second part of the stepped drift region ...

MOS transistor having a gate dielectric with multiple thicknesses

A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.

High Voltage Resistor With Pin Diode Isolation

Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. 1. A semiconductor device , comprising:a substrate;a first doped region disposed in the substrate;a second doped region disposed in the substrate, the second doped region being oppositely doped from the first doped region;a third doped region disposed in the substrate and between the first and second doped regions, the third doped region having a lower doping concentration level than both the first and second doped regions;an insulating device disposed over a portion of the first doped region; anda resistor disposed over the insulating device.2. The semiconductor device of claim 1 , wherein the first claim 1 , second claim 1 , and third doped regions collectively form a PIN diode.3. The semiconductor device of claim 1 , wherein:the substrate is a P-type substrate;the first doped region includes an N-type doped well;the second doped region includes a P-type doped well; andthe third doped region includes one of: a lightly-doped N-type intrinsic region and a lightly-doped P-type intrinsic region. ...

Transistor and method of manufacturing the same

A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 m.

Transistor and method of manufacturing the same

A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer.

HIGH VOLTAGE MOS TRANSISTOR

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.

TRANSISTOR DEVICE WITH RECESSED GATE STRUCTURE

A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

High voltage devices and methods of forming the high voltage devices

A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

High voltage transistor structure

An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Source tip optimization for high voltage transistor devices

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE

The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided. 1. A semiconductor device , comprising:a substrate having a resistor element region and a transistor region;a floating substrate in the resistor element region of the substrate;an epitaxial layer disposed over the floating substrate;an active region defined in the epitaxial layer, the active region surrounded by isolation structures;a resistor block disposed over an isolation structure; anda dielectric layer disposed over the resistor block, the isolation structures, and the active region.2. The semiconductor device of claim 1 , wherein the floating substrate is doped with a p-type dopant claim 1 , the epitaxial layer is doped with an n-type dopant claim 1 , and the active region is doped with an n-type dopant.3. The semiconductor device of claim 1 , wherein the epitaxial layer is a floating layer.4. The semiconductor device of claim 1 , wherein the isolation structures include one of shallow trench isolation (STI) structures or local oxidation of semiconductor (LOCOS) structures.5. The semiconductor device of claim 1 , wherein an isolation structure is formed above a p-well.6. A semiconductor device claim 1 , comprising:a substrate having a resistor element region and a transistor region;a p-type substrate in the resistor element region of the substrate;a floating n-type buried layer disposed over the p-type substrate;a floating p-type buried ...

High voltage resistor with pin diode isolation

Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Bootstrap MOS for high voltage applications

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.

HIGH VOLTAGE RESISTOR

Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. 1. A semiconductor device , comprising:a resistor having a spiral shape, the resistor having a first portion and a second portion; and a first doped region that is electrically coupled to the first portion of the resistor; and', 'a second doped region that is electrically coupled to the second portion of the resistor, the first and second doped regions having opposite doping polarities., 'a voltage protection device that includes2. The semiconductor device of claim 1 , wherein:the resistor is formed within a metal layer of an interconnect structure; andthe resistor includes a plurality of turns, the turns being spaced substantially evenly apart.3. The semiconductor device of claim 1 , wherein the first and second portions of the resistor are coupled to the first and second doped regions through vias and metal lines of an interconnect structure.4. The semiconductor device of claim 1 , wherein the first and second portions of the resistor are end portions of the resistor.5. The semiconductor device of claim 1 , wherein:the first portion of the resistor includes a cathode terminal;the second portion of the resistor includes an anode terminal;the first doped region is doped with a P-type dopant and is coupled to the cathode terminal; andthe second doped region is doped with an N-type dopant and is coupled to the anode terminal.6. The semiconductor device of claim 1 , wherein the voltage protection device further includes: a third doped region having the ...

Semiconductor device having multiple wells and method of making

A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall. 1. A method for forming a semiconductor device , the method comprising:forming an isolation structure in a semiconductor substrate, wherein inner sidewalls of the isolation structure demarcate a device region of the semiconductor substrate;forming a plate at least partially overlying the device region and at least partially overlying the isolation structure, wherein the plate exposes a first portion of the device region and a second portion of the device region that is laterally spaced from the first portion of the device region, wherein the first portion of the device region adjoins a first inner sidewall of the isolation structure and the second portion of the device region adjoins a second inner sidewall of the isolation structure, and wherein the plate at least partially overlies the first inner sidewall and the second inner sidewall; andwith the plate at least partially overlying the device region, forming a first source/drain region in the first portion of the device region and a second source/ ...

High voltage resistor with high voltage junction termination

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

High voltage resistor with PIN diode isolation

Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Source tip optimization for high voltage transistor devices which includes a P-body extension region

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Quasi-vertical structure having a sidewall implantation for high voltage MOS device

A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.

Embedded JFETs for High Voltage Applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. 1. A device comprising:a substrate;a buried well region of a first conductivity type over the substrate;a High Voltage Well (HVW) region of the first conductivity type over the buried well region;an insulation region over the HVW region;a drain region of the first conductivity type on a first side of the insulation region;a gate electrode on a second side of the insulation region;a well region adjacent to the insulation region, wherein the well region is of a second conductivity type opposite to the first conductivity type, and wherein the well region comprises a continuous portion, and a first leg connecting to the continuous portion; anda first heavily doped region and a second heavily doped region of the first conductivity type in a top region of the HVW region, wherein the first heavily doped region and the second heavily doped region are separated from each other by the first leg.2. The device of claim 1 , wherein the continuous portion and the gate electrode are on opposing sides of the first and the second heavily doped regions claim 1 , and the first leg extends from the continuous portion in a direction toward the gate electrode.3. The device of further ...

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.

Stacked and tunable power fuse

The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Embedded JFETs for High Voltage Applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. 1. A device comprising:a substrate;a buried well region of a first conductivity type over the substrate;a first High Voltage Well (HVW) region of the first conductivity type over the buried well region;an insulation region over the first HVW region;a drain region of the first conductivity type on a first side of the insulation region and in a top surface region of the first HVW region;a gate electrode comprising a first portion on a second side of the insulation region, and a second portion extending over the insulation region;a first well region and a second well region of a second conductivity type opposite the first conductivity type and on the second side of the insulation region;a second HVW region of the first conductivity type between the first and the second well regions, wherein the second HVW region is connected to the buried well region; anda source region of the first conductivity type and in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a Junction Field-Effect Transistor (JFET).2. The device of claim 1 , wherein the first and the second well regions are configured to pinch ...

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Power MOSFETs and methods for forming the same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

MOS transistor and method for manufacturing MOS transistor

A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Source Tip Optimization For High Voltage Transistor Devices

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region. 1. A semiconductor device , comprising:a substrate having first, second, and third regions, the first and second regions having different doping polarities and being separated by the third region, the third region having the same doping polarity as the second region and a lower dopant concentration level than the second region;a source formed in the substrate and over the first region, the source and the first region having different doping polarities;a drain formed in the substrate and over the second region, the drain and the second region having the same doping polarity; anda gate formed over a portion of the third region, the gate being formed closer to the source than to the drain.2. The semiconductor device of claim 1 , wherein the first region has a portion that protrudes toward the third region.3. The semiconductor device of claim 1 , further including a dielectric structure formed over the third region claim 1 , wherein the gate is formed on a portion of the dielectric structure.4. The semiconductor device of claim 1 , wherein a portion of the source adjacent to the third region has a substantially curved profile from a top view.5. The semiconductor device of claim 4 , wherein the portion of the ...

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Bootstrap MOS for High Voltage Applications

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.

BOOTSTRAP MOS FOR HIGH VOLTAGE APPLICATIONS

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. 1. A device comprising:a buried well region of a first conductivity type;a first High-Voltage Well (HVW) region of the first conductivity type over the buried well region;a first well region of a second conductivity type opposite to the first conductivity type, wherein the first well region comprises an edge contacting an edge of the first HVW region;a drain region of the first conductivity type in a surface portion of the first HVW region;a first source region of the first conductivity type in a surface portion of the first well region;a first gate electrode over the first HVW region and the first well region, with the drain region and the first source region on opposite sides of the first gate electrode;a plurality of buried regions of the second conductivity type, wherein the plurality of buried regions is parallel to each other, and is over and contacting a top surface of the buried well region; anda plurality of HVW regions of the first conductivity type separating the plurality of buried regions from each other, wherein the plurality of buried regions and the plurality of HVW regions are spaced apart from the first source region by the first well region.2. The device of ...

Power MOSFETs and methods for forming the same

A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.

Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage

A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Embedded JFETs for High Voltage Applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Plate design to decrease noise in semiconductor devices

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Embedded JFETs for high voltage applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

HV Interconnection Solution Using Floating Conductors

A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region. 1. A device comprising:a semiconductor substrate;a first and a second heavily doped region in the semiconductor substrate;an insulation region having at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions;a gate dielectric over the semiconductor substrate and comprising a portion over a portion of the insulation region;a gate over the gate dielectric;a floating conductor over and vertically overlapping the insulation region; anda metal line comprising a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.2. The device of claim 1 , wherein the first and the second heavily doped regions are of a same conductivity type claim 1 , and wherein the first and the second heavily doped regions are a source and a drain of a respective high-voltage MOS device comprising the gate and the first and the second heavily doped regions.3. The device of claim 1 , wherein the first and the second heavily doped regions are of opposite conductivity types claim 1 , and wherein the gate is electrically coupled to the first heavily doped region.4. A device comprising: a source and a drain;', 'a drain insulation region ...

PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall. 1. A semiconductor device comprising:an isolation structure disposed in a semiconductor substrate, wherein the isolation structure demarcates a device region in the semiconductor substrate;a first source/drain region disposed in the device region, wherein the isolation structure has a first sidewall disposed on a first side of the first source/drain region;a second source/drain region disposed in the device region and laterally spaced from the first source/drain region, wherein the first source/drain region is disposed laterally between the first sidewall of the isolation structure and the second source/drain region, and wherein a first portion of the device region extends laterally from the first source/drain region to the second source/drain region;a gate region disposed in the device region, wherein the gate region adjoins a side of the first portion of the device region laterally between the first source/drain region and the second source/drain region; anda plate disposed over the semiconductor ...

Semiconductor structure having field plate and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

High Voltage Resistor

Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. 1. A method , comprising:forming a first doped region in a substrate;forming a second doped region in the substrate, the second doped region being oppositely doped from the first doped region and being at least partially surrounded by the first doped region; andforming an interconnect structure over the first and second doped regions, the interconnect structure having a plurality of interconnect layers;wherein the forming the interconnect structure includes forming a resistor in one of the interconnect layers, the resistor having a spiral shape and having first and second portions that are coupled to the first and second doped regions, respectively.2. The method of claim 1 , wherein the forming the first doped region is carried out in a manner so that the first doped region is formed in a portion of the substrate that is oppositely doped from the first doped region.3. The method of claim 1 , wherein the forming the first doped region and the forming the second doped region are carried out in a manner so that:the first doped region includes a portion that extends at least partially into the second doped region; andthe first doped region completely surrounds the second doped region in an approximately circular manner from a top level view.4. The method of claim 1 , further including:forming a polysilicon device partially over the first and second doped regions; andcoupling the polysilicon device to the first portion of the resistor.5. The method of ...

Embedded JFETs for high voltage applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Layout to reduce noise in semiconductor devices

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

High Voltage Resistor with Pin Diode Isolation

Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. 1. A method of fabricating a semiconductor device , comprising:forming a PIN diode in a substrate, wherein the PIN diode includes a lightly-doped intrinsic region disposed between a heavily-doped first well and a heavily-doped second well, wherein the intrinsic region has a different type of conductivity than the first and second wells and is located between the first and second wells;forming a dielectric structure over a portion of the first well; andforming an elongate resistor over the dielectric structure.2. The method of claim 1 , wherein the forming of the PIN diode comprises:growing an epi-layer over the substrate via epitaxial growth; andforming the first and second wells in different portions of the epi-layer via ion implantation;wherein the intrinsic region is formed by a remaining portion of the epi-layer disposed between the first and second wells.3. The method of claim 1 , wherein the forming of the PIN diode comprises forming a buried well within the first well claim 1 , the ...

TRANSISTOR DEVICE WITH RECESSED GATE STRUCTURE

A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

HIGH VOLTAGE TRANSISTOR STRUCTURE

An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied. 1. A high voltage semiconductor transistor , comprising:a semiconductor substrate having a first type of conductivity;a first well region having a second type of conductivity and formed over the semiconductor substrate;a second well region in the first well region and having the first type of conductivity;a first insulating structure over the first well region;a gate structure adjacent the first insulating structure and between a source region and a drain region;the drain region comprising a first drain portion between the first insulating structure and a second insulating structure and a second drain portion across the second insulating structure from the first drain portion; andthe source region disposed on a side of the gate structure opposite from the drain region.2. The transistor of claim 1 , wherein the second well region has a U-shape in a cross section and extends from an interface with the source region to an interface with the second insulating structure claim 1 , and the cross section is taken in a direction perpendicular to a top surface of the semiconductor substrate.3. The transistor of claim 1 , wherein the gate structure includes a gate dielectric layer and a gate electrode layer claim 1 , wherein the gate electrode layer is disposed on a surface of the first insulating structure.4. The transistor of claim 1 , wherein the first drain portion has the ...

Embedded JFETs for High Voltage Applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. 1. A method comprising: a first portion underlying a first P-type Buried Layer (PBL), wherein the first portion of the current is further conducted through a first portion of an n-well region, with the n-well region between a first p-well region and a second p-well region; and', 'a second portion through a second portion of the n-well region, wherein the second portion of the n-well region is between the first PBL and a second PBL;, 'conducting a current between a source region and a drain region of a Junction Field-Effect Transistor (JFET), wherein the current comprisesapplying a voltage to a first gate of the JFET, wherein the voltage is applied from the first gate to the first p-well region; andapplying the voltage to a second gate of the JFET, with the first gate and the second gate being on opposite sides of the source region, wherein the voltage is applied from the second gate to the second p-well region, and wherein the first portion of the current is pinched-off by first depletion regions formed due to the voltage.2. The method of further comprising:applying the voltage to a third p-well region, wherein the second p-well region and the third p-well region ...

Quasi-vertical structure for high voltage MOS device

A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

Semiconductor device having multiple wells

A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.

JFET structure and manufacturing method of the same

The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

HIGH VOLTAGE RESISTOR WITH PIN DIODE ISOLATION

Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. 1. A semiconductor device , comprising:a substrate;a PIN diode formed in the substrate, the PIN diode containing an N-type region, a P-type region, and an intrinsic region formed between the N-type region and the P-type region;an insulating structure formed over a portion of the PIN diode;a resistor formed over the insulating structure; andan interconnect structure formed over the resistor, wherein the interconnect structure electrically couples the resistor with the PIN diode.2. The semiconductor device of claim 1 , wherein the N-type region and the P-type region are each more heavily doped than the intrinsic region.3. The semiconductor device of claim 1 , wherein the intrinsic region is doped with an N-type dopant.4. The semiconductor device of claim 1 , wherein the N-type region contains an N-type doped buried well.5. The semiconductor device of claim 1 , wherein the insulation structure is formed over the N-type region or the P-type region but not over the intrinsic region.6. The ...

SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

High voltage resistor

Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

High side gate driver device

The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

High voltage resistor with biased-well

Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

NOVEL LAYOUT TO REDUCE NOISE IN SEMICONDUCTOR DEVICES

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate. 1. A semiconductor device , comprising:an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate;a gate overlying the device region;a first source/drain region disposed in the device region and on a first side of the gate;a second source/drain region disposed in the device region and on a second side of the gate opposite the first side of the gate; anda silicide blocking structure at least partially overlying a portion of the device region and at least partially overlying the isolation structure.2. The semiconductor device of claim 1 , wherein the silicide blocking structure at least partially overlies the gate.3. The semiconductor device of claim 1 , wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure.4. The semiconductor device of claim 1 , wherein the silicide blocking structure at least partially overlies the first source/drain region.5. The semiconductor device of claim 1 , wherein the portion of the device region is ...

Layout to reduce noise in semiconductor devices

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Embedded JFETs for high voltage applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Insulated gate bipolar transistor structure having low substrate leakage

A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Transistor device with a gate structure having recesses overlying an interface between isolation and device regions

A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

HIGH VOLTAGE RESISTOR WITH BIASED-WELL

Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. 1. A method of fabricating a semiconductor device , comprising:forming a doped region in a substrate, the doped region and the substrate having opposite types of conductivity;forming an isolation structure over a portion of the doped region, the isolation structure having electrical isolation properties;forming a resistor over the isolation structure, the resistor having a first distal end and a second distal end opposite the first distal end; andforming an interconnect structure over the substrate, wherein the interconnect structure includes interconnecting elements that electrically couple the doped region with a segment of the resistor that is disposed between the first and second distal ends.2. The method of claim 1 , wherein the segment of the resistor electrically coupled to the doped region is located substantially near a midpoint of the resistor.3. The method of claim 1 , wherein:the forming of the resistor comprises forming a polysilicon resistor; andthe forming of the isolation structure comprises forming field oxide as the isolation structure.4. The method of claim 1 , ...

Power MOSFETs and methods for forming the same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE

A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

Stacked and Tunable Power Fuse

The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. 1. A semiconductor device , comprising:a transistor including a substrate, a source, a drain, and a gate, wherein the source is grounded; and a first contact coupled to the drain of the transistor;', 'a second contact; and', 'a resistor coupled to the first contact and the second contact via at least one Schottky diode, and', 'wherein the fuse is configured to blow at a voltage between about 20 V and about 700 V., 'a fuse coupled to the transistor, the fuse including2. The semiconductor device of claim 1 , wherein the first contact is an anode contact and the second contact is a cathode contact.3. The semiconductor device of claim 1 , the at least one Schottky diode further includes:a first Schottky diode coupled between the first contact of the fuse and the resistor;a second Schottky diode coupled between the second contact of the fuse and the resistor.4. The semiconductor device of claim 1 , wherein the transistor includes an isolation structure disposed between the gate and the drain claim 1 , the isolation structure and the drain being within a n-well within the substrate claim 1 , and the substrate being doped with a p-type dopant.5. The semiconductor device of claim 1 , wherein the resistor includes a plurality of turns.6. The semiconductor device of claim 1 , further comprising a dielectric layer between the gate of the transistor and the resistor of the fuse.7. A semiconductor device claim 1 , comprising:a plurality of transistors, each transistor including a substrate, a source, a drain, ...

Plate design to decrease noise in semiconductor devices

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

High voltage resistor with high voltage junction termination

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

STACKED AND TUNABLE POWER FUSE

The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Semiconductor structure and method for manufacturing the same

A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.

HIGH VOLTAGE RESISTOR WITH HIGH VOLTAGE JUNCTION TERMINATION

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.

Embedded JFETs for high voltage applications

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Sliding hinge and a portable device with the sliding hinge

A portable device has lower and upper casings. A sliding hinge has a stationary frame attached to the lower casing, a sliding frame attached to the upper casing and a resilient positioning assembly mounted between the stationary and sliding frames. The sliding frame has multiple pushing pins protruding toward the stationary frame. The resilient positioning assembly has two sliders and multiple resilient elements disposed between and abutting the sliders. When the upper casing slides relative to the lower casing, the pushing pins move along and push corresponding sliders and pressing the resilient elements. As long as the pushing pins are moved to the other sides of the corresponding sliders, the resilient elements push the sliders back and the upper and lower casings of the portable device are open relative to each other. 1. A sliding hinge comprisinga stationary frame; an inner surface corresponding to the stationary frame; and', 'at least one pushing pin mounted on the inner surface of the sliding frame; and, 'a sliding frame mounted on the stationary frame and having'} [ at least one side surface corresponding to the at least one pushing pin of the sliding frame; and', 'multiple mounting recesses formed in the at least one side surface of the mounting bracket;, 'a mounting bracket mounted securely on the stationary frame and having'}, multiple mounting rods separately protruding from a side surface of the first slider and mounted respectively in the mounting recesses of the mounting bracket; and', 'a pushing protrusion formed on another side surface of the first slider and abutting the corresponding pushing pin of the sliding frame; and, 'a first slider mounted on one of the at least one side surface of the mounting bracket, disposed between the mounting bracket and the at least one pushing pin and having'}, 'multiple resilient elements mounted respectively around the mounting rods of the first slider, and each resilient element having two ends respectively ...

METHOD FOR FORMING A TOUCH SENSING PATTERN AND SIGNAL WIRES

A method for forming a touch sensing pattern and signal wires, comprises the steps of: installing a first and a second conductive plating films on a surface of a highly transparency substrate; projecting a high energy light beam to the conductive plating films; and the high energy light beam moving with respect to the substrate along a predetermined track; a plurality of insulating trenches being formed in the first and second conductive plating films so as to form predetermined patterns for a sensing area and a wire area; a yellow light process being performed on the substrate; a layer of light resistor thin film being formed on a surfaces of the wire area; and etching the first conductive plating film in the sensing area; by above steps, the predetermined pattern in the sensing area being formed in the second conductive plating film. 1. A method for forming a touch sensing pattern and signal wires , comprising the steps of:installing a first and a second conductive plating films on a surface of a highly transparency substrate;projecting a high energy light beam to the conductive plating films; and the high energy light beam moving with respect to the substrate along a predetermined track; a plurality of insulating trenches being formed in the first and second conductive plating films so as to form predetermined patterns for a sensing area and a wire area;a yellow light process being performed on the substrate; a layer of light resistor thin film being formed on a surfaces of the wire area; andetching the first conductive plating film in the sensing area; by above steps, the predetermined pattern in the sensing area being formed in the second conductive plating film; and the first and second conductive plating films being existed in the wire area with a predetermined pattern.2. The method for forming a touch sensing pattern and signal wires as claimed in claim 1 , wherein the substrate is a plane thin film with a material selected of glass claim 1 , poly carbonic ...

Feed Mixtures for Extraction Process to Produce Rubber Processing Oil

Deasphalted residual oil (DAO) and the aromatics-rich extract that is derived from DAO have low polycyclic aromatics contents, relatively low aniline points, and high flash points. They form blending stocks that improve properties of mixed feedstocks to consistently produce environmentally qualified rubber processing oil (RPO) by extraction under low solvent-to-oil ratios and moderate extraction temperatures. Distilling a petroleum crude oil under atmospheric pressure generates a bottom residual oil which is then subject to vacuum distillation to yield a bottom residual oil. DAO is produced by removing the asphalt from the vacuum bottom residual oil through extraction with light paraffinic solvent. The extract of DAO is a co-product in the production of the bright stock of the lubricating oil through extraction. The feedstock is mixed with the extract from a petroleum fraction boiling in lube oil range. Liquid-liquid counter-current extraction yields a raffinate stream; removal of solvent therefrom produces the RPO. 1. A process for preparing a rubber processing oil (RPO) , having a total aromatics content of more than 50 wt % , (or an aromatic carbon content of more than 20 wt %) , a polycyclic aromatic content of less than 3 wt % , an aniline point that is lower than 80° C. , a kinematic viscosity from 15 to 30 mm/s at 100° C. , and a flash point that is higher than 250° C. , which comprises the steps of:(a) producing a first aromatics-rich extract, from a petroleum fraction boiling in the lube oil range, through solvent extraction with a first polar extractive solvent;(b) producing a second aromatics-rich extract, from a deasphalted residual oil that is derived from vacuum distillation, through solvent extraction with a second polar extractive solvent;(c) mixing the first aromatics-rich extract and the second aromatics-rich extract to yield a mixture that is subject to solvent extraction with a third polar extractive solvent to yield a raffinate phase; and(d) ...

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

ADJUSTABLE JIG FOR RETAINING GLASS PLATE

An adjustable jig for retaining glass plate includes a frame, at least two clamp guides, and a plurality of clamp. The frame has a plurality of symmetric retaining component on two parallel frame columns. The clamp guide has a connecting portion for being retained by the retaining component on two ends of the clamp guide so that the clamp guide can be fixed across the parallel frame columns. The clamp guide has an approximated T-shaped guide on at least one longitudinal side of the clamp guide. The clamp has an approximated T-shaped groove and an approximated V-shaped groove. The T-shaped groove serves to be slid into the T-shaped guide so that the clamp is sliding along the clamp guide for clamping glass of any size or shape The glass will be firmly clamped by multiple clamps through predetermined positions without risk of breakage. 1. An adjustable jig for retaining glass plate comprising:a rectangular frame for being arranged to a platform of a processing machine; the frame having a plurality of retaining component formed symmetrically on a pair of parallel frame column thereof;at least two clamp guides having connecting portion on two ends of the clamp guide; the connecting portion being fixed to the retaining component so that the clamp guide will be fixed across the parallel frame columns; the clamp guide having an approximated T-shaped guide on at least one longitudinal side thereof;a plurality of clamp having an approximated T-shaped groove and an approximated V-shaped groove; the T-shaped groove being slid into the T-shaped guide so that the clamp is sliding along the clamp guide for clamping glass of any size or shape.2. The adjustable jig for retaining glass plate as claimed in claim 1 , wherein the retaining component is a screw and the connecting portion is a screw hole.3. The adjustable jig for retaining glass plate as claimed in claim 1 , wherein the retaining component is a bolt and the connecting portion is a bolt hole.4. The adjustable jig for ...

High Voltage Resistor with High Voltage Junction Termination

Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Power MOSFETs and Methods for Forming the Same

A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate 1. A power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) comprising:a semiconductor substrate;a semiconductor region extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type;a gate dielectric over the semiconductor region;a gate electrode over the gate dielectric;a first drift region extending from the top surface of the semiconductor substrate into the semiconductor substrate, wherein the first drift region is of a second conductivity type opposite the first conductivity type;a dielectric layer comprising a first portion over and in contact with a top surface of the first drift region;a field plate over the dielectric layer, wherein the field plate is conductive, and comprises a first portion over the first portion of the dielectric layer;a source region on a first side of the gate electrode;a drain region on a second side of the gate electrode opposite the first side, wherein the drain region is in contact with the first drift region; anda bottom metal layer over the field plate.2. The power MOSFET of claim 1 , wherein the dielectric layer further comprises a second ...

INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE

A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well. 1. A high voltage semiconductor transistor , comprising:a lightly doped semiconductor substrate having a first type of conductivity;a buried layer in a first portion of the semiconductor substrate having a second type of conductivity;a first well region having the second type of conductivity and formed over the lightly doped semiconductor substrate, the first well region having a lower dopant concentration than the buried layer, the buried layer being partially in the first well region;a second well region in the first well region and having the first type of conductivity, the second well region having a U-shape in a cross section between a drain and source, wherein both ends of the U-shape extends to a top surface of the first well region;a first insulating structure over and partially embedded in the first well region within the U-shape of the second well region and not contacting the second well region;a second insulating structure over a first end of the U-shape of the second well region;a gate structure near the first insulating structure over the first well region and partially over a second end of the U-shape of the second well region;a drain region in the first well region across the first insulating structure from the gate structure, the drain region comprising a first drain portion between the first and second insulating structure and a second drain ...

INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. 1. A high voltage semiconductor transistor , comprising:a lightly doped semiconductor substrate having a first type of conductivity, wherein a portion of the lightly doped semiconductor substrate includes an implanted oxygen layer below a top surface of the lightly doped semiconductor substrate;a first well region having a second type of conductivity and formed over the lightly doped semiconductor substrate;a second well region in the first well region and having the first type of conductivity;an insulating structure over and partially embedded in the first well region and not contacting the second well region;a gate structure near the insulating structure over the first well region;a drain region in the first well region across the insulating structure from the gate structure, the drain region comprising a first drain portion adjacent to the insulating structure anda second drain portion further away from the insulating structure;a source region in the second well region disposed on a side of the gate structure opposite from the drain region; anda deep trench isolation feature in the first well region surrounding the second well region, the insulating structure, the gate structure, the source region, and the first drain portion, wherein the deep trench isolation feature contacts the implanted ...

QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE

A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer. 1. A semiconductor device , comprising:a buried layer having a first dopant type disposed in a substrate;a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer;a first well of a second dopant type disposed in the second layer;a first source region of the first dopant type disposed in the first well and connected to a source contact on one side;a gate disposed on top of the well and the second layer; anda metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer.2. The semiconductor device of claim 1 , wherein the insulation layer has a width of approximately 24 micron.3. The semiconductor device of claim 1 , wherein the insulation layer has an aspect ratio ranges from about 2.08 to about 3.33.4. The semiconductor device of claim 1 , wherein the insulation layer has a height ranging from about 50 μm to about 80 μm.5. The semiconductor device of claim 1 , wherein the metal electrode has a width ranging from about 3 μm ...

TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm. 1. A manufacture , comprising:a doped layer having a first type doping, the doped layer defining a trench therein, and the trench having a bottom surface;a body structure over the doped layer, the body structure having an upper surface and comprising a body region, and the body region having a second type doping different from the first type doping;an insulator partially filling the trench; anda first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator, the first conductive feature extending from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench, the first conductive feature overlapping the doped layer for an overlapping distance,the overlapping distance ranging from 0 to 2 μm.2. The manufacture of claim 1 , wherein the insulator comprises a material including silicon oxide claim 1 , or silicon nitride.3. The manufacture of claim 1 , wherein the first conductive feature comprises a material including polycrystalline silicon claim 1 , copper claim 1 , aluminum claim 1 , copper-aluminum alloy claim 1 , or tungsten.4. The manufacture of claim 1 , wherein a minimum ...

TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING

A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well. 1. A triple well isolated diode comprising:a substrate having a first conductivity type;a buried layer in the substrate, wherein the buried layer has a second conductivity type opposite to the first conductivity type;an epi-layer over the substrate and the buried layer, wherein the epi-layer has the first conductivity type;a first well in the epi-layer, wherein the first well has the second conductivity type;a second well in the epi-layer and surrounding sides of the first well, wherein the second well has the first conductivity type;a third well formed in the epi-layer and surrounding sides of the second well, wherein the third well has the second conductivity type; anda deep well in the epi-layer extending beneath the first well to electrically connect to the second well on opposite sides of the first well, wherein the deep well has the first conductivity type.2. The triple well isolated diode of claim 1 , further comprising:a first contact region electrically connected to the epi-layer in an area of the epi-layer surrounding sides of the third well, wherein the first contact region has the first ...

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC LIGHTLY DOPED DRAIN REGIONS AND METHOD OF MAKING THE SAME

A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. A surface portion of the substrate extending from the source to the drain has an asymmetric dopant concentration profile. 1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:a substrate;a gate structure over a top surface of the substrate;a source in the substrate on a first side of the gate structure; anda drain in the substrate on a second side of the gate structure opposite the first side,wherein a surface portion of the substrate extending from the source to the drain has an asymmetric dopant concentration profile.2. The MOSFET of claim 1 , wherein the gate structure comprises:a gate dielectric layer over the top surface of the substrate;a gate electrode layer over the gate dielectric layer; anda spacer over a sidewall of the gate dielectric layer and the gate electrode layer adjacent to the source;a spacer over a sidewall of the gate dielectric layer and the gate electrode layer adjacent to the drain,wherein a first dopant concentration in the surface portion of the substrate under the spacer adjacent to the source is greater than a second dopant concentration in the surface portion of the substrate under the spacer adjacent to the drain.3. The MOSFET of claim 2 , further comprising a doped body in the substrate claim 2 , the doped body surrounding the source and extending under the spacer adjacent to the source and a portion of the gate dielectric layer.4. The MOSFET of claim 2 , further comprising a lightly doped drain (LDD) region in the substrate claim 2 , the LDD region under the spacer adjacent to the source but not under the gate dielectric layer.5. The MOSFET of claim 2 , further comprising:a first well having a ...

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING VARIABLE THICKNESS GATE DIELECTRIC AND METHOD OF MAKING THE SAME

A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. The gate structure includes a variable thickness gate dielectric layer. The variable thickness gate dielectric layer includes a first portion closest to the drain, the first portion having a first thickness. The variable thickness gate dielectric layer further includes a second portion distal from the drain, the second portion having a second thickness less than the first thickness. 1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:a substrate;a gate structure over a top surface of the substrate;a source in the substrate on a first side of the gate structure; anda drain in the substrate on a second side of the gate structure opposite the first side, a first portion closest to the drain, the first portion having a first thickness; and', 'a second portion distal from the drain, the second portion having a second thickness less than the first thickness., 'wherein the gate structure comprises a variable thickness gate dielectric layer, the variable thickness gate dielectric layer comprising2. The MOSFET of claim 1 , wherein the variable thickness gate dielectric layer further comprises a third portion between the first portion and the second portion claim 1 , the third portion having an intermediate thickness greater than the second thickness and less than the first thickness.3. The MOSFET of claim 1 , wherein a width of the first portion is equal to a width of the second portion.4. The MOSFET of claim 1 , wherein a width of the first portion is different from a width of the second portion.5. The MOSFET of claim 1 , wherein a material of the first portion is a same material as the second portion.6. The MOSFET of claim 1 , ...

TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

A method of forming a manufacture includes forming a trench in a doped layer; and forming a gate dielectric layer along sidewalls of an upper portion of the trench. The method further includes forming a first conductive feature along sidewalls of the gate dielectric layer, wherein the first conductive feature has a first depth in the trench. The method further includes forming an insulating layer covering the first conductive feature and the first insulating layer. The method further includes forming a second conductive feature along sidewalls of the second insulating layer, wherein the second conductive feature has a second depth in the trench different from the first depth.

MOS TRANSISTOR

A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously. 1. A metal-oxide-semiconductor (MOS) transistor in a semiconductor substrate , comprising:a well region of a first conductivity type extending into the semiconductor substrate;a gate dielectric layer over the well region;a gate electrode over the gate dielectric layer; anda source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type in the well region and on opposite sides of the gate electrode, wherein the gate dielectric layer has a first portion and a second portion closest to the source region and the drain region, respectively, wherein the second portion has a thickness greater than a thickness of the first portion.2. The MOS transistor of claim 1 , further comprising a first spacer and a second spacer claim 1 , wherein the first spacer is positioned on a sidewall of the first portion and the gate electrode and substantially aligned with one edge of the source region claim 1 , the second spacer is positioned on a sidewall of the second portion and the gate electrode and substantially aligned with one edge of the drain region.3. The MOS transistor of claim 2 , ...

MOS TRANSISTOR AND METHOD FOR MANUFACTURING MOS TRANSISTOR

A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability. 1. A MOS transistor in a semiconductor substrate , the MOS transistor comprising:a source region of a first conductivity type and a drain region of the first conductivity type in the semiconductor substrate;a channel region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate between the source region and the drain region;an isolation region adjacent to the drain region;a drift region of the first conductivity type laterally adjacent to the channel region and beneath the isolation region and the drain region;a gate dielectric layer over the channel region and extending over the drift region;a gate electrode over the gate dielectric layer having a first portion and a second portion, wherein the first portion of the first conductivity type is over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region, and the second portion is un-doped and over the isolation region; anda field plate contacting an upper surface of the gate electrode, wherein the field plate comprises polycide.2. The MOS transistor of claim 1 , wherein the gate electrode and the field plate are substantially identical in pattern.3. The MOS transistor of claim 1 , wherein the width of the first portion is less than a sum of the distance of the gate ...

METHOD OF MAKING AN INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE

A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region. 1. A method for fabricating a high voltage semiconductor transistor , comprising:forming a buried layer having a second type of conductivity in a portion of a semiconductor substrate, wherein the semiconductor substrate has a first type of conductivity;epitaxially growing a doped first well region over the substrate, the first well region having the second type of conductivity different from the first type of conductivity;doping a first portion and a third portion of a second well region having the first type of conductivity in the first well region, the first portion and the third portion occupying a region starting from the top surface of the first well region and extending down in the first well region;doping a second portion of the second well region in the first well region, the second portion extending laterally from the first portion to the third portion under the top surface of the first well region, wherein the first portion, the second portion, and the third portion of the second well form a U-shaped second well region;thermally growing a first insulating layer in and over the first portion within the U-shape of ...

JFET STRUCTURE AND MANUFACTURING METHOD OF THE SAME

The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure. 1. A transistor structure , comprising a source and a drain of a first conductive type;', 'a channel between the source and the drain; and', 'a polysilicon contact over and aligned with the channel; and, 'a self-aligned source-drain structure surrounded by an insulating structure, comprisinga gate of a second conductive type separated from the source and the drain by the insulating structure.2. The transistor structure of claim 1 , further comprising:a substrate of the second conductive type;an isolation layer of the first conductive type embedded in the substrate;a first well of the second conductive type over the isolation layer; anda second well of the first conductive type in connection with the first well and between the source and the drain.3. The transistor structure of claim 2 , further comprising:a third well of the second conductive type in connection with the second well and between the source and the drain, the third well being in contact with the polysilicon contact.4. The transistor structure of claim 1 , further comprising:a substrate of the first conductive type;a first well of the second conductive type in the substrate; anda second well of the first conductive type in connection with the first well and between the source and the drain.5. The transistor structure of claim 2 , wherein a dopant concentration of the isolation layer is greater than a dopant concentration of the second well.6. The transistor ...

THIN MOBILE DEVICE WITH METAL INDUCTION SHEET ON REAR HOUSING FOR DETECTING HUMAN OR OBJECT APPROACHING

A mobile device with integral radiation shielding includes a body, a rear housing, and a metal induction sheet. The body includes therein a circuit board, an antenna, and a capacitive proximity sensor circuit. The rear housing covers the body. The metal induction sheet is formed directly on the rear housing as a single part. The metal induction sheet doesn't add extra space, enabling the manufacture of very thin mobile device. 1. A mobile device comprising:a body comprising therein a circuit board, an antenna, and a capacitive proximity sensor circuit;a rear housing covering the body; anda metal induction sheet formed directly on the rear housing.2. The mobile device of claim 1 , wherein the rear housing has a bottom cover on which the metal induction sheet is formed.3. The mobile device of claim 1 , wherein the metal induction sheet is located adjacent the antenna.4. The mobile device of claim 2 , wherein the metal induction sheet is located adjacent the antenna.5. The mobile device of claim 3 , wherein the metal induction sheet is U-shaped.6. The mobile device of claim 4 , wherein the metal induction sheet is U-shaped.7. The mobile device of claim 1 , wherein the rear housing has a bottom cover and a frame side wall extending around the bottom cover claim 1 , and the metal induction sheet is formed on of the frame side wall.8. The mobile device of claim 7 , wherein the metal induction sheet is located adjacent a top of the antenna.9. The mobile device of claim 8 , wherein the metal induction sheet is in rectangular shape.10. The mobile device of claim 1 , wherein the rear housing has a bottom cover and a frame side wall extending around a periphery of the bottom cover claim 1 , the frame side wall is made of a metal material claim 1 , at least one pair of non-metal strips are provided on the frame side wall claim 1 , and the metal induction sheet comprises each metal portion of the frame side wall between each two spaced apart non-metal strips.11. The mobile ...

ULTRAHIGH-VOLTAGE SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein. 1. A semiconductor structure capable of ultrahigh-voltage (UHV) operation , comprising: a semiconductor substrate;', 'a first semiconductor well positioned in the semiconductor substrate;', 'a second well positioned in the first semiconductor well;', 'a third semiconductor well and a fourth semiconductor well positioned in the second semiconductor well; and', 'a first electrode electrically connected to the third semiconductor well;, 'a first electrical portion comprising a fifth semiconductor well positioned in the semiconductor substrate;', 'at least one semiconductor layer positioned in the fifth semiconductor well;', 'a sixth semiconductor well and a seventh semiconductor well positioned in the fifth semiconductor well, wherein the sixth semiconductor well and the seventh semiconductor well are isolated by the semiconductor layer; and', 'a second electrode electrically connected to the seventh semiconductor well; and, 'a second electrical portion comprisinga bridged conductive layer directly connected between the fourth semiconductor well of the first electrical portion and the sixth semiconductor well of the second electrical portion,wherein the first electrical portion and the second electrical portion are isolated to each other.2. The semiconductor structure of claim 1 , further comprising a bias applied to the first semiconductor well of the first electrical portion claim 1 , so that the first semiconductor well is biased.3. The ...

Backlight Module and Switching Method thereof

A backlight module for a display device includes a clock generation module for generating a clock signal, a control module for generating a control signal and a selection control signal, a selection module coupled to the clock generation module and the control module for generating a selection result according to the clock signal and the control signal, and an output module coupled to the selection module for outputting the selection result according to the selection control signal, wherein the selection result controls the display device to be operated in a normal backlight mode, a transition mode or a flashing backlight mode. 1. A backlight module for a display device , comprising:a clock generation module for generating a clock signal;a control module for generating a control signal and a selection control signal;a selection module coupled to the clock generation module and the control module for generating a selection result according to the clock signal and the control signal; andan output module coupled to the selection module for outputting the selection result according to the selection control signal;wherein the selection result controls the display device to be operated in a normal backlight mode, a transition mode or a flashing backlight mode.2. The backlight module of claim 1 , wherein the selection module further comprises a normal backlight mode unit for generating a normal backlight mode signal to the output module according to the clock signal and the control signal claim 1 , such that the output module switches the display device to be operated in the normal backlight mode.3. The backlight module of claim 1 , wherein the selection module further comprises a flashing backlight mode unit for generating a flashing backlight mode signal to the output module according to the clock signal and the control signal claim 1 , such that the output module switches the display device to be operated in the flashing backlight mode.4. The backlight module of claim 1 ...

QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. 1. A semiconductor device , comprising:a buried layer in a substrate, the buried layer having a first dopant type;a first layer over the buried layer, the first layer having the first dopant type;at least one first well in the first layer, the at least one first well having a second dopant type; andan implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well.2. The semiconductor device of claim 1 , wherein a dopant concentration of the implantation region ranges from about 1E15 atoms/cmto about 1E17 atoms/cm.3. The semiconductor device of claim 1 , wherein the at least one first well includes:a first p-well in contact with the implantation region; anda second p-well spaced from the first p-well.4. The semiconductor device of claim 3 , further comprising a gate structure over the first p-well and the second p-well.5. The semiconductor device of claim 1 , further comprising a first highly doped region in the at least one first well claim 1 , wherein the first highly doped region has the first dopant type.6. The semiconductor device of claim 5 , further comprising a second highly doped region in the at least one first well claim 5 , wherein the second highly doped region has the second dopant type claim 5 , and a dopant concentration of the second highly doped ...

FORCE SENSOR DEVICE AND METHOD FOR DETECTING FORCE BASED ON TEMPORAL OR SPATIAL DIFFERENTIAL IMAGE

A force sensor device includes a first structure component, an optical sensor, and a flexible structure component. The optical sensor is disposed on the first structure component. The flexible structure component has a convex portion, and the flexible structure component is assembled with the first structure component to form a chamber in which the optical sensor is disposed. The optical sensor senses light ray transmitted from the flexible structure component to at least one pixel unit to generate at least one differential image and then detects a user's control force applied for the flexible structure component according to the at least one differential image. Differential image is temporal differential image, generated from successive pixel values of a single pixel unit, or is spatial differential image, generated based on temporal differential images of at least two neighboring pixel units.

METHOD OF MAKING TRIPLE WELL ISOLATED DIODE

A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer. 1. A method of making a triple well isolated diode comprising:forming a buried layer in a substrate, wherein the buried layer has a second conductivity type and the substrate has a first conductivity type opposite to the second conductivity type;forming an epi-layer over the substrate and the buried layer, wherein the epi-layer has the first conductivity type;forming a first well in the epi-layer, wherein the first well has the second conductivity type, wherein the first well forms an interface with the buried layer;forming a second well in the epi-layer, wherein the second well has the first conductivity type and surrounds the first well;forming a third well in the epi-layer, wherein the third well has the second conductivity type and surrounds the second well, and a surface of the third well closest to the substrate is coplanar with a surface of the second well closest to the substrate;forming a deep well in the epi-layer, wherein the deep well has the first conductivity type and extends beneath the first well to electrically connect to the second well on both sides of the first well;forming a first ...

Method of forming high voltage device

A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

SEMICONDUCTOR ISOLATION STRUCTURE AND METHOD FOR MAKING THE SEMICONDUCTOR ISOLATION STRUCTURE

A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer. 1. A semiconductor isolation structure comprising:a handle layer;a buried insulation layer that is disposed on the handle layer;a semiconductor layer that is disposed on the buried insulation layer and that has a first doping type, the semiconductor layer having a functional area in which doped regions of a semiconductor device are to be formed;a deep trench isolation structure that penetrates the semiconductor layer and the buried insulation layer, and that surrounds the functional area; anda first heavy doping region that is formed in the semiconductor layer, that is disposed between the functional area and the deep trench isolation structure, and that is surrounded by the deep trench isolation structure, the first heavy doping region having the first doping type, a doping concentration of the first heavy doping region being higher than that of the semiconductor layer.2. The semiconductor isolation structure as claimed in claim 1 , wherein:the deep trench isolation structure has a first side wall that faces the functional area; andthe first heavy doping region ...

DEVICE AND METHOD FOR OPERATING THE SAME

A device includes first wires, second wires, resistors, and a processor. Input signals are transmitted from the first wires through the resistors to the second wires. The processor receives a sum value of the input signals from one of the second wires, and shifts the sum value by a nonlinear activation function to generate a shifted sum value. The processor calculates a backpropagation value based on the shifted sum value and a target value, and generates a pulse number based on a corresponding input signal of the input signal and the backpropagation value. Each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value. The processor applies a voltage pulse to one of the resistors related to the corresponding input signal based on the pulse number. 1. A memory-based device , comprising:a plurality of first wires;a plurality of second wires arranged across the plurality of first wires;a plurality of resistors, wherein each of the plurality of resistors is coupled to one of the plurality of first wires and one of the plurality of second wires, wherein a plurality of input signals are transmitted from the plurality of first wires through the plurality of resistors to the plurality of second wires; anda processor configured to receive a sum value of the input signals from one of the plurality of second wires, and shift the sum value by a nonlinear activation function to generate a shifted sum value, wherein the processor is configured to calculate a backpropagation value based on the shifted sum value and a target value related to a corresponding input signal of the plurality of input signals, and generate a pulse number based on the corresponding input signal of the plurality of input signals and the backpropagation value, wherein each of a value of the corresponding input signal and the backpropagation value is higher than or equal to a threshold value, wherein the processor is configured to apply a voltage ...

SEMICONDUCTOR DEVICE HAVING MULTIPLE WELLS AND METHOD OF MAKING

A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type. 1. A semiconductor device comprising:a substrate;a gate structure over the substrate;a source in the substrate on a first side of the gate structure;a drain in the substrate on a second side of the gate structure;a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source;a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain; anda deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well.2. The semiconductor device of claim 1 , wherein the deep well has a second dopant type claim 1 , and the second dopant type is opposite the first dopant type.3. The semiconductor device of claim 1 , wherein the second well contacts at least two surfaces of the first well.4. The semiconductor device of claim 1 , wherein the gate structure comprises a variable thickness gate dielectric layer.5. The semiconductor device of claim 1 , wherein an uppermost surface of the second well between the drain and the first well is coplanar ...

QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE

A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer. 1. A semiconductor device , comprising:a buried layer in a substrate, the buried layer having a first dopant type;a first layer over the buried layer, the first layer having the first dopant type;at least one first well in the first layer, the at least one first well having a second dopant type;an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well; anda metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.2. The semiconductor device of claim 1 , wherein a bottom surface of the implantation region is spaced from a top surface of the buried layer.3. The semiconductor device of claim 1 , wherein a bottom surface of the implantation region contacts a top surface of the buried layer.4. The semiconductor device of claim 1 , wherein a breakdown voltage of the semiconductor device is greater than 850 volts (V).5. The semiconductor device of claim 1 , wherein a dopant concentration in the implantation ...

QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE

A semiconductor device includes a buried layer having a first dopant type in a substrate. The semiconductor device includes a first layer having the first dopant type over the buried layer. The semiconductor device includes at least one first well of a second dopant type disposed in the first layer. The semiconductor device includes an implantation region of the second dopant type in a sidewall of the first layer, wherein the implantation region is below the at least one first well. The semiconductor device includes a first source region disposed in the at least one first well; and at least one gate disposed on top of the first well and the first layer. The semiconductor device includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer. 1. A semiconductor device , comprising:a buried layer in a substrate, the buried layer having a first dopant type;a first layer over the buried layer, the first layer having the first dopant type;at least one first well in the first layer, the at least one first well having a second dopant type;an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well;a first source region disposed in the at least one first well;at least one gate disposed on top of the first well and the first layer; anda metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.2. The semiconductor device of claim 1 , wherein a dopant concentration of the implantation region ranges from 1E15 atoms/cmto 1E17 atoms/cm.3. The semiconductor device of claim 1 , wherein the implantation region extends along an entirety of a sidewall of the first layer below the at least one first well.4. The ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed. 1. A method for fabricating a semiconductor structure , the method comprising:providing a substrate;forming a gate structure over the substrate;forming a field plate at least partially over the substrate;forming a source region and a drain region in the substrate on either side of the gate structure; andcoupling the field plate to the source region or a bulk electrode of the substrate.2. The method of claim 1 , further comprising:forming a semiconductor fin over the substrate.3. The method of claim 1 , wherein a distance between the gate structure and the field plate is in a range from about 0 to about 200 nm.4. The method of claim 1 , further comprising:forming a well region having the first type of conductivity in the substrate, wherein the well region is substantially self-aligned to an edge of the gate structure; andthe formation of the drain region in the substrate includes:disposing the drain region in the well region.5. The method of claim 1 , further comprising:forming a well region having the first type of conductivity in the substrate to at least partially overlap the gate structure; andthe formation of the drain region in the substrate includes:disposing the drain region in the well region.6. The method of claim 1 , wherein the field plate includes a doped polycrystalline silicon (or polysilicon).7. The method of claim 1 , wherein the field plate includes a metal.8. The method of ...

SEMICONDUCTOR DEVICE HAVING MULTIPLE WELLS

A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well. 1. A semiconductor device comprising:a substrate;a gate structure over a top surface of the substrate;a source in the substrate on a first side of the gate structure;a drain in the substrate on a second side of the gate structure;a first well having a first dopant type, wherein the first well surrounds the source;a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.2. The semiconductor device of claim 1 , wherein the gate structure comprises a variable thickness gate dielectric layer.3. The semiconductor device of claim 1 , wherein the source is a split source.4. The semiconductor device of claim 1 , further comprising a lightly doped drain (LDD) region extending from the source claim 1 , wherein the LDD region is in the first well.5. The semiconductor device of claim 1 , further comprising a deep well below the first well and below the second well.6. The semiconductor device of claim 1 , wherein the first well directly ...

TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. 1. A method of forming a manufacture , the method comprising:forming a first trench in a doped layer, the first trench having an upper portion and a lower portion, a width of the upper portion being greater than a width of the lower portion;forming a first insulating layer along sidewalls of the lower portion of the first trench and a bottom surface of the first trench;forming a gate dielectric layer along sidewalls of the upper portion of the first trench;forming a first conductive feature along sidewalls of the gate dielectric layer;forming a second insulating layer covering the first conductive feature and the first insulating layer; andforming a second conductive feature along sidewalls of the second insulating layer and a bottom surface of the second insulating layer.2. The method of claim 1 , wherein a first distance from a lower end of the first conductive feature to the bottom surface of the second insulating layer is 50% to 95% of a second distance from the lower end of the first conductive feature to the bottom surface of the first trench.3. The method of claim 1 , wherein the gate dielectric structure is formed to a thickness of 5 nm to 100 nm.4. The method of claim 1 , wherein the second insulating layer is formed to a ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well. 1. A semiconductor structure , comprising:a semiconductor substrate having a first electrical portion and a second electrical portion; a first semiconductor well;', 'a second semiconductor well positioned in the first semiconductor well;', 'a third semiconductor well and a fourth semiconductor well positioned in the second semiconductor well; and', 'a first electrode electrically connected to the third semiconductor well;, 'the first electrical portion comprising a fifth semiconductor well;', 'a semiconductor layer positioned in the fifth semiconductor well, wherein the semiconductor layer has a first portion and a second portion, and the first portion is separated from the second portion by a portion of the fifth semiconductor well;', 'a sixth semiconductor well and a seventh semiconductor well positioned in the fifth semiconductor well, wherein the second portion of the semiconductor layer is between the sixth semiconductor well and the seventh semiconductor well; and', 'a second electrode electrically connected to the seventh semiconductor well; and, 'the second electrical portion comprisinga bridged conductive layer connecting the fourth semiconductor well of the first electrical portion and the sixth ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a substrate;a gate structure formed over the substrate;a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity;a field plate formed over the substrate between the gate structure and the drain region; anda well region in the substrate, the well region having the first type of conductivity and being self-aligned to an edge of the gate structure;wherein the drain region is disposed in the well region, and the field plate is coupled to the source region or a bulk electrode of the substrate.2. The semiconductor structure of claim 1 , wherein the semiconductor structure further comprises a semiconductor fin claim 1 , and the gate structure is formed over the semiconductor fin.3. The semiconductor structure of claim 1 , wherein a distance between the gate structure and the field plate is in a range from about 0 to about 200 nm.4. (canceled)5. (canceled)6. The semiconductor structure of claim 1 , wherein the field plate includes a doped polycrystalline silicon (or polysilicon).7. The semiconductor structure of claim 1 , wherein the field plate includes a metal.8. The semiconductor structure of claim 1 , wherein an isolation feature structure is formed between the gate structure and the drain region.9. The semiconductor structure of claim 1 , ...

HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. 1. A transistor structure comprising:a gate electrode having straight portions and a curved portion, a source region disposed outside said gate electrode;a drain region formed inside said gate electrode;a dielectric disposed between said gate electrode and said drain region; and,a plurality of isolated floating conductor leads disposed at least one of in and on said dielectric, said isolated floating conductor leads each having straight portions and a curved portion and formed at multiple device levels such that portions of said isolated floating conductor leads formed at one device level directly overlap portions of said isolated floating conductor leads formed at another device level.2. The transistor structure as in claim 1 , wherein said drain region is spaced from claim 1 , and surrounded by claim 1 , said gate electrode and said straight portions of said gate electrode are parallel to one another.3. The transistor structure as in claim 1 , wherein said source region and said drain region are formed in a substrate having a top surface and further comprising a field oxide region formed in and above said top ...

Power MOSFETs and Methods for Forming the Same

Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. 1. A method comprising:forming a gate structure over a first region, the first region being of a first conductivity type and having a first impurity concentration, the gate structure comprising a gate dielectric and a gate electrode;implanting a second region of the first conductivity type into the first region, the second region having a second impurity concentration;implanting a first drift region of a second conductivity type into the first region, the second conductivity type being opposite to the first conductivity type, the first drift region having a third impurity concentration;implanting a second drift region of the second conductivity type into the first region through the gate structure, the second drift region having the third impurity concentration, the second drift region being entirely beneath the gate electrode, the second drift region abutting the first drift region, a depth of the second drift region being less than a depth of the first drift region;implanting a source region of the second conductivity type into the second region; andimplanting a drain region of the second conductivity type into the first drift region.2. The method of claim 1 , wherein the first drift region and the second drift ...

HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAWKDOWN VOLTAGES

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. 1. A transistor structure comprising:a gate electrode,a source region disposed outside said gate electrode;a drain region formed inside said gate electrode;a dielectric disposed between said gate electrode and said drain region; and,a plurality of isolated floating conductor leads disposed-in or on, or both in and on said dielectric, said plurality of isolated floating conductor leads disposed at multiple device levels such that at least some of said isolated floating conductor leads disposed at one device level cross completely over portions of said isolated floating conductor leads disposed at another device level.2. The transistor structure as in claim 1 , wherein said drain region is spaced from claim 1 , and surrounded by claim 1 , said gate electrode and said straight portions of said gate electrode are parallel to one another.3. The transistor structure as in claim 1 , wherein said source region and said drain region are formed in a substrate having a top surface and further comprising a field oxide region formed in and above said top surface claim 1 , said field oxide region extending from said gate ...

HOUSING ASSEMBLY AND ELECTRONIC DEVICE USING THE SAME

A housing assembly of an electronic device includes an outer housing, an inner housing mounted to the outer housing, a first waterproof film positioned between the outer housing and the inner housing, and a second waterproof film spaced from the first waterproof film. The first waterproof film, the outer housing, and the inner housing cooperatively define a first cavity of the housing assembly. The second waterproof film, the inner housing, and the first waterproof film cooperatively form a second cavity of the housing assembly. The first and second waterproof films provide the housing assembly an excellent waterproof property. The electronic device using the housing assembly is also described. 1. A housing assembly , comprising:an outer housing;an inner housing mounted to the outer housing;a first waterproof film positioned between the outer housing and the inner housing to define a first cavity with the outer housing and the inner housing; anda second waterproof film spaced from the first waterproof film , the second waterproof film, the inner housing, and the first waterproof film cooperatively forming a second cavity.2. The housing assembly as claimed in claim 1 , wherein the outer housing defines a plurality of first sound holes at one end of the outer housing claim 1 , the inner housing defines a first receiving chamber at one end of the inner housing claim 1 , towards the outer housing and communicating with the plurality of first sound holes.3. The housing assembly as claimed in claim 2 , wherein two first shoulders protrude from two sidewalls of the first receiving chamber claim 2 , the first waterproof film is attached on the first shoulders and faces the first sound holes claim 2 , the first waterproof film is positioned between the first shoulders and the outer housing so as to define the first cavity.4. The housing assembly as claimed in claim 2 , wherein the outer housing defines a plurality of second sound holes at another end of the outer housing ...

High voltage resistor with high voltage junction termination

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING

A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well. 1. A triple well isolated diode comprising:a substrate having a first conductivity type;a buried layer in the substrate, wherein the buried layer has a second conductivity type opposite to the first conductivity type;an epi-layer over the substrate and the buried layer, wherein a portion of the epi-layer having the first conductivity type is in contact with the buried layer;a first well in the epi-layer, wherein the first well has the second conductivity type;a second well in the epi-layer and surrounding sides of the first well, wherein the second well has the first conductivity type;a third well formed in the epi-layer and surrounding sides of the second well, wherein the third well has the second conductivity type; anda deep well in the epi-layer extending beneath the first well to electrically connect to the second well on opposite sides of the first well, wherein the deep well has the first conductivity type.2. The triple well isolated diode of claim 1 , further comprising:a first contact region electrically connected to the epi-layer in an area of the epi-layer surrounding sides of the third well, ...

High Voltage Resistor with High Voltage Junction Termination

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

NEURAL NETWORK PROCESSING SYSTEM

A neural network processing system includes at least one synapse and a neuron circuit. The synapse receives an input signal and has an external weighted value and an internal weighted value, and the internal weighted value has a variation caused by an external stimulus. When the variation of the internal weighted value accumulates to a threshold value, the external weighted value varies and the input signal is multiplied by the external weighted value of the synapse to generate a weighted signal. A neuron circuit is connected with the synapse to receive the weighted signal transmitted by the synapse, and calculates and outputs the weighted signal. The present invention can simultaneously accelerate the prediction and learning functions of the deep learning and realize a hardware neural network with high precision and real-time learning. 1. A neural network processing system comprising:at least one synapse receiving at least one input signal and having an external weighted value and an internal weighted value, and said internal weighted value has a variation caused by an external stimulus, and when said variation of said internal weighted value accumulates to a threshold value, said external weighted value varies and said at least one input signal is multiplied by said external weighted value of said at least one synapse to generate at least one weighted signal; anda neuron circuit connected with said at least one synapse to receive said weighted signal transmitted by said at least one synapse, and calculating and outputting said at least one weighted signal.2. The neural network processing system according to claim 1 , wherein said external weighted value is obtained by electrical measurement.3. The neural network processing system according to claim 2 , wherein said electrical measurement is measurement of resistance claim 2 , capacitance claim 2 , inductance or impedance.4. The neural network processing system according to claim 1 , wherein said internal weighted ...

Production system and method for location-aware environment

The present invention discloses a production system and method for location-aware environment. The method comprises the following steps: making each of the gateways sense a test RS SI corresponded to a test position of the end device; obtaining a corresponded reference GPS parameter through finding corresponding data of the fingerprint positioning database according to the test RSSI; and determining the selected area is a location-aware completed area if a difference between the reference GPS parameter and the real GPS parameter is smaller than or equal to a preset error.

Triple well isolated diode and method of making

A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well.

Triple well isolated diode and manufacturing method thereof and semiconductor device

Method and apparatus of locating programs in a frequency band

A method for searching a frequency band to locate a program. The method includes the steps of setting an initial frequency and a first crequeney step; determining a frequency point based on the initial frequency and the first frequency step; determining whether the frequency point satisfies a first condition, which is continuously detecting a horizontal signal a predetermined number of times. When the first condition is satisfied, the frequency point is recorded as an entrance point. A second frequency step based on the entrance point determines a second frequency point, wherein the second frequency step is less than the first frequency step. It is then determined if a program exists at the second frequency point. The entrance point is recorded as the updated initial frequency for the next search. The described steps are repeated for the entire frequency band.

Feed mixtures for extraction process to produce rubber processing oil

Deasphalted residual oil (DAO) and the aromatics-rich extract that is derived from DAO have low polycyclic aromatics contents, relatively low aniline points, and high flash points. They form blending stocks that improve properties of mixed feedstocks to consistently produce environmentally qualified rubber processing oil (RPO) by extraction under low solvent-to-oil ratios and moderate extraction temperatures. Distilling a petroleum crude oil under atmospheric pressure generates a bottom residual oil which is then subject to vacuum distillation to yield a bottom residual oil. DAO is produced by removing the asphalt from the vacuum bottom residual oil through extraction with light paraffinic solvent. The extract of DAO is a co-product in the production of the bright stock of the lubricating oil through extraction. The feedstock is mixed with the extract from a petroleum fraction boiling in lube oil range. Liquid-liquid counter-current extraction yields a raffinate stream; removal of solvent therefrom produces the RPO.

Feed mixtures for extraction process to produce rubber processing oil

Method and apparatus of locating programs in a frequency band

Semi-interpenetrating network hydrogel polymer, method for manufacturing the same, and cement composition containing the same

Camera systems for tracking target objects

An example camera system for tracking a target object within a coverage area, the camera system includes: a camera having a primary field of view; a plurality of auxiliary sensors, each auxiliary sensor to generate auxiliary sensor data representing a respective auxiliary field of view of at least a portion of the coverage area; a controller to: obtain the auxiliary sensor data from each of the auxiliary sensors; and determine, based on the auxiliary sensor data, a location of the target object within the coverage area; and a motor connected to the camera to rotate the camera to locate the target object within the primary field of view.

Semiconductor device having multiple wells

A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

電晶體及其製造方法

電晶體包含一具有溝槽於其中之摻雜層、一基體結構位於此摻雜層上、一絕緣體部分覆蓋此溝槽、及一第一導電元件埋藏於此摻雜層及此基體結構中並藉由一絕緣體與此此摻雜層及此基體結構相隔。此摻雜層具有第一摻雜型態。此基體結構具有一上表面及包含一基體區。此基體區具有一不同於第一摻雜型態之第二摻雜型態。此溝槽具有一底表面。此第一導電元件自一實質上與此基體結構之上表面齊平之位置朝此溝槽之底表面延伸。此第一導電元件與此摻雜層重疊而具有一重疊距離，且此重疊距離為0至2 μm。

Method of making an insulated gate bipolar transistor structure

A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.

Layout to reduce noise in semiconductor devices

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Task dispatching method and system for electrophoretic display (epd) tag devices

A task dispatching method for EPD tag devices includes: receiving a task command; the server system forwarding the task command to a target router to which the target EPD tag device is connected; the target router checking whether the target EPD tag device is currently connected thereto; when it is determined that the target EPD tag device is not currently connected to the target router, the target router notifying the server system that the target EPD tag device is offline; in response to receiving an online notification indicating that the target EPD tag device is connected to another router, the server system updating a connection list accordingly, and forwarding the task command to an updated target router; and when it is determined that the target EPD tag device is currently connected to the target router, the target router delivering the task command to the target EPD tag device.