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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 362. Отображено 170.
18-03-2021 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK

Номер: US20210082903A1
Автор: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU, YOUNG CHARLES CHEW-YUEN, CHEN CHIH-LIANG, LAI CHIH-MING, TZENG JIANN-TYNG, CHEN SHUN-LI, SIO KAM-TOU, PENG SHIH-WEI, CHEN CHUN-KUANG, LIU RU-GUN, YOUNG, Charles Chew-Yuen, CHEN, Chih-Liang, LAI, Chih-Ming, TZENG, Jiann-Tyng, CHEN, Shun-Li, SIO, Kam-Tou, PENG, Shih-Wei, CHEN, Chun-Kuang, LIU, Ru-Gun
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region. 1. A method , comprising:arranging a first gate structure extending continuously above a first active region and a second active region of a substrate;arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; andarranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.2. The method of claim 1 , further comprising:arranging a second separation spacer disposed on a second gate structure to isolate an electronic signal transmitted through a third gate via and a fourth gate via that are disposed on the second gate structure.3. The method of claim 2 , wherein the first to fourth gate via are disposed outside a non-active region arranged between the first active region and the ...

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Номер записи: 1
07-09-2017 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20170256484A1
Автор: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN, SHEN MENG-HUNG, CHEN CHIH-LIANG, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, SIO KAM-TOU, LIN WEI-CHENG, SHEN Meng-Hung, CHEN Chih-Liang, YOUNG Charles Chew-Yuen, TZENG Jiann-Tyng, SIO Kam-Tou, LIN Wei-Cheng
Принадлежит:

A semiconductor structure is disclosed that includes a semiconductor structure includes an active area, a first conductive line, a conductive via, a first conductive metal segment coupled to the conductive line through the conductive via, a second conductive metal segment disposed over the active area, and a local conductive segment configured to couple the first conductive metal segment and the second conductive metal segment. 1. A semiconductor structure , comprising:a first active area;a first conductive line;a first conductive via;a second conductive via;a first conductive metal segment electrically coupled to the first conductive line through the first conductive via;a second conductive metal segment disposed over the first active area and electrically coupled to the first conductive line through the second conductive via; anda first conductive segment configured to electrically couple the first conductive metal segment and the second conductive metal segment,wherein the first conductive line and the first conductive segment are disposed at two sides of the first conductive via respectively.2. The semiconductor structure of claim 1 , further comprising:a gate disposed over the first active area and disposed under the first conductive segment.3. The semiconductor structure of claim 2 , wherein the gate is disposed between the first conductive metal segment and the second conductive metal segment.4. The semiconductor structure of claim 2 , wherein a height of the first conductive segment plus a height of the gate is substantially equal to a height of the second conductive metal segment.5. The semiconductor structure of claim 1 , wherein a height of the first conductive metal segment is greater than a height of the second conductive metal segment.6. The semiconductor structure of claim 1 , wherein a current path is formed from the first conductive line through the second conductive via to the second conductive metal segment claim 1 , and another current path is ...

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Номер записи: 2
04-01-2024 дата публикации

POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS

Номер: US20240006318A1
Автор: Chih-Liang CHEN, Guo-Huei WU, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
Принадлежит:

A method includes fabricating a first-type active-region semiconductor, depositing a layer of dielectric material covering the first-type active-region semiconductor structure, and fabricating a second-type active-region semiconductor structure atop the layer of dielectric material. The method includes forming a front-side power rail and a front-side signal line extending in the first direction in a front-side metal layer overlying a first insulating material that covers the first-type active-region semiconductor. The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure. The method includes forming a back-side metal layer on a backside of the substrate, and forming a back-side power rail and a back-side signal line extending in the first direction in the back-side metal layer. The back-side power rail is conductively connected to a first source conductive segment intersecting the first-type ...

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Номер записи: 3
31-05-2018 дата публикации

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

Номер: US20180151559A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Yi-Hsun CHIU
Принадлежит:

An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants. 1. An integrated circuit structure comprising: a first dopant type;', 'a first portion extending in a first direction and having a first width, and', 'a second portion adjacent to the first portion, the second portion extending in the first direction and having a second width greater than the first width;, 'a first well, the first well comprisinga first set of implants in the first portion of the first well, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage, anda second set of implants in the second portion of the first well, each implant of the second set of implants having a second dopant type different from the first dopant type and being separated from each other in the first direction, and the second set of implants being separated from the first set of implants in a second direction different from the first direction.2. The integrated circuit structure of claim 1 , further comprising:a second well adjacent to the second portion of the first well, the second well having the second dopant type and a third width, the second well ...

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Номер записи: 4
28-03-2024 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20240104288A1
Автор: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
Принадлежит:

A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

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Номер записи: 5
30-12-2021 дата публикации

MULTI-BIT STRUCTURE

Номер: US20210407986A1
Автор: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.

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Номер записи: 6
15-06-2023 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK

Номер: US20230187434A1
Автор: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

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Номер записи: 7
24-10-2019 дата публикации

SYSTEM FOR AND METHOD OF FABRICATING AN INTEGRATED CIRCUIT

Номер: US20190325109A1
Автор: Wei-Cheng LIN, Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Shih-Wei PENG, Wei-Chen CHIEN, LIN WEI-CHENG, CHEN CHIH-LIANG, LAI CHIH-MING, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, SIO KAM-TOU, LIU RU-GUN, PENG SHIH-WEI, CHIEN WEI-CHEN, LIN, Wei-Cheng, CHEN, Chih-Liang, LAI, Chih-Ming, YOUNG, Charles Chew-Yuen, TZENG, Jiann-Tyng, SIO, Kam-Tou, LIU, Ru-Gun, PENG, Shih-Wei, CHIEN, Wei-Chen
Принадлежит:

A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias. 1. A method of fabricating an integrated circuit , the method comprising:defining a via grid having a first minimum pitch in a first direction and a second minimum pitch in a second direction different from the first direction;generating a first layout design of the integrated circuit based on at least the via grid or design criteria, the first layout design having a first set of vias arranged in first rows and first columns based on the via grid, the first rows of the first set of vias being arranged in the first direction, the first columns of the first set of vias being arranged in the second direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set;generating a standard cell layout design of the integrated circuit, the standard cell layout design having standard cells and a second set of vias arranged in the standard cells;generating a via color ...

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Номер записи: 8
18-11-2021 дата публикации

SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS AND METHOD OF MAKING THE SAME

Номер: US20210358847A1
Автор: Chih-Liang CHEN, Guo-Huei WU, Li-Chun TIEN
Принадлежит:

A semiconductor device, includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as a ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

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Номер записи: 9
28-06-2018 дата публикации

DESKTOP LIFTABLE PLATFORM

Номер: US20180177289A1
Автор: Chih-Liang CHEN
Принадлежит:

A desktop liftable platform has a base, a supporting frame, a platform, and a driving device. The base has two side beams and two connecting beams. The supporting frame is connected to the base and has two pivot arms. The pivot arms are respectively connected to the side beams. The platform is connected to the pivot arms of the supporting frame over the base. The driving device is connected to the base and the platform, and has a swing arm and a driving cylinder. The swing arm is pivotally connected to one of the connecting beams and is pivotally connected to the platform. The driving cylinder is pivotally connected to the other one of the connecting beams and has a driving shaft pivotally connected to the swing arm. Then, the platform may move relative to the base by the driving shaft pushing or pulling the swing arm. 1. A desktop liftable platform comprising: two side beams being parallel with each other at a spaced interval, and each one of the side beams having a rear end, a middle, and a front end; and', 'two connecting beams, one of the two connecting beams connected to the rear ends of the side beams, and the other one of the connecting beams connected to the middles of the side beams;, 'a base having'} a bottom end, the bottom end of one of the pivot arms connected to a corresponding one of the side beams adjacent to the front end of the corresponding side beam, and the bottom end of the other one of the pivot arms connected to the other one of the side beams adjacent to the front end of said the other side beam; and', 'a top end;, 'two pivot arms, each one of the pivot arms having'}, 'a supporting frame connected to the base and having'}a platform connected to the top ends of the pivot arms of the supporting frame over the base; and a swing arm pivotally connected to the connecting arm that is connected to the middles of the side beams, and pivotally connected to a bottom of the platform; and', 'a driving cylinder pivotally connected to the connecting beam ...

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Номер записи: 10
09-05-2024 дата публикации

MULTI-BIT STRUCTURE

Номер: US20240153942A1
Автор: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

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Номер записи: 11
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067113A1
Автор: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG, CHIANG HUNG-LI, CHENG CHAO-CHING, CHEN CHIH-LIANG, CHEN TZU-CHIANG, GUO TA-PEN, YANG YU-LIN, CHEN I-SHENG, HUANG SZU-WEI, CHIANG, Hung-Li, CHENG, Chao-Ching, CHEN, Chih-Liang, CHEN, Tzu-Chiang, GUO, Ta-Pen, YANG, Yu-Lin, CHEN, I-Sheng, HUANG, Szu-Wei
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; andforming a source/drain epitaxial layer in the second source/drain space, wherein:at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, andat least one of the second semiconductor layers is separated from the source/drain epitaxial layer disposed thereabove by the dielectric ...

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Номер записи: 12
13-04-2023 дата публикации

INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME

Номер: US20230114558A1
Автор: Guo-Huei WU, Pochun WANG, Wei-Hsin TSAI, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.

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Номер записи: 13
10-08-2023 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20230253406A1
Автор: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
Принадлежит:

A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

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Номер записи: 14
09-02-2023 дата публикации

POWER RAIL AND SIGNAL CONDUCTING LINE ARRANGEMENT

Номер: US20230045167A1
Автор: Guo-Huei WU, Shih-Wei PENG, Wei-Cheng LIN, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN, Lee-Chung LU
Принадлежит:

An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

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Номер записи: 15
28-11-2013 дата публикации

INTEGRATED CIRCUIT LAYOUT HAVING MIXED TRACK STANDARD CELL

Номер: US20130313615A1
Автор: Jiann-Tyng TZENG, Chih-Liang CHEN, Yi-Feng CHEN, Kam-Tou SIO, Shang-Chih HSIEH, Helen Shu-Hui CHANG
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer. 1. An integrated circuit layout having a mixed track standard cell configuration comprising:first well regions of a first predetermined height and second well regions of a second predetermined height, the first and second well regions arranged within a substrate;first conductors and second conductors extending across the corresponding first and second well regions; and 'a first standard cell having a first cell height substantially equal to I(X+Y)+X or I(X+Y)+Y, wherein X is one half the first predetermined height, Y is one half the second predetermined height, and I is a positive integer.', 'a plurality of standard cells in multiple rows, the plurality of standard cells comprising2. The integrated circuit layout of claim 1 , further comprising:a second standard cell having a second cell height substantially equal to 2(X+Y).3. The integrated circuit layout of claim 2 , wherein the first and second standard cells each comprise:a plurality of transistor regions including a first transistor region of a first type and a second transistor region of a second type.4. The integrated circuit layout of claim 3 , further comprising:a third standard cell having a third cell height substantially equal ...

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Номер записи: 16
30-05-2024 дата публикации

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

Номер: US20240178215A1
Автор: Xin-Yong WANG, Li-Chun TIEN, Chih-Liang CHEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited

An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

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Номер записи: 17
10-08-2023 дата публикации

METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH V2V RAIL

Номер: US20230253328A1
Автор: Jung-Chan YANG, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

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Номер записи: 18
12-01-2023 дата публикации

CELL STRUCTURE HAVING DIFFERENT POLY EXTENSION LENGTHS

Номер: US20230009224A1
Автор: Jian-Sing LI, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

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Номер записи: 19
18-01-2024 дата публикации

METHOD OF MAKING AMPHI-FET STRUCTURE AND METHOD OF DESIGNING

Номер: US20240021606A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
Принадлежит:

A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

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Номер записи: 20
16-02-2023 дата публикации

INTEGRATED CIRCUIT AND METHOD OF FORMING SAME

Номер: US20230050555A1
Автор: Chih-Yu LAI, Chih-Liang CHEN
Принадлежит:

An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

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Номер записи: 21
26-10-2023 дата публикации

INTEGRATED CIRCUIT

Номер: US20230343784A1
Автор: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

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Номер записи: 22
14-03-2024 дата публикации

CELL STRUCTURE HAVING DIFFERENT POLY EXTENSION LENGTHS

Номер: US20240088126A1
Автор: Jian-Sing LI, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

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Номер записи: 23
23-03-2023 дата публикации

FOOTPRINT FOR MULTI-BIT FLIP FLOP

Номер: US20230090614A1
Автор: Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Jerry Chang-Jui KAO, Tzu-Ying LIN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

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Номер записи: 24
02-02-2023 дата публикации

POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS

Номер: US20230036522A1
Автор: Chih-Liang CHEN, Guo-Huei WU, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
Принадлежит:

An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail. The integrated circuit device further includes a drain conductive segment connected to either ...

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Номер записи: 25
18-05-2023 дата публикации

NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD

Номер: US20230154917A1
Автор: Chih-Liang CHEN, Shun Li CHEN, Li-Chun TIEN, Ting Yu CHEN, Hui-Zhong ZHUANG
Принадлежит:

A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

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Номер записи: 26
21-03-2024 дата публикации

ARRANGEMENT OF SOURCE OR DRAIN CONDUCTORS OF TRANSISTOR

Номер: US20240095433A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Hsuan CHIU
Принадлежит:

An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

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Номер записи: 27
03-03-2022 дата публикации

SEMICONDUCTOR DEVICE WITH V2V RAIL AND METHODS OF MAKING SAME

Номер: US20220068816A1
Автор: Jung-Chan YANG, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.

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Номер записи: 28
30-12-2021 дата публикации

INTEGRATED CIRCUIT DEVICE AND METHOD

Номер: US20210407985A1
Автор: Chih-Liang CHEN, Shun Li CHEN, Li-Chun TIEN, Ting Yu CHEN, Hui-Zhong ZHUANG
Принадлежит:

A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

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Номер записи: 29
29-11-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180342509A1
Автор: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU, CHING KUO-CHENG, WANG CHIH-HAO, CHEN CHIH-LIANG, JU SHI NING, CHING, Kuo-Cheng, WANG, Chih-Hao, CHEN, Chih-Liang, JU, Shi Ning
Принадлежит:

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

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Номер записи: 30
29-09-2022 дата публикации

ACTIVE ZONES WITH OFFSET IN SEMICONDUCTOR CELL

Номер: US20220310584A1
Автор: Guo-Huei WU, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor cell structure includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail. Each of the first-type active zone and the second-type active zone is between a first alignment boundary and a second alignment boundary extending in a first direction which is perpendicular to a second direction. A first distance along the second direction between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance along the second direction between the long edge of the second power rail and the first alignment boundary of the second-type active zone by a predetermined distance. 1. A semiconductor cell structure comprising:first-type transistors having channel regions, source regions, and drain regions aligned within a first-type active zone between a first alignment boundary and a second alignment boundary each extending in a first direction;second-type transistors having channel regions, source regions, and drain regions aligned within a second-type active zone between a first alignment boundary and a second alignment boundary each extending in the first direction, wherein the first alignment boundary of the second-type active zone is adjacent to the first alignment boundary of the first-type active zone and is separated from the first alignment boundary of the first-type active zone along a second direction perpendicular to the first direction;a first power rail extending in the first direction and having a long edge adjacent the first-type active zone;a second power rail extending in the first direction and having a long edge adjacent the second-type active zone; andwherein a first distance along the second direction between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance along ...

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Номер записи: 31
13-04-2023 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20230113294A1
Автор: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

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Номер записи: 32
26-01-2023 дата публикации

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

Номер: US20230022333A1
Автор: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.

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Номер записи: 33
29-09-2022 дата публикации

AMPHI-FET STRUCTURE, METHOD OF MAKING AND METHOD OF DESIGNING

Номер: US20220310591A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
Принадлежит:

A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure. 1. A semiconductor device comprising:a substrate;a first active region on a first side of the substrate;a first gate structure surrounding a first portion of the first active region;a second active region on a second side of the substrate, wherein the second side is opposite the first side;a second gate structure surrounding a first portion of the second active region; anda gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.2. The semiconductor device of claim 1 , wherein the gate via has a tapered profile.3. The semiconductor device of claim 1 , wherein the gate via has a uniform width.4. The semiconductor device of claim 1 , further comprising:a conductive line, wherein the first gate structure is between the conductive line and the substrate; anda first via, wherein the first via electrically connects the conductive line to the first gate structure.5. The semiconductor device of claim 4 , wherein the first via is aligned with the gate via.6. The semiconductor device of claim 4 , wherein a size of the first via is equal to a size of the gate via.7. The semiconductor device of claim 1 , further comprising:a first source/drain (S/D) ...

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Номер записи: 34
04-11-2021 дата публикации

INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME

Номер: US20210343646A1
Автор: Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

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Номер записи: 35
19-10-2023 дата публикации

METHOD OF MANUFACTURING CONDUCTORS FOR SEMICONDUCTOR DEVICE

Номер: US20230335545A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Hui-Ting YANG, Shun Li CHEN, Ko-Bin KAO, Chih-Ming LAI, Ru-Gun LIU, Charles Chew-Yuen YOUNG
Принадлежит:

A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

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Номер записи: 36
03-03-2016 дата публикации

DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE

Номер: US20160064322A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Yung-Sung YEN, Kam-Tou SIO, Tsong-Hua OU, Chun-Kuang CHEN, Ru-Gun LIU, Shu-Hui SUNG, Charles Chew-Yuen YOUNG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 P gate min is the minimum value among gate pitches of the gate structures. L gate min is the minimum value among gate lengths of the gate structures. H gate min is the minimum value among gate heights of the gate structures.

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Номер записи: 37
31-05-2018 дата публикации

METHOD OF MANUFACTURING CONDUCTORS AND SEMICONDUCTOR DEVICE WHICH INCLUDES CONDUCTORS

Номер: US20180151552A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Hui-Ting YANG, Ko-Bin KAO, Ru-Gun LIU, Shun Li CHEN
Принадлежит:

A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different. 1. A method of manufacturing conductors for a semiconductor device , the method comprising: capped first conductors arranged parallel to a first direction; and', 'capped second conductors arranged parallel to and interspersed with the capped first conductors;, 'forming a structure on a base, the structure including each member of the first set having a first cap with a first etch sensitivity;', 'each member of the second set having a second cap with a second etch sensitivity;', 'each of the second conductors has a third cap with a third etch sensitivity; and', 'the first, second and third etch sensitivities are different from each other; and, 'wherein the capped first conductors are organized into at least first and second sets;'}eliminating selected portions of members of the first set and selected portions of members of the second set from the structure.2. The method of claim 1 , wherein the eliminating includes:removing the first cap from selected portions of members of the first set resulting in first uncapped portions of the first conductors;removing the second cap from selected portions of members of the second set resulting in second uncapped portions of the first conductors ...

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Номер записи: 38
09-12-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210384128A1
Автор: Xin-Yong WANG, Liu HAN, Li-Chun TIEN, Chih-Liang CHEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED

A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact. 1. A device comprising: a source/drain region; and', 'a source/drain contact above the source/drain region;, 'a transistor above a substrate, wherein the transistor comprisesan insulating structure above the substrate and laterally surrounding the transistor;a buried conductive line in the insulating structure and spaced apart from the transistor; anda buried via in the insulating structure and interconnecting the transistor and the buried conductive line, wherein a height of the buried conductive line is greater than a height of the source/drain contact.2. The device of claim 1 , wherein the source/drain contact is spaced apart from the buried conductive line.3. The device of claim 1 , wherein the buried via is in direct contact with the buried conductive line and the source/drain contact.4. The device of claim 2 , wherein a bottom surface of the buried conductive line is lower than a bottom surface of the source/drain contact.5. The device of claim 2 , wherein a top surface of the buried conductive line is higher than a top surface of the source/drain contact.6. The device of claim 1 , wherein the transistor further comprises a gate structure claim 1 , and the buried via is in direct contact with the buried conductive line and the gate structure.7. The device of claim 6 , wherein the gate structure and the buried conductive line extend in different ...

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Номер записи: 39
11-07-2019 дата публикации

METHOD FOR MANAGING SYSTEM BOOT CODE MEMORY, MEMORY DEVICE AND ELECTRONIC SYSTEM USING THE SAME

Номер: US20190213012A1
Автор: Chih-Liang CHEN, CHEN CHIH-LIANG, CHEN, Chih-Liang
Принадлежит: Macronix International Co Ltd

A memory device includes: a non-volatile memory having a first portion and a second portion which are utilized by a current configuration among a first configuration and a second configuration, a primary booting code is stored in one of the first portion and the second portion, and a backup booting code is stored in the other of the first portion and the second portion. In response that a updated booting code replaces the backup booting code, the updated booting code are performed by a prequalify operation, and the first portion and the second portion being temporarily utilized by another configuration, other than the current configuration, among the first configuration and the second configuration. If the updated booting code is operated successfully, after system reset, the first portion and the second portion being utilized by another configuration among the first configuration and the second configuration.

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Номер записи: 40
21-03-2024 дата публикации

SEMICONDUCTOR DEVICE, METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20240096865A1
Автор: Wei-Hsin TSAI, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

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Номер записи: 41
07-07-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20220216112A1
Автор: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

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Номер записи: 42
04-11-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210343715A1
Автор: Guo-Huei WU, Jerry Chang-Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
Принадлежит:

A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other. 1. A semiconductor device , comprising:a first gate-all-around field effect transistor (GAA FET) disposed over a substrate;a second GAA FET located at vertically different levels from the first GAA FET;a first power supply line connected to the first GAA FET; anda second power supply line connected to the second GAA FET, wherein:the first GAA FET and the second GAA FET share a gate,the first power supply line and the second power supply line are located at vertically different levels from each other, andthe first power supply line is buried in an isolation insulating layer.2. The semiconductor device of claim 1 , wherein the second power supply line is located above the second GAA FET.3. The semiconductor device of claim 1 , wherein the second power supply line is located at t same level as the second GAA FET.4. The semiconductor device of claim 1 , wherein the first GAA FET and the second GAA FET are different conductivity type from each other.5. The semiconductor device of claim 1 , wherein the first power supply line is disposed between two fin structures buried in the isolation insulating layer.6. The semiconductor device of claim 1 , wherein the first GAA FET and the second GAA FET constitute an inverter.7. A semiconductor device having a standard cell claim 1 , the standard cell comprising:a first gate-all-around field effect transistor (GAA FET) disposed over a substrate;a second GAA FET disposed at a vertically different level from the first GAA FET and sharing a gate with the first GAA FET;a first power supply line;a second power supply line; anda first signal line, a second signal line and a ...

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Номер записи: 43
22-07-2021 дата публикации

METHOD AND SYSTEM OF MANUFACTURING CONDUCTORS AND SEMICONDUCTOR DEVICE WHICH INCLUDES CONDUCTORS

Номер: US20210225831A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Hui-Ting YANG, Shun Li CHEN, Ko-Bin KAO, Chih-Ming LAI, Ru-Gun LIU, Charles Chew-Yuen YOUNG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

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Номер записи: 44
16-06-2016 дата публикации

DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE

Номер: US20160172297A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Yung-Sung YEN, Kam-Tou SIO, Tsong-Hua OU, Chun-Kuang CHEN, Ru-Gun LIU, Shu-Hui SUNG, Charles Chew-Yuen YOUNG, CHEN CHIH-LIANG, LAI CHIH-MING, YEN YUNG-SUNG, SIO KAM-TOU, OU TSONG-HUA, CHEN CHUN-KUANG, LIU RU-GUN, SUNG SHU-HUI, YOUNG CHARLES CHEW-YUEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 P gate min is the minimum value among gate pitches of the gate structures, and L gate min is the minimum value among gate lengths of the gate structures. H gate min is the minimum value among gate heights of the gate structures.

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Номер записи: 45
27-10-2022 дата публикации

FOOTPRINT FOR MULTI-BIT FLIP FLOP

Номер: US20220345116A1
Автор: Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Jerry Chang-Jui KAO, Tzu-Ying LIN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

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Номер записи: 46
30-11-2023 дата публикации

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

Номер: US20230387128A1
Автор: Chin-Wei HSU, Shun Li CHEN, Ting Yu CHEN, Hui-Zhong ZHUANG, Chih-Liang CHEN
Принадлежит:

An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

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Номер записи: 47
14-03-2024 дата публикации

INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT

Номер: US20240086609A1
Автор: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
Принадлежит:

A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

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Номер записи: 48
22-10-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200335400A1
Автор: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG, CHIANG HUNG-LI, CHENG CHAO-CHING, CHEN CHIH-LIANG, CHEN TZU-CHIANG, GUO TA-PEN, YANG YU-LIN, CHEN I-SHENG, HUANG SZU-WEI, CHIANG, Hung-Li, CHENG, Chao-Ching, CHEN, Chih-Liang, CHEN, Tzu-Chiang, GUO, Ta-Pen, YANG, Yu-Lin, CHEN, I-Sheng, HUANG, Szu-Wei
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

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Номер записи: 49
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067125A1
Автор: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG, CHIANG HUNG-LI, CHENG CHAO-CHING, CHEN CHIH-LIANG, CHEN TZU-CHIANG, GUO TA-PEN, YANG YU-LIN, CHEN I-SHENG, HUANG SZU-WEI, CHIANG, Hung-Li, CHENG, Chao-Ching, CHEN, Chih-Liang, CHEN, Tzu-Chiang, GUO, Ta-Pen, YANG, Yu-Lin, CHEN, I-Sheng, HUANG, Szu-Wei
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;forming a sacrificial gate structure over the fin structure;etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; andforming a source/drain epitaxial layer in the second source/drain space, wherein:at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,at least one of the second semiconductor layers is separated from a bottom of the source/ ...

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Номер записи: 50
30-05-2019 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20190165177A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHING, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU, CHEN CHIH-LIANG, LAI CHIH-MING, TSAI CHING-WEI, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, CHING KUO-CHENG, LIU RU-GUN, WU WEI-HAO, LIN YI-HSIUNG, CHANG CHIA-HAO, CHOU LEI-CHUN, CHEN, Chih-Liang, LAI, Chih-Ming, TSAI, Ching-Wei, YOUNG, Charles Chew-Yuen, TZENG, Jiann-Tyng, CHING, Kuo-Cheng, LIU, Ru-Gun, WU, Wei-Hao, LIN, Yi-Hsiung, CHANG, Chia-Hao, CHOU, Lei-Chun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices. 1. A non-planar semiconductor device , comprising:a dielectric region formed on a substrate;a plurality of fins protruding from the dielectric region;a plurality of terminal regions situated onto the dielectric region; anda rail conductor situated within the dielectric region and over the substrate, the rail conductor being electrically connected to a first terminal region from among the plurality of terminal regions.2. The non-planar semiconductor device of claim 1 , wherein the plurality of terminal regions comprise:a source region;a gate region; anda drain region.3. The non-planar semiconductor device of claim 1 , wherein the rail conductor is electrically connected to a second terminal region from among the plurality of terminal regions.4. The non-planar semiconductor device of claim 3 , wherein the first and second terminal regions are selected from among ...

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Номер записи: 51
17-08-2023 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20230260906A1
Автор: Wan-Yu LO, Chin-Shen LIN, Chi-Yu LU, Kuo-Nan YANG, Chih-Liang CHEN, Chung-Hsing WANG
Принадлежит:

Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

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Номер записи: 52
22-10-2020 дата публикации

SEMICONDUCTOR DEVICE WHICH INCLUDES FINS AND METHOD OF MAKING SAME

Номер: US20200335507A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU, CHEN CHIH-LIANG, LAI CHIH-MING, YOUNG CHARLES CHEW-YUEN, TSENG CHIN-YUAN, TZENG JIANN-TYNG, SIO KAM-TOU, LIU RU-GUN, LIN WEI-LIANG, CHOU L C, CHEN, Chih-Liang, LAI, Chih-Ming, YOUNG, Charles Chew-Yuen, TSENG, Chin-Yuan, TZENG, Jiann-Tyng, SIO, Kam-Tou, LIU, Ru-Gun, LIN, Wei-Liang, CHOU, L. C.
Принадлежит:

A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(≈90%)*T1)≤Pmin≤(Gmin+(≈110%)*T1).

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Номер записи: 53
19-05-2022 дата публикации

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

Номер: US20220157804A1
Автор: Xin-Yong WANG, Li-Chun TIEN, Chih-Liang CHEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited

An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

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Номер записи: 54
07-12-2023 дата публикации

INTEGRATED CIRCUIT (IC) DESIGN METHODS USING PROCESS FRIENDLY CELL ARCHITECTURES

Номер: US20230394217A1
Автор: Fei Fan DUAN, Li-Chun TIEN, Chih-Liang CHEN
Принадлежит:

Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.

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Номер записи: 55
30-11-2023 дата публикации

METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS

Номер: US20230387016A1
Автор: Chih-Liang CHEN, Guo-Huei WU, Li-Chun TIEN
Принадлежит:

A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

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Номер записи: 56
24-05-2018 дата публикации

CURVED TREADMILL

Номер: US20180140896A1
Автор: Chih-Liang CHEN
Принадлежит: YING LIANG HEALTH TECH. CO., LTD.

A curved treadmill has a frame, a handrail assembly, and a belt assembly. The frame has a support frame, two arced guide tracks and multiple guide wheels. The two arced guide tracks are downwardly concave, and the multiple guide wheels are disposed at a front end and a rear end of the support frame. The belt assembly is mounted around the frame and has at least one connection belt mounted around the guide wheels and multiple pedals fixed with the at least one connection belt. The pedals are adjacent and connected to each other, the pedals are covered on an outer side face of each of the at least one connection belts, and each pedal has a plate fixed to the at least one connection belt and multiple bearings mounted on two ends of the plate and selectively abutting against the two arced guide tracks.

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Номер записи: 57
13-06-2024 дата публикации

LOCAL INTERCONNECT STRUCTURE

Номер: US20240194682A1
Автор: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien WU, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
Принадлежит: Tiawan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

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Номер записи: 58
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006155A1
Автор: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU, CHIANG HUNG-LI, CHEN CHIH-LIANG, CHEN TZU-CHIANG, CHEN I-SHENG, CHOU LEI-CHUN, CHIANG, Hung-Li, CHEN, Chih-Liang, CHEN, Tzu-Chiang, CHEN, I-Sheng, CHOU, Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of fin structures extending in a first direction over a semiconductor substrate,wherein each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate;forming an electrically conductive layer between the first regions of a first adjacent pair of fin structures;forming a gate electrode structure extending in a second direction substantially perpendicular to the first direction over the fin structure second region; andforming a metallization layer including at least one conductive line over the gate electrode structure.2. The method according to claim 1 , wherein forming a plurality of fin structures comprises forming a nanowire structure in the second region of the fin structure.3. The method according to claim 2 , wherein forming the gate electrode structure comprises:forming a gate dielectric layer over at least one wire of the nanowire structure; andforming a gate electrode layer over the gate dielectric layer,wherein the gate dielectric layer and the gate electrode layer wrap around the at least one wire of the nanowire structure.4. The method according to claim 1 , wherein forming an electrically conductive layer comprises:forming ...

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Номер записи: 59
30-11-2023 дата публикации

FIRST METAL STRUCTURE, LAYOUT, AND METHOD

Номер: US20230387011A1
Автор: Chi-Yu LU, Chih-Liang CHEN, Chia-Tien WU, Chih-Yu LAI, Shang-Hsuan CHIU
Принадлежит:

An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

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Номер записи: 60
15-10-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200328212A1
Автор: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN, WU GUO-HUEI, KAO JERRY CHANG JUI, CHEN CHIH-LIANG, ZHUANG HUI-ZHONG, YANG JUNG-CHAN, LU LEE-CHUNG, CHEN XIANGDONG, WU, Guo-Huei, KAO, Jerry Chang Jui, CHEN, Chih-Liang, ZHUANG, Hui-Zhong, YANG, Jung-Chan, LU, Lee-Chung, CHEN, Xiangdong
Принадлежит:

A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

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Номер записи: 61
12-10-2023 дата публикации

INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME

Номер: US20230326856A1
Автор: Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

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Номер записи: 62
15-10-2020 дата публикации

INTEGRATED CIRCUIT

Номер: US20200328210A1
Автор: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN, WU GUO-HUEI, WANG PO-CHUN, ZHUANG HUI-ZHONG, CHEN CHIH-LIANG, TIEN LI-CHUN, WU, Guo-Huei, WANG, Po-Chun, ZHUANG, Hui-Zhong, CHEN, Chih-Liang, TIEN, Li-Chun
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.

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Номер записи: 63
17-01-2019 дата публикации

SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

Номер: US20190019797A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU, CHEN CHIH-LIANG, LAI CHIH-MING, YOUNG CHARLES CHEW-YUEN, TSENG CHIN-YUAN, TZENG JIANN-TYNG, SIO KAM-TOU, LIU RU-GUN, LIN WEI-LIANG, CHOU L C, CHEN, Chih-Liang, LAI, Chih-Ming, YOUNG, Charles Chew-Yuen, TSENG, Chin-Yuan, TZENG, Jiann-Tyng, SIO, Kam-Tou, LIU, Ru-Gun, LIN, Wei-Liang, CHOU, L. C.
Принадлежит:

A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness. 1. A semiconductor device comprising:a plurality of fins; at least a first set of fins among the plurality of fins is substantially parallel;', 'at least a second set of fins among the plurality of fins is substantially collinear; and', 'any given first and second fins of the plurality of fins have corresponding first and second fin-thicknesses such that the second fin-thickness is less than plus or minus about 50% of the first fin-thickness., 'wherein2. The semiconductor device of claim 1 , wherein:the second fin-thickness is plus or minus about 20% of the first fin-thickness.3. The semiconductor device of claim 1 , further comprising:SRAM cell regions; and 'components of the SRAM cell regions include corresponding portions of corresponding ones of the plurality of fins.', 'wherein4. The semiconductor device of claim 3 , wherein:long axes of the fins are substantially parallel to a first direction;the SRAM cell regions are arranged in pairs such that each pair includes first and second SRAM cell regions;the first and second SRAM cell regions of each pair are substantially mirror symmetric with respect to a corresponding mirror axis; andeach mirror axis is substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction.5. The semiconductor device of claim 4 , wherein:each SRAM cell region includes corresponding portions of four of the plurality of fins such that each of the four fins is partially included therein; andthree of the four fins partially included in the first SRAM cell region are continuous ...

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Номер записи: 64
14-12-2023 дата публикации

SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS

Номер: US20230402374A1
Автор: Wei-Ling CHANG, Chih-Liang CHEN, Chia-Tien WU, Guo-Huei WU
Принадлежит:

A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

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Номер записи: 65
30-05-2019 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20190164883A1
Автор: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN, SHEN MENG-HUNG, CHEN CHIH-LIANG, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, SIO KAM-TOU, LIN WEI-CHENG, SHEN, Meng-Hung, CHEN, Chih-Liang, YOUNG, Charles Chew-Yuen, TZENG, Jiann-Tyng, SIO, Kam-Tou, LIN, Wei-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively.

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Номер записи: 66
14-09-2023 дата публикации

INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME

Номер: US20230290766A1
Автор: Chia Chun WU, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Yung-Chen CHIEN
Принадлежит:

An integrated circuit includes a first and second active region extending in a first direction, and a floating gate, a first dummy gate, a first conductor and a second conductor extending in the second direction. The floating gate is electrically floating. The first dummy gate is separated from the floating gate in the second direction. The dummy gate and the floating gate separate a first cell that corresponds to a first transistor from a second cell that corresponds to a second transistor. The first and second conductors are separated from each other in the first direction, and overlap the second active region. The first and second conductors are electrically coupled to a corresponding source/drain of the second active region, and are configured to supply a same signal/voltage to the corresponding source/drain of the second active region. The floating gate is between the first and second conductors.

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Номер записи: 67
17-11-2022 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20220367458A1
Автор: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
Принадлежит:

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

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Номер записи: 68
22-04-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20210118745A1
Автор: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU, CHIANG HUNG-LI, CHEN CHIH-LIANG, CHEN TZU-CHIANG, CHEN I-SHENG, CHOU LEI-CHUN, CHIANG, Hung-Li, CHEN, Chih-Liang, CHEN, Tzu-Chiang, CHEN, I-Sheng, CHOU, Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

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Номер записи: 69
02-11-2017 дата публикации

METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

Номер: US20170317089A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
Принадлежит:

A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure. 1. A method of manufacturing fins for a semiconductor device , the method comprising: each member of the first set having a first cap with a first etch sensitivity; and', 'each member of the second set having a second cap with a second etch sensitivity, the second etch sensitivity being different than the first etch sensitivity; and, 'forming a structure including a semiconductor substrate and a plurality of capped semiconductor fins, the plurality of capped semiconductor fins being organized into at least first and second sets;'}eliminating selected members of the first set and selected members of the second set from the structure.2. The method of claim 1 , wherein the eliminating includes:removing second caps of selected members of the second set resulting in second uncapped fins;removing first caps of selected members of the first set resulting in first uncapped fins; andremoving the first and second uncapped fins from the structure.3. The method of claim 2 , wherein the removing the second caps of the selected members of the second set includes:forming first masks over unselected members of the second set to leave the selected members of the second set exposed;etching the selected members of the second set and the other members of the first set with a second etchant appropriate to the second etch sensitivity to remove the second cap from each selected member of the second ...

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Номер записи: 70
07-04-2022 дата публикации

METHOD OF MAKING SEMICONDUCTOR DEVICE WHICH INCLUDES FINS

Номер: US20220108990A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
Принадлежит:

In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

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Номер записи: 71
07-09-2023 дата публикации

INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20230282639A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Yi-Hsun CHIU
Принадлежит:

A method of forming an integrated circuit structure includes generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure. The generating the first well layout pattern includes generating a first layout pattern having a first width, and corresponding to fabricating a first portion of the first well, and generating a second layout pattern having a second width and corresponding to fabricating a second portion of the first well. The method further includes generating a first implant layout pattern having a third width and corresponding to fabricating a first set of implants in the first portion of the first well, generating a second implant layout pattern having a fourth width and corresponding to fabricating a second set of implants in the second portion of the first well, and manufacturing the integrated circuit structure based on the above layout patterns.

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Номер записи: 72
30-11-2023 дата публикации

SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD

Номер: US20230386998A1
Автор: Chi-Yu LU, Yi-Hsun CHIU, Chih-Liang CHEN, Chih-Yu LAI, Shang-Hsuan CHIU
Принадлежит:

An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.

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Номер записи: 73
10-12-2020 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20200388706A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU, CHEN CHIH-LIANG, LAI CHIH-MING, TSAI CHING-WEI, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, CHIANG KUO-CHENG, LIU RU-GUN, WU WEI-HAO, LIN YI-HSIUNG, CHANG CHIA-HAO, CHOU LEI-CHUN, CHEN, Chih-Liang, LAI, Chih-Ming, TSAI, Ching-Wei, YOUNG, Charles Chew-Yuen, TZENG, Jiann-Tyng, CHIANG, Kuo-Cheng, LIU, Ru-Gun, WU, Wei-Hao, LIN, Yi-Hsiung, CHANG, Chia-Hao, CHOU, Lei-Chun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or ...

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Номер записи: 74
18-11-2021 дата публикации

INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME

Номер: US20210358848A1
Автор: Guo-Huei WU, Pochun WANG, Wei-Hsin TSAI, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. 1. An integrated circuit comprising:a first power rail on a back-side of a substrate, and extending in a first direction,a second power rail on the back-side of the substrate, extending in the first direction, and being separated from the first power rail in a second direction different from the first direction;a signal line on the back-side of the substrate, and extending in the first direction, and being between the first power rail and the second power rail; anda first active region of a first set of transistors, the first active region extending in the first direction, and being on a first level of a front-side of the substrate opposite from the back-side.2. The integrated circuit of claim 1 , further comprising:a second active region of a second set of transistors, the second active region extending in the first direction, being on the first level of the front-side of the substrate, and being separated from the first active region in the second direction.3. The integrated circuit of claim 2 , further comprising:a first contact extending in the second direction, overlapping the first active region, and being located on a second level different from the first level; anda second contact extending in the second direction, ...

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Номер записи: 75
26-12-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190393102A1
Автор: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG, CHIANG HUNG-LI, CHENG CHAO-CHING, CHEN CHIH-LIANG, CHEN TZU-CHIANG, GUO TA-PEN, YANG YU-LIN, CHEN I-SHENG, HUANG SZU-WEI, CHIANG, Hung-Li, CHENG, Chao-Ching, CHEN, Chih-Liang, CHEN, Tzu-Chiang, GUO, Ta-Pen, YANG, Yu-Lin, CHEN, I-Sheng, HUANG, Szu-Wei
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

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Номер записи: 76
22-04-2021 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20210118793A1
Автор: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN, SHEN MENG-HUNG, CHEN CHIH-LIANG, YOUNG CHARLES CHEW-YUEN, TZENG JIANN-TYNG, SIO KAM-TOU, LIN WEI-CHENG, SHEN, Meng-Hung, CHEN, Chih-Liang, YOUNG, Charles Chew-Yuen, TZENG, Jiann-Tyng, SIO, Kam-Tou, LIN, Wei-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.

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Номер записи: 77
06-04-2023 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20230103578A1
Автор: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.

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Номер записи: 78
09-12-2021 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20210383054A1
Автор: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
Принадлежит:

An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

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Номер записи: 79
09-07-2009 дата публикации

Adductor Exerciser

Номер: US20090176623A1
Автор: Chih-Liang CHEN
Принадлежит:

An adductor exerciser has a stanchion, a stand, a crossbar and two legs. The stanchion has an upper end and a lower end. The stand is attached to the lower end. The crossbar is attached to the upper end of the stanchion. Each leg is pivotally connected to the crossbar and has a distal end and a pedal assembly. The pedal assembly is mounted rotatably to the distal end of the leg.

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Номер записи: 80
22-09-2022 дата публикации

INTEGRATED CIRCUIT

Номер: US20220302111A1
Автор: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack. 1. A method , comprising:forming a multilayer stack, wherein the multilayer stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked;forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack;removing the plurality of second semiconductor layers in the multilayer stack;forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack;forming a first insulating layer above the first gate region; andforming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.2. The method of claim 1 , wherein forming the first insulating layer comprises:filling a space between the first portion of the multilayer stack and the second portion of the multilayer stack with an insulating material.3. The method of claim 1 , further comprising:forming a ...

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Номер записи: 81
18-05-2023 дата публикации

ARRANGEMENT OF SOURCE OR DRAIN CONDUCTORS OF TRANSISTOR

Номер: US20230154990A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Hsuan CHIU
Принадлежит:

An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. The first conductor has a distal edge separated from a first power rail, and the second conductor segment is connected to a second power rail through a via-connector. A distance from the first power rail to a proximal edge of the first conductor segment is larger than a distance from the second power rail to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

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Номер записи: 82
21-03-2024 дата публикации

ACTIVE ZONES WITH OFFSET IN SEMICONDUCTOR CELL

Номер: US20240096866A1
Автор: Guo-Huei WU, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.

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Номер записи: 83
02-02-2023 дата публикации

SEMICONDUCTOR DEVICE, METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20230035939A1
Автор: Wei-Hsin TSAI, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

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Номер записи: 84
23-03-2023 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20230091869A1
Автор: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or ...

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Номер записи: 85
09-09-2021 дата публикации

LOCAL INTERCONNECT STRUCTURE

Номер: US20210280607A1
Автор: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures. 1. A method , comprising:routing a reference metal line to couple to a first source/drain terminal of a transistor with a gate terminal, the first source/drain terminal, and a second source/drain terminal;routing, at a same interconnect level as the reference metal line, a local interconnect structure to couple to the gate terminal;routing, above an interconnect level of the local interconnect structure, a first interconnect structure to couple to the second source/drain terminal; androuting, above the interconnect level of the local interconnect structure and at a same interconnect level as the first interconnect structure, a second interconnect structure.2. The method of claim 1 , further comprising:routing an other reference metal line to couple to a third source/drain terminal of an other transistor having an other gate terminal, the third source/drain terminal, and a fourth source/drain terminal, wherein the local interconnect structure is coupled to the gate terminal and the other gate terminal;routing a third interconnect structure above the ...

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Номер записи: 86
25-07-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190229120A1
Автор: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU, CHING KUO-CHENG, WANG CHIH-HAO, CHEN CHIH-LIANG, JU SHI NING, CHING, Kuo-Cheng, WANG, Chih-Hao, CHEN, Chih-Liang, JU, Shi Ning
Принадлежит:

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall. 1. A semiconductor device , comprising:a first gate electrode disposed over an isolation insulating layer formed on a substrate;first sidewall spacers disposed on opposing sides of the first gate electrode;a second gate electrode disposed over the isolation insulating layer, the first and second gate electrode extending in and being aligned along a first direction;second sidewall spacers disposed on opposing sides of the second gate electrode;a first dielectric separation wall disposed on isolation insulating layer and disposed between and separating the first gate electrode and the second gate electrode; anda third sidewall spacer disposed on sides of the first dielectric separation wall, wherein:the first dielectric separation wall is made of a different dielectric material than the isolation insulating layer,the first gate electrode are separated by the first dielectric separation wall from the second gate electrode, andone of the first sidewall spacers, the third sidewall spacers and one of the second sidewall spacers are continuous.2. The semiconductor device of claim 1 , further comprising:a fourth sidewall spacers formed on a side of the first dielectric separation wall; anda fifth sidewall spacers formed on another side of the first dielectric ...

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Номер записи: 87
10-11-2022 дата публикации

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

Номер: US20220359493A1
Автор: Xin-Yong WANG, Li-Chun TIEN, Chih-Liang CHEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited

An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

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Номер записи: 88
28-04-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SAME

Номер: US20220130760A1
Автор: Guo-Huei WU, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

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Номер записи: 89
26-10-2023 дата публикации

SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA AND METHOD OF MAKING

Номер: US20230343703A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Chung-Hsing WANG
Принадлежит:

A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.

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Номер записи: 90
20-10-2022 дата публикации

SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED INTERCONNECT STRUCTURE AND METHOD OF MAKING

Номер: US20220336325A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
Принадлежит:

A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

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Номер записи: 91
17-11-2022 дата публикации

MULTI-BIT STRUCTURE

Номер: US20220367440A1
Автор: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

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Номер записи: 92
25-04-2019 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK

Номер: US20190123036A1
Автор: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU, YOUNG CHARLES CHEW-YUEN, CHEN CHIH-LIANG, LAI CHIH-MING, TZENG JIANN-TYNG, CHEN SHUN-LI, SIO KAM-TOU, PENG SHIH-WEI, CHEN CHUN-KUANG, LIU RU-GUN, YOUNG, Charles Chew-Yuen, CHEN, Chih-Liang, LAI, Chih-Ming, TZENG, Jiann-Tyng, CHEN, Shun-Li, SIO, Kam-Tou, PENG, Shih-Wei, CHEN, Chun-Kuang, LIU, Ru-Gun
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

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Номер записи: 93
05-12-2019 дата публикации

METHOD AND SYSTEM OF MANUFACTURING CONDUCTORS AND SEMICONDUCTOR DEVICE WHICH INCLUDES CONDUCTORS

Номер: US20190371784A1
Автор: Kam-Tou SIO, Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Hui-Ting YANG, Ko-Bin KAO, Ru-Gun LIU, Shun Li CHEN
Принадлежит:

A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

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Номер записи: 94
30-11-2023 дата публикации

POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS

Номер: US20230387013A1
Автор: Chih-Liang CHEN, Guo-Huei WU, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
Принадлежит:

An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.

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Номер записи: 95
27-04-2023 дата публикации

SEMICONDUCTOR DEVICES, SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE

Номер: US20230127579A1
Автор: Chia-Chung CHEN, Szu-Lin LIU, Jaw-Juinn HORNG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Ya Yun LIU
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

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Номер записи: 96
02-03-2023 дата публикации

SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS

Номер: US20230064108A1
Автор: Wei-Ling CHANG, Chih-Liang CHEN, Chia-Tien WU, Guo-Huei WU
Принадлежит:

An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.

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Номер записи: 97
29-02-2024 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20240071834A1
Автор: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

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Номер записи: 98
05-08-2021 дата публикации

SEMICONDUCTOR DEVICE HAVING BURIED LOGIC CONDUCTOR TYPE OF COMPLEMENTARY FIELD EFFECT TRANSISTOR, METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME

Номер: US20210242205A1
Автор: Guo-Huei WU, Pochun WANG, Chih-Liang CHEN, Li-Chun TIEN
Принадлежит:

A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures. 1. A semiconductor device comprising a buried logic conductor (BLC) CFET , the BLC CFET including:relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration;first and second contact structures correspondingly electrically coupled to the first active region;third and fourth contact structures correspondingly electrically coupled to the second active region; alpha logic conductors configured for logic signals (alpha logic conductors); and', 'the alpha logic and PG conductors being non-overlapping of each other; and', 'power grid (PG) conductors;'}], 'a first layer of metallization (M_1st layer) over the stack which includesa layer of metallization below the stack (M_B layer) which includes beta logic conductors which are non-overlapping of each other; andwherein, relative to a second direction perpendicular to the first direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, ...

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Номер записи: 99
21-03-2024 дата публикации

MEHTOD OF MAKING SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED INTERCONNECT STRUCTURE

Номер: US20240096756A1
Автор: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
Принадлежит:

A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

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Номер записи: 100
28-06-2012 дата публикации

Elliptical trainer having two crank assemblies

Номер: US20120165160A1
Автор: CHEN Chih-Liang, Yu Chao-Chi
Принадлежит:

An elliptical trainer has a base, and two crank assemblies, a handle assembly and a linkage assembly mounted on the base. Each crank assembly has two cranks and a transmission wheel. A transmission strip is mounted around the transmission wheels of the crank assemblies to simulate rotations of the crank assemblies. The linkage assembly connects the cranks of the crank assemblies to the handle assembly. When the elliptical trainer is operated, the linkage assembly drives the cranks to alternately rotate upwardly and downwardly. The cranks that rotate downwardly drag the other cranks to rotate upwardly. Therefore, the crank assemblies and the linkage assembly operate smoothly, and consequently, the user is capable of smoothly performing walking or running movements. 1. An elliptical trainer comprising a bottom frame;', 'a crank support and a handle support mounted separately on and protruding up from the bottom frame;, 'a base having'} a first axle mounted pivotally through the crank support and having two opposite ends;', 'a first transmission wheel mounted securely around one of the ends of the first axle; and', a distal end; and', 'a proximal end mounted securely on a corresponding end of the first axle;, 'two first cranks respectively mounted securely on the ends of the first axle and extending perpendicularly to the first axle, and each first crank having'}], 'a first crank assembly mounted rotatably on the crank support and having'} a second axle mounted pivotally through the crank support and having two opposite ends;', 'a second transmission wheel mounted securely around one of the ends of the second axle and corresponding to the first transmission wheel;', 'a transmission strip being looped around the first and second transmission wheels; and', a distal end; and', 'a proximal end mounted securely on a corresponding end of the second axle;, 'two second cranks respectively mounted securely on the ends of the second axle and extending perpendicularly to the ...

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Номер записи: 101
13-12-2012 дата публикации

Asynchronous/synchronous interface

Номер: US20120314517A1
Автор: Chih Liang Chen, Dean K. Nobunaga, June Lee
Принадлежит: Micron Technology Inc

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

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Номер записи: 102
03-02-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND LAYOUT METHOD OF A SEMICONDUCTOR STRUCTURE

Номер: US20220037233A1
Автор: Chang Wei-Ling, CHEN Chih-Liang, Chen Wei-Ren, TIEN Li-Chun, Zhuang Hui-Zhong
Принадлежит:

A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch. 1. A semiconductor structure , comprising:a plurality of vias on a semiconductor substrate; anda metal layer, having a plurality of metal lines and at least one transmission gate line region, the metal lines connected to the vias, the at least one transmission gate line region connected to at least one transmission gate corresponding to at least one transmission gate circuit, the transmission gate line region comprising at least one different-net via pair, the different-net via pair having two metal lines and each of the two metal lines connected to a via respectively, the two metal lines extending along a first axis but toward opposite directions, a distance between the two vias of the different-net via pair within about 1.5 poly pitch.2. The semiconductor structure of claim 1 , wherein the distance is between about 0.8-1.5 poly pitch.3. The semiconductor structure of claim 1 , wherein the metal layer further comprises at least one 1-dimension section around the different-net via pair.4. The semiconductor structure of claim 3 , wherein the 1-dimension section comprises at least one upper metal line and at least one lower metal line claim 3 , the upper metal line disposed on an upper position ...

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Номер записи: 103
18-01-2018 дата публикации

DUAL POWER STRUCTURE WITH CONNECTION PINS

Номер: US20180019207A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen
Принадлежит:

In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch. 1. An integrated chip , comprising:a lower power rail continuously extending over a plurality of gate structures;a first set of connection pins straddling a first edge of the lower power rail;a second set of connection pins straddling a second edge of the lower power rail, which is opposite the first edge, wherein the first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail, and wherein the first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch; andan upper power rail over the lower power rail, and electrically coupled to the first set of connection pins and the second set of connection pins.2. The integrated chip of claim 1 , further comprising:a first conductive wire laterally separated from the lower power rail by a dielectric material and continuously extending over the plurality of gate structures, wherein one of the first set of connection pins continuously extends from over the first conductive wire to over the lower power rail and is ...

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Номер записи: 104
16-01-2020 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20200020588A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch. 1. A method of forming an integrated chip , comprising:forming a plurality of gate structures over a substrate;forming a plurality of source and drain regions along opposing sides of the plurality of gate structures;defining a plurality of middle-of-the-line (MOL) structures at locations laterally interleaved between the plurality of gate structures; andredefining the plurality of MOL structures by getting rid of a part but not all of one or more of the plurality of MOL structures, wherein redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.2. The method of claim 1 ,wherein the plurality of MOL structures are defined according to a first photomask; andwherein the plurality of MOL structures are redefined according to a cut mask.3. The method of claim 1 , wherein redefining the plurality of MOL structures forms two separate MOL active structures from a single one of the plurality of MOL structures.4. The method of claim 1 , wherein the plurality of MOL structures are defined to be at a substantially regular pitch that is smaller than the irregular pitch.5. The method of claim 1 , further comprising:forming an inter-level ...

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Номер записи: 105
16-01-2020 дата публикации

Advanced Metal Connection With Metal Cut

Номер: US20200020625A1
Автор: CHEN Chih-Liang, CHEN Shun Li, Chuang Cheng-Chi, Lai Chih-Ming, Lin Tien-Lu, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit;cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures; andfabricating a plurality of polysilicon structures comprising patterned polysilicon lines that provide gate structures for a semiconductor device.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit.3. The method of claim 2 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon ...

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Номер записи: 106
28-01-2021 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20210028311A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices. 1. A method , comprising:forming a plurality of fins protruding from a first dielectric layer;depositing a spacer on a sidewall of the fin and in contact with the first dielectric layer;depositing a second dielectric layer on the first dielectric layer;depositing a conductive material between the second dielectric layer and the spacer to form a conductive rail, wherein a top surface of the conductive rail is below a top surface of the plurality of fins; andforming a source/drain terminal in contact with the conductive rail.2. The method of claim 1 , further comprising forming a seed layer on the first dielectric layer.3. The method of claim 2 , wherein depositing the conductive material comprises epitaxially growing the conductive material from a top surface of the seed layer.4. The method of claim 2 , wherein forming the seed layer comprises:depositing a seed ...

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Номер записи: 107
08-02-2018 дата публикации

METHOD OF ADJUSTING METAL LINE PITCH

Номер: US20180039723A1
Автор: CHEN Chih-Liang, Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P. 1. A method , performed by at least one processor , comprising:obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form;determining a unit pattern having a width of n times of the gate pitch;assigning m consecutive metal lines to the unit pattern;dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R);determining an integer P so that a value of the remainder R divided by P satisfies a layout precision; anddetermining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.2. The method according to further comprising generating a netlist data including information on the inter-pattern metal line pitch and the intra-pattern metal line pitch.3. The method according to claim 1 , wherein the ratio between gate pitch and metal line pitch is 3:2 or 4:3.4. The method according to claim 1 , wherein the metal line belongs to metal-1 (M1) layer.5. The method according to further comprising claim 1 , after the assigning claim 1 , determining whether the gate pitch is divisible by m.6. The method according to further comprising determining the metal pitch to be 2n/m times of the gate pitch if the gate pitch is divisible by m.7. The method ...

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Номер записи: 108
09-02-2017 дата публикации

Structure And Method For Semiconductor Device

Номер: US20170040259A1
Автор: CHEN Chih-Liang, Lai Chih-Ming, LIOU CHUN-HUNG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, SUNG Shu-Hui, Young Charles Chew-Yuen
Принадлежит:

A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer. 1. A semiconductor device , comprising:a substrate having a source region and a drain region;a channel region arranged between the source and drain regions;a gate structure over the substrate and adjacent to the channel region, wherein the gate structure includes a gate stack, a spacer on at least sidewalls of the gate stack, and a conductor over the gate stack;a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions, a top surface of the first contact feature being lower than a top surface of the gate structure; anda first dielectric layer over the first contact feature, a top surface of the first dielectric layer being below or substantially co-planar with the top surface of the gate structure, wherein the conductor at most partially overlaps in plan view with the first dielectric layer.2. The semiconductor device of claim 1 , wherein the first dielectric layer has a thickness that is 0.2-4 times of a height of the gate stack.3. The semiconductor device of claim 1 , wherein:the gate stack has a first dimension along a ...

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Номер записи: 109
07-02-2019 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20190043759A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch. 1. An integrated chip , comprising:a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction;a plurality of gate structures arranged over the substrate at a substantially regular pitch;a plurality of middle-of-the-line (MOL) structures respectively interleaved between adjacent ones of the plurality of gate structures;wherein the plurality of MOL structures comprise MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect; andwherein the plurality of MOL active structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.2. The integrated chip of claim 1 , further comprising:a plurality of vias disposed within an inter-level dielectric (ILD) layer and contacting the MOL active structures, wherein the plurality of vias have sidewalls continuously extending between a bottom of the ILD layer and a top of the ILD layer.3. The ...

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Номер записи: 110
06-02-2020 дата публикации

High-Density Semiconductor Device

Номер: US20200043741A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a first material on a substrate;depositing on the substrate a second material;depositing a spacer material on the first and second materials;forming a third material on a top surface and a sidewall of the spacer; andetching the third material on the sidewall of the spacer to expose a portion of the first material.2. The method of claim 1 , wherein the second material has an etch selectivity different from an etch selectivity of the first material3. The method of claim 1 , further comprising converting the third material on the top surface and the sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.4. The method of claim 3 , wherein converting the third material on the top surface and the sidewall of the spacer into the fourth material includes implanting ions in the third material on the top surface and the sidewall of the spacer.5. The method of claim 3 , wherein converting the third material on the top surface and the sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.6. The method of claim 5 , wherein the tilt angle is between about 30 degrees and about 60 degrees relative to a horizontal axis.7. The method of claim 1 , further comprising removing the exposed portion of the first material to expose a portion of the substrate.8. The method of claim 1 , further comprising etching back the second material to a ...

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Номер записи: 111
14-02-2019 дата публикации

Advanced Metal Connection With Metal Cut

Номер: US20190051595A1
Автор: CHEN Chih-Liang, CHEN Shun Li, Chuang Cheng-Chi, Lai Chih-Ming, Lin Tien-Lu, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit.3. The method of claim 2 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.4. The method of claim 3 , further comprising:fabricating via interconnections between the conductive interconnection layer and the ...

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Номер записи: 112
10-03-2022 дата публикации

INTERCONNECT STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20220077059A1
Автор: CHEN Chih-Liang, CHEN SHUN-LI, TIEN Li-Chun, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит:

A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail. 1. A semiconductor device , comprising:a gate electrode extending in a first direction in a first layer over an active region;a first conductive line extending in the first layer adjacent to the gate electrode;a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer;a second conductive line arranged in a third layer over the second layer; anda conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line, wherein the conductive via is electrically insulated from the first power rail.2. The semiconductor device according to claim 1 , further comprising a spacer layer electrically insulating the conductive via from the first power rail.3. The semiconductor device according to claim 2 , wherein spacer layer extends from the first conductive line to the second conductive line.4. The semiconductor device according to claim 2 , wherein the spacer layer is at least partially laterally surrounded by the first power rail.5. The semiconductor device according to claim 1 , further comprising a second power rail arranged in the second layer and parallel to the first power rail.6. The semiconductor device according to claim 5 , wherein the second power rail is ...

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Номер записи: 113
03-03-2016 дата публикации

Asynchronous/synchronous interface

Номер: US20160064048A1
Автор: Chih Liang Chen, Dean K. Nobunaga, June Lee
Принадлежит: Micron Technology Inc

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

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Номер записи: 114
04-03-2021 дата публикации

Advanced Metal Connection With Metal Cut

Номер: US20210066182A1
Автор: CHEN Chih-Liang, CHEN Shun Li, Chuang Cheng-Chi, Lai Chih-Ming, Lin Tien-Lu, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of a circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing a conductive material from the conductive connector portion at at least one locations between a plurality of semiconductor structures.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple the plurality of semiconductor structures in a different layer of the circuit.3. The method of claim 2 , wherein the different layer of the circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.4. The method of claim 3 , further comprising:fabricating a plurality of polysilicon structures comprising patterned polysilicon lines that provide gate ...

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Номер записи: 115
28-02-2019 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20190065658A1
Автор: CHEN Chih-Liang, CHEN Shun Li, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Zhuang Hui-Zhong
Принадлежит:

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule. 1. A method of forming an integrated circuit , the method comprising: generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction and being located on a first layout level;', 'generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns; and', 'generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature ...

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Номер записи: 116
17-03-2022 дата публикации

CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES

Номер: US20220084945A1
Автор: CHEN Chih-Liang, CHEN Shun Li, Chen Ting Yu, TIEN Li-Chun, Zhuang Hui-Zhong
Принадлежит:

A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track. 1. A cell on an integrated circuit , comprising:a fin structure;an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; anda first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track, wherein a first power supply terminal is connected to the first intermediate gate connection metal track, wherein the first intermediate gate connection metal track extends in a first direction, and wherein the first intermediate gate connection metal track extends outside the cell and is connected to a power connecting cell, the power connecting cell being a first neighboring cell of the cell in the first direction.2. The cell of claim 1 , further comprising:a plurality of metal tracks disposed in a first metal (M1) layer above the intermediate gate connection metal layer, wherein no power supply terminal is connected to the plurality of metal tracks.3. The cell of claim 2 , wherein the ...

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Номер записи: 117
08-03-2018 дата публикации

System for and method of manufacturing a layout design of an integrated circuit

Номер: US20180068050A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou SIO, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

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Номер записи: 118
05-06-2014 дата публикации

ASYNCHRONOUS/SYNCHRONOUS INTERFACE

Номер: US20140153335A1
Автор: Chen Chih Liang, LEE June, Nobunaga Dean K.
Принадлежит: MICRON TECHNOLOGY, INC.

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. 120-. (canceled)21. A memory system comprising:a memory access device; a memory cell array; and', 'a memory interface coupled to the memory cell array and configured for switchably operating in either an asynchronous mode or a synchronous mode,, 'a memory device coupled to the memory access device, the memory device comprisingwherein three or fewer additional memory interface control signals are utilized in the synchronous mode in addition to memory interface control signals utilized in the asynchronous mode.22. The memory system of claim 21 , wherein the three or fewer additional memory interface signals at least includes two signals complementary to memory interface control signals utilized in the synchronous mode.23. The memory system of claim 21 , wherein the three or fewer additional memory interface control signals includes a bidirectional data strobe signal.24. The memory system of claim 23 , wherein the memory interface is configured to utilize a signal on a first contact of the memory interface as a write enable signal in an asynchronous mode and as a clock signal in a synchronous mode claim 23 , and the memory interface is configured to utilize a signal on a second contact of the memory interface as a read ...

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Номер записи: 119
05-03-2020 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20200074044A1
Автор: CHEN Chih-Liang, CHEN Shun Li, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Zhuang Hui-Zhong
Принадлежит:

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules. 1. A system for designing an integrated circuit , the system comprises:a non-transitory computer readable medium configured to store executable instructions; anda processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction;', 'placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns;', 'placing a first conductive feature layout pattern on a second layout level different from the first layout ...

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Номер записи: 120
12-03-2020 дата публикации

VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION

Номер: US20200083182A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Wen-Hao, Lai Chih-Ming, Liu Ru-Gun, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Yu Chi-Yeh
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail. 1. An integrated chip , comprising:a first conductive interconnect wire extending in a first direction over a substrate;a second conductive interconnect wire arranged over the first conductive interconnect wire; anda via rail configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire, wherein the first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.2. The integrated chip of claim 1 , wherein the via rail and the second conductive interconnect wire comprise copper.3. The integrated chip of claim 1 , further comprising:a gate structure arranged over the substrate between a source region and a drain region;a middle-end-of-the-line (MEOL) structure having a bottom surface that continually extends past a first edge of the source region along a second direction that is perpendicular to the first direction; anda conductive contact disposed directly between a top surface of the MEOL structure and a bottom surface of the first conductive interconnect wire.4. The integrated chip of claim 3 , wherein the MEOL structure has a first height that is substantially equal to a second height of the gate structure.5. The integrated chip of claim 3 , wherein the conductive contact is disposed over the MEOL structure at a location that is outside of the source region.6. The ...

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Номер записи: 121
05-04-2018 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20180096930A1
Автор: CHEN Chih-Liang, LIN WEI-CHENG, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method is disclosed that includes disposing a first conductive metal segment; disposing a second conductive metal segment over an active area; disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment; disposing a first conductive via on the first conductive metal segment; and disposing a first conductive line coupled to the first conductive metal segment through the first conductive via. 1. A method comprising:disposing a first conductive metal segment;disposing a second conductive metal segment over an active area;disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment;disposing a first conductive via on the first conductive metal segment; anddisposing a first conductive line coupled to the first conductive metal segment through the first conductive via.2. The method of claim 1 , further comprising:disposing a second conductive via on the second conductive metal segment, wherein the conductive line is coupled to the second conductive via.3. The method of claim 1 , further comprising:disposing a gate over the active area, under the local conductive segment, and between the first conductive metal segment and the second conductive metal segment.4. The method of claim 3 , wherein a height of the local conductive segment plus a height of the gate is substantially equal to a height of the second conductive metal segment.5. The method of claim 1 , wherein a height of the first conductive metal segment is greater than a height of the second conductive metal segment.6. The method of claim 1 , further comprising:disposing an isolation segment over the second conductive metal segment for isolating the conductive line from a second conductive line.7. The method of claim 1 , wherein a length of the second conductive metal segment is shorter than a length of the first conductive metal segment.8. A method comprising:disposing a first conductive ...

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Номер записи: 122
01-04-2021 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210098500A1
Автор: CHEN Chih-Liang, TIEN Li-Chun, Wang Pochun, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит:

A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided. 1. A semiconductor structure , comprising:a first transistor and a second transistor disposed adjacent to the first transistor, the first transistor and the second transistor being at a first elevation;a first dummy source/drain disposed at the first elevation;a third transistor and a fourth transistor disposed adjacent to the third transistor, the third transistor and the fourth transistor being at a second elevation different from the first elevation; anda second dummy source/drain disposed at the second elevation,wherein the second transistor is vertically aligned with the third transistor, the first dummy source/drain is vertically aligned with a source/drain of the fourth transistor, the second dummy source/drain is vertically aligned with a source/drain of the first transistor, and a gate structure between the second dummy source/drain and a source/drain of the third transistor is absent.2. The semiconductor structure of claim 1 , wherein a gate structure between the first ...

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Номер записи: 123
28-03-2019 дата публикации

STANDARD CELLS HAVING VIA RAIL AND DEEP VIA STRUCTURES

Номер: US20190096809A1
Автор: CHEN Chih-Liang, Chuang Cheng-Chi, Lai Wayne, LIN WEI-CHENG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines. 1. A semiconductor structure comprising:a plurality of gate structures;a plurality of vias formed in a first dielectric layer, wherein each via of the plurality of vias is formed on each gate structure of the plurality of gate structures;a conductive rail structure formed in the first dielectric layer and over at least one via of the plurality of vias, wherein the conductive rail structure is electrically connected to the at least one via of the plurality of vias;a second dielectric layer formed over the first dielectric layer and the conductive rail structure;a deep via formed at least in the second dielectric layer and over the conductive rail structure, wherein the deep via is electrically connected to the conductive rail structure; anda first plurality of metal lines formed over and electrically connected to the deep via.2. The semiconductor structure of claim 1 , wherein the plurality of gate structures are formed perpendicular to the conductive rail structure.3. The semiconductor structure of claim 1 , wherein the plurality of gate structures are gate structures of transistor devices.4. The semiconductor structure of claim 3 , wherein the transistor devices comprise a fin field-effect transistor.5. The semiconductor structure of further comprising a second plurality of metal lines formed above the conductive rail structure and in parallel with the conductive rail structure.6. The semiconductor structure of claim 5 , wherein the second plurality of metal ...

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Номер записи: 124
28-03-2019 дата публикации

LOCAL INTERCONNECT STRUCTURE

Номер: US20190096909A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, Chuang Cheng-Chi, Lai Chih-Ming, LAI Wei-An, LIN WEI-CHENG, Liu Ru-Gun, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures. 1. An apparatus comprising:a transistor with a gate terminal, a first source/drain terminal coupled to a reference metal line, and a second source/drain terminal;a local interconnect structure coupled to the gate terminal and routed at a same interconnect level as the reference metal line;a first interconnect structure coupled to the first source/drain terminal and routed above the local interconnect structure; anda second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure.2. The apparatus of claim 1 , further comprising:an other transistor with an other gate terminal, a third source/drain terminal coupled to an other reference metal line, and a fourth source/drain terminal, wherein the local interconnect structure is coupled to the gate terminal and the other gate terminal;a third interconnect structure coupled to the third source/drain terminal and routed above the local interconnect structure and at the same interconnect level as the first and second ...

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Номер записи: 125
02-06-2022 дата публикации

MANUFACTURING METHOD OF AN INPUT CIRCUIT OF A FLIP-FLOP

Номер: US20220173726A1
Автор: CHEN Chih-Liang, XU JIN-WEI, Zhuang Hui-Zhong
Принадлежит:

A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip. 1. A manufacturing method of an input circuit of a flip-flop , comprising:depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first gate strip and the second gate strip, a distance between the second gate strip and the third gate strip, and a distance between the third gate strip and the fourth gate strip equal;executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip, wherein the first first gate strip is a gate terminal of a first PMOS, and the second first gate strip is a gate terminal of a first NMOS;executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip, wherein the first third gate strip is a gate terminal of a second PMOS and the second third gate strip is a gate terminal of a second NMOS, anddirecting a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.2. The manufacturing method of claim 1 , further comprising:directing a first voltage to a source terminal of the first PMOS; anddirecting a ...

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Номер записи: 126
20-04-2017 дата публикации

Dual Power Structure with Connection Pins

Номер: US20170110405A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen
Принадлежит:

The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues. 1. An integrated chip , comprising:a first metal interconnect layer comprising a lower metal wire extending in a first direction;a second metal interconnect layer comprising a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction; anda third metal interconnect layer comprising an upper metal wire extending over the lower metal wire and the plurality of connection pins in the first direction, wherein the upper metal wire is coupled to the plurality of connection pins by way of a second via layer arranged over the first via layer.2. The integrated chip of claim 1 , wherein the plurality of connection pins comprise:a first set of connection pins straddling a first edge of the lower metal wire and arranged at a first pitch; anda second set of connection pins straddling a second edge of the lower metal wire, which is opposite the first edge, wherein the second set of connection pins is arranged with respect to the first set of connection pins at a second pitch ...

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Номер записи: 127
02-04-2020 дата публикации

Method for manufacturing semiconductor device

Номер: US20200105795A1
Автор: Chew-Yuen Young, Chih-Liang Chen, Ching-Fang Huang, Jack Liu, Jiann-Tyng Tzeng, Sing-Kai Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.

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Номер записи: 128
27-04-2017 дата публикации

Via Rail Solution for High Power Electromigration

Номер: US20170117272A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Wen-Hao, Lai Chih-Ming, Liu Ru-Gun, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Yu Chi-Yeh
Принадлежит:

The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit. 1. An integrated circuit , comprising:a plurality of conductive contacts arranged over a semiconductor substrate;a first metal interconnect wire arranged over the plurality of conductive contacts;a second metal interconnect wire arranged over the first metal interconnect wire; anda via rail arranged over the first metal interconnect wire and configured to electrically couple the first metal interconnect wire and the second metal interconnect wire, wherein the via rail has a length that continuously extends over two or more of the plurality of conductive contacts.2. The integrated circuit of claim 1 , further comprising:a via arranged over the first metal interconnect wire at a location offset from the via rail, wherein the via and the via rail have a same width and different lengths.3. The integrated circuit of claim 1 , further comprising:an active area comprising a plurality of source/drain regions arranged within a well region disposed within the semiconductor substrate;a plurality of gate structures ...

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Номер записи: 129
04-05-2017 дата публикации

WIRING CONCENTRATION APPARATUS WITH REMOVABLE POWER SOURCE

Номер: US20170126042A1
Автор: CHEN LIANG-CHIH
Принадлежит:

A wiring concentration apparatus with a removable power source is introduced. The wiring concentration apparatus includes a wiring concentration portion having a first connection end and a power portion having a second connection end corresponding to the first connection end. The wiring concentration portion and the power portion connect with and operate in conjunction with each other. Ports of the wiring concentration portion and ports of the power portion are regarded by each other as expansion ports. The ports of the wiring concentration portion enable external apparatuses to be charged. The ports of the power portion enable the external apparatuses to exchange data with a host apparatus. The wiring concentration portion and the power portion are separable from each other such that a user carries only one of them as needed, thereby achieving enhanced portability. 1. A wiring concentration apparatus with a removable power source , adapted to effect at least one of charging an external apparatus and exchanging data with a host apparatus , the wiring concentration apparatus comprising:a wiring concentration portion having a first processor, a plurality of first ports, a first connection end and a host port, wherein the first ports exchange data with the external apparatus connected thereto and exchange data with a host apparatus connected to the host port through the first processor; anda power portion having a second processor, a plurality of second ports, a second connection end corresponding to the first connection end, and an internal battery, wherein the second ports effectuate a charging process performed on the external apparatus connected to the second ports with a power derived from the internal battery through the second processor,wherein, when the wiring concentration portion and the power portion are connected through the first connection end and the second connection end, first ports of the wiring concentration portion function as the second ports ...

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Номер записи: 130
25-04-2019 дата публикации

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Номер: US20190122987A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Wen-Hao, Lai Chih-Ming, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, SUE Pin-Dai, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen, Yu Chi-Yeh
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire. 1. An integrated chip , comprising:a source region and a drain region separated by a channel region within a substrate;a middle-end-of-the-line (MEOL) structure over the drain region;a gate structure over the channel region, wherein the MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure;a first interconnect wire connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure; anda conductive strap located over the first interconnect wire, wherein the conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.2. The integrated chip of claim 1 , further comprising:a first conductive via arranged directly between the first interconnect wire and a lower surface of the conductive strap; anda second conductive via arranged directly between the conductive strap and the power rail.3. The integrated chip of claim 2 , wherein the second conductive via is directly below the lower surface of the ...

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Номер записи: 131
16-04-2020 дата публикации

FINFET SWITCH

Номер: US20200118875A1
Автор: CHEN Chih-Liang, Sio Kam-Tou, Young Charles Chew-Yuen, YU Ho Che
Принадлежит:

An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin. 1. A semiconductor switch structure comprising:contacts, including at least one source contact and at least one drain contact,gates, wherein the contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction;fins that underlie both the contacts and the gates and that are elongated in the second direction and are spaced apart from each other in the first direction;a contact via that does not contact a gate or a fin;a gate via that does not contact a contact or a fin; anda contact-gate via that is in contact with both a contact and a gate but not a fin.2. The semiconductor switch structure of claim 1 , further comprising: a first side periphery and an opposite second side periphery that extend in the first direction and together define a width of the respective rectangular area, in which the width of the wider rectangular area is greater than the width of the narrower rectangular area, and', 'a top periphery and a bottom periphery that extend in the second direction and together define a length of the respective rectangular area;, 'a coverage area, through which the switch structure extends, defined by two adjacent rectangular areas, wherein one of the rectangular areas is wider than the other, wherein each of the ...

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Номер записи: 132
27-05-2021 дата публикации

FINFET SWITCH

Номер: US20210159120A1
Автор: CHEN Chih-Liang, Sio Kam-Tou, Young Charles Chew-Yuen, YU Ho Che
Принадлежит:

An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin. 1. A semiconductor switch structure comprising:contacts, including at least one source contact and at least one drain contact,gates, wherein the gates are interspersed between the contacts;fins that underlie both the contacts and the gates, wherein the contacts and the gates are electrically and physically connected to the fins, wherein the contacts, gates, and fins occupy an overall coverage area;contact vias that do not touch a gate or a fin; andgate vias that do not touch a contact or a fin.2. The semiconductor switch structure of claim 1 , further comprising: a first side periphery and an opposite second side periphery that together define a width of the respective rectangular area, in which the width of the wider rectangular area is greater than the width of the narrower rectangular area, and', 'a top periphery and a bottom periphery that together define a length of the respective rectangular area;, 'wherein the overall coverage area has a polygonal periphery, wherein the overall coverage area is defined by two adjacent rectangular areas, wherein one of the rectangular areas is wider than the other, wherein each of the narrower rectangular area and the wider rectangular area is defined bywherein the top periphery of the narrower rectangular area coincides ...

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Номер записи: 133
11-05-2017 дата публикации

Seated Inversion Table

Номер: US20170128309A1
Автор: CHEN Chih-Liang
Принадлежит:

The seated inversion table is provided having a support frame assembly, and a seat back assembly, and a seat cushion assembly tiltably mounted on the support frame assembly. The seat back assembly connects to the seat cushion assembly and connects to a rotating frame assembly through a lower connecting tube assembly. The rotating frame assembly is tiltably mounted on the seat cushion assembly and is adjustably mounted on a foot-clamping frame. With a front swinging rod of the seat cushion assembly tiltably mounted on the support frame assembly, a range of an inversion angle is restricted and thereby the seated inversion table may not over tilt. 1. A seated inversion table comprising: at least one rear support component,', 'at least one front support component connected to the at least one rear support component, and', 'a connecting tube, two opposite ends of the connecting tube securely mounted on the at least one front support component;, 'a support frame assembly comprising a rear swinging rod, two opposite ends of the rear swinging rod tiltably mounted on the support frame assembly,', 'a rear-rod-tilting frame tiltably mounted at a center of the rear swinging rod, and', 'a back cushion securely mounted at one end of the rear-rod-tilting frame;, 'a seat back assembly comprising a front swinging rod, two opposite ends of the front swinging rod tiltably mounted on the support frame assembly,', 'a cushion bottom rod, one end of the cushion bottom rod securely mounted on the rear swinging rod of the seat back assembly, and another end of the cushion bottom rod securely mounted on the front swinging rod, and', 'a sitting cushion movably mounted on the cushion bottom rod and the cushion bottom rod located on a bottom surface of the sitting cushion;, 'a seat cushion assembly comprising a lower connecting tube located on the bottom surface of the sitting cushion, one end of the lower connecting tube securely mounted at another end of the rear-rod-tilting frame of the seat ...

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Номер записи: 134
23-04-2020 дата публикации

ASYNCHRONOUS/SYNCHRONOUS INTERFACE

Номер: US20200126601A1
Автор: Chen Chih Liang, LEE June, Nobunaga Dean K.
Принадлежит:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. 120-. (canceled)21. An apparatus , comprising: receive, on a first edge of a signal, a first command corresponding to performance of a memory operation performed using the memory interface while the memory interface is operating in a synchronous mode;', 'switch from the synchronous mode to an asynchronous mode; and', 'receive, on a second edge of the signal, a second command corresponding to performance of a memory operation performed using the memory interface while the memory interface is operating in the asynchronous mode., 'a memory interface configured to22. The apparatus of claim 21 , wherein the first edge is a rising edge of the signal and wherein the second edge is a falling edge of the signal.23. The apparatus of claim 21 , wherein the signal is an address latch enable signal claim 21 , a command latch enable signal claim 21 , or both.24. The apparatus of claim 21 , wherein the memory interface is further configured to receive claim 21 , on the first edge of the signal claim 21 , address information claim 21 , data claim 21 , or both.25. The apparatus of claim 21 , wherein the memory interface is configured to latch data in the synchronous mode such that the data is center aligned with a data strobe signal ...

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Номер записи: 135
03-06-2021 дата публикации

High-Density Semiconductor Device

Номер: US20210166947A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method comprising:depositing a first material on a substrate;depositing on the substrate a second material;depositing a spacer material on the first and second materials;forming a third material on a sidewall of the spacer; andetching the third material on the sidewall of the spacer to expose a portion of the first material.2. The method of claim 1 , wherein the second material has an etch selectivity different from an etch selectivity of the first material3. The method of claim 1 , further comprising converting the third material on the sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.4. The method of claim 3 , wherein converting the third material on the sidewall of the spacer into the fourth material includes implanting ions in the third material on the sidewall of the spacer.5. The method of claim 3 , wherein converting the third material on the sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.6. The method of claim 5 , wherein the tilt angle is between about 30 degrees and about 60 degrees relative to a horizontal axis.7. The method of claim 1 , further comprising removing the exposed portion of the first material to expose a portion of the substrate.8. The method of claim 1 , further comprising etching back the second material to a height of the first material.9. The method of claim 1 , further comprising etching the substrate using a second spacer material as an etch mask to form a ...

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Номер записи: 136
18-05-2017 дата публикации

LAYOUT MODIFICATION METHOD AND SYSTEM

Номер: US20170140086A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Yen-Ming, Lai Chih-Ming, Lai Jui-Yao, Liu Ru-Gun, Sio Kam-Tou, Wen Tsung-Yao, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level. 1. A layout modification method performed by at least one processor , the layout modification method comprising:analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments;determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; andmerging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.2. The layout modification method of claim 1 , further comprising:analyzing, by the at least one processor, allocation of the plurality of specific layout segments of the circuit cell layout to determine a third specific layout segment and a fourth specific layout segment from the plurality of specific layout segments;determining, by the at least one processor, if the third specific layout segment and the fourth specific ...

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Номер записи: 137
15-09-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20220293638A1
Автор: CHEN Chih-Liang, TIEN Li-Chun, Wang Pochun, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит:

A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided. 1. A method for manufacturing a semiconductor structure , comprising:forming a fin structure over a substrate;forming a source/drain of a first transistor, a source/drain of a second transistor and a first semiconductive component in the fin structure of the substrate at a first elevation, wherein the first semiconductive component is adjacent to the source/drain of the second transistor;forming a gate structure of the first transistor and a gate structure of the second transistor surrounding the fin structure of the substrate, wherein the source/drain and the gate structure of the first transistor are arranged along a horizontal direction, and the source/drain and the gate structure of the second transistor are arranged along the horizontal direction;forming a source/drain of a third transistor, a source/drain of a fourth transistor, and a second semiconductive component in the fin structure of the substrate at a second elevation, wherein the second semiconductive component is ...

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Номер записи: 138
31-05-2018 дата публикации

High-Density Semiconductor Device

Номер: US20180151381A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a first material on a substrate;depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material;depositing a spacer material on the first and second materials; andetching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.2. The method of claim 1 , further comprising:forming a mandrel above the substrate;depositing a second spacer material on a sidewall of the mandrel; andremoving the mandrel, thereby leaving a spacer.3. The method of claim 2 , further comprising forming a third material on a top surface and opposite first and second sidewalls of the spacer.4. The method of claim 3 , further comprising converting the third material on the top surface and the second sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.5. The method of claim 4 , wherein converting the third material on the top surface and the second sidewall of the spacer into the fourth material includes implanting ions in the third material on the top surface and the second sidewall of the spacer.6. The method of claim 4 , wherein converting the third material on the top surface and the second sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.7. The method of claim 3 , further comprising etching the ...

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Номер записи: 139
31-05-2018 дата публикации

Self Aligned Via and Method for Fabricating the Same

Номер: US20180151432A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, Chuang Cheng-Chi, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, Young Charles Chew-Yuen
Принадлежит:

A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal. 1. A method for fabricating a semiconductor device , comprising:depositing a first metal into a first trench of a first dielectric layer such that a top surface of the first metal is below a top surface of the first dielectric layer;depositing a second dielectric layer over the first metal;depositing a third dielectric layer over the first dielectric layer and the second dielectric layer;etching the third dielectric layer to create a second trench that exposes a portion of the first dielectric layer and a portion of the second dielectric layer; andetching the exposed portion of the second dielectric layer to expose a portion of the first metal to create a via to the first metal.2. The method of claim 1 , further comprising depositing a second metal into the second trench such that the second metal is electrically coupled to the first metal.3. The method of claim 1 , wherein a top surface of the second dielectric layer is at substantially the same level as the top surface of the first dielectric layer4. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer have different etching sensitivities.5. The method of claim 1 , wherein the third dielectric ...

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Номер записи: 140
31-05-2018 дата публикации

Semiconductor Device with Reduced Leakage Current

Номер: US20180151550A1
Автор: CHEN Chih-Liang, CHIU Yi-Hsun, HOU Yuan-Te, PENG SHIH-WEI, TZENG JIANN-TYNG, WANG Chung-Hsing, Young Charles Chew-Yuen
Принадлежит:

An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced. 1. An integrated circuit comprising:a substrate; and a first pair of functional cells, a first cell in the first pair having a first threshold voltage and a second cell in the first pair having a second threshold voltage; and', 'a filler cell between the functional cells thereof;, 'a first set of functional cell units formed over the substrate, each of the functional cell units comprisinga second set of functional cell units, each of which includes a second pair of functional cells, a third cell in the pair having a third threshold voltage and a fourth cell in the second pair having a fourth threshold voltage, the third cell and the fourth cell abutting against each other;wherein a first number of the functional cell units in the first set is equal to or greater than a second number of the functional cell units in the second set.2. The integrated circuit of claim 1 , wherein a ratio of the first number to the sum of the first and second numbers ranges from 0.5 to 1.3. The integrated circuit of claim 1 , wherein the filler cell of one of the functional cell units in the first set has a filler gate electrode.4. The integrated circuit of claim 3 , wherein the filler gate electrode is floating.5. The integrated circuit of claim 3 , wherein the filler gate electrode is tied to a power supply line.6. The integrated circuit of claim 1 , wherein the filler cell of one of the functional ...

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Номер записи: 141
31-05-2018 дата публикации

High-Density Semiconductor Device

Номер: US20180151551A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou SIO, Lei-Chun Chou, Ru-Gun Liu, Wei-Hao Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of manufacturing a semiconductor device includes providing a material above a substrate and respectively forming separate gate electrode lines on opposite sidewalls of the material. As such, a width of cut between the gate electrode lines can be minimized. This shortens a height of cell of the semiconductor device, increasing a cell density of the semiconductor device.

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Номер записи: 142
17-06-2021 дата публикации

STANDARD CELLS HAVING VIA RAIL AND DEEP VIA STRUCTURES

Номер: US20210183772A1
Автор: CHEN Chih-Liang, Chuang Cheng-Chi, Lai Wayne, LIN WEI-CHENG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines. 1. A method for forming a semiconductor structure , comprising:forming a plurality of source/drain (S/D) contact structures;depositing a first conductive material to form first and second via rail structures, wherein at least one of the first and second via rail structures is in physical contact with two or more S/D contact structures of the plurality of S/D contact structures;depositing a second conductive material to form a deep via in physical contact with the second via rail structure;forming a first interconnect line above the first and second via rail structures and in physical contact with the first via rail structure, wherein the first interconnect line is formed in a lowest wiring level; andforming a second interconnect line over and physically connected to the deep via, wherein the second interconnect line is in a second lowest wiring level.2. The method of claim 1 , further comprising depositing a first dielectric layer and etching a plurality of first trenches in the first dielectric layer.3. The method of claim 2 , wherein depositing the first conductive material comprises depositing copper into the plurality of first trenches.4. The method of claim 2 , further comprising depositing a second dielectric layer on the first dielectric layer and etching a second trench in the second dielectric layer.5. The method of claim 4 , wherein depositing the second conductive material comprises depositing copper into the second trench.6. The method of claim 1 ...

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Номер записи: 143
22-09-2022 дата публикации

SEMICONDUCTOR DEVICE INCLUDING RECESSED INTERCONNECT STRUCTURE

Номер: US20220302026A1
Автор: Chang Shang-Wen, CHEN Chih-Liang, CHIU Yi-Hsun, Chuang Cheng-Chi, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction. 1. A semiconductor device , comprising:a first gate structure extending along a first lateral direction;a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction, the first interconnect structure including a first portion and a second portion electrically isolated from each other by a first dielectric structure;a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure,wherein the second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.2. The semiconductor device of claim 1 , wherein the recessed portion of the second interconnect structure is directly connected to the first gate structure claim 1 , and wherein the second interconnect structure further includes a non-recessed portion that is directly connected to the first ...

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Номер записи: 144
22-09-2022 дата публикации

SEMICONDUCTOR DEVICE INCLUDING RECESSED INTERCONNECT STRUCTURE

Номер: US20220302027A1
Автор: Chang Shang-Wen, CHEN Chih-Liang, CHIU Yi-Hsun, Chuang Cheng-Chi, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction. 1. A method for manufacturing a semiconductor device , comprising:forming a first gate structure overlaid by a first sacrificial layer;forming a source/drain structure overlaid by a second sacrificial layer;replacing the first sacrificial layer and an upper portion of the second sacrificial layer with a first interconnect structure;recessing a portion of the first interconnect structure, wherein the recessed portion is vertically aligned with the first gate structure;filling the recessed portion with a dielectric material to form a recessed dielectric structure; andforming a second interconnect structure over the first interconnect structure.2. The method of claim 1 , wherein a top boundary of a first portion of the first interconnect structure is in direct contact with one of a plurality of separated portions of the second interconnect structure claim 1 , and a bottom boundary of a second portion of the first interconnect structure is in direct contact with the first gate structure.3. The method of claim 2 , wherein the second portion is shorter than the first portion claim 2 , with respective bottom ...

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Номер записи: 145
24-06-2021 дата публикации

Buried Metal for FinFET Device and Method

Номер: US20210193504A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Lei-Chun Chou, Ru-Gun Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

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Номер записи: 146
30-05-2019 дата публикации

Buried Metal for FinFET Device and Method

Номер: US20190164805A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Lei-Chun Chou, Ru-Gun Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

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Номер записи: 147
30-05-2019 дата публикации

SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD

Номер: US20190164882A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, LIOU CHUN-HUNG, Liu Jack, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail. 1. A semiconductor device , comprising:a substrate;a dielectric region situated on the substrate;a plurality of conductive regions situated on the dielectric region;a first conductive rail situated within the dielectric region, the first conductive rail being electrically connected to a first conductive region of the plurality of conductive regions; anda conductive structure penetrating through the substrate and formed under the first conductive rail, the conductive structure being electrically connected to the first conductive rail.2. The semiconductor device of claim 1 , the conductive structure comprises a conductive through-substrate via.3. The semiconductor device of claim 1 , further comprising:a power grid conductor situated under the substrate, the power grid conductor being electrically connected to the conductive structure.4. The semiconductor device of claim 3 , further comprising:a metal pad situated between the substrate and the power grid conductor, the metal pad configured to electrically connect the power grid conductor to the substrate.5. The semiconductor device of claim 1 , further comprising:a fin structure protruding from the substrate and the dielectric region and contacting the conductive structure.6. The semiconductor device of claim 5 , further comprising:a second conductive rail situated within the dielectric ...

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Номер записи: 148
30-05-2019 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20190165178A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices. 1. A semiconductor structure comprising:a substrate and an interlayer dielectric layer formed on the substrate;a fin protruding from the substrate and the interlayer dielectric layer;a rail structure formed in the interlayer dielectric layer, wherein the rail structure is opposing a first sidewall of the fin and in parallel with the fin; andfirst and second conductive structures formed around the fin and directly contacting the rail structure.2. The semiconductor structure of claim 1 , further comprises another rail structure formed in the interlayer dielectric layer claim 1 , wherein the another rail structure is opposing a second sidewall of the fin and in parallel with the fin.3. The semiconductor structure of claim 2 , wherein at least one of the first and second conductive structures directly contacts the another rail structure.4. The semiconductor ...

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Номер записи: 149
29-09-2022 дата публикации

SEMICONDUCTOR DEVICE HAVING BURIED LOGIC CONDUCTOR TYPE OF COMPLEMENTARY FIELD EFFECT TRANSISTOR, METHOD OF FORMING SAME

Номер: US20220310598A1
Автор: CHEN Chih-Liang, TIEN Li-Chun, Wang Pochun, Wu Guo-Huei
Принадлежит:

A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors. 1. A semiconductor device comprising a buried logic conductor (BLC) CFET including:a complementary field effect transistor (CFET) including active regions arranged in a stack relative to a first direction; alpha logic conductors configured for logic signals (alpha logic conductors); and', 'power grid (PG) conductors; and, 'relative to the first direction, a first layer of metallization (M_1st layer) over the CFET which includes 'beta logic conductors;', 'relative to the first direction, a layer of metallization (M_B layer) below the CFET which includesthe alpha logic, beta logic and PG conductors extending in a second direction which is perpendicular to the first direction; and the zone being occupied by the alpha logic and PG conductors; and', 'each of the CFET and the beta logic conductors overlapping the zone., 'relative to a zone defined in terms of a third direction which is perpendicular to each of the first and second directions2. The semiconductor device of claim 1 , wherein: a pitch of the alpha logic conductors (pch_M_1st_lgk); and', 'a pitch of the PG conductors (pch_M_1st_pg); and pch_M_1st_lgk Подробнее

Номер записи: 150
25-06-2015 дата публикации

Thermal analysis for tiered semiconductor structure

Номер: US20150179529A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Jiann-Tyng Tzeng, Shu-Hui Sung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure. The one or more segments are iteratively evaluated during electrical simulation while taking into account thermal properties to determine power metrics for the segments. The power metrics are used to determine temperatures generated by integrated circuitry within the segments. Responsive to a segment having a temperature above a temperature threshold, a temperature action plan, such as providing an alert or inserting one or more thermal release structures into the segment, is implemented. In this way, the one or more segments are iteratively evaluated to identify and resolve thermal and reliability issues.

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Номер записи: 151
21-06-2018 дата публикации

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Номер: US20180174967A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Wen-Hao, Lai Chih-Ming, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, SUE Pin-Dai, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen, Yu Chi-Yeh
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail. 1. A method of forming an integrated chip , comprising:forming a plurality of gate structures extending in a first direction over an active area of a substrate;forming a plurality of middle-end-of-the-line (MEOL) structures extending in the first direction over the active area, wherein the plurality of MEOL structures are interleaved between the plurality of gate structures along a second direction;forming a power rail that extends in the second direction;forming a first metal wire extending in the second direction over the plurality of MEOL structures;performing a double patterning process to form a second metal wire extending in the first direction over the first metal wire and a third metal wire extending in the first direction over the first metal wire, wherein the second metal wire is separated from the third metal wire along the second direction; andcutting the second metal wire according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the plurality of MEOL structures to the power rail.2. The method of claim 1 ,wherein the first metal wire is connected to the first one of the ...

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Номер записи: 152
05-07-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180190652A1
Автор: CHEN Chih-Liang, Ching Kuo-Cheng, Ju Shi Ning, Wang Chih-hao
Принадлежит:

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall. 1. A method of manufacturing a semiconductor device , the method comprising:forming a separation wall made of a dielectric material between two fin structures;forming a dummy gate structure over the separation wall and the two fin structures;forming an interlayer dielectric (ILD) layer over the dummy gate structure;removing an upper portion of the ILD layer, thereby exposing the dummy gate structure;replacing the dummy gate structure with a metal gate structure; andperforming a planarization operation to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure,wherein the first gate structure and the second gate structure are separated by the separation wall.2. The method of claim 1 , wherein the separation wall includes one or more layers of SiCN claim 1 , zirconium oxide claim 1 , aluminum oxide and hafnium oxide.3. The method of claim 1 , wherein the dummy gate structure includes a dummy gate electrode made of poly silicon.4. The method of claim 1 , further comprising:forming the two fin structures; andforming an isolation insulating layer such that upper portions of the two fin structures protrude from the isolation insulating layer,wherein a bottom of the separation wall is embedded in ...

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Номер записи: 153
11-06-2020 дата публикации

SYSTEM FOR AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

Номер: US20200184139A1
Автор: CHEN Chih-Liang, Chien Wei-Chen, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias. 1. A method of manufacturing an integrated circuit , the method comprising:defining a via grid having a first minimum pitch in a first direction and a second minimum pitch in a second direction different from the first direction;defining design criteria of the integrated circuit, the design criteria including at least via spacing rules of the integrated circuit;generating a first layout design of the integrated circuit based on the via grid and the design criteria, the first layout design having a first set of vias arranged in first rows and first columns based on the via grid, the first rows of the first set of vias being arranged in the first direction, the first columns of the first set of vias being arranged in the second direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set;generating a via color layout design of the integrated circuit based on the first layout design ...

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Номер записи: 154
11-07-2019 дата публикации

SYSTEM BOOT CODE CLONE

Номер: US20190212999A1
Автор: CHEN Chih-Liang
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A memory device includes a non-volatile memory configured with a block including first and second portions and an address decoder mapping received command addresses to physical addresses of the non-volatile memory. The memory device includes control circuitry maintaining a current status of the first portion and the second portion and implementing an update operation, including responsive to receiving a write command sequence to the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information, and upon completion of the updating, changing the current status to indicate that the selected one of the first and second portion is the current area. 1. A memory device , comprising: the first portion is represented by a first range of physical addresses; and', 'the second portion is represented by a second range of physical addresses;, 'a non-volatile memory configured with a block having a first portion and a second portion, whereinan address decoder that maps received command addresses to physical addresses of the non-volatile memory; and responsive to receiving a write command sequence including a write command address of the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information; and', 'upon completion of the updating of the selected one of the first portion and the second portion, changing the current status to indicate that the selected one of the first portion and the second portion is the current area storing the information and to indicate that the unselected one of the first portion and the second portion is available for being updated with ...

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Номер записи: 155
08-08-2019 дата публикации

DUAL POWER STRUCTURE WITH CONNECTION PINS

Номер: US20190244901A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin. 1. A method of forming an integrated chip , comprising:forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions;forming a lower power rail extending in a second direction perpendicular to the first direction;forming a first connection pin electrically coupled to one of the plurality of source/drain regions and to the lower power rail, wherein the first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin; andforming an upper power rail directly over the lower power rail and extending in the second direction, the upper power rail electrically coupled to the first connection pin.2. The method of claim 1 , wherein one of the opposing ends of the first connection pin is directly over the lower power rail.3. The method of claim 1 , wherein the first connection pin is between adjacent ones of the plurality of gate structures along the second direction.4. The method of claim 1 , further comprising:forming a middle-of-the-line (MOL) structure contacting a first one of the plurality of source/drain regions and extending in the first direction between ...

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Номер записи: 156
30-07-2020 дата публикации

Metal Patterning For Internal Cell Routing

Номер: US20200243447A1
Автор: CHEN Chih-Liang, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal. 1. A semiconductor device , comprising:a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, wherein the first supply metal tract, and the second supply metal tract are arranged in parallel, the first pattern metal layer comprising:an internal route; anda first power route; anda follow pin coupling the first supply metal to the power route.2. The semiconductor device of claim 1 , wherein the second supply metal tract is wider than the first supply metal tract.3. The semiconductor device of claim 2 , wherein the first supply metal tract has a thickness substantially same as the first pattern metal layer.4. The semiconductor device of claim 1 , further comprising:a second pattern metal layer disposed between the first supply metal tract and the second supply metal tract, the second pattern metal layer comprising:a second internal route; anda second power route,wherein the follow pin couples the first supply metal tract to the second power route.5. The semiconductor device of claim 1 , wherein:the first supply metal tract is a power supply or a voltage drain drain (“VDD”) and the second supply metal tract is a ground supply or a voltage source source (“VSS”).6. The semiconductor device of claim 1 , wherein the first supply metal tract and the second supply metal tract comprise a first metal and the follow pin comprises a second metal.7. A semiconductor structure claim 1 , comprising:a first cell, including:a first supply metal line;a second supply metal line; anda first pattern metal layer disposed between the first supply metal line and ...

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Номер записи: 157
15-09-2016 дата публикации

Structure and method for semiconductor device

Номер: US20160268244A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Chun-Kuang Chen, Jiann-Tyng Tzeng, Kam-Tou SIO, Ru-Gun Liu, Shih-Wei Peng, Shun-Li Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a semiconductor structure includes following operations. Gate structures are arranged above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure. The first and second active regions are spaced apart by the non-active region. Contacts are arranged above the first and second active regions. At least one gate via is arranged above the first active region or the second active region. The at least one gate via is electrically coupled with the gate structures. At least one local interconnect is selectively arranged over the non-active region, to couple at least one of the contacts above the first active region to at least one of the contacts above the second active region.

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Номер записи: 158
20-09-2018 дата публикации

CURVED TREADMILL

Номер: US20180264315A1
Автор: Chen Chih Liang
Принадлежит:

A curved treadmill has a frame assembly, a handrail assembly, and a belt assembly. The frame assembly has a support frame, two arced guide tracks, two cushions, multiple guide wheels, and multiple positioning wheels. Each arced guide track is concaved downward. The cushions are mounted on the arced guide tracks. The guide wheels are mounted on the support frame. The positioning wheels are mounted between two ends of the support frame. The belt assembly includes two connection belts and multiple pedals. The connection belts are wrapped around the guide wheels, and one side of each connection belt abuts the positioning wheels. The pedals are mounted on the connection belts and optionally abut the cushions. Therefore, with the cushions, impacts may be absorbed and noises may be reduced. Besides, by abutting the positioning wheels, the connection belt may not be distorted sideward, and the noises are reduced further. 1. A curved treadmill comprising: a support frame;', 'two arced guide tracks being concaved downward and disposed on two sides of the support frame respectively;', 'two cushions mounted securely on upper surfaces of the two arced guide tracks respectively;', 'a plurality of guide wheels mounted on a front end and a rear end of the support frame; and', 'a plurality of positioning wheels mounted between the front end and the rear end of the support frame;, 'a frame assembly comprisinga handrail assembly mounted on two sides of the frame assembly and comprising a handrail; and at least one connection belt wrapped around the guide wheels, and one side of the at least one connection belt abutting or adjacent to the positioning wheels; and', 'a plurality of pedals securely mounted on the at least one connection belt, juxtaposed and adjacent to each other, and downward and optionally abutting the two cushions., 'a belt assembly wrapped around the frame assembly, and comprising2. The curved treadmill as claimed in claim 1 , wherein each one of the pedals of the ...

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Номер записи: 159
09-12-2021 дата публикации

SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD

Номер: US20210384351A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, LIOU CHUN-HUNG, Liu Jack, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail. 1. A semiconductor device , comprising:a substrate;a dielectric region situated on the substrate;a first fin structure protruding from the substrate and the dielectric region;a second fin structure protruding from the substrate and the dielectric region, the second fin structure extending parallel to the first fin structure;a plurality of conductive regions situated on the dielectric region;a first conductive rail situated within the dielectric region, the first conductive rail being electrically connected to a first conductive region of the plurality of conductive regions, wherein a first side of the first conductive rail faces the first fin structure, and a second side of the first conductive rail opposite to the first side faces the second fin structure; anda conductive structure penetrating through the substrate and formed under the first conductive rail, the conductive structure being electrically connected to the first conductive rail.2. The semiconductor device of claim 1 , wherein the conductive structure ...

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Номер записи: 160
16-12-2021 дата публикации

Footprint for multi-bit flip flop

Номер: US20210391850A1
Автор: Chih-Liang Chen, Hui-Zhong ZHUANG, Jerry Chang-Jui Kao, Po-Chun Wang, Tzu-Ying LIN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

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Номер записи: 161
19-10-2017 дата публикации

FINFET SWITCH

Номер: US20170301586A1
Автор: CHEN Chih-Liang, Sio Kam-Tou, Young Charles Chew-Yuen, YU Ho Che
Принадлежит:

An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin. 1. A semiconductor switch structure comprising:contacts, including source contacts and drain contacts;gates, wherein the contacts and the gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction, and wherein the gates are interspersed between the contacts;fins that underlie both the contacts and the gates and that are elongated in the second direction and are spaced apart from each other in the first direction;a contact via that extends through one of the contacts without contacting a gate or a fin;a gate via that extends through one of the gates without contacting a contact or a fin; anda contact-gate via that is in contact with both a contact and a gate but not a fin.2. The semiconductor switch structure of claim 1 , further comprising: a first side periphery and an opposite second side periphery that extend in the first direction and together define a width of the respective rectangular area, in which the width of the wider rectangular area is greater than the width of the narrower rectangular area, and', 'a top periphery and a bottom periphery that extend in the second direction and together define a length of the respective rectangular area;, 'a coverage area, through which the ...

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Номер записи: 162
19-10-2017 дата публикации

Advanced Metal Connection With Metal Cut

Номер: US20170301618A1
Автор: CHEN Chih-Liang, CHEN Shun Li, Chuang Cheng-Chi, Lai Chih-Ming, Lin Tien-Lu, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures.2. The method of claim 1 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 1 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.3. The method of claim 2 , further comprising:fabricating via interconnections between the conductive interconnection ...

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Номер записи: 163
25-10-2018 дата публикации

Metal Patterning For Internal Cell Routing

Номер: US20180308796A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Hui-Ting Yang, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The second supply metal tract is wider than the first supply metal tract. The first supply metal tract has a thickness substantially same as the first pattern metal layer. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

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Номер записи: 164
02-11-2017 дата публикации

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Номер: US20170317027A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Chen Wen-Hao, Lai Chih-Ming, Liu Ru-Gun, Peng Shi-Wei, Sio Kam-Tou, SUE Pin-Dai, TZENG JIANN-TYNG, YEN Yung-Sung, Young Charles Chew-Yuen, Yu Chi-Yeh
Принадлежит:

The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced. 1. An integrated chip comprising:an active area comprising a plurality of source/drain regions;a middle-end-of-the-line (MEOL) structure contacting the active area and extending in a first direction;a first metal wire layer comprising a first metal wire connected to the MEOL structure by a conductive contact, wherein the first metal wire extends in a second direction perpendicular to the first direction;a power rail located on a metal wire layer that extends in the second direction at a location laterally offset from the active area; anda metal strap extending in the first direction and connected to the first metal wire by a first conductive via and to the power rail by a second conductive via.2. The integrated chip of claim 1 , further comprising:a plurality of gate structures arranged over the active area on opposing sides of the MEOL structure and extending in the first direction.3. The integrated chip of claim 2 , wherein the active area continuously extends past two or more of the plurality of gate structures.4. The integrated chip of claim 2 , further comprising:a ...

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Номер записи: 165
24-09-2020 дата публикации

SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD

Номер: US20200303551A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, LIOU CHUN-HUNG, Liu Jack, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate. 1. A method for forming a non-planar semiconductor device , comprising:forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device;depositing a dielectric region on the front side of the substrate, wherein the dielectric region comprises a first conductive rail buried within the dielectric region and being in parallel with the fin structure;etching the dielectric region to create a first opening in the dielectric region to expose the first conductive rail and a portion of the dielectric region;depositing a plurality of conductive regions on the dielectric region, wherein a first conductive region of the conductive regions contacts the first conductive rail through the first opening, and the first conductive region contacts a top surface of the first conductive rail at a level where the first conductive region contacts a top surface of the portion of the dielectric region;etching the substrate from a backside of the substrate to form a second opening to expose the first conductive rail; andfilling a first conductive material into the second opening to form a through-substrate ...

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Номер записи: 166
03-10-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20190305006A1
Автор: CHEN Chih-Liang, Huang Ching-Fang, HUANG SING-KAI, Liu Jack, TZENG JIANN-TYNG, YOUNG CHEW-YUEN
Принадлежит:

A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions. 1. A semiconductor device , comprising:a substrate;a pair of transistor devices over the substrate, wherein each of the pair of the transistor devices comprises a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode; andan isolation region between the source/drain regions of the pair of the transistor devices, wherein the isolation region has a first doping type opposite to a second doping type of the source/drain regions.2. The semiconductor device of claim 1 , wherein a thickness of the isolation region is substantially equal to a thickness of the channel.3. The semiconductor device of claim 1 , wherein a thickness of the isolation region is larger than a thickness of the channel.4. The semiconductor device of claim 1 , further comprising a pair of second isolation regions on two opposing sides of the isolation region claim 1 , wherein the pair of the second isolation regions has the first doping type claim 1 , and a doping concentration of the pair of the second isolation regions is lower than that of the isolation region.5. The semiconductor device of claim 4 , wherein a thickness of the the pair of the second isolation regions is substantially equal to a thickness of the isolation region.6. The semiconductor device of claim 1 , wherein the substrate comprises a semiconductor base and an insulation layer claim 1 , the insulation layer is between the semiconductor base and the the pair of the ...

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Номер записи: 167
19-11-2015 дата публикации

Structure and Method for Semiconductor Device

Номер: US20150332962A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Chun-Hung Liou, Kam-Tou SIO, Meng-Hung Shen, Ru-Gun Liu, Shu-Hui Sung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

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Номер записи: 168
09-11-2017 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20170323832A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance. 1. An integrated chip , comprising:a well region comprising a plurality of source/drain regions;a plurality of gate structures arranged over the well region at a substantially regular pitch;a plurality of middle-of-the-line (MOL) structures vertically confined between the well region and a plane extending along upper surfaces of the plurality of gate structures and laterally interleaved between some of the plurality of gate structures;wherein the plurality of MOL structures are arranged over the well region at an irregular pitch comprising a first pitch that is larger than the substantially regular pitch; andwherein the plurality of MOL structures respectively have a first width that is larger than a second width of respective ones of the plurality of gate structures along a direction parallel to a direction of the first pitch.2. The integrated chip of claim 1 , further comprising:conductive contacts arranged over the plurality of MOL structures and configured to electrically coupled the plurality of MOL structures to overlying metal wires, wherein the conductive contacts have smooth sidewalls continuously ...

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Номер записи: 169
03-12-2015 дата публикации

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Номер: US20150349071A1
Автор: CHANG Helen Shu-Hui, CHEN Chih-Liang, LIN WEI-CHENG, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Company Limited

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance. 2. The semiconductor arrangement of claim 1 , where the dimensions of the semiconductor arrangement conform to W≧k7×L claim 1 , whereW is a sum of contact widths of contacts between the first gate and the second gate,k7 is a seventh constant of about 1.48 to about 1.52, andL is at least one of the first gate length or the second gate length.3. The semiconductor arrangement of claim 1 , where the dimensions of the semiconductor arrangement conform to C≧(k8×H)+(k9×L) claim 1 , where{'sub': 'tl', 'Cis the first top contact length,'}k8 is an eighth constant of about 0.18 to about 0.22,H is at least one of the first gate height or the second gate height,k9 is a ninth constant of about 0.74 to about 0.78, andL is at least one of the first gate length or the second gate length.4. The semiconductor arrangement of claim 1 , where the dimensions of the semiconductor arrangement conform to C≧(k10×H)+(k11×L) claim 1 , where{'sub': 'bl', 'Cis the first bottom contact length,'}k10 is a tenth constant ...

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Номер записи: 170