Semiconductor Structure

The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region. 1. A semiconductor structure , comprising:a gate structure disposed on a substrate;at least one source/drain region disposed in the substrate at two sides of the gate structure; andat least a dislocation disposed in the source/drain region and asymmetrical relating to a middle axis of the source/drain region.2. The semiconductor structure according to claim 1 , wherein there is only one dislocation located at one side relating to the middle axis of the source/drain region.3. The semiconductor structure according to claim 1 , wherein there are two dislocations which are respectively located at two sides relating to the middle axis of the source/drain region.4. The semiconductor structure according to claim 3 , wherein one dislocation is more severe than the other.5. The semiconductor structure according to claim 3 , wherein one dislocation extends a larger distance than the other.6. The semiconductor structure according to claim 1 , further comprising a plurality of fin structures disposed on the substrate claim 1 , wherein the source/drain region is located in the fin structure at two sides of the gate structure.7. The semiconductor structure according to claim 6 , wherein a region is defined on the substrate claim 6 , and the two opposite fin structures closest to an edge of the region have greater width than those of other fin structures.8. The semiconductor structure according to claim 7 , wherein there are two dislocations which are respectively located at two sides relating to the middle axis of the source/drain region claim 7 , and the dislocation far ...

Fabrication method of semiconductor structure

A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers

A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

Interacting exercise device

An interacting exercise device is revealed. The interacting exercise device includes a driving device and a non-concentric actuator driven by the driving device. While the driving device is operated to rotate, the non-concentric actuator vibrates and the vibration generated is delivered to the interacting exercise device for interacting shaking fitness.

Buffer board structure of a treadmill

A buffer board structure of a treadmill includes bamboo layers made by attaching bamboo sheets side by side, a bottom surface of which is adhered by a membrane layer whereby the bamboo sheets are firmly stuck on the membrane layer. Each membrane layer has an upper and lower faces respectively stuck between the bamboo layers. The bamboo sheets of each bamboo layer face the same juxtaposing direction, whereas bamboo layers juxtaposed lengthways provide a better buffer. By setting one membrane layer between two bamboo layers, contact faces of the bamboo layers and the membrane layer adhered together become smoother, and an adhesive fills in a gap more evenly. A slip resistant layer is stuck on the top bamboo layer. A smoother buffering effect and a stable juxtaposition are obtained when the bamboo layers are trodden to prevent the breakdown of buffer relations between the bamboo sheets and the membrane layers.

Method of manufacturing a semiconductor device

The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

BUFFER BOARD STRUCTURE OF A TREADMILL

A buffer board structure of a treadmill includes bamboo layers made by attaching bamboo sheets side by side, a bottom surface of which is adhered by a membrane layer whereby the bamboo sheets are firmly stuck on the membrane layer. Each membrane layer has an upper and lower faces respectively stuck between the bamboo layers. The bamboo sheets of each bamboo layer face the same juxtaposing direction, whereas bamboo layers juxtaposed lengthways provide a better buffer. By setting one membrane layer between two bamboo layers, contact faces of the bamboo layers and the membrane layer adhered together become smoother, and an adhesive fills in a gap more evenly. A slip resistant layer is stuck on the top bamboo layer. A smoother buffering effect and a stable juxtaposition are obtained when the bamboo layers are trodden to prevent the breakdown of buffer relations between the bamboo sheets and the membrane layers. 1. A buffer board structure of a treadmill being installed under a belt of said treadmill and applied to create a buffering effect when said belt is trodden to sink and impact on said buffer board structure , said buffer board structure comprising:a plurality of bamboo layers which are placed one over another, each of said bamboo layers including a plurality of bamboo sheets attached side by side along an axial direction, said bamboo sheets of any two of said adjacent bamboo layers being parallel to each other along said axial direction;a plurality of membrane layers, each of said membrane layers being laid between said two adjacent bamboo layers;an adhesive arranged between each of said membrane layers and each of said bamboo layers to adhere said bamboo layer to said membrane layer; anda slip resistant layer adhered to an upper surface of one of said bamboo layers which is placed at a top position.2. The buffer board structure of the treadmill as claimed in claim 1 , wherein said membrane layer is a whole wood sheet or is made by laminating wood sheets.3. The ...

Method of manufacturing semiconductor devices

A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Processes for fabricating FinFET structures with semiconductor compound portions formed in cavities and extending over sidewall spacers

A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

EXERCISE MACHINE HAVING CHANGEABLE DAMPING MECHANISM

An exercise machine having a changeable damping mechanism is provided. A first transmission rope on a first shifting wheel of a first rotating shaft drives a damping device of a damping shaft to generate a relative damping action for training the leg muscular endurance of the user. Through a first changeable damping mechanism, the first transmission rope, which having stretch elasticity on the first shifting wheel is controlled to adjust the rotational speed according to the gear ratio, which may be in cooperation with a second transmission rope, which having stretch elasticity on a second shifting wheel through a second changeable damping mechanism, and is in cooperation with the damping action of a magnetic control wheel or a blower fan of the damping device to extend the range of damping control for different users to train muscular endurance. 1. An exercise machine having a changeable damping mechanism , the exercise machine comprising a first rotating shaft , a damping device and a first changeable damping mechanism which are disposed at a front end of a main body of the exercise machine , characterized by:one side of the first rotating shaft being provided with a first shifting wheel, stepped grooves of different diameters being provided on the first shifting wheel and sized down;the damping device being disposed on a damping shaft, the damping shaft being disposed close to the first rotating shaft and located at the front end of the main body, the first rotating shaft and the damping shaft being disposed on the main body of the exercise machine, the first rotating shaft and the damping shaft being parallel and spaced apart from each other;the first changeable damping mechanism including a first speed control mechanism disposed close to the first shifting wheel and a first transmission rope, the first transmission rope which having stretch elasticity and being wound on the first shifting wheel and the damping shaft; the first speed control mechanism including ...

Interacting Exercise Device

An interacting exercise device is revealed. The interacting exercise device includes a driving device and a non-concentric actuator driven by the driving device. While the driving device is operated to rotate, the non-concentric actuator vibrates and the vibration generated is delivered to the interacting exercise device for interacting shaking fitness. 1. An interacting exercise device comprising:at least a non-concentric actuator;at least a driving device;at least an operation portion;a plurality of bearings; andat least two shafts, inserted into said interacting exercise device, wherein said driving device comprises at least a driving wheel and at least a driven wheel set, wherein said shafts are connected with said interacting exercise device through said bearings respectively, wherein an end of one of said shafts protrudes from said interacting exercise device to be connected to said operation portion and the other end thereof is passed through said driving wheel, wherein the other said shaft is passed through said driven wheel set, wherein said driving wheel meshes said driven wheel set, while said driven wheel set meshes said non-concentric actuator, wherein said driven wheel set comprises a large wheel and a small wheel coaxially disposed on said large wheel, wherein said non-concentric actuator is passed through by one of said shafts, wherein said non-concentric actuator comprises a disc, a tiny wheel coaxially arranged on said disc, and a counter weight mounted on at least an end of said disc in an unbalanced manner, wherein the diameter of said driving wheel is larger than the diameter of said small wheel of said driven wheel set, while the diameter of said large wheel of said driven wheel is larger than the diameter of said tiny wheel of said non-concentric actuator, wherein when said operation portion operated drives said driving wheel to rotate, said driven wheel set will be rotated faster at the same time and said non-concentric actuator will further ...

Method for fabricating semiconductor device with strained silicon structure

A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURE

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure. 1. A semiconductor device , comprising:a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;an isolation structure, surrounding the fin structure;a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure and covering a portion of the isolation structure, wherein the isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, and the first top surface is higher than the second top surface; andan epitaxial layer, disposed at one side of the gate structure and in direct contact with the fin structure.2. The semiconductor device according to claim 1 , wherein there is a height difference between the first top surface and second top surface claim 1 , and the height difference ranges from 100 Angstroms to 250 Angstroms.3. The semiconductor device according to claim 1 , wherein the gate structure is a metal gate structure.4. The semiconductor device according to claim 1 , wherein the isolation structure under the gate structure comprises a sidewall and the epitaxial structure is indirect contact with ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess. 1. A semiconductor process , comprising:providing a substrate;forming at least a fin-shaped structure in the substrate;forming a gate structure partially overlapping the fin-shaped structure;blanketly forming a dielectric layer on the substrate;removing a part of the dielectric layer to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure;removing the second spacer and a part of the fin-shaped structure to form at least a recess at a side of the gate structure; andforming an epitaxial layer in the recess.2. The semiconductor process according to claim 1 , wherein the first spacer partially overlaps the fin-shaped structure.3. The semiconductor process according to claim 1 , wherein the first spacer surrounds the gate structure and overlaps a part of the fin-shaped structure adjacent to the gate structure.4. The semiconductor process according to claim 1 , wherein the second spacer is aligned with the fin-shaped structure before forming the recess.5. The semiconductor process according to claim 1 , wherein the second spacer surrounds the fin-shaped structure and does not cover the gate structure and the first spacer.6. The semiconductor process according to claim 1 , wherein the gate structure comprises a gate dielectric layer claim 1 , a gate electrode and a cap layer.7. The semiconductor process ...

Horse riding exercise machine

A horse riding exercise machine is not only compact in structure but also easy to be assembled and disassembled. When in use, a second N-shaped connecting rod and/or a return member are provided to achieve a labor-saving effect for exercise. Through a compact structure and the detachable connection of a bolt, when the horse riding exercise machine is not used, the bolt can be loosened so that a rear support base can be pushed toward a front support base to close up, thereby reducing the storage space to facilitate the storage.

METHOD OF MAKING A BUFFER BOARD OF A TREADMILL

A method of making a buffer board of a treadmill includes a sizing step, a shade drying step, a presetting step, a clamping and heat-pressing step, a cooling step, and a die opening step. The method can easily make the desired buffer board adapted to the treadmill and can only change different dies to make buffer boards with different structures when an upper die and a lower die of a die set provide protrusions, flat surfaces or depressed surfaces, thereby reducing the manufacturing cost. 1. A method of making a buffer board of a treadmill comprising:{'b': '1', 'step SA: immersing a plurality of making materials in a glue pool or coating an outer surface of each of said plurality of making materials with glue for a predetermined sizing time;'}{'b': '2', 'step SA: shade drying said making materials after said predetermined sizing time is over;'}{'b': '3', 'step SA: putting said sized making materials over one another to form a board body and then putting said board body into a die set of a hydraulic press;'}{'b': '4', 'step SA: clamping and heat-pressing said board body with said die set of said hydraulic press to heat said board body to a predetermined heating temperature for a predetermined clamping time;'}{'b': '5', 'step SA: stop heating said board body when said predetermined clamping time is over and then cooling said board body, said board body being cooled to a predetermined cooling temperature for a predetermined cooling time; and'}{'b': '6', 'step SA: opening said die set after said predetermined cooling time is over in order to form said buffer board of said treadmill.'}2. The method of making the buffer board of the treadmill as claimed in claim 1 , wherein said predetermined sizing time is set between 10 minutes and 30 minutes.3. The method of making the buffer board of the treadmill as claimed in claim 1 , wherein said board body is pre-dried before being put into said glue pool or being coated with said glue.4. The method of making the buffer board of ...

FITNESS AUXILIARY DEVICE

A fitness auxiliary device includes first and second support boards, a holding rod, a top rod, a pull rod, a caster seat, a buckle member, and casters. The top rod is transversely disposed at upper ends of inclined surfaces of the first and second support boards. The holding rod is located under the top rod. The pull rod is transversely disposed at the lower ends of the inclined surfaces and located under the holding rod. The caster seat is fixedly connected to the middle of the pull rod. A front end of the caster seat is provided with the buckle member. Two ends of an elastic rope are provided with buckle heads for connecting the buckle hole and a slide board or a flat board, such that the fitness auxiliary device can be used variously. 1. A fitness auxiliary device , comprising first and second support boards , the first and second support boards each having an inclined surface at one side thereof , a top rod being transversely provided at upper ends of the inclined surfaces of the first and second support boards , the top rod being connected with the first and second support boards , a holding rod being provided under the top rod and parallel to the top rod , bottoms of the first and second support boards being provided with first and second casters; characterized by:a pull rod being provided under the holding rod and disposed at lower ends of the inclined surfaces of the first and second support boards, the pull rod being parallel to the holding rod, a central section of the pull rod being provided with a caster seat, the caster seat being provided with a third caster, a front end of the caster seat being provided with a buckle member, the buckle member being formed with a buckle hole, the third caster and the first and second casters at rear ends of the bottoms of the first and second support boards forming a three-way support;at least one elastic rope being provided, the elastic rope being provided with two buckle heads at two ends thereof, the buckle heads ...

Replacement gate process and device manufactured using the same

A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. 1. A method of manufacturing a semiconductor device , comprising the steps of:providing a substrate including strained silicon device regions and non-strained silicon device regions, wherein said strained silicon device regions and non-strained silicon device regions are provided respectively with at least one gate structure;forming an epitaxy mask layer conformally on said gate structures and said substrate; andremoving a part of said epitaxy mask layer on said strained silicon device regions and forming an epitaxial layer in said substrate at both sides of each said gate structure in said strained silicon device regions.2. The method of manufacturing the semiconductor device according to claim 1 , wherein the step of forming said epitaxial layers comprises:forming epitaxy recesses in said substrate at both sides of each said gate structure in said strained silicon device regions; andforming said epitaxial layer in each said epitaxy recess.3. The method of manufacturing the semiconductor device according to claim 2 , wherein the step of forming said epitaxy recesses comprises:forming a photoresist layer on said non-strained silicon device regions; andperforming an etch process with said photoresist layer as an etch mask to remove a part of said epitaxy mask layer and a part of said substrate in said strained silicon device regions, thereby forming said epitaxy recesses, and the remaining said epitaxy mask layer becomes spacers of said gate ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess. 1. A semiconductor process , comprising:providing a substrate;forming a gate structure on the substrate;forming a spacer on the substrate beside the gate structure, wherein the spacer comprises a first spacer and a second spacer on the external side of the first spacer;performing a first etching process to etch and form at least a recess in the substrate beside the spacer and at least partially remove the second spacer, wherein the etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer; andforming an epitaxial layer in the recess.2. The semiconductor process according to claim 1 , wherein the epitaxial layer comprises a silicon-germanium epitaxial layer or a silicon-carbide epitaxial layer.3. The semiconductor process according to claim 1 , wherein the top surface of the epitaxial layer is higher than the top surface of the substrate.4. The semiconductor process according to claim 1 , wherein the epitaxial layer has a diamond-shaped profile structure.5. The semiconductor process according to claim 1 , wherein the materials of the first spacer and the second spacer both contain silicon nitride.6. The semiconductor process according to claim 5 , wherein the thickness of the first spacer is thinner than the thickness of the second spacer.7. The semiconductor ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH STRAINED SILICON STRUCTURE

A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed. 1. A method for fabricating a semiconductor device , comprising:providing a substrate;forming a gate on the substrate;forming a spacer on a sidewall of the gate;forming a hard mask layer on the spacer;forming a recessed region in the substrate and adjacent to the hard mask layer;forming an epitaxial layer in the recessed region;altering particle defects on the hard mask layer from a granular structure to an amorphous structure;performing an annealing process to repair damages to the epitaxial layer; andremoving the hard mask layer and the particle defects on the hard mask layer.2. The method according to claim 1 , wherein said altering particle defects on the hard mask layer from a granular structure to an amorphous structure comprises subjecting the substrate to an ion implantation process with inert gas ions claim 1 , and wherein the ion implantation process is a tilt-angle ion implantation process.3. The method according to claim 2 , wherein the inert gas ions are implanted at a tilt angle of about approximately 0° to 15°.4. The method according to claim 3 , wherein an energy of the inert gas ions ranges between 0˜5 KeV.5. The method according to claim 4 , wherein a dosage of the inert gas ions ranges between 1E13˜1E16 atoms/cm.6. The method according to claim 1 , wherein the inert gas ions comprise argon gas claim 1 , nitrogen gas claim 1 , helium claim 1 , neon claim 1 , krypton ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure. 1. A semiconductor device , comprising:a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;an isolation structure, surrounding the fin structure;a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure, wherein the isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, and the first top surface is higher than the second top surface; andan epitaxial layer, disposed at one side of the gate structure and in direct contact with the fin structure.2. The semiconductor device according to claim 1 , wherein there is a height difference between the first top surface and second top surface claim 1 , and the height difference ranges from 100 Angstroms to 250 Angstroms.3. The semiconductor device according to claim 1 , wherein the gate structure is a metal gate structure.4. The semiconductor device according to claim 1 , wherein the isolation structure under the gate structure comprises a sidewall and the epitaxial structure is in direct ...

MULTI-GAS SENSOR AND METHOD OF FABRICATING THE SENSOR

The present invention is a multi-gas sensor and a method for fabricating the multi-gas sensor. The multi-gas sensor comprises a substrate, an epitaxial layer, a metal oxide layer, a first metal layer, a second metal layer and multiple third metal layers. The method for fabricating the multi-gas sensor comprises steps of forming an epitaxial layer on a substrate; etching the epitaxial layer to form a first epitaxial structure and a second epitaxial structure a fixed distance from the first epitaxial structure; forming a metal oxide layer on the first epitaxial structure; forming a first metal layer that has at least two metal layers on the second epitaxial structure; forming a second metal layer a fixed distance from the first metal layer on the second epitaxial structure; forming third metal layers respectively on the metal oxide layer, the first metal layer and the second metal layer.

Method of forming fin-shaped structure having ladder-shaped cross-sectional profile

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Fin-shaped field-effect transistor (FinFET)

A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

Etching method for forming grooves in Si-substrate and fin field-effect transistor

An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME

A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. 1. A replacement gate process , comprising:providing a substrate, and a dummy gate structure formed on the substrate, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer, wherein the spacers and the CESL are made of the same material;removing a top portion of the CESL to expose the hard mask layer;removing the hard mask layer; andremoving the dummy layer to form a trench.2. The method according to claim 1 , wherein material of the HM layer is different from that of the spacers and the CESL.3. The method according to claim 1 , wherein the dummy layer is a polysilicon layer claim 1 , or amorphous silicon layer.4. The method according to claim 1 , wherein the spacers and the CESL are made of SICN claim 1 , which is formed by atomic layer deposition (ALD).5. The method according to claim 1 , wherein the hard mask layer is made of nitrite or oxide.6. The method according to claim 5 , wherein the hard mask layer is made of SIN.7. The method according to claim 1 , wherein the top portion of the CESL is removed by dry etching.8. The method according to claim 1 , wherein the hard mask layer is removed by wet etching.9. The method according to claim 1 ...

PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF

A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. 1. A process for fabricating a fin-type field effect transistor (FinFET) structure , comprising:patterning a semiconductor substrate to form a plurality of fins;forming a gate dielectric layer on surfaces of the fins;trimming the gate dielectric layer to reduce a thickness thereof; andforming a spacer material layer on the trimmed gate dielectric layer.2. The process of claim 1 , wherein the step of trimming the gate dielectric layer comprises a dry or wet etching step.3. The process of claim 1 , wherein the trimmed gate dielectric layer has a thickness within a range of 30 to 60 Å.4. A process for fabricating a FinFET structure claim 1 , comprising:patterning a semiconductor substrate in a first area to form a first fin;forming a first spacer on a sidewall of the first fin;removing a portion of the first fin, such that the first spacer and a surface of the remaining first fin together define a first cavity; andforming a piece of a first semiconductor compound from the first cavity, wherein an upper portion of the piece of the first semiconductor compound laterally extends over the first spacer.5. The process of claim 4 , wherein the first semiconductor compound comprises SiGe claim 4 , and the first spacer comprise silicon oxide.6. The process of claim 4 , wherein the first semiconductor compound comprises silicon phosphorous (SiP) claim 4 , and the first spacer comprises a silicon oxide spacer on the sidewall of the first fin and a SiN spacer on a sidewall of the silicon oxide spacer.7. The ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers. 1. A semiconductor process , comprising:forming a gate structure on a substrate;forming a main spacer on the substrate beside the gate structure;forming a source/drain in the substrate beside the main spacer;removing the main spacer;forming an epitaxial spacer on the substrate beside the gate structure; andforming an epitaxial structure in the substrate beside the gate structure after the source/drain is formed.2. The semiconductor process according to claim 1 , wherein the steps of forming the source/drain comprise:performing a source/drain ion implantation process to form the source/drain in the substrate beside the main spacer; andperforming a source/drain annealing process to activate the source/drain.3. The semiconductor process according to claim 1 , further comprising:performing a stress memorization technique (SMT) to the substrate beneath the gate structure before the epitaxial structure is formed.4. The semiconductor process according to claim 3 , wherein the steps of performing the stress memorization technique (SMT) and forming the source/drain comprise:performing a source/drain ion implantation process to form the source/drain in the substrate beside the main spacer;forming a stress layer to cover the gate structure and the substrate; ...

Method of forming fin-shaped structure

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Method of manufacturing semiconductor devices

A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

HORSE RIDING EXERCISE MACHINE

A horse riding exercise machine is not only compact in structure but also easy to be assembled and disassembled. When in use, a second N-shaped connecting rod and/or a return member are provided to achieve a labor-saving effect for exercise. Through a compact structure and the detachable connection of a bolt, when the horse riding exercise machine is not used, the bolt can be loosened so that a rear support base can be pushed toward a front support base to close up, thereby reducing the storage space to facilitate the storage. 1. A horse riding exercise machine , comprising:a front support base;two coupling plates, disposed at two sides of an upper end of the front support base, the coupling plates each having a plate body, a first fixing hole, a first arc groove, a second fixing hole, a second arc groove, and at least one third fixing hole, the plate body being disposed at the upper end of the front support base, the first fixing hole and the first arc groove being spaced from each other and disposed close to a front end of the plate body, the first fixing hole being above the first arc groove, the at least one third fixing hole being disposed close to a rear end of the plate body, the second fixing hole and the second arc groove being spaced from each other and disposed at a predetermined position between the front end and the rear end of the plate body, the second fixing hole being above the second arc groove;a rear support base, a top end of the rear support base being detachably connected to the at least one third fixing hole of each coupling plate;a handle support unit, a bottom end of the handle support unit being pivotally connected to a top end of each coupling plate, the handle support unit having at least one handle, a connecting rod, a first shaft hole, a first slide hole, two extension pieces, and two pivot holes, the at least one handle extending upward from a top end of the connecting rod, the two extension pieces extending downward from two sides of ...

FinFET transistor with epitaxial structures

A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

MULTI-FUNCTIONAL EXERCISE DEVICE

A multi-functional exercise device includes an upper part and a lower part. The upper part has a base. The base includes two side walls extending from two sides thereof, a grip member mounted between the two side walls, and an elastic engaging hook beneath the base. The lower part includes a support disc having a central engaging hole for the elastic engaging hook to be engaged therein, at least one mounting portion at a lower end of the support disc, and at least one rolling element mounted to the mounting portion. The elastic engaging hook of the upper part is engaged with the engaging hole of the lower part so that the upper part and the lower part are connected together. The upper part is applied with a force to drive the lower part to move along the direction of the applied force for the user to do exercises. 1. A multi-functional exercise device , comprising:an upper part, the upper part having a base, the base including two side walls extending from two sides thereof, a grip member mounted between the two side walls, and an elastic engaging hook beneath the base;a lower part, the lower part including a support disc having a central engaging hole for the elastic engaging hook to be engaged therein, at least one mounting portion at a lower end of the support disc, and at least one rolling element mounted to the mounting portion; the elastic engaging hook of the upper part being engaged with the engaging hole of the lower part so that the upper part and the lower part are connected together.2. The multi-functional exercise device as claimed in claim 1 , wherein the elastic engaging hook serves as the center of a circle claim 1 , a periphery of the elastic engaging hook is provided with engaging tenons which are radially arranged; and the support disc of the lower part is provided with a plurality of connecting grooves corresponding to the engaging tenons.3. The multi-functional exercise device as claimed in claim 1 , wherein the rolling element is in the form of ...

Stepper

SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF

A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure. 1. A semiconductor structure , comprising:a gate located on a substrate;a dual spacer located on the substrate beside the gate; andtwo recesses located in the substrate and the dual spacer, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle, located in the dual spacer and directly next to the substrate.2. The semiconductor structure according to claim 1 , wherein the dual spacer has an internal spacer and an outer spacer.3. The semiconductor structure according to claim 2 , wherein the internal spacer comprises an oxide spacer and the outer spacer comprises a nitride spacer.4. The semiconductor structure according to claim 1 , further comprising:a first spacer located between the gate and the dual spacer.5. The semiconductor structure according to claim 4 , wherein the first spacer comprises a silicon carbon-nitride spacer.6. The semiconductor structure according to claim 1 , wherein the gate comprises a gate dielectric layer having a high dielectric constant.7. The semiconductor structure according to claim 1 , wherein an epitaxial structure is disposed on each of the recesses.8. The semiconductor structure according to claim 7 , wherein the sidewall of the epitaxial structures next to the gate has a W-shaped cross-sectional profile.9. The semiconductor structure according to claim ...

Fin-shaped structure and manufacturing method thereof

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Pedaling vibrational apparatus

A pedaling vibrational apparatus includes a seat body, a pedal assembly, a gear plate assembly, a drive assembly and an eccentric assembly, like a lever structure. By treading the pedal assembly, the gear plate assembly drives the drive assembly to rotate. The drive assembly is connected with the eccentric assembly. A user can fully exercise muscles of the user's body during exercise, and a vibrational effect generated by the eccentric assembly can stimulate acupuncture points of the user's body to improve blood circulation. Left and right pedals of the pedal assembly can be treaded in turn to continuously drive a gear to rotate in a same direction so as to achieve an effect of acceleration and to enhance vibrations.

Method of forming semiconductor device

A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE STRUCTURE

A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer. 1. A method of fabricating a semiconductor device structure , comprising:forming a gate dielectric layer on a substrate;forming a gate electrode on the gate dielectric layer;treating the gate dielectric layer exposed by the gate electrode;performing a first etching process to remove at least a portion of the gate dielectric layer exposed by the gate electrode, wherein a portion of the gate dielectric layer is remained on the substrate not covered by the gate electrode to form a thinned gate dielectric layer;forming a spacer on a sidewall of the gate electrode;performing a second etching process to remove a portion of the thinned gate dielectric layer and a portion of the substrate so as to form recesses in the substrate beside the gate electrode,wherein during the first etching process and the second etching process, an etching rate of a treated gate dielectric layer is greater than an etching rate of an untreated gate dielectric layer.2. The method of claim 1 , wherein the treating comprises performing an implant process with boron or carbon.3. (canceled)4. The method of claim 1 , wherein a thickness of the thinned gate dielectric layer is less than 15 Å.5. The method of claim 4 , wherein the thickness of the thinned ...

FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE

A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region. 1. A fabrication method of a semiconductor structure , comprising:forming a gate structure on a substrate;forming a first material layer on the substrate and the gate structure;implanting boron into the substrate at two sides of the gate structure, to form a first doped region;implanting P type conductive dopant into the substrate at the two sides of the gate structure, to form a second doped region;forming a second material layer on the first material layer; andperforming an etching process, etching the second material layer, the first material layer and the substrate respectively, and forming a recess in the substrate at the two sides of the gate structure, wherein the recess is positioned within the first doped region.2. The fabrication method of the semiconductor structure according to claim 1 , wherein the recess comprises a round angle at a side thereof claim 1 , and the round angle is positioned underneath the second material layer.3. The fabrication method of the semiconductor structure according to claim 1 , wherein the etching process further comprises:anisotropically etching the second material layer and the first material layer, to form a ...

FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed. 1. A fin-shaped structure , comprising:a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure comprises a ladder-shaped cross-sectional profile part, wherein the width of a top part of the ladder-shaped cross-sectional profile is smaller than the width of a lower part of the ladder-shaped cross-sectional profile, wherein the change of width from the lower part to the top part is step-like; andtwo gates directly disposed over the first fin-shaped structure and the second fin-shaped structure respectively.2. The fin-shaped structure according to claim 1 , wherein the width of a top part of the first fin-shaped structure is larger than the width of the top part of the second fin-shaped structure.3. The fin-shaped structure according to claim 1 , further comprising:an isolation structure disposed beside the first fin-shaped structure of the first area and beside the second fin-shaped structure of the second area respectively, and the ladder-shaped cross-sectional profile part is ...

Semiconductor structure and process thereof

A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

TREADMILL HAVING A CURVED TREADMILL DECK

A treadmill having a curved treadmill deck is provided. Two curved side frames are disposed at two sides of the treadmill frame. Front and rear end ends of each curved side frame are higher than a middle section thereof. Inner sides of the two curved side frames are provided with a plurality of fixing seats, respectively. The fixing seats have fixing holes, respectively. An elastic deck is composed of a plurality of sheets connected side by side. The sheets each have perforations corresponding in position to the fixing holes of the respective fixing seats. A plurality of fixing pins are inserted in the perforations of the sheets of the elastic deck and secured to the fixing holes of the fixing seats. The elastic deck is forcibly fastened by the fixing pins and slightly deformed according to the curvature of the curved side frames to form the curved treadmill deck. 1. A treadmill having a curved treadmill deck , comprising:two curved side frames, disposed at two sides of a treadmill frame, the two curved side frames being parallel to each other and spaced apart from each other, the two curved side frames each having a high front end and a low rear end to form a curved shape, inner sides of the two curved side frames being provided with a plurality of fixing seats respectively, the fixing seats have fixing holes respectively, the fixing holes of the fixing seats of one curved side frame corresponding in position to the fixing holes of the fixing seats of the other curved side frame;an elastic deck, including a plurality of sheets connected side by side, the sheets each having perforations corresponding in position to the fixing holes of the respective fixing seats;a plurality of fixing pins, inserted in the perforations of the elastic deck and secured to the fixing holes of the fixing seats, the elastic deck being forcibly fastened by the fixing pins and slightly deformed according to the curved shape of the two curved side frames to form the curved treadmill deck; ...

Treadmill having a curved treadmill deck

A treadmill having a curved treadmill deck is provided. Two curved side frames are disposed at two sides of the treadmill frame. Front and rear end ends of each curved side frame are higher than a middle section thereof. Inner sides of the two curved side frames are provided with a plurality of fixing seats, respectively. The fixing seats have fixing holes, respectively. An elastic deck is composed of a plurality of sheets connected side by side. The sheets each have perforations corresponding in position to the fixing holes of the respective fixing seats. A plurality of fixing pins are inserted in the perforations of the sheets of the elastic deck and secured to the fixing holes of the fixing seats. The elastic deck is forcibly fastened by the fixing pins and slightly deformed according to the curvature of the curved side frames to form the curved treadmill deck.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYER HARD MASK

A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate with an underlying layer formed thereon;forming a gate layer overlying the underlying layer; andforming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising:a silicon nitride layer directly formed on the gate layer;an oxide layer directly formed on the silicon nitride layer; anda top hard mask made of amorphous silicon directly formed on the oxide layer,wherein the gate layer and the top hard mask contain the same element of silicon, a thickness of the to hard mask is thicker than a thickness of the silicon nitride layer and thinner than a thickness of the oxide layer.2. The method according to claim 1 , wherein the gate layer is made of polysilicon while the top hard mask is made of amorphous silicon.3. The method according to claim 1 , wherein the gate layer and the top hard mask are made of amorphous silicon.4. (canceled)5. The method according to claim 1 , wherein a thickness of the gate layer is in a range of about 750 Ř1350 Å.6. The method according to claim 1 , wherein the silicon nitride layer is a first dielectric layer directly formed on the gate layer the oxide layer is a second dielectric layer directly formed on the first dielectric layer.7. The method according to claim 6 , wherein a thickness of the first dielectric layer is thinner than a thickness of the second dielectric layer.8. The method according to claim 6 , wherein a thickness ratio of the first ...

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.

PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE

A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. 1. A process for fabricating a fin-type field effect transistor (FinFET) structure , comprising:patterning a semiconductor substrate to form a plurality of fins;forming a gate dielectric layer on surfaces of the fins;trimming the gate dielectric layer to reduce a thickness thereof; andforming a spacer material layer on the trimmed gate dielectric layer.2. The process of claim 1 , wherein the step of trimming the gate dielectric layer comprises a dry or wet etching step.3. The process of claim 1 , wherein the trimmed gate dielectric layer has a thickness within a range of 30 Å to 60 Å.4. A process for fabricating a FinFET structure claim 1 , comprising:patterning a semiconductor substrate in a first area to form a first fin;forming a first spacer on a sidewall of the first fin;removing a portion of the first fin, such that the first spacer and a surface of the remaining first fin together define a first cavity; andforming a piece of a first semiconductor compound from the first cavity, wherein an upper portion of the piece of the first semiconductor compound laterally extends over the first spacer.5. The process of claim 4 , wherein the first semiconductor compound comprises SiGe claim 4 , and the first spacer comprise silicon oxide.6. The process of claim 4 , wherein the first semiconductor compound comprises silicon phosphorous (SiP) claim 4 , and the first spacer comprises a silicon oxide spacer on the sidewall of the first fin and a SiN spacer on a sidewall of the silicon oxide spacer.7. The ...

METHOD OF FORMING FIN-SHAPED STRUCTURE

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed. 1. A method of forming a fin-shaped structure , comprising:providing a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area;filling an isolation structure beside the first fin-shaped structure of the first area and beside the second fin-shaped structure of the second area respectively;forming a patterned mask covering the first area but exposing the second area;removing a top part of the isolation structure of the second area, thereby exposing a first top part of the second fin-shaped structure;performing a treatment process to modify an external surface of the first top part of the second fin-shaped structure, thereby forming a modified part covering the first top part of the second fin-shaped structure;removing the patterned mask; andperforming a removing process to remove a part of the isolation structure and the modified part by the high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part and the isolation structure, thereby exposing a top part of the ...

Fin field-effect transistor

An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

Exercise machine having changeable damping mechanism

An exercise machine having a changeable damping mechanism is provided. A first transmission rope on a first shifting wheel of a first rotating shaft drives a damping device of a damping shaft to generate a relative damping action for training the leg muscular endurance of the user. Through a first changeable damping mechanism, the first transmission rope, which having stretch elasticity on the first shifting wheel is controlled to adjust the rotational speed according to the gear ratio, which may be in cooperation with a second transmission rope, which having stretch elasticity on a second shifting wheel through a second changeable damping mechanism, and is in cooperation with the damping action of a magnetic control wheel or a blower fan of the damping device to extend the range of damping control for different users to train muscular endurance.

COLLAPSIBLE EXERCISE STEPPER

A collapsible exercise stepper contains: a base, a movable extension rack, a grip assembly, two stepping units, two hydraulic cylinders, and a folding unit. The base includes a first fixing rod and a first connection rod, and the first fixing rod has a first coupling portion. The movable extension rack includes a second fixing rod and a second connection rod with a second coupling portion and two extending tabs, wherein the second connection rod has a horizontal bar and a third coupling portion. The grip assembly rotatably includes a handle, a fitting tube, an accommodation portion, and an actuation seat. Each stepping unit includes a support plate and a pedal, wherein the support plate has a rotation portion and a driving portion. Each hydraulic cylinder includes a first joining portion and a second joining portion. The folding unit includes a first operation element and a second operation element. 1. A collapsible exercise stepper comprising: a base , a movable extension rack , a grip assembly , two stepping units , two hydraulic cylinders , and a folding unit;the base including a first fixing rod and a first connection rod connected on the first fixing rod, the first fixing rod having a first coupling portion extending from a bottom thereof, the first connection rod having a first connector extending from a first side thereof, and the first connection rod having a second connector extending from a second side thereof opposite to the first side of the first connection rod;the movable extension rack including a second fixing rod and a second connection rod connected on the second fixing rod, the second fixing rod having a second coupling portion and two extending tabs adjacent to the two ends of the second fixing rod individually, the second connection rod having a horizontal bar inserted through a lower end thereof and a third coupling portion arranged on an upper end of the second connection rod, wherein the third coupling portion is rotatably connected with the ...

Semiconductor structure

The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures

An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME

A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. 1. A semiconductor structure , comprising:a substrate;spacers formed oppositely on the substrate and spaced apart to form a trench therebetween;a patterned CESL formed at outsides of the spacers and covering the substrate; anda metal gate formed in the trench;wherein the spacers and the CESL are made of the same material.2. The semiconductor structure according to claim 1 , wherein the spacers and the CESL are made of SICN claim 1 , which is formed by atomic layer deposition (ALD).3. The semiconductor structure according to claim 1 , further comprising a gate dielectric layer formed in the trench and positioned between the substrate and the metal gate.4. The semiconductor structure according to claim 3 , wherein the gate dielectric layer is a high-K dielectric layer claim 3 , or a multi-layer comprising an oxide layer and the high-K dielectric layer formed on the oxide layer.5. The semiconductor structure according to claim 1 , further comprising a fin channel formed on the substrate claim 1 , a source and a drain claim 1 , an extending direction of the fin channel being perpendicular to an extending direction of the trench claim 1 , the source and the drain separately formed on two oppositely sides of the fin channel claim 1 , and the source and the drain positioned outside and adjacent to the spacers. This application is a Divisional of pending U.S. patent ...

VIBRATIONAL REHABILITATION DEVICE

A vibrational rehabilitation device includes two drive assemblies, an eccentric assembly, and two half housings. Each drive assembly includes a driving wheel assembly and a driven wheel assembly. The driving wheel assembly has a driving wheel and a driving shaft. The driving shaft is mounted to a center of the driving wheel. A grip member is provided at one side of the driving shaft opposite the driving wheel. The driven wheel assembly includes a first driven wheel and a second driven wheel. The first driven wheel is connected with the driving wheel and driven by the driving wheel. The second driven wheel is coaxially disposed with the first driven wheel. The eccentric assembly includes two transmission wheels at two sides thereof and an eccentric block sandwiched between the two transmission wheels. The drive assemblies and the eccentric assembly are mounted in the housings.

Exercise Machine Providing Back-and Forth Movement and Vibration

An exercise machine which provides back-and-forth movement and vibration is revealed. The exercise machine includes a base and a loading platform in which two sides of a middle portion thereof are pivotally connected to the base. A motor, a first transmission device, and a second transmission device are mounted in the base. The motor drives the first transmission device which further drives the second transmission device. The second transmission device which is connected to the loading platform drives the loading platform to move back and forth while the first transmission device makes the base to have vibration. Thereby the exercise machine generates vibration and back-and-forth movement, allowing users to experience both motions.

Semiconductor device with epitaxial structure

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

METHOD FOR MANUFACTURING MASSAGE WEAR-RESISTANT TREADMILL DECK AND FINISHED PRODUCT THEREOF

A method for manufacturing a massage wear-resistant treadmill deck and a finished product thereof are provided. The method includes step 1: providing a mold, the mold having a plurality of cavities thereon, a wear-resistant material being injected into the cavities of the mold; step 2: placing a deck in the mold so that the wear-resistant material is bonded to a surface of the deck to form a plurality of massage protrusions on the deck; and step 3: demoulding the deck from the mold, the surface of the deck being formed with the massage protrusions to form the massage wear-resistant treadmill deck. A wear-resistant layer having the massage protrusions is first formed in the mold, and then the deck is placed into the mold to bond with the wear-resistant layer to form the massage wear-resistant treadmill deck. The manufacturing cost is reduced and the manufacturing mobility is improved.

METHOD OF FORMING SEMICONDUCTOR DEVICE

A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

Method of making a buffer board of a treadmill

A method of making a buffer board of a treadmill includes a sizing step, a shade drying step, a presetting step, a clamping and heat-pressing step, a cooling step, and a die opening step. The method can easily make the desired buffer board adapted to the treadmill and can only change different dies to make buffer boards with different structures when an upper die and a lower die of a die set provide protrusions, flat surfaces or depressed surfaces, thereby reducing the manufacturing cost.

Method for manufacturing massage wear-resistant treadmill deck and finished product thereof

A method for manufacturing a massage wear-resistant treadmill deck and a finished product thereof are provided. The method includes step 1: providing a mold, the mold having a plurality of cavities thereon, a wear-resistant material being injected into the cavities of the mold; step 2: placing a deck in the mold so that the wear-resistant material is bonded to a surface of the deck to form a plurality of massage protrusions on the deck; and step 3: demoulding the deck from the mold, the surface of the deck being formed with the massage protrusions to form the massage wear-resistant treadmill deck. A wear-resistant layer having the massage protrusions is first formed in the mold, and then the deck is placed into the mold to bond with the wear-resistant layer to form the massage wear-resistant treadmill deck. The manufacturing cost is reduced and the manufacturing mobility is improved.

Multi-gas sensor and method of fabricating the sensor

The present invention is a multi-gas sensor and a method for fabricating the multi-gas sensor. The multi-gas sensor comprises a substrate, an epitaxial layer, a metal oxide layer, a first metal layer, a second metal layer and multiple third metal layers. The method for fabricating the multi-gas sensor comprises steps of forming an epitaxial layer on a substrate; etching the epitaxial layer to form a first epitaxial structure and a second epitaxial structure a fixed distance from the first epitaxial structure; forming a metal oxide layer on the first epitaxial structure; forming a first metal layer that has at least two metal layers on the second epitaxial structure; forming a second metal layer a fixed distance from the first metal layer on the second epitaxial structure; forming third metal layers respectively on the metal oxide layer, the first metal layer and the second metal layer.

Semiconductor device

A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.

Power domain crossing interface analysis

A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.

MOS TRANSISTOR AND SEMICONDUCTOR PROCESS FOR FORMING EPITAXIAL STRUCTURE

A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer. 1. A MOS transistor , comprising:a gate structure disposed on a substrate;an epitaxial spacer disposed on the substrate besides the gate structure, wherein the epitaxial spacer comprises silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3; andan epitaxial structure disposed in the substrate besides the epitaxial spacer.2. The MOS transistor according to claim 1 , wherein the ratio of nitrogen to silicon of the epitaxial spacer is larger than or equal to 1.37.3. The MOS transistor according to claim 1 , wherein the epitaxial spacer comprises a silicon nitride spacer claim 1 , and the silicon content of the silicon nitride spacer is lower than 43%.4. The MOS transistor according to claim 1 , further comprising: a spacer disposed between the gate structure and the epitaxial spacer claim 1 , wherein the silicon content of the spacer is larger than 43%.5. The MOS transistor according to claim 4 , wherein the spacer comprises a silicon oxide spacer claim 4 , a silicon oxynitride spacer or a carbon-containing silicon nitride spacer.6. The MOS transistor according to claim 5 , ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode. 1. A method for fabricating semiconductor device , comprising:forming a fin-shaped structure on a substrate;forming a gate dielectric layer on the fin-shaped structure;forming a gate electrode on the fin-shaped structure;performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; andforming an epitaxial layer adjacent to two sides of the gate electrode.2. The method of claim 1 , further comprising performing the nitridation process to implant nitrogen ions into the gate dielectric layer for dividing the gate dielectric layer into a first portion directly under the gate electrode and a second portion adjacent to two sides of the gate electrode.3. The method of claim 2 , wherein the first portion and the second portion comprise different materials.4. The method of claim 3 , wherein the first portion comprises silicon oxide and the second portion comprises silicon oxynitride (SiON).5. The method of claim 2 , further comprising:forming a lightly doped drain adjacent to two sides of the gate electrode after performing the nitridation process;removing part of the second portion and part of the fin-shaped structure to forma recess adjacent to two sides of the gate electrode; andforming the epitaxial layer in the recess.6. The method of claim 1 , wherein the fin-shaped structure and the gate dielectric layer are extended along a first direction on the substrate and the gate electrode is extended along a second direction.7. The method of claim 6 , wherein the first direction is ...

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Fin field effect transistor device and fabrication method thereof

A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure. 1. A semiconductor device , comprising:a fin structure, disposed on a substrate;an insulating structure, disposed on the substrate;a protruding structure, in direct contact with the substrate and partially protruding from the insulating structure, wherein portions of the protruding structure protruding from the insulating structure is the fin structure;an epitaxial structure, disposed on a top surface of the fin structure and completely covering the top surface of the fin structure, wherein the epitaxial structure has a curved top surface, and a bottom surface of the epitaxial structure is disposed only on a top surface of the fin structure; anda gate structure, covering the fin structure and the epitaxial structure.2. (canceled)3. The semiconductor device according to claim 1 , wherein the fin structure and the epitaxial structure have a total height claim 1 , and a ratio of the height of the epitaxial structure to the total height is less than 0.5.4. The semiconductor device according to claim 1 , wherein the width of the epitaxial structure is gradually reduced from a location close to the fin structure to a location away from the fin structure.5100. The semiconductor device according to claim 1 , wherein the top surface of the fin structure has a () crystal surface.6. (canceled)7. (canceled)8. The semiconductor ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.

Method of controlling etching process for forming epitaxial structure

A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.

Semiconductor process

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; and performing a second dry etching process to expand the recess. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a gate structure on the substrate;performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; andperforming a second dry etching process to expand the recess.2. The method of claim 1 , further comprising forming a spacer around the gate structure before performing the first dry etching process.3. The method of claim 1 , further comprising forming a buffer layer in the recess after performing the second dry etching process.4. The method of claim 3 , wherein the buffer layer comprises silicon germanium.5. The method of claim 3 , wherein the buffer layer comprises an even thickness.6. The method of claim 3 , further comprising forming an epitaxial layer in the recess after forming the buffer layer.7. The method of claim 6 , wherein the germanium concentration of the buffer layer is lower than the germanium concentration of the epitaxial layer.8. The method of claim 6 , wherein the epitaxial layer comprises silicon germanium.9. The method of claim 1 , further comprising:performing the first drying etching process for vertically etching the recess; andperforming the second dry etching process for laterally etching the recess.10. The method of claim 9 , further comprising adjusting the bias power of an equipment for performing the second dry etching process to expand the recess laterally.11. The method of claim 1 , wherein the shape of the recess comprises a perfect circle.12. A semiconductor device claim 1 , comprising:a substrate;a gate structure on the substrate; anda recess adjacent to the gate structure, ...

FINFET TRANSISTOR WITH EPITAXIAL STRUCTURES

A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate. 1. A field effect transistor with epitaxial structures , comprising:a fin-shaped structure, disposed on a semiconductor substrate; anda metal gate across the fin-shaped structure, wherein the metal gate comprises a pair of recess regions respectively disposed on two sides of the bottom of the metal gate, a width of an upper part of the metal gate being greater than a width of a lower part of the metal gate.2. The field effect transistor of claim 1 , wherein the metal gate overlaps portions of the fin-shaped structure.3. The field effect transistor of claim 1 , wherein each of the recess regions comprises a vertical region and a slanted region sequentially arranged from the bottom to the top of the recess regions.4. The field effect transistor of claim 3 , wherein the metal gate further comprises another vertical region disposed on the slanted region.5. The field effect transistor of claim 3 , the field effect transistor further comprises a spacer conformally covering the vertical region and the slanted region.6. The field effect transistor of claim 5 , wherein the spacer covering the vertical region is more inward than the spacer covering the slanted region.7. The field effect transistor of claim 3 , wherein there is a boundary between the vertical region and the slanted region claim 3 , wherein the boundary is on a top side of the fin-shaped structure.8. The field effect transistor of claim 3 , wherein the metal gate claim 3 , the vertical region claim 3 , and the slanted region are along a first axis.9. The field effect transistor of claim 1 , further comprising two epitaxial structures claim 1 , respectively disposed on two sides of the metal gate claim 1 , wherein portions of the epitaxial structures are respectively disposed in ...

Semiconductor device and fabrication method thereof

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

METHOD OF FORMING FIN-SHAPED STRUCTURE

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Semiconductor device and method of forming the same

A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

FINFET structure

A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

Method of fabricating semiconductor device structure

A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

METHOD FOR CREATING VIA IN IC MANUFACTURING PROCESS

In a method for creating a via in an IC manufacturing process, a substrate is provided and a circuitry structure is formed over the substrate. Then, a dielectric layer is formed over the circuitry structure; a hard mask is formed on and a trench is created through the dielectric layer; a coating layer is formed on the hard mask, filling the trench; an etch opening is defined in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; and the bottom of the trench exposed from the etch opening is etched off with the hard mask, thereby creating a via for conductors. 1. A method for creating a via in an IC manufacturing process , comprising steps of:providing a substrate formed thereon a circuitry structure, a dielectric layer and a hard mask, wherein the circuitry structure includes a conductor and an etch stop layer directly on the conductor;creating a trench in the dielectric layer without penetrating the entire dielectric layer;forming a coating layer on the hard mask, filling the trench;defining an etch opening in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; andcreating a via to expose the conductor by etching the dielectric layer and the etch stop layer exposed from the etch opening with the hard mask.2. The method according to wherein the substrate is a silicon substrate claim 1 , the dielectric layer is made of a composite material and configured as multiple layers or the dielectric layer is single-layered claim 1 , the hard mask is made of composite material and configured as multiple layers or the hard mask is single-layered claim 1 , and the coating layer includes a bottom anti-reflective layer and a photoresist layer.3. The method according to claim 1 , further comprising:removing the coating layer;forming a metal conductor on the hard mask, filling the via and the trench; andperforming a ...

FINFET AND METHOD FOR FABRICATING THE SAME

A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure. 1. A method for fabricating fin-shaped field-effect transistor (FinFET) , comprising:providing a substrate;forming a fin-shaped structure in the substrate;forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure;forming a first gate structure on the STI and the fin-shaped structure; andremoving a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.2. The method of claim 1 , wherein the first gate structure comprises:a silicon layer on the fin-shaped structure and the STI; anda hard mask on the silicon layer.3. The method of claim 1 , wherein the STI comprises oxides.4. The method of claim 1 , further comprising:forming the first gate structure on a first transistor region of the substrate and on the STI and a second gate structure on a second transistor region of the substrate and on the STI;removing a portion of the STI for exposing the STI underneath the first gate structure and the second gate structure;forming a first hard mask on the first gate structure and the second gate structure;removing a portion of the first hard mask on the first transistor region to form a first spacer around the first gate structure and a first recess in the fin-shaped structure adjacent to two sides of the first gate structure;forming a first epitaxial layer in the first recess;forming a second hard mask on the first gate structure and the second gate structure;removing the second hard mask on the second ...

FIN FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF

A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided. 1. A method of fabricating a fin field effect transistor device , comprising:providing a substrate having a fin structure on a surface of the substrate;forming at least a shallow trench isolation structure on the surface of the substrate and forming a base fin structure concurrently, wherein the shallow trench isolation structure comprises a peripheral zone and a concave zone, and the peripheral zone physically contacts with the fin structure; and;forming an epitaxial fin structure on a top surface of the base fin structure;forming a gate structure on the epitaxial fin structure, wherein an extending direction of the gate structure is perpendicular to an extending direction of the epitaxial fin structure.2. The method of fabricating a fin field effect transistor device according to claim 1 , wherein a top surface of the peripheral zone is higher than a top surface of the concave zone.3. The method of fabricating a fin field effect transistor device according to claim 2 , wherein a top surface of the base fin structure is coplanar with the top surface of the peripheral zone.4. The method of fabricating a fin field effect transistor device according to claim 2 , wherein a top surface of the base fin structure is higher than the top surface of the peripheral zone.5. The method of fabricating a fin field effect transistor device ...

ETCHING METHOD FOR FORMING GROOVES IN Si-SUBSTRATE AND FIN FIELD-EFFECT TRANSISTOR

An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process. 1. An etching method adapted for forming grooves in Si-substrate , comprising:providing a silicon substrate, at least two gate structures being formed on the silicon substrate and at least two gate spacer structures being disposed on the silicon substrate;performing a first etching process on the silicon substrate so as to form a first groove, wherein the first groove has a base and two inclined sidewalls, the two inclined sidewalls are ascending to respective bottoms of the gate structures, and interconnected with the base, respectively;{'img': {'@id': 'CUSTOM-CHARACTER-00015', '@he': '3.13mm', '@wi': '2.46mm', '@file': 'US20160093737A1-20160331-P00001.TIF', '@alt': 'custom-character', '@img-content': 'character', '@img-format': 'tif'}, 'performing a second etching process on the silicon substrate at the base of the first groove so as to form a second groove in an inverted -symbol shape, wherein the inclined sidewalls of the first groove are interconnected with the second groove, respectively, and the first etching process is substantially different from the second etching ...

Finfet structure

A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

FIN FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF

A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided. 1. A method of fabricating a fin field effect transistor device , comprising:providing a substrate having a fin structure on a surface of the substrate;forming at least a shallow trench isolation structure on the surface of the substrate;forming a base fin structure with the shallow trench isolation structure concurrently, wherein the shallow trench isolation structure comprises a peripheral zone and a concave zone, and the peripheral zone physically contacts with the fin structure;forming a pair of spacers on a portion of a surface of the shallow trench isolation structure on two sides of a portion of the fin structure, respectively;forming an epitaxial fin structure on a top surface of the base fin structure; andforming a gate structure on the epitaxial fin structure, wherein an extending direction of the gate structure is perpendicular to an extending direction of the epitaxial fin structure.2. The method of fabricating a fin field effect transistor device according to claim 1 , wherein a top surface of the peripheral zone is higher than a top surface of the concave zone.3. The method of fabricating a fin field effect transistor device according to claim 2 , wherein a top surface of the base fin structure is coplanar with the top surface of the peripheral zone.4. The method of fabricating a fin field effect transistor device ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. 1. A method of manufacturing a semiconductor device , comprising the steps of:providing a substrate having first type semiconductor regions and second type semiconductor regions, wherein said first type semiconductor region and said second type semiconductor region are provided respectively with at least one gate structure;forming a first epitaxy mask layer conformally on said gate structures and said substrate;removing a part of said first epitaxy mask layer on said first type semiconductor region and forming a first type epitaxial layer in said substrate at both sides of each said gate structure in said first type semiconductor region;forming a second epitaxy mask layer conformally on said gate structures, said first type epitaxy layers and said substrate, wherein said second epitaxy mask layer covers on said first epitaxy mask layer on said second type semiconductor regions;forming a second type epitaxial layer in said substrate at both sides of each said gate structure in said second type semiconductor region; andremoving said second epitaxy mask layer.2. A method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming said first type epitaxial layers comprises:forming first epitaxy recesses in said substrate at both sides of each said gate structure in said first type semiconductor region; andforming said first type epitaxial layer in each said first epitaxy recess.3. A method of manufacturing a ...

BELT PULLING EXERCISE APPARATUS

A belt pulling exercise apparatus includes an adjusting belt, having a first ladder lock disposed thereon, and one end of the adjusting belt is passed through a first ring; two connecting belts, two first ends of the two connecting belts are fastened to the first ring simultaneously, two second ends of each connecting belts opposite to the first ends are respectively fastened to a third ring, and two second rings are respectively fastened to an upper surface of each connecting belt between the first end and the second end; two elastic rope assemblies, each elastic rope assembly is arranged corresponding to each connecting belt, and two ends of each elastic rope assembly are respectively connected to the second ring and the third ring of each corresponding connecting belt; and two hand grips, each hand grip is arranged at each corresponding connecting belt and each corresponding elastic rope assembly. 1. A belt pulling exercise apparatus , comprising:{'b': 1', '11', '1, 'an adjusting belt (), having a first ladder lock () disposed thereon, and one end of the adjusting belt () is passed through a first ring;'}{'b': 2', '21', '2', '23', '22, 'two connecting belts (), each connecting belt having a first end and a second end, the first ends of the two connecting belts are simultaneously fastened to the first ring (), the second end of each connecting belt () is opposite to the respective first end and is fastened to a third ring (), and a second ring () is fastened to an upper surface of each connecting belt between the respective first end and the respective second end;'}{'b': 3', '3', '2', '22', '23, 'two elastic rope assemblies (), each elastic rope assembly () is arranged corresponding to each connecting belt (), and two ends of each elastic rope assembly are respectively connected to the second ring () and the third ring () of each corresponding connecting belt; and'}{'b': 4', '4', '2', '3, 'two hand grips (), each hand grip () is arranged at each corresponding ...

Pedal-type vibrational apparatus

A pedal-type vibrational apparatus includes a seat body, a pedal assembly, a gear plate assembly, a drive assembly and an eccentric assembly, like a lever structure. By treading the pedal assembly, the gear plate assembly drives the drive assembly to rotate. The drive assembly is connected with the eccentric assembly. The user can fully exercise the muscles of the body during exercise, and the vibrational effect generated by the eccentric assembly can stimulate the acupuncture points of the body to improve the blood circulation. The left and right pedals can be treaded in turn to continuously drive a gear to rotate in the same direction so as to achieve the effect of acceleration and to enhance vibrations.

FIN FIELD-EFFECT TRANSISTOR

An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process. 1. A fin field-effect transistor (FinFET) , comprising:a silicon substrate;at least two gate structures disposed on the silicon substrate;at least two gate spacer structures disposed on the silicon substrate; anda semiconductor structure, embedded in the silicon substrate, the semiconductor structure having an ascending portion and a portion in a trench shape that is interconnected with the ascending portion, wherein the ascending portion ascends to respective bottoms of the gate structures.2. The fin field-effect transistor (FinFET) according to claim 1 , wherein the semiconductor structure is made of a silicon germanium epitaxial material claim 1 , and the semiconductor structure is an epitaxial drain structure or an epitaxial source structure.3. The fin field-effect transistor (FinFET) according to claim 1 , wherein the semiconductor structure further includes a blind via portion that is interconnected with the portion in the trench shape.4. A fin field-effect transistor (FinFET) claim 1 , comprising:a silicon substrate;at least two gate structures disposed on the silicon substrate; ...

Belt pulling exercise apparatus

A belt pulling exercise apparatus includes an adjusting belt, having a first ladder lock disposed thereon, and one end of the adjusting belt is passed through a first ring; two connecting belts, two first ends of the two connecting belts are fastened to the first ring simultaneously, two second ends of each connecting belts opposite to the first ends are respectively fastened to a third ring, and two second rings are respectively fastened to an upper surface of each connecting belt between the first end and the second end; two elastic rope assemblies, each elastic rope assembly is arranged corresponding to each connecting belt, and two ends of each elastic rope assembly are respectively connected to the second ring and the third ring of each corresponding connecting belt; and two hand grips, each hand grip is arranged at each corresponding connecting belt and each corresponding elastic rope assembly.

TRACTION EXERCISE APPARATUS WITH STRAPS

Un appareil d'exercice par tractions muni de sangles comprend une sangle de réglage (1), ayant un premier passant de réglage (11) disposé sur celle-ci, et une extrémité de la sangle de réglage (1) est passée dans un premier anneau (21) ; deux sangles de jonction (2) deux premières extrémités des deux sangles de jonction (2) sont simultanément attachées au premier anneau (21), deux secondes extrémités de chaque sangle de jonction (2) situées à l'opposé des premières extrémités sont respectivement attachées à un troisième anneau (23), et deux deuxièmes anneaux (22) sont respectivement attachés à une surface supérieure de chaque sangle de jonction (2) entre la première extrémité et la seconde extrémité ; deux ensembles de corde élastique (3), chaque ensemble de corde élastique (3) est disposé en correspondance avec chaque sangle de jonction (2), et deux extrémités de chaque ensemble de corde élastique (3) sont respectivement raccordées au deuxième anneau (22) et au troisième anneau (33) de chaque sangle de jonction correspondante (2) ; et deux poignées (4), chaque poignée (4) est disposée sur chaque sangle de jonction correspondante (2) et sur chaque ensemble de corde élastique correspondant (3). A stretchable exercise apparatus with straps comprises an adjustment strap (1) having a first adjustment loop (11) disposed thereon, and an end of the adjustment strap (1) is passed through a first ring (21); two connecting straps (2) two first ends of the two connecting straps (2) are simultaneously attached to the first ring (21), two second ends of each connecting strap (2) located opposite the first ends are respectively attached a third ring (23), and two second rings (22) are respectively attached to an upper surface of each connecting strap (2) between the first end and the second end; two sets of elastic rope (3), each set of elastic rope (3) is arranged in correspondence with each connecting strap (2), and two ends of each set of elastic rope (3) are ...

Interacting exercise device

An interacting exercise device is revealed. The interacting exercise device includes a driving device and a non-concentric actuator driven by the driving device. While the driving device is operated to rotate, the non-concentric actuator vibrates and the vibration generated is delivered to the interacting exercise device for interacting shaking fitness.

Treadmill having a curved treadmill deck

A treadmill having a curved treadmill deck is provided. Two curved side frames are disposed at two sides of the treadmill frame. Front and rear end ends of each curved side frame are higher than a middle section thereof. Inner sides of the two curved side frames are provided with a plurality of fixing seats, respectively. The fixing seats have fixing holes, respectively. An elastic deck is composed of a plurality of sheets connected side by side. The sheets each have perforations corresponding in position to the fixing holes of the respective fixing seats. A plurality of fixing pins are inserted in the perforations of the sheets of the elastic deck and secured to the fixing holes of the fixing seats. The elastic deck is forcibly fastened by the fixing pins and slightly deformed according to the curvature of the curved side frames to form the curved treadmill deck.

Belt Pulling Exercise Apparatus

A belt pulling exercise apparatus includes an adjusting belt, having a first ladder lock disposed thereon, and one end of the 5 adjusting belt is passed through a first ring; two connecting belts, two first ends of the two connecting belts are fastened to the first ring simultaneously, two second ends of each connecting belts opposite to the first ends are respectively fastened to a third ring, and two second rings are respectively fastened to an upper surface of each 10 connecting belt between the first end and the second end; two elastic rope assemblies, each elastic rope assembly is arranged corresponding to each connecting belt, and two ends of each elastic rope assembly are respectively connected to the second ring and the third ring of each corresponding connecting belt; and two hand grips, 15 each hand grip is arranged at each corresponding connecting belt and each corresponding elastic rope assembly.

Bicycle brake device and its bicycle brake device

トレッドミル用マッサージ滑り止め板の成形方法及びその成形装置

【課題】スポーツ用品の技術分野に関し、製造コストが低下し、技術的柔軟性が高まるトレッドミル用マッサージ滑り止め板の成形方法及びその成形装置を提供する。【解決手段】トレッドミル用マッサージ滑り止め板１００の成形方法は、複数の空洞２１が設けられる金型２が設置され、耐摩耗材料１が金型２の空洞２１内に注入される工程１と、プレート３が金型２中に設置され、耐摩耗材料１がプレート３の表面に結合され、複数のマッサージ凸状体３１が形成される工程２と、プレート３が金型２から脱型され、プレート３の表面にマッサージ凸状体３１を有するマッサージ滑り止め板が形成される工程３とを備え、金型２内にまずマッサージ凸状体３１を有する耐摩耗層が設けられ、プレート３が金型２に設置されて耐摩耗層に結合され、結合後にプレート３の表面に立体状のマッサージ凸状体３１が設けられる。【選択図】図３

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Exercise machine having changeable damping mechanism

Bicycle braking device

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

半導體製程

本發明提供一種半導體製程，係包含以下步驟。首先，在一基底上形成一閘極結構，並且在該基底及該閘極結構上形成一第一材料層。接著，將硼摻質佈植至該閘極結構兩側之該基底中，形成一第一摻雜區，並且將P型導電摻質佈植至該閘極結構兩側之該基底中，形成一第二摻雜區。隨後，在該第一材料層上形成一第二材料層。最後，依序蝕刻該第二材料層、該第一材料層以及該基底，且在該閘極結構兩側之該基底形成一凹槽，其中，該凹槽位在該第一摻雜區之範圍內。

取代閘極製程及應用其製得之元件

一種取代閘極製程。提供一基板和形成一假性閘極結構於基板上，其中假性閘極結構包括一暫置層位於基板上，一硬質遮罩層位於暫置層上，間隙壁位於暫置層和硬質遮罩層之兩側，及一接觸蝕刻停止層覆蓋基板、間隙壁和硬質遮罩層層，其中間隙壁和接觸蝕刻停止層係為相同材料。接著，移除接觸蝕刻停止層之一頂部以暴露出硬質遮罩層。然後移除硬質遮罩層，再移除暫置層以形成一溝槽。

製作半導體元件的方法

一種製作半導體元件的方法，其步驟包含：提供一基底，該基底包含第一型半導體元件區域以及第二型半導體元件區域、在該基底上共形地形成一第一磊晶遮罩層、在該第一型半導體元件區域的基底中形成一第一型磊晶層、在該基底上共形地形成一第二磊晶遮罩層、在該第二型半導體元件區域的基底中形成第二型磊晶層、以及移除該第二磊晶遮罩層。

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region, forming a first gate structure and a second gate structure on the MV region and a second gate structure on the LV region, forming a patterned mask on the MV region as the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure, and then forming a first epitaxial layer between the first gate structure and the second gate structure.