Method for manufacturing single level polysilicon electric removal and programmable read only memory cell

The present invention relates to a method for producing storage cell characterized in depletion type, single layer, polysilicion, electrical erase and programme read only. The method includes the steps as follows: providing a substrate which consists of a floating area and a control area, forming a separated pit area and a pit area respectively in the substrate of the floating area and the control area; next, establishing a well region and a separated well region respectively in the separated pit area and the substrate between the separated pit area and the well region; forming a depletion dope area and a storage cell injecting area respectively in the well area and the pit area; constructing a floating grid which crosses the floating area and the control area on the substrate. Wherein, the floating grid exposes part of the depletion dope area as well as part of the storage cell injecting area; finally, carrying out a technique of doping for the aim of forming a source electrode or drain ...

Method for manufacturing single level polysilicon electric removal and programmable read only memory cell

IC chip

The invention relates to an integrated circuit chip, which comprises a switch LDMOS element and an analog LDMOS element respectively positioned on a substrate provided with a first conductive type. The switch LDMOS element and the analog LDMOS element have same components and respectively comprise: two grid conducting layers which are positioned on two first active areas of the substrate respectively; a common drain electrode contact area provided with a second conductive type, which is positioned in a second active area, wherein the second active area is positioned between the two first active areas; and an isolation structure, which isolates the second active area from the first active areas. The length of the isolation structure between each first active area and the second active areaalong the length direction of a channel below each grid conducting layer is A, the length of each grid conducting layer positioned on each first active area along the length direction of the channel is ...

IC chip

The invention relates to an integrated circuit chip, which comprises a switch LDMOS element and an analog LDMOS element respectively positioned on a substrate provided with a first conductive type. The switch LDMOS element and the analog LDMOS element have same components and respectively comprise: two grid conducting layers which are positioned on two first active areas of the substrate respectively; a common drain electrode contact area provided with a second conductive type, which is positioned in a second active area, wherein the second active area is positioned between the two first active areas; and an isolation structure, which isolates the second active area from the first active areas. The length of the isolation structure between each first active area and the second active area along the length direction of a channel below each grid conducting layer is A, the length of each grid conducting layer positioned on each first active area along the length direction of the channel is ...

System chip structure and its making method

A kind of semiconductor structure of system chip includes a base, a low voltage element, a middle voltage element, at least one high voltage element and several separating structures. The base possesses low voltage circuit area and high voltage circuit area. The low voltage element and middle element are distributed to base of the low voltage circuit area. The high voltage element is distributed to the base of the high voltage circuit area. The separating structure is distributed to the base to separate the low voltage element, middle voltage element and the high voltage element.

System chip structure and preparation method thereof

High-voltage component structure