ERROR RECOVERY IN A STORAGE CLUSTER

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory. 1. A method for error recovery in a storage system , performed by a plurality of storage nodes of the storage system , comprising:detecting a failure of a first one of the plurality of storage nodes having a remote procedure call cache; andaccessing a mirrored remote procedure call cache in a second one of the plurality of storage nodes, with the mirrored remote procedure call cache mirroring the remote procedure call cache of the first one of the plurality of storage nodes.2. The method of claim 1 , further comprising:determining, from the mirrored remote procedure call cache, whether a result of servicing a remote procedure call is already posted.3. The method of claim 1 , further comprising:returning a result of servicing a remote procedure call, responsive to determining from the mirrored remote procedure call cache that the result for the remote procedure call is posted.4. The method of claim 1 , further comprising:servicing a remote procedure call, responsive to determining from the mirrored remote procedure call cache that a result for the remote procedure call is not posted.5. The ...

Failure mapping in a storage array

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

STORAGE SYSTEM ARCHITECTURE

A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes. 1a first storage cluster, in a first chassis, the first storage cluster having a first plurality of storage nodes coupled together, each storage node of the first plurality of storage nodes having one or more storage units;a second storage cluster, in a second chassis, the second storage cluster having a second plurality of storage nodes coupled together, each storage node of the second plurality of storage nodes having one or more storage units;a chassis-to-chassis interconnect coupling the first storage cluster and the second storage cluster, with the first storage cluster and the second storage cluster configurable as a single logical unit; andthe first storage cluster, the second storage cluster and the chassis-to-chassis interconnect having a pathway coupling storage units such that a first storage unit in the first storage cluster is configurable to communicate with at least one other storage unit in the first storage cluster and communicate with at least one storage unit in the second storage cluster, via the pathway without storage node processor assistance.. A storage system, comprising: Solid-state memory, such as flash, is currently in use in solid-state drives (SSD) to augment or replace conventional hard disk drives (HDD), writable CD (compact disk) or writable DVD (digital versatile disk) drives, collectively known as spinning media, and tape drives, for storage of large amounts of ...

Storage cluster

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

Self-identifying memory errors

A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.

AGGRESSIVE DATA DEDUPLICATION USING LAZY GARBAGE COLLECTION

A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval. 1. A method for extending reference data lifetime in deduplication , comprising:determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system; andprotecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for deduplication of further user data in the storage system during the predetermined time interval.2. The method of claim 1 , wherein the determining comprises:forming a data structure, over one or more sampling windows of time, of data of the storage system, the data structure indicating amounts of the data of files or blocks in the storage system having hash function results matching hash function results of at least one other file or block seen during the one or more sampling windows of time.3. The method of claim 1 , wherein the protecting is based on metadata that includes an aging parameter for each of the at least portions of the quantity of user data claim 1 , and further comprising:setting the aging parameter for one of the at least portions of the quantity of user data to a first value, responsive to determining the one of the at least portions matches a fingerprint result of a file or block seen during a sampling window of time, wherein the first value indicates to not erase during garbage collection; ...

Multifunction Reaction Washer and Stack accessed by Slim Reaction Socket

Accurate reaction socket access within an outer washer diameter is provided via a number of tool access castles extending from a stepped bushing and serration top, which in turn provides low friction during initial tightening and securing after final loading of a nut/bolt. Bottom serration slipping during initial tightening and thread locking during initial loosening are eliminated by the reaction washer stacked on top and in contact with a support washer via helical ramps and ramp mates. During initial tightening or loosening, the ramp mates slide up or down the helical ramps whereby an axial load on the nut/bolt is ramped up or down prior to screwing it on the main thread. A clamp ring or ramp indenters may secure the two washers. An interposition washer may extend the axial reaction range of the washer stack. Direct tension indicators may be combined with the ramp indenters. 1) A reaction washer comprising:a) a washer axis;b) a top face;c) a number of tool access castles that are circumferentially arrayed with respect to said washer axis and that are extending away from said top face and within and up to an outer washer diameter of said reaction washer.2) The reaction washer of claim 1 , wherein at least one of said number of tool access castles comprises a lock-on groove that is circumferentially at least partially undercutting said at least one tool access castle.3) The reaction washer of claim 1 , further comprising a bottom face that is radially extending up to said outer washer diameter.4) The reaction washer of claim 1 , wherein at least one of said number of tool access castles is extending downward away from said top face.5) The reaction washer of claim 1 , wherein at least one of said number of tool access castles is extending upward away from said top face.6) The reaction washer of claim 1 , further comprising a number of bite spikes circumferentially arrayed on a bottom face of said reaction washer.7) The reaction washer of claim 1 , further comprising ...

STORAGE SYSTEM ARCHITECTURE

A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes. 1. A storage system comprising:a plurality of storage nodes, each having a processor;a plurality of storage units, each having a controller and solid-state storage memory;a first pathway that couples the processors of the plurality of storage nodes and is configured to couple to a network external to the storage system; anda second pathway that couples at least a first controller of a first storage unit to a second controller of a second storage unit for communication, wherein the second pathway is a direct controller to controller coupling.2. The storage system of claim 1 , further comprising:the first controller of the first storage unit configured to send a write request and a data shard or a parity shard through the second pathway to the second controller of the second storage units; andthe second controller of the second storage unit configured to write the data shard or the parity shard into the solid-state storage memory of the second storage unit, responsive to the write request.3. The storage system of claim 1 , further comprising:the first controller of the first storage unit configured to send an inquiry through the second pathway to the second controller of the second storage unit; andthe second controller of the second storage unit configured to send a reply, through the second pathway to the first controller of the first storage unit, responsive to the inquiry, with the processors ...

FAILURE MAPPING IN A STORAGE ARRAY

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data. 1. A method of failure mapping , performed by a storage cluster , the method comprising:cooperating among one or more processors of storage nodes of a storage cluster and a plurality of controllers of solid-state storage units of the storage cluster to identify defects in solid-state memory of the solid-state storages;generating a defects map, based on the identified defects;generating an address translation table that maps around the identified defects in accordance with the defects map; andaccessing user data in the storage cluster, in accordance with the address translation table.2. The method of claim 1 , wherein the cooperating to identify the defects comprises:identifying first defects in the solid-state memory of the solid-state storage units, based on tracking errors or error correction; andidentifying second defects in the solid-state memory of the solid-state storage units, based on characterizing the solid-state memory over time.3. The method of claim 1 , wherein the cooperating to identify the defects comprises:receiving information regarding first defects from a source external to the storage cluster; anddetermining information ...

Data rebuild on feedback from a queue in a non-volatile solid-state storage

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Aggressive data deduplication using lazy garbage collection

A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval.

Managing semiconductor memory array leakage current

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

Die-level monitoring in a storage cluster

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Extended lifetime memory

A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block.

Power sequencing for optimal system load at start up

A method for power sequencing is provided. The method includes determining a chassis configuration prior to blades within slots of the chassis being powered up and generating a power sequence based on the determining. The method includes applying the power sequence to the blades and monitoring the applying and the chassis configuration to achieve an optimal system load.

Incorporating bit write capability with column interleave write enable and column redundancy steering

A column access control circuit for generating column write enable outputs with redundancy steering control and bit write control for an integrated circuit chip, and an integrated circuit chip having the same. A column access control circuit may include: a column write enable driver, a redundancy steering logic, and a bit write controller. The column write enable driver may produce column write enable outputs through an output. The column write enable driver is configured to receive certain column interleave write enable and enable column write according to the column interleave write enable received. The redundancy steering logic is configured to receive one or more fuses and skip a damaged column indicated by a corresponding fuse. The bit write controller is configured to receive one or more bit write and provide bit write control according to the one or more bit write received.

Storage cluster

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

Storage system architecture

A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

DATA REBUILD ON FEEDBACK FROM A QUEUE IN A NON-VOLATILE SOLID-STATE STORAGE

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget. 1. A method of reading data in a storage system , performed by the storage system , comprising:receiving a request to read a bit in a storage memory;evaluating, using feedback from a plurality of operations queues coupled to the storage memory, a path to the bit in the storage memory, responsive to the request to read the bit; anddetermining a value of the bit via an alternate path to the storage memory, responsive to the evaluating.2. The method of claim 1 , wherein the evaluating comprises:determining whether reading the bit via the path is within a targeted read time according to the feedback from the plurality of operations queues.3. The method of claim 1 , wherein the determining the value of the bit via the alternate path comprises determining a value of a redundant copy of the bit in the storage memory.4. The method of claim 1 , wherein the determining the value of the bit via the alternate path comprises reconstructing or rebuilding the bit.5. The method of claim 1 , wherein the feedback from the plurality of operations queues is regarding at least one of: priority of operations in the operations ...

Compact hydraulic torque wrench cartridge

Drive plates of a hydraulic torque wrench cartridge are thickened for extended surface contact with three pawls and a direct contact with the piston rod. The drive plates are held together and are additionally stiffened by dowel pins and shoulder screws. Snap pins are axially slide able and spring loaded connecting the piston rod with the drive plates in an easily disengage able fashion. Three pawls are arrayed in a pitch adjusted with respect to the ratchet teeth pitch in correspondence with an elastic deformation of the drive plates for a balanced force transfer across them. The pawl-tooth interfaces are also in an outward opening angle preventing them from snapping free under load.

Masking defective bits in a storage array

A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

Hydraulic Torque Wrench with Stacked Drive Plate Cartridge, Multiple Cartridge Pawls and Snap-in Retract Lock

Drive plates of a hydraulic torque wrench are stacked and mating combined in a cartridge for extended surface contact within the ratchet teeth width of the joints along the piston force transmission path into the drive plates and into the cartridge pawls. A snap-in retract lock provides for an easy connect with the cartridge also in case of a rotationally coupled modular torque wrench. There, the stacked and mated drive plates are rotationally guided in the housing leaving the ratchet wheel peripherally clear for maximum housing support. The pawls interface the ratchet teeth with contact pressures that increase at the ratchet teeth grooves and gradually propagate away from the ratchet wheel axis such that the ratchet teeth edges remain free of peak pressures and deformations. 1. A hydraulic torque wrench comprising:A. a housing;B. a hydraulic piston that is slide able along a piston axis guided in said housing and that is transforming a hydraulic pressure into a piston force along a piston axis;C. a piston force transfer member that is receiving said piston force from said hydraulic piston;D. at least two drive plates that are receiving said piston force from said piston force transfer member via a member-plate interface;E. a cartridge pawl that is receiving said piston force from said drive plate via a plate-pawl interface;F. a ratchet wheel that is rotate able concentric with respect to a torque transfer axis held in said housing and rotate able held on to by said drive plate and that is receiving said piston force from said cartridge pawl via a pawl-tooth interface such that said piston force is transformed into a torque around said torque transfer axis, said ratchet wheel comprising ratchet teeth that are extending along said torque transfer axis with a ratchet teeth width;wherein said at least two drive plates are stacked and in mating contact with each other along said torque transfer axis and that are extending within said ratchet teeth width.2. The hydraulic ...

Error recovery in a storage cluster

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Managing semiconductor memory array leakage current

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.

STORAGE CLUSTER

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data. 1. A method for managing processing power in a storage system , comprising:providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node; anddistributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.2. The method of claim 1 , further comprising:adding another blade having a compute-only node; andre-distributing the authorities across the plurality of blades and the another blade.3. The method of claim 1 , wherein the distributing the authorities comprises:moving one or more authorities from one or more of the plurality of blades to a further one of the plurality of blades, responsive to adding the further one of the plurality of blades to the storage system.4. The method of claim 1 , wherein the distributing the authorities is in accordance with balancing computing resources across the authorities claim 1 , for each of the plurality of blades.5. The method of claim 1 , further comprising:distributing computing tasks of external I/O (input/output) processing across the plurality of blades so that I/O processing for each of a plurality of classes of service is assigned to one or more storage nodes or compute nodes on an individual service class basis.6. The method of claim 1 , wherein:the plurality of blades includes a first blade having a first set of processing characteristics including an ...

Message storage in memory blocks using codewords

A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.

Stacked symmetric printed circuit boards

A printed circuit board (PCB) is provided. The PCB includes a connector extending from a surface of the PCB and a bypass feature extending through the PCB. The PCB is constructed so that a first copy of the PCB is configured to be assembled to a second copy of the PCB with the second copy rotated and/or flipped relative to the first copy. An electrical connection to the first copy is accessible via the connector of the first copy, and an electrical connection to the second copy is accessible via the connector of the second copy through the bypass feature of the first copy.

REMAPPING OF INOPERABLE MEMORY BLOCKS

Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table. 1. A method comprising:receiving a request to access a memory block by a memory controller;determining if the memory block is an inoperable memory block by the memory controller; and determining if memory block has been remapped to an operable memory block by the memory controller; and', 'if the memory block has been remapped to the operable memory block, providing access to the operable memory block by the memory controller., 'if the memory block is an inoperable memory block2. The method of claim 1 , wherein determining if the memory block is an inoperable memory block comprises referencing an inoperable block table with an address associated with the memory block.3. The method of claim 1 , wherein determining if the memory block is an inoperable memory block comprises determining if a remapping bit has been set in the memory block claim 1 , and if so claim 1 , determining that the memory block is an inoperable memory block.4. The method of claim 3 , wherein the remapping bit comprises an additional error-correcting pointer (ECP) bit.5. The method of claim 1 , further comprising determining an ...

REMAPPING INOPERABLE MEMORY BLOCKS USING POINTERS

Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits. 1. A method comprising:receiving an indication of one or more inoperable bits in a memory block by a memory controller, wherein the memory block includes a plurality of bytes and each byte includes one or more bits;determining an address of a byte that includes the one or more inoperable bits by the memory controller;generating a data structure that includes the address of the determined byte by the memory controller; andassociating the data structure with the memory block by the memory controller.2. The method of claim 1 , wherein associating the data structure with the memory block by the memory controller comprises storing a pointer to the data structure in metadata associated with the memory block.3. The method of claim 1 , wherein the memory block is a phase change memory block.4. The method of claim 1 , wherein generating the data structure that includes the address of the determined byte comprises:generating a first address of a byte from the memory block that precedes the determined byte; andgenerating a second address of a byte from the memory block that follows the determined byte.5. The method of claim 1 , wherein generating the data structure that includes the address of the determined byte comprises adding a directional bit to the data structure that indicates whether one or more unusable bytes follow or precede the ...

ESTIMATING AND MANAGING POWER CONSUMPTION OF COMPUTING DEVICES USING POWER MODELS

Power consumption of computing devices are monitored with performance counters and used to generate a power model for each computing device. The power models are used to estimate the power consumption of each computing device based on the performance counters. Each computing device is assigned a power cap, and a software-based power control at each computing device monitors the performance counters, estimates the power consumption using the performance counters and the model, and compares the estimated power consumption with the power cap. Depending on whether the estimated power consumption violates the power cap, the power control may transition the computing device to a lower power state to prevent a violation of the power cap or a higher power state if the computing device is below the power cap. 1. A method comprising:receiving a power model at a computing device;receiving a power cap at the computing device;estimating a power consumption of the computing device using the power model; andadjusting or maintaining a current power state of the computing device based on the power cap and the estimated power consumption.2. The method of claim 1 , further comprising determining values of a plurality of performance counters associated with the computing device claim 1 , and estimating the power consumption of the computing device using the power model and the values of the plurality of performance counters.3. The method of claim 1 , wherein the power cap comprises an upper bound and a lower bound claim 1 , and adjusting or maintaining a current power state of the computing device based on the power model comprises:determining if the estimated power consumption of the computing device is less than the upper bound and greater than the lower bound, and if so, maintaining the current power state of the computing device;determining if the estimated power consumption of the computing device is greater than the upper bound, and if so, decreasing the current power state of ...

INCREASING MEMORY OPERATING FREQUENCY

A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates. 1. A memory apparatus , comprising:a plurality of memory arrays, each memory array comprising a plurality of memory cells;a plurality of local bit lines (LBLs), each connected to a separate plurality of the memory cells;a plurality of global bit lines, each connected to a separate plurality of the local bit lines;a plurality of global bit line (GBL) latches, each located along a separate global bit line to latch a signal along the respective global bit line;a plurality of first logic gates, each receiving as inputs a separate plurality of the global bit lines; anda plurality of solar bit lines, each configured to connect an output of a separate one of the plurality of first logic gates with a same output latch.2. The memory apparatus of claim 1 , wherein the plurality of first logic gates are NAND gates.3. The memory apparatus of claim 1 , further comprising a multiplexer between the plurality of solar bit lines and the output latch.4. The memory apparatus of claim 1 , wherein each of the plurality of memory arrays comprises 128 memory cells.5. The memory apparatus of claim 1 , wherein each of the plurality of first logic gates is located geographically between two memory arrays of the plurality of memory arrays claim 1 , andthe first logic gate between the two memory arrays receives as inputs the global bit lines ...

HIGH FREQUENCY MEMORY

Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation. 1. A high frequency write through memory device comprising:a plurality of memory cells; anda plurality of local evaluation circuits, wherein each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells;wherein each of the local evaluation circuits are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.2. The high frequency write through memory device of claim 1 , further comprising:a common signal path configured to receive an address signal, the address signal corresponding to the at least one of the plurality of memory cells of the write through memory device;wherein the local evaluation circuit is configured to receive an output of the common signal path and a read enable signal and to responsively prevent the data stored in the coupled memory cell from being written to the latch node during the write through operation and to permit the data stored in the coupled memory cell to be written to the latch node during a read operation.3. The high frequency write through memory device of claim 2 , further comprising:a write through circuit configured to receive a write enable signal and a data signal and to permit the data signal to be written to the latch node when the write enable signal is active.4. The high frequency write through memory device of claim 3 , wherein a variation between a timing of the data signal being written to the latch node during the write through operation and the stored data being written to the latch ...

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched. 1. A method for reducing power consumption of a cache array having a plurality of cache sets , the method comprising:receiving a read signal for the cache array;receiving a set selection signal indicating that the read signal corresponds to a subset of the plurality of cache sets of the cache array; andbased on the set selection signal, reading only the cache sets of the subset of the cache array.2. The method of claim 1 , wherein reading the cache sets of the subset of the cache array comprises switching a bit line of each of the cache sets of the subset.3. The method of claim 1 , wherein the subset of the plurality of cache sets of the cache array includes two cache sets.4. The method of claim 2 , wherein reading the cache sets of the subset of the cache array further comprises multiplexing an output of each of the cache sets of the subset.5. The method of claim 1 , wherein the set selection signal and the read signal are received contemporaneously.6. The method of claim 1 , wherein a number of subsets is less than a number of cache sets.7. A cache array comprising:a plurality of cache sets, wherein the plurality of cache sets are grouped into a plurality of subsets;a read line configured to receive a read signal for the cache array;a set selection line configured to receive a set selection signal, wherein the set selection signal indicates that the read signal ...

Writing memory blocks using codewords

A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.

Masking Defective Bits in a Storage Array

A method of failure mapping is provided. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACKED CIRCUIT TOPOLOGY WITH LOGIC PRESERVATION

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit. 1a memory;a processor being coupled to a memory;a pre-charge circuit for pre-charging a global bitline to enable switching of the global bitline;a sleep mode control circuit for providing a signal to disable an array of circuit elements and switch a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit;a keeper circuit coupled to the global bitline;the logic function circuit coupled to a solar bitline; andan effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit, wherein the logic function circuit comprises at least two stacked transistors to pull-up the solar bitline based on a received signal from the sleep mode control circuit, wherein the two stacked transistors are p-type field-effect transistors (PFET), wherein the two stacked transistors are smaller than the effective pull-up transistor.. A system for dual mode power saving in a stacked circuit topology having logic preservation, comprising: This ...

CACHE ARRAY WITH REDUCED POWER CONSUMPTION

Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched. 1. A method for reducing power consumption of a cache array having a plurality of cache sets , the method comprising:receiving a read signal for the cache array;receiving a set selection signal indicating that the read signal corresponds to a subset of the plurality of cache sets of the cache array; andbased on the set selection signal, reading only the cache sets of the subset of the cache array.2. The method of claim 1 , wherein reading the cache sets of the subset of the cache array comprises switching a bit line of each of the cache sets of the subset.3. The method of claim 1 , wherein the subset of the plurality of cache sets of the cache array includes two cache sets.4. The method of claim 2 , wherein reading the cache sets of the subset of the cache array further comprises multiplexing an output of each of the cache sets of the subset.5. The method of claim 1 , wherein the set selection signal and the read signal are received contemporaneously.6. The method of claim 1 , wherein a number of subsets is less than a number of cache sets. This application is a continuation application of the legally related U.S. Ser. No. 13/622,191 filed Sep. 19, 2012, the contents of which are incorporated by reference herein in their entirety.The present invention relates generally to reducing power consumption in a processor, and more specifically, to reducing power ...

UNIVERSAL FPGA/ASIC MATRIX-VECTOR MULTIPLICATION ARCHITECTURE

A universal single-bitstream FPGA library or ASIC implementation accelerates matrix-vector multiplication processing multiple matrix encodings including dense and multiple sparse formats. A hardware-optimized sparse matrix representation referred to herein as the Compressed Variable-Length Bit Vector (CVBV) format is used to take advantage of the capabilities of FPGAs and reduce storage and bandwidth requirements across the matrices compared to that typically achieved when using the Compressed Sparse Row (CSR) format in typical CPU- and GPU-based approaches. Also disclosed is a class of sparse matrix formats that are better suited for FPGA implementations than existing formats reducing storage and bandwidth requirements. A partitioned CVBV format is described to enable parallel decoding. 1. A method for representing a matrix comprising a plurality of non-zero elements , the method comprising:populating, by a computing device, a data array with the plurality of non-zero elements from the matrix;populating, by the computing device, a vector array with information corresponding to the location of each value from among the plurality of non-zero elements.2. The method of claim 1 , wherein the vector array comprises a mapping of each element location in the matrix to indicate whether a zero value or non-zero value is present in each element location in the matrix.3. The method of claim 3 , wherein the vector array comprises a Bit Vector (BV).4. The method of claim 3 , wherein the vector array comprises a compressed BV.5. The method of claim 4 , wherein the vector array comprises a Compressed Bit Vector (CBV).6. The method of claim 1 , wherein the vector array comprises a compressed variable-length BV.7. The method of claim 6 , wherein the vector array comprises a Compressed Variable Bit Vector (CVBV).8. The method of claim 1 , further comprising claim 1 , before the populating functions claim 1 , determining location coordinates for non-zero elements in the matrix from ...

Self-identifying memory errors

A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.

Data Rebuild on Feedback from a Queue in a Non-Volatile Solid-State Storage

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget. 1. A method for accessing data in a plurality of storage nodes having nonvolatile solid-state memory , comprising:distributing user data throughout the plurality of storage nodes through erasure coding such that in event of a determination by the plurality of storage nodes that two of the plurality of storage nodes are unreachable the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes, wherein the plurality of storage nodes are coupled as a storage cluster;receiving a request that directs a read of the non-volatile solid-state memory, wherein the read of the non-volatile solid-state memory is based at least in part on reading a first bit in the non-volatile solid-state memory via a first path, and wherein a plurality of operations queues is coupled to the first path;determining, based on contents of the plurality of operations queues, whether the reading the first bit via the first path can be performed within a latency budget; anddetermining a second path to achieve the read of the non-volatile solid-state memory, responsive to determining that the reading of ...

Masking Defective Bits in a Storage Array

A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage. 1. A method of failure mapping , comprising:distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster, wherein each of the plurality of storage nodes has a non-volatile solid-state storage with non-volatile memory;determining that the non-volatile memory has a defect;generating a mask that indicates the defect, the generating based on error correction of reads of the non-volatile solid-state storage, wherein the mask is one of a plurality of masks in a mask hierarchy in the storage cluster; andreading from the non-volatile memory with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.2. The method of claim 1 , wherein application of the mask comprises:substituting of a replacement page for a defective page from the non-volatile memory.3. The method of claim 1 , wherein application of the mask comprises: ...

Adjustable Error Correction Based on Memory Health in a Storage Unit

A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable. 1. A method for adjustable error correction , comprising:determining health of a plurality of storage nodes in a storage cluster, wherein each of the plurality of storage nodes is configured to have at least one authority that controls erasure coding of a range of user data of which the at least one authority is an owner; andadjusting erasure coding based on the health of at least one of the plurality of storage nodes.2. The method of claim 1 , further comprising:ranking portions of non-volatile memory of at least one of the plurality of storage nodes based on the health of the at least one of the plurality of storage nodes, wherein adjusting the erasure coding includes assigning differing numbers of bits for error correction code (ECC) to differing portions of the non-volatile memory of the at least one of the plurality of storage nodes according to the ranking.3. The method of claim 1 , wherein adjusting the erasure coding comprises:adjusting a stripe width and a type of error correction code (ECC).4. The method of claim 1 , wherein the at least one authority selects an erasure coding ...

DIE-LEVEL MONITORING IN A STORAGE CLUSTER

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster. 1. A method for die-level monitoring in a storage cluster , comprising:distributing user data throughout a plurality of storage nodes of the storage cluster through erasure coding; andperforming, in a controller in a non-volatile solid-state storage, error correction of reads of a non-volatile memory.2. The method of claim 1 , further comprising:characterizing the non-volatile memory over time, based on diagnostic information that diagnoses the non-volatile memory of the non-volatile solid-state storage of each of the plurality of storage nodes.3. The method of claim 2 , further comprising:sending at least a portion of the diagnostic information from the storage cluster to a network.4. The method of claim 1 , further comprising:biasing at least one of a read from or a write to the non-volatile memory, responsive to producing diagnostic information.5. The method of claim 2 , further comprising:tracking wear of a plurality of blocks of the non-volatile memory, based on the diagnostic information.6. The method of claim 1 , further comprising:producing diagnostic information;tracking bit errors per page or per codeword, each page having a plurality of ...

Failure Mapping in a Storage Array

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data. 1. A method of failure mapping , comprising:distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster, wherein each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory and wherein the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable;mapping physical addresses of defects in the flash memory, on a basis of one of per flash package, per flash die, per flash plane, per flash block, per flash page, or per physical memory address; andmapping around the defects in the flash memory during accesses to the user data, wherein a processor performs at least one method operation.2. The method of claim 1 , wherein mapping the physical addresses of defects in the flash memory includes generating a defects map of a physical address space of a flash memory claim 1 , the defects map indicating the physical addresses of the defects in the flash memory.3. The method of ...

Error Recovery in a Storage Cluster

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory. 1. A plurality of storage nodes within a single chassis , comprising:the plurality of storage nodes configured to communicate together as a storage cluster, each of the plurality of storage nodes having a non-volatile solid-state storage for user data storage, the non-volatile solid state storage including flash memory, the plurality of storage nodes configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data;the plurality of storage nodes configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to reading the user data from a remainder of the plurality of storage nodes; andthe plurality of storage nodes configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.2. The plurality of storage nodes of claim 1 , wherein the flash memory applies error correction to data stored therein.3. The plurality of ...

Die-Level Monitoring in a Storage Cluster

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

CONFIGURABLE HYPERCONVERGED MULTI-TENANT STORAGE SYSTEM

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data. 1. A storage system , comprising:a first subset of storage nodes including storage memory;a second subset of storage nodes; anda plurality of authorities associated with the system with each authority owning a range of data stored in the system, the plurality of authorities configurable to control erasure coding of data to be written across the first subset of storage nodes, wherein a number of authorities is greater than a number of storage nodes.2. The system of claim 1 , wherein the storage nodes are contained within multiple chassis claim 1 , each of the multiple chassis having vast storage.3. The system of claim 1 , wherein the plurality of authorities are distributed at least across the first subset of storage nodes.4. The system of claim 1 , wherein an I/O request received for the external I/O processing is routed from one of the storage nodes to another one of the storage nodes claim 1 , in accordance with the plurality of authorities.5. The system of claim 1 , wherein at least one of the plurality of authorities is relocatable from one of the storage nodes to another of the storage nodes.6. The system of claim 1 , wherein the second subset of storage nodes includes at least one compute node.7. The system of claim 1 , wherein processing power for external I/O processing is distributed in accordance with one or more policies claim 1 , agreements claim 1 , service classes or multi-tenant services.8. The system of claim 1 , wherein the second subset of storage nodes comprises at least one compute node in a ...

AGGRESSIVE DATA DEDUPLICATION USING LAZY GARBAGE COLLECTION

A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval. 1. A method , comprising:determining data received by a storage system has a threshold amount of data repeated in the storage system;protecting at least portions of the repeated data from deletion by garbage collection, during a predetermined time interval, the repeated data having a status as being unreferenced in the storage system; andperforming garbage collection except where deletion immunity prevents the deletion during the garbage collection.2. The method of claim 1 , further comprising:indicating in metadata that at least portions of recreated data associated with memory to be reclaimed are to have deletion immunity.3. The method of claim 1 , further comprising:forming a histogram, over one or more sampling windows of time, of data of the storage system, the histogram indicating amounts of the data of the storage system having hash function results matching hash function results of another portion of the data during the one or more sampling windows of time.4. The method of claim 1 , further comprising:setting an aging parameter for one of the at least portions of the repeated data to a first value, responsive to determining the one of the at least portions matches a fingerprint result of another portion of data during a sampling window of time, wherein the first value indicates to not delete during garbage collection.5. The method of claim 1 , further comprising:tracking file creation, file deletion, or frequency ...

STORAGE CLUSTER

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided. 1. A method for storing user data in a storage cluster , comprising:determining, by one of a plurality of authorities in a plurality of storage nodes of a storage cluster, which of a plurality of erasure coding schemes to use for a range of user data owned by the authority; andstoring a portion of user data across the plurality of storage nodes using the erasure coding scheme determined by the authority.2. The method of claim 1 , further comprising:determining, in one of the plurality of storage nodes, which authority in which storage node of the storage cluster has ownership of the range of user data that includes the portion of user data that is arriving for storage in the storage cluster.3. The method of claim 1 , further comprising:determining, in one or more of the plurality of storage nodes, for a further portion of user data, which authority in which storage node of the storage cluster has ownership of a range of user data that includes the further portion of user data;determining, in the one or more of the plurality of storage nodes, that the authority that has the ownership of the ...

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge. 1. A plurality of dynamic decode circuits , each dynamic decode circuit comprising a decoder configured to decode a corresponding plurality of input signals , wherein each decoder is conductively connected to a respective first node , each dynamic decode circuit further comprising a conditioning transistor configured to condition a conditioned node of the dynamic decode circuit , the conditioning transistor having a gate conductively connected to a clock signal , the conditioning transistor conductively connected between the conditioned node and a power source , each conditioning transistor of each dynamic decode circuit conductively connected in parallel between the power source and interconnected conditioned nodes of the plurality of dynamic decode circuits , wherein each dynamic decode circuit comprises a respective evaluate clock circuit conductively connected between a first power source and a second node , each evaluate clock circuit consisting of a first transistor and a second transistor , wherein the first transistor is the conditioning transistor , wherein the first transistor is serially connected by a first interconnecting node to the second transistor , the first transistor comprising a first gate configured to receive the evaluation clock signal , the first transistor configured to conduct based on the evaluation clock signal ...

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge. 1. A plurality of dynamic decode circuits , each dynamic decode circuit connected between a first power source and a second power source , each dynamic decode circuit comprising a respective decoder , a respective first node , a respective second node and a respective third node ,wherein each decoder is configured to decode a respective plurality of input signals, wherein each decoder is conductively connected to a respective first node and to a respective third node,wherein each dynamic decode circuit further comprises one or more respective evaluate transistors, each evaluate transistor connected to the first power source, each evaluate transistor configured to evaluate respective dynamic logic during an evaluate phase of dynamic logic,wherein each dynamic decode circuit further comprises one or more respective precharge circuits, each precharge circuit connected to the second power source, each precharge circuit configured to precharge a respective node in a precharge phase of dynamic logic,wherein each first node is connected to a respective precharge circuit,wherein each the third node is connected to a respective evaluate transistor,wherein each dynamic decode circuit further comprises a respective conditioning circuit configured to condition a shared node of the dynamic decode circuit, the shared node shared by each of the plurality of ...

STORAGE CLUSTER

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data. 1. A system configurable for distributing processing power across a plurality of blades of a storage system , the system , comprising:a plurality of blades, a first subset of blades of the plurality of blades including a storage node and storage memory, and a second subset of blades of the plurality of blades comprising a compute-only node;a plurality of authorities in the system with each authority owning a range of data stored in the system, the plurality of authorities configurable to write erasure coded data across the first subset of blades of the plurality of blades.2. The system of claim 1 , wherein the plurality of blades are contained within multiple chassis.3. The system of claim 1 , wherein the plurality of authorities are distributed at least across the first subset of blades of the plurality of blades.4. The system of claim 1 , wherein an I/O request received for the external I/O processing is routed from one of the plurality of blades to another one of the plurality of blades claim 1 , in accordance with the plurality of authorities.5. The system of claim 1 , wherein at least one of the plurality of authorities is relocatable from one of the plurality of blades to another of the plurality of blades.6. The system of claim 1 , wherein the plurality of authorities are distributed across the plurality of blades in proportion to an amount of RAM (random-access memory) on each of the plurality of blades.7. The system of claim 1 , wherein processing power for external I/O processing is distributed in ...

Multifunction Reaction Washer and Stack accessed by Slim Reaction Socket

Accurate reaction socket access within an outer washer diameter is provided via a number of tool access castles extending from a stepped bushing and serration top, which in turn provides low friction during initial tightening and securing after final loading of a nut/bolt. Bottom serration slipping during initial tightening and thread locking during initial loosening are eliminated by the reaction washer stacked on top and in contact with a support washer via helical ramps and ramp mates. During initial tightening or loosening, the ramp mates slide up or down the helical ramps whereby an axial load on the nut/bolt is ramped up or down prior to screwing it on the main thread. A clamp ring or ramp indenters may secure the two washers. An interposition washer may extend the axial reaction range of the washer stack. Direct tension indicators may be combined with the ramp indenters. 1) A reaction washer comprising:a) a washer axis;b) a top face;c) a number of tool access castles that are circumferentially arrayed with respect to said washer axis and that are extending away from said top face and within and up to an outer washer diameter of said reaction washer.2) The reaction washer of claim 1 , wherein at least one of said number of tool access castles comprises a lock-on groove that is circumferentially at least partially undercutting said at least one tool access castle.3) The reaction washer of claim 1 , further comprising a bottom face that s radially extending up to said outer washer diameter.4) The reaction washer of claim 1 , wherein at least one of said number of tool access castles is extending downward away from said top face.5) The reaction washer of claim 1 , wherein at least one of said number of tool access castles is extending upward away from said top face.6) The reaction washer of claim 1 , further comprising a number of bite spikes circumferentially arrayed on a bottom face of said reaction washer.7) The reaction washer of claim 1 , further comprising ...

SCALABLE NON-UNIFORM STORAGE SIZES

A storage cluster includes a plurality of storage nodes. Each of the plurality of storage nodes includes nonvolatile solid-state memory and each of the plurality of storage nodes is configured to cooperate with others of the plurality of storage nodes having differing storage capacities in applying erasure coding. The plurality of storage nodes are configured to distribute the user data and metadata throughout the plurality of storage nodes. 1. A plurality of storage nodes , comprising:each of the plurality of storage nodes having a storage capacity with nonvolatile solid-state memory;the plurality of storage nodes configured to support uniform storage capacities and non-uniform storage capacities among the plurality of storage nodes, as a storage cluster; andthe plurality of storage nodes configured to distribute user data via erasure coding and redundant copies of metadata throughout the plurality of storage nodes.2. The plurality of storage nodes of claim 1 , wherein the nonvolatile solid-state memory of each of the plurality of storage nodes comprises storage class memory.3. The plurality of storage nodes of claim 1 , further comprising:each of the plurality of storage nodes configured so that the plurality of storage nodes uses all of the storage capacities among the plurality of storage nodes via erasure coding.4. The plurality of storage nodes of claim 1 , further comprising:each of the plurality of storage nodes configured to cooperate with others of the plurality of storage nodes in response to an addition of a further storage node, as to an erasure coding scheme that supports the storage capacity of the further storage node.5. The plurality of storage nodes of claim 1 , further comprising:each of the plurality of storage nodes configured to determine a data stripe width in accordance with an erasure coding scheme and configured to write the user data to the plurality of storage nodes in support of the uniform storage capacities and the non-uniform storage ...

MESSAGE STORAGE IN MEMORY BLOCKS USING CODEWORDS

A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword. 1. A method comprising:receiving a message to store in a memory block by a computing device, wherein the memory block comprises a plurality of cells, and each cell has a value of a plurality of values;generating a first string from the message by the computing device, wherein the first string comprises a plurality of positions, each position corresponds to a cell of the plurality of cells, and each position has a value of the plurality of values;determining a plurality of stuck cells of the plurality of cells by the computing device;determining a value of each of the plurality of stuck cells by the computing device;generating a second string using a mapping function, the first string, the determined value of each of the plurality of stuck cells, and the positions of the first string corresponding to the plurality of stuck cells; andstoring the second string in the memory block by the computing device.2. The method of claim 1 , wherein the mapping function is a linear function over a finite field.3. The method of claim 1 , further comprising:retrieving the stored second string;determining positions in the second string of a plurality of anchor values;recovering the first string from the second string based on the determined positions in the second string of the plurality of anchor ...

DIE-LEVEL MONITORING IN A STORAGE CLUSTER

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster. 1. A plurality of storage nodes in a chassis , comprising:each of the plurality of storage nodes having non-volatile solid state storage; andeach non-volatile solid-state storage having a controller configured to track bit errors, wherein diagnostic information for each non-volatile solid-state storage is based at least in part on the bit errors.2. The plurality of storage nodes in a chassis of claim 1 , further comprising:the plurality of storage nodes configured to derive characterization information from the diagnostic information, the characterization information indicating at least one change, prediction or trend in the non-volatile solid state storage.3. The plurality of storage nodes in a chassis of claim 1 , further comprising:the plurality of storage nodes configured to report the diagnostic information via a network.4. The plurality of storage nodes in a chassis of claim 1 , further comprising:non-volatile memory included in the non-volatile solid-state storage;each non-volatile solid-state storage having a controller, the controller configured to track bit errors of the non-volatile memory;each of the plurality of storage nodes having a ...

Reaction washer with belleville spring induced radially inward progressing bottom bite action and tightening and securing system

A Belleville reaction washer flattens out while being fully loaded such that its bottom serrations initially contact and bite with their peripheral ends only. Thereby washer slippage is circumvented as the maximum distance to the washer axis offsets eventual increased thread friction and eventual presence of lubricants or paint on the base surface. During washer flattening, the bottom serrations extend their bite radially inward and underneath the nut or bolt head. The Belleville spring action may secure the nut or bolt head on top against inadvertent loosening. In addition, a dual washer stack may include a conical ramp interface for a low overall height and lock washer functionality. Radial torque receive faces remain in plane during washer flattening and receive the torque substantially free of radial force components. A radially slim reaction socket interface may thus be tapered down around them without need for continuous circumferential structural support.

CONCENTRIC ACTUATION AND REACTION TORQUE TRANSFER SYSTEM

An actuation and reaction socket tool features a reaction coupling that is slid onto the spline flange of a power torque wrench prior to attaching the actuation socket on the drive shaft of the torque wrench and prior to securing it with a well-known safety pin. The reaction coupling is then coupled to the reaction socket via circumferentially arrayed and interlocking castles on both the reaction coupling and reaction socket. A lock plate spring loaded snaps into grooves on the inside of the castles and axially locks the reaction coupling with the reaction socket. At least one of the reaction coupling and reaction socket is axially withheld by the central actuation socket such that the entire tool system remains connected to the torque wrench. To remove the tool again, the reaction coupling and reaction socket are first decoupled, which provides access again to the safety pin for its removal. 1. A concentric actuation and reaction torque transfer system comprising:a. a torque transfer axis; i. a drive shaft torque interface;', 'ii. an axial shaft lock interface;', 'iii. an actuation interface; and', 'iv. an axial retention feature; wherein and while said actuation socket is being coupled with a torque wrench drive shaft via said drive shaft torque interface, said actuation interface is positioned substantially centrally and concentrically with respect to said torque transfer axis and is facing away from said torque wrench for transferring said actuation torque from said drive shaft onto an actuation receiving structure; and wherein and while said actuation socket is axially coupled to said drive shaft via said axial shaft lock interface, said axial retention feature is axially positioned with respect to said torque wrench;, 'b. an actuation socket comprisingc. a reaction coupling comprising a torque wrench interface and a reaction socket interface, wherein and while said torque wrench interface is torque transferring and axially slide able coupled with a housing of ...

INTERCHANGEABLE, DEBRIS INSENSITIVE AND NON-SLIPPING REACTION TORQUE TRANSFER SYSTEM

Interchangeable monolithic or stacked Belleville reaction washers initially penetrate with outward bottom serration edges only during manual pre-tightening. Slippage is thereby avoided at begin of the consecutive power torque wrench assisted full tightening of the nut and/or bolt head resting on it. As the load ramps up, the reaction washer or stack flattens out and the bottom serrations gradually penetrate radially inwards. Reaction and actuation sockets of varying sizes matching a broad range of reaction washers and nut and/or bolt heads may be interchangeably snapped on a reaction coupling connected to the torque wrench housing. A clearance undercut underneath the reaction washer torque receiving flanges captures eventual debris to further assist unimpeded and fast coupling of the system. Radially oriented contact faces between reaction washer and reaction socket provide a snug contact unaffected by their toroidal movement during washer flattening and a force transfer free of radial force components. 1. An interchangeable actuation and reaction torque transfer system comprising:a. a torque transfer axis; i. a drive shaft torque interface on a first axial actuation socket end for coupling with a torque drive shaft; and', 'ii. an actuation interface on a second axial actuation socket end that is opposite said first axial actuation socket end for coupling with an actuation receiving structure;, 'b. an actuation socket comprising i. a torque wrench interface on a first axial coupling end for coupling with a torque wrench housing; and', 'ii. a reaction socket interface on a second axial coupling end that is opposite said first axial coupling end;, 'c. a reaction coupling comprising i. a coupling interface on a first axial reaction socket end for coupling with said reaction coupling; and', 'ii. a drain interface on a second axial reaction socket end that is opposite said first axial reaction socket end;, 'd. a reaction socket comprising i. a reaction washer axis;', 'ii ...

Proactive Data Rebuild Based On Queue Feedback

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Proactive Data Rebuild Based On Queue Feedback

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget. 1. A method , comprising:evaluating whether a read time to read data stored within memory of a distributed storage system via a first path is within a latency budget, responsive to a request to read the data from the distributed storage system; andidentifying a second path to read a redundant copy of the data, responsive to the evaluating determining the read time exceeds the latency budget, wherein the evaluating and the identifying are executed through a processor of the storage system.2. The method of claim 1 , wherein the evaluating comprises:determining whether reading the data via the first path is within the latency budget according to feedback from the plurality of operations queues.3. The method of claim 1 , wherein the data is distributed throughout a plurality of storage nodes through erasure coding.4. The method of claim 1 , further comprising:reconstructing the data responsive to the evaluating determining the read time exceeds the latency budget.5. The method of claim 1 , wherein the first path includes a first channel bus coupled to a first flash die and to a plurality of operations queues and ...

Adjustable Error Correction Based on Memory Health in a Storage Unit

A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable. 1. A method , comprising:determining wear level of storage devices within a plurality of storage nodes in a storage cluster, wherein two or more authorities are located within a first storage node of the plurality of storage nodes, and wherein each authority owns a range of data;adjusting a variable parameter supportive to increase reliability of the data, based on the wear level of the storage devices; andadjusting erasure coding based on the wear level of the storage devices.2. The method of claim 1 , further comprising:ranking portions of non-volatile memory of at least one of the storage devices based on the wear level of the at least one of the storage devices, wherein adjusting the variable parameter includes assigning differing numbers of bits for error correction code (ECC) to differing portions of the at least one storage device according to the ranking.3. The method of claim 1 , wherein adjusting the variable parameter comprises:adjusting a stripe width and a type of error correction code (ECC).4. The method of claim 1 , wherein each of one or more storage nodes in the storage ...

DATA REDUCTION WITH END-TO-END SECURITY

A storage controller coupled to a storage array comprising one or more storage devices receives a request to write encrypted data to a volume resident on a storage array, where the encrypted data comprises data encrypted by a first encryption key that is associated with at least one property of the data. The storage controller determines a decryption key to decrypt the encrypted data, decrypts the encrypted data using the decryption key, performs at least one data reduction operation on the decrypted data, encrypts the reduced data using a second encryption key to generate a second encrypted data, and storing the second encrypted data on the storage array. 1. A system comprisinga storage array comprising one or more storage devices; and receive a first request from a first client device to write a first encrypted data to a logical volume resident on a storage array, wherein the first encrypted data comprises a first data encrypted by a first encryption key, wherein the first encryption key is associated with at least one of the logical volume, a logical volume range on the storage array, or a client identifier associated with the first data;', 'determine a first decryption key to decrypt the encrypted data, wherein the first decryption key is associated with the at least one of the logical volume, the logical volume range on the storage array, the client identifier associated with the first data, or the first encryption key;', 'decrypt the encrypted data using the first decryption key to generate a first decrypted data;', 'perform at least one of a data deduplication operation or a data compression operation on the first decrypted data to generate a first reduced data;', 'encrypt the first reduced data using a second encryption key to generate a second encrypted data, wherein the second encryption key is associated with at least one property of the storage array; and', 'store the second encrypted data on the storage array., 'a storage controller coupled to the ...

Die-Level Monitoring in a Storage Cluster

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster. 1. A method for die-level monitoring in a storage cluster , comprising:performing error correction of reads of a non-volatile solid state storage;forwarding error information, based at least in part on the error correction, from a controller for the non-volatile solid-state storage; andcharacterizing the non-volatile solid state storage by combining the error information at differing time points from the controller for the non-volatile solid state storage.2. The method of claim 1 , wherein the characterization of the non-volatile solid state storage indicates at least one change in the non-volatile solid-state storage.3. The method of claim 1 , further comprising:biasing at least one of a read from or a write to the non-volatile solid state storage, responsive to the combining the error information.4. The method of claim 1 , further comprising:tracking wear of a plurality of blocks of the non-volatile solid state storage, based on the error information.5. The method of claim 1 , wherein combining the error information further comprises:tracking bit errors per page, each page having a plurality of codewords; andforwarding information pertaining to ...

STORAGE CLUSTER

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided. 1. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory , comprising:distributing the user data throughout the plurality of storage nodes through erasure coding, the erasure coding determined by a plurality of authorities, each authority of the plurality of authorities having ownership for a corresponding range of the user data;determining that one of the plurality of storage nodes is unreachable; andaccessing the user data, via the erasure coding as determined by at least one of the plurality of authorities, from a remainder of the plurality of storage nodes.2. The method of claim 1 , further comprising:reading the user data across the remainder of the plurality of storage nodes, using a first type of the erasure coding; andwriting the user data across the remainder of the plurality of storage nodes, using a second type of the erasure coding.3. The method of claim 1 , wherein the erasure coding includes two differing erasure coding schemes coexisting in the plurality of storage nodes.4. The method of claim 1 , wherein determining that one of ...

AGGRESSIVE DATA DEDUPLICATION USING LAZY GARBAGE COLLECTION

A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval. 1. A method for extending data lifetime for reference in deduplication , comprising:monitoring repeated data in a storage system;indicating in metadata that at least portions of the repeated data are to have erasure immunity responsive to the monitoring;protecting the at least portions of the repeated data from erasure by garbage collection, during a predetermined time interval; andperforming garbage collection except where the erasure immunity as indicated by the metadata prevents the erasure during the garbage collection.2. The method of claim 1 , wherein the monitoring comprises:forming a histogram, over one or more sampling windows of time, of data of the system, the histogram indicating amounts of the data of the system having hash function results matching hash function results of another portion of the data during the one or more sampling windows of time.3. The method of claim 1 , wherein the metadata includes an aging parameter for each of the at least portions of the repeated data claim 1 , and further comprising:setting the aging parameter for one of the at least portions of the repeated data to a first value, responsive to determining the one of the at least portions matches a fingerprint result of another portion of data during a sampling window of time, wherein the first value indicates to not erase during garbage collection; andadjusting the aging parameter for a further one of the at least portions of the ...

Mapping Defective Memory in a Storage System

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Dual Actuated Jackscrew Nut And/Or Bolt Head

A jackscrew nut and/or bolt head assembly includes a circumferentially and radially interlocked bottom washer. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary torque exerted onto the main body of the nut and/or bolt head via an outside spline such as well known triple square, twelve spline or the like, which may be incorporated also into the bottom washer for a concurrent application of an external torque. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced. 1. A jackscrew tightening assembly comprising:a. a central thread with a central thread axis; i. a main top;', 'ii. a main bottom that is opposite said main top in axial direction with respect to said central thread axis;', 'iii. a through hole with a through hole axis being in an offset to said central thread axis;', 'iv. a secondary thread at least along a portion of said through hole;, 'b. a main body radially outward extending with respect to said central thread, said main body comprising i. a jackscrew head that is facing away from said main bottom;', 'ii. a spherical bottom that is facing away from said main top, 'c. a jackscrew that is extending through said through hole and that is engaging with said secondary thread, said jackscrew comprising i. a washer top that is facing said main bottom;', 'ii. a spherical face that is formed into said washer top and that is in substantial axial alignment with said spherical bottom with respect to said central thread axis and that is matching said spherical bottom;, 'd. a bottom washer that is adjacent to said main bottom and that is surrounding said central thread, said bottom washer comprising i. a first interlock ...

Dual Actuated Nut And/Or Bolt Head With Reversed Thinned Jackscrews And Washer/Nut Castle Interlock

A jackscrew nut and/or bolt head assembly includes a bottom washer that is interlocked via circumferentially arrayed castle extensions and recesses. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary pre tightening torque exerted onto the main body of the nut and/or bolt head via a tool that concurrently accesses all jackscrew heads extending above the main body. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced. The jackscrews are thinned in reverse for maximum contact area at their spherical bottoms. 1. A jackscrew tightening assembly comprising:a. a central thread with a central thread axis; i. a main top;', 'ii. a main bottom that is opposite said main top in axial direction with respect to said central thread axis;', 'iii. a top guide hole that is extending from said main top with a through hole axis being in an offset to said central thread axis;', 'iv. a secondary thread that is adjacent and below said top guide hole and concentric with respect to said top guide hole;', 'v. a castle recess recessed in said main bottom;', 'vi. a bottom guide hole that is extending from said main bottom concentric with respect to said top guide hole, 'b. a main body radially outward extending with respect to said central thread, said main body comprising i. a jackscrew head that is facing away from said main bottom;', 'ii. a spherical bottom that is facing away from said main top;', 'iii. a top guide shaft that is adjacent said jackscrew head and in between said jackscrew head and said spherical bottom and that is guided in said top guide hole;', 'iv. a bottom guide shaft that is adjacent said spherical bottom and in between said ...

Nut And/Or Bolt Head With Jackscrew Actuated Lock Washer Stack

A jackscrew nut and/or bolt head assembly includes a load washer that may be selectively engaged via the jackscrews. Spherical faces at the washer top are held in alignment with corresponding spherical jackscrew bottoms via axially interlocking pins. The pins may partially extend radial beyond the circumference of the main body of the nut and/or bolt head thereby defining ridges of an outside tool access profile. The assembly may be initially tightened via a primary torque induced onto the pins and the main body. Final tightening and load setting may be provided via the jackscrews whereby a lock feature of the load washer may be engaged and the assembly secured against inadvertent loosening. The load washer may be part of a lock washer stack including a lock washer. The interface between the lock and load washer may be configured for ratchet locking and/or helical wedge locking of the central thread. 2. The lock washer stack of claim 1 , wherein said load washer further comprises a washer interlock recessed from said first washer top.3. The lock washer stack of claim 2 , wherein said washer interlock is radially recessed in a circumference of said load washer.4. The lock washer stack of claim 1 , wherein said lock washer further comprises:a. a second washer through hole that is substantially smaller than said first washer through hole, andb. a bearing face that is inside of said second ratchet feature and that is axially accessible through said first washer through hole while said first ratchet feature and said second ratchet feature are in contact.5. The lock washer stack of claim 1 , wherein said lock feature includes a radial serration.6. The lock washer stack of claim 1 , wherein said lock feature is a coupling protrusion that is protruding away from said second washer bottom.7. A jackscrew tightening assembly comprising:a. a central thread with a central thread axis; i. a main top;', 'ii. a main bottom that is opposite said main top in axial direction with ...

HARDWARE ACCELERATION FOR QUERY OPERATORS

A hardware device is used to accelerate query operators including Where, Select, SelectMany, Aggregate, Join, GroupBy and GroupByAggregate. A program that includes query operators is processed to create a query plan. A hardware template associated with the query operators in the query plan is used to configure the hardware device to implement each query operator. The hardware device can be configured to operate in one or more of a partition mode, hash table mode, filter and map mode, and aggregate mode according to the hardware template. During the various modes, configurable cores are used to implement aspects of the query operators including user-defined lambda functions. The memory structures in the hardware device are also configurable and used to implement aspects of the query operators. The hardware device can be implemented using a Field Programmable Gate Array or an Application Specific Integrated Circuit. 1. A method comprising:receiving a query plan at a computing device, wherein the query plan comprises a plurality of computational nodes and each computational node corresponds to a query operator;generating a mapping of the query operators corresponding to one or more of the computational nodes to one or more components of a hardware device; andcausing one or more of the query operators to be executed at the hardware device according to the mapping by the computing device.2. The method of claim 1 , wherein the hardware device comprises one or more of a Field Programmable Gate Array or an Application Specific Integrated Circuit.3. The method of claim 1 , wherein the query operators are one or more of LINQ operators or SQL operators.4. The method of claim 1 , wherein the query operators are one or more of a Join operator claim 1 , a Select operator claim 1 , a SelectMany operator claim 1 , a Where operator claim 1 , an Aggregate operator claim 1 , a GroupBy operator claim 1 , or a GroupByAggregate operator.5. The method of claim 1 , wherein the one or more ...

MESSAGE STORAGE IN MEMORY BLOCKS USING CODEWORDS

A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword. 1. A method comprising:receiving a message to store in a memory block by a computing device, wherein the memory block comprises a plurality of cells and each cell has a value of a plurality of values;generating a first string from the message by the computing device, wherein the first string comprises a plurality of positions, and wherein each position corresponds to a cell of the plurality of cells and each position has a value of the plurality of values;determining a value of a stuck cell of the plurality of cells of the memory block by the computing device;determining a difference between the value of the stuck cell and the value of the position of the first string corresponding to the stuck cell by the computing device;adding the determined difference to each value of the first string modulo an alphabet size to generate a second string by the computing device; andstoring the second string in the memory block by the computing device.2. The method of claim 1 , further comprising:retrieving the stored second string;determining the difference based on the second string;subtracting the determined difference from each value of the second string modulo the alphabet size to recover the first string;generating the message based on the first string; andproviding the message.3. The ...

Storage cluster

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

Compact Hydraulic Torque Wrench Cartridge

Drive plates of a hydraulic torque wrench cartridge are thickened for extended surface contact with three pawls and a direct contact with the piston rod. The drive plates are held together and are additionally stiffened by dowel pins and shoulder screws. Snap pins are axially slide able and spring loaded connecting the piston rod with the drive plates in an easily disengage able fashion. Three pawls are arrayed in a pitch adjusted with respect to the ratchet teeth pitch in correspondence with an elastic deformation of the drive plates for a balanced force transfer across them. The pawl-tooth interfaces are also in an outward opening angle preventing them from snapping free under load. 1. A hydraulic torque wrench comprising:A. a housing;B. a hydraulic piston that is slide able along a piston axis guided in said housing and that is transforming a hydraulic pressure into a piston force along a piston axis;C. a piston rod that is receiving said piston force from said hydraulic piston;D. a drive plate that is receiving said piston force from said piston rod via a rod-plate interface;E. a cartridge pawl that is receiving said piston force from said drive plate via a plate-pawl interface;F. a ratchet wheel that is rotate able concentric with respect to a torque transfer axis held in said housing and rotate able held on to by said drive plate and that is receiving said piston force from said cartridge pawl via a pawl-tooth interface such that said piston force is transformed into a torque around said torque transfer axis;wherein said drive plate comprises:1. a drive plate base that is extending lateral to said ratchet wheel; and2. a drive plate castle that is extending within a width of said ratchet wheel.2. The hydraulic torque wrench of claim 1 , wherein said rod-plate interface is extending within said drive plate castle.3. The hydraulic torque wrench of claim 2 , wherein said rod-plate interface comprises:A. a rod push face at a distal end of said piston rod; andB. a ...

Recovering Error Corrected Data

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory. 1. A method for error recovery in a storage system , performed by a plurality of storage nodes of the storage system , comprising:detecting a read error in reading data from solid-state memory of the storage system;retrying the reading the data from the solid-state memory; anddetermining error corrected data as a result of analysis of data from the retrying the reading of the data.2. The method of claim 1 , wherein the retrying the reading the data from the solid-state memory comprises:retrying the reading the data with differing levels of reference voltage in or to the solid-state memory.3. The method of claim 1 , wherein the retrying the reading the data from the solid-state memory comprises:retrying the reading the data with differing levels of reference current in or to the solid-state memory.4. The method of claim 1 , wherein the retrying the reading the data from the solid-state memory comprises:retrying the reading the data with error correction internal to a die in the solid-state memory.5. The method of claim 1 , wherein the retrying the reading the data from the solid-state memory ...

WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH

A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation. 1. A write block read apparatus for a memory device , the apparatus comprising:a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits;a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; anda static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.2. The apparatus of claim 1 , wherein the address conflict occurs when a group of most significant bits of the static write address bits equals a group of most significant bits of the static read address bits.3. The apparatus of claim 2 , wherein an ...

Write/read priority blocking scheme using parallel static address decode path

A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL Method

A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate. 1. A method for conditioning a shared node of a plurality of dynamic decode circuits , each dynamic decode circuit having a decoder , an output transistor and a conditioning transistor , each conditioning transistor of the plurality of dynamic decode circuits connected in parallel to the shared node , the each dynamic decode circuit performing a method , the method comprising:receiving input signals, by a plurality of inputs of the decoder;precharging a first node of the decoder to a high state, by a first precharge circuit comprising a first precharge transistor, based on being in a precharge phase of an evaluation clock, the first node being conductively connected to a gate of the output transistor;precharging a second node of the output transistor to the high state, by a second precharge circuit comprising a second precharge transistor, based on being in the precharge phase of the evaluation clock, the output transistor being disposed between the second node and an interconnecting node;pulling a third node of the decoder to a low state, by a first evaluate transistor, based on being in an evaluation phase of the evaluation clock; based on the plurality of inputs being in a predetermined state, causing the first node to be in the high state; and', 'based on the plurality of inputs not being in the predetermined state, causing the first node to be in the low state;, 'pulling the interconnecting node of the output transistor to the low state, by a second evaluate transistor, ...

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL METHOD

A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive. 1. A method for precharging a dynamic decode circuit , the dynamic decode circuit comprising a decoder connected to a first node and an evaluate circuit , the evaluate circuit comprising a first transistor serially connected to a second transistor by way of an interconnecting node , the evaluate circuit connected between a second node and a first power source , the dynamic decode circuit performing a method , the method comprising:receiving input signals, by a plurality of inputs of the decoder;based on the plurality of inputs of the decoder being in a predetermined input state and based on being in an evaluation phase, causing, by the decoder, the first node to be low;receiving an evaluation clock signal by a first gate of the first transistor of the evaluate circuit;receiving the first node by a second gate of the second transistor of the evaluate circuit;based on the first node being low and based on being in the evaluation phase, causing, by the evaluate circuit, the second node to be high;precharging the first node to a high state, by a first precharge circuit comprising a first precharge transistor, based on not being in the evaluation phase of the evaluation clock signal;precharging the second node to the high state, by a second precharge circuit comprising a second precharge transistor, based on not being in the evaluation phase of the evaluation clock signal; andprecharging the interconnecting ...

DYNAMIC DECODE CIRCUIT WITH DELAYED PRECHARGE

A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase. 1. A dynamic decode circuit connected between a first power source and a second power source , the dynamic decode circuit comprising a decoder connected to a first node and an evaluate clock circuit connected to a second node , wherein the decoder is configured to decode a plurality of inputs , wherein the evaluate clock circuit is configured to present a result of the decode to the second node , wherein the first node of the decoder is conductively connected to a base of a first transistor of the evaluate clock circuit , andwherein the dynamic decode circuit further comprises one or more precharge circuits, wherein at least one of the one or more precharge circuits is a delay precharge circuit, wherein the delay precharge circuit consists of a respective first precharge transistor serially connected to a respective second precharge transistor, wherein a base of the first precharge transistor is configured to receive an evaluation clock signal, and a base of the second precharge transistor is configured to receive a delayed evaluation clock signal, each precharge circuit is conductively connected to the second power source, wherein the each precharge circuit is configured to precharge a respective node based on the evaluation clock signal being inactive, and the precharge circuit configured to not conduct based on the evaluation clock signal being active,wherein the first node is conductively connected to a first delay precharge circuit.2. The dynamic decode circuit according to claim 1 , further comprising one or more evaluate transistors claim 1 , wherein each evaluate transistor is connected to the first power source claim 1 , wherein the each evaluate ...

STORAGE CLUSTER

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided. 1. A storage cluster in a single chassis , comprising:a plurality of storage nodes configured to communicate together as the storage cluster;each of the plurality of storage nodes having one or more storage units;each of the one or more storage units having solid-state storage memory;the plurality of storage nodes configured to distribute user data and metadata associated with the user data throughout the plurality of storage nodes; anda plurality of compute nodes in the single chassis, each of the plurality of compute nodes configured to communicate with the plurality of storage nodes.2. The storage cluster of claim 1 , wherein the plurality of storage nodes is configured to distribute the user data according to two erasure coding schemes claim 1 , wherein the two erasure coding schemes coexist in the plurality of storage nodes and wherein at least one of the plurality of compute nodes can make use of user data having each of the two erasure coding schemes.3. The storage cluster of claim 1 , wherein the single chassis is an enclosure with internal power distribution and an internal ...

Concentric Actuation and Reaction Torque Transfer System

An actuation and reaction socket tool features a reaction coupling that is slid onto the spline flange of a power torque wrench prior to attaching the actuation socket on the drive shaft of the torque wrench and prior to securing it with a well known safety pin. The reaction coupling is then coupled to the reaction socket via circumferentially arrayed and interlocking castles on both the reaction coupling and reaction socket. A lock plate spring loaded snaps into grooves on the inside of the castles and axially locks the reaction coupling with the reaction socket. At least one of the reaction coupling and reaction socket is axially withheld by the central actuation socket such that the entire tool system remains connected to the torque wrench. To remove the tool again, the reaction coupling and reaction socket are first decoupled, which provides access again to the safety pin for its removal. 1. A concentric actuation and reaction torque transfer system comprising:a. a torque transfer axis; i. a drive shaft torque interface;', 'ii. an axial shaft lock interface;', 'iii. an actuation interface;', 'iv. an axial retention feature;', 'wherein and while said actuation socket is being coupled with a torque wrench drive shaft via said drive shaft torque interface, said actuation interface is positioned substantially centrally and concentrically with respect to said torque transfer axis and is facing away from said torque wrench for transferring said actuation torque from said drive shaft onto an actuation receiving structure; and', 'wherein and while said actuation socket is axially coupled to said drive shaft via said axial shaft lock interface, said axial retention feature is axially positioned with respect to said torque wrench;, 'b. an actuation socket comprisingc. a reaction coupling comprising a torque wrench interface and a reaction socket interface, wherein and while said torque wrench interface is torque transferring and axially slide able coupled with a housing ...

STORAGE EFFICIENCY OF ENCRYPTED HOST SYSTEM DATA

A storage controller coupled to a storage array comprising one or more storage devices that performs at least one data reduction operation on decrypted data, encrypts the reduced data using a second encryption key to generate a second encrypted data, and stores the second encrypted data on the storage array. 1. A system comprisinga storage array comprising one or more storage devices; and perform at least one of a data deduplication operation or a data compression operation on a first decrypted data to generate a first reduced data;', 'encrypt the first reduced data using a second encryption key to generate a second encrypted data, wherein the second encryption key is associated with at least one property of the storage array; and', 'store the second encrypted data on the storage array., 'a storage controller coupled to the storage array, the storage controller comprising a processing device, wherein the processing device comprising one or more processor cores to2. The system of claim 1 , wherein to determine the first decryption key claim 1 , wherein the one or more processor cores to:receive a first request from a first client device to write the first encrypted data to a logical volume resident on the storage array, wherein the first encrypted data comprises a first data encrypted by a first encryption key;determine a first decryption key to decrypt the first encrypted data;decrypt the encrypted data using the first decryption key to generate a first decrypted data.3. The system of claim 2 , wherein to determine the first decryption key claim 2 , the wherein the one or more processor cores to:determine a security identifier associated with the at least one of the logical volume, the logical volume range on the storage array, or the client identifier associated with the first data;send a second request to a key management service for the first decryption key, the second request comprising the security identifier; andreceive a response with the first decryption key ...

EXTENDED LIFETIME MEMORY

A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block. 1. A memory controller for extended lifetime memory , comprising:an error correction module that manages blocks of non-fault consecutive bits within a disabled page of a memory as spare blocks; and for an active block of the memory containing at least one fault, applies a correction code to the active block using at least one of the spare blocks.2. The memory controller of claim 1 , wherein the correction code is an XOR correction and the error correction module applies the XOR correction such that the active block is XORed with a first spare block and a second spare block of the spare blocks.3. The memory controller of claim 2 , wherein the second spare block is located at a next consecutive spare block address location from the first spare block in a spare block pool managed by the memory controller.4. The memory controller of claim 2 , wherein the active block is further XORed with a third spare block of the spare blocks.5. The memory controller of claim 1 , wherein the correction code is an erasure code.6. The memory controller of claim 1 , wherein the memory is phase change memory.7. The memory controller of claim 1 , wherein the active block contains data and metadata.8. ...

Dynamic decode circuit with active glitch control

A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

CONFIGURABLE HYPERCONVERGED MULTI-TENANT STORAGE SYSTEM

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data. 1. A configurable storage system , comprising:a first subset of storage nodes including storage memory;a second subset of storage nodes; anda plurality of authorities associated with the system with each authority owning a range of data stored in the system, the plurality of authorities configurable to enable erasure coded data to be written across the first subset of storage nodes.2. The system of claim 1 , wherein the storage nodes are contained within multiple chassis claim 1 , each of the multiple chassis having vast storage.3. The system of claim 1 , wherein the plurality of authorities are distributed at least across the first subset of storage nodes.4. The system of claim 1 , wherein an I/O request received for the external I/O processing is routed from one of the storage nodes to another one of the storage nodes claim 1 , in accordance with the plurality of authorities.5. The system of claim 1 , wherein at least one of the plurality of authorities is relocatable from one of the storage nodes to another of the storage nodes.6. The system of claim 1 , wherein the plurality of authorities are distributed across storage nodes in proportion to an amount of memory on each of the storage nodes.7. The system of claim 1 , wherein processing power for external I/O processing is distributed in accordance with one or more policies claim 1 , agreements claim 1 , service classes or multi-tenant services.8. The system of claim 1 , wherein the second subset of storage nodes comprises at least one compute node in a ...

REACTION WASHER-BASED ACTUATION-REACTION TORQUE TRANSFER

A reaction washer is optimized for lock-on, optional stiction ring and for a predetermined indentation depth of bidirectional serrations for secure reaction torque transfer during initial and full actuation of respective nut or bolt heads resting on it. An optional lock-on ring embedded around the reaction socket is ergonomically actuated to latch on and off underneath the reaction washer. Axial offset of the peak stress areas away from the actuation socket edges provides for reduced actuation socket diameter and consequently for the entire tool and system remaining substantially within radial assembly limits established for prior art actuation sockets alone. A coupling unit is attached to and tightened on a power torque wrench via a clamp tool utilizing the power wrench's own torque. A hand hold groove and a lock able snap release button offset from the coupling castle snap connection contribute to safe and ergonomic operation and system peak performance. 1. A reaction washer-based actuation and reaction torque transfer system comprising:a torque transfer axis;a number of torque receive structures that are circumferentially arrayed around a base flange of said reaction washer, at least one of said torque receive structures comprising a torque receive face portion that is radially oriented with respect to said torque transfer axis within a radial friction angle between 0.1 and 31 degrees such that a reaction torque is received by said torque receive face portion around said torque transfer axis remains substantially free of a radial slippage between a torque inducing structure and a respective one of said torque receive structures,wherein a first set of two of said torque receive face portions are in a receive face structure angle circumferentially oppositely positioned to each other on a first of said torque receive structures;wherein a second set of two of said torque receive face portions are in a receive face gap angle circumferentially facing each other on said ...

ENGAGING WASHERS

Engaging washers such as reaction washers and backup washers can include novel advantageous features. For example, an engaging washer can include an inner row of teeth and an outer row of teeth, where the teeth in the inner row can slope in a first circumferential direction to primarily engage a flange during bolt tightening, and the teeth in the outer row can slope in a second circumferential direction to primarily engage during bolt loosening. The engaging washers may also include an arched design to allow gradual increasing of contact surface areas as a clamping force in the washer gradually increases. Additionally, a reaction washer can include stepped castles for engaging a reaction socket. The castles may also include sloped or curved engaging surfaces that can provide decreased contact surface area and may also inhibit outward biasing of reaction fingers that are engaging the castles. 1. An engaging washer comprising:an inner row of teeth extending around a central axis of the engaging washer, with the inner row of teeth comprising a plurality of teeth that each extends in a flange direction from a body of the engaging washer, with the flange direction being parallel to the central axis; andan outer row of teeth extending around the inner row of teeth, with the outer row of teeth comprising a plurality of teeth that each extends in the flange direction from the body of the engaging washer, and with the outer row of teeth being farther from the central axis of the engaging washer than the inner row of teeth.2. The engaging washer of claim 1 , further comprising a bridge between the inner row of teeth and the outer row of teeth claim 1 , with the bridge defining a cavity opening in the flange direction and extending around the inner row of teeth claim 1 , and with the cavity being between the inner row of teeth and the outer row of teeth.3. The engaging washer of claim 2 , wherein a flange-facing surface of the engaging washer defines the inner row of teeth and ...

Intelligent operation scheduling based on latency of operations

A storage system is provided. The storage system includes a plurality of non-volatile memory units and a processor operatively coupled to a plurality of non-volatile memory units. The processor is to perform a method including receiving a request to read data from the storage system. The method also includes determining whether a storage operation should be delayed, based on the request to read the data from the storage system. The method further includes in response to determining that the storage operation should be delayed, delaying the storage operation. The method further includes performing a read operation for the request to read the data.

Estimating and managing power consumption of computing devices using power models

Power consumption of computing devices are monitored with performance counters and used to generate a power model for each computing device. The power models are used to estimate the power consumption of each computing device based on the performance counters. Each computing device is assigned a power cap, and a software-based power control at each computing device monitors the performance counters, estimates the power consumption using the performance counters and the model, and compares the estimated power consumption with the power cap. Depending on whether the estimated power consumption violates the power cap, the power control may transition the computing device to a lower power state to prevent a violation of the power cap or a higher power state if the computing device is below the power cap.

Failure mapping in a storage array

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Multifunction reaction washer and stack accessed by slim reaction socket

Accurate reaction socket access within an outer washer diameter is provided via a number of tool access castles extending from a stepped bushing and serration top, which in turn provides low friction during initial tightening and securing after final loading of a nut/bolt. Bottom serration slipping during initial tightening and thread locking during initial loosening are eliminated by the reaction washer stacked on top and in contact with a support washer via helical ramps and ramp mates. During initial tightening or loosening, the ramp mates slide up or down the helical ramps whereby an axial load on the nut/bolt is ramped up or down prior to screwing it on the main thread. A clamp ring or ramp indenters may secure the two washers. An interposition washer may extend the axial reaction range of the washer stack. Direct tension indicators may be combined with the ramp indenters.

Programmable analog control of a bitline evaluation circuit

The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

Tooling with stepping motor drive

Apparatus is disclosed which includes a carriage having mounted thereon tooling for trimming wires and inserting trimmed wires into electrical contacts successively along an electrical connector mounted on an anvil. A stepping motor drive transports and repeatedly stops the carriage and the tooling successively in alignment with the multiple contacts preparatory to insertion of corresponding trimmed wires therein. The tooling is quickly replaceable and follows along a reference surface of the connector for positive alignment with the contacts.

Increased storage unit encryption based on loss of trust

A method for storage unit communication is provided. The method includes detecting an event associated with a loss of trust for the data stored within a storage unit and encrypting, at the storage unit, data that is being transmitted along an outbound path from the storage unit to a requestor, wherein the encrypting is responsive to detecting the event.

Extended lifetime memory

A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block.

Failure mapping in a storage array

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Dynamic decode circuit with active glitch control

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

System and method for synchronizing memory array signals

A method of generating access signals for a memory array. The method includes receiving a synchronization signal and generating a wordline select signal in response to the synchronization signal. A local precharge signal is generated in response to the synchronization signal. A precharge signal is generated in response to the synchronization signal, the precharge signal being a row signal for regulating memory array read operations. A write signal is generated in response to the synchronization signal, the write signal being a row signal for regulating memory array write operations.

Storage system architecture

A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Electrical conductor terminating apparatus

Integrated system logic and ABIST data compression for an SRAM directory

ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

Mechanism for persisting messages in a storage system

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The plurality of storage nodes configured to initiate an action based on the redundant copies of the metadata, responsive to achieving a level of redundancy for the redundant copies of the metadata. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

Storage system architecture

A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Metal and fluorine values recovery from fluoride salt matrices

The process for converting feed materials of high mineral content containing primary metal values and fluorine values to the primary metal or useful compounds thereof and to fluorine values or useful compounds thereof, wherein the feed materials constitutes a difficultly soluble matrix, the process having the steps of contacting the feed materials in a reactor with a humidified, gaseous system at from about 200 ~C to about 1600 ~C, the contacting being carried out such as to convert the primary metal values to oxide residues at commercially acceptable rates and to evolve gaseous fluoride from the feed, digesting said oxide residues in an acidic digest medium and separating the primary metal values from the resulting digest liquor and from other components of the residues.

Radiant burner

Fabrication system for continuously fabricating graded extended length lumber with maximum grade utilization of input low quality raw lumber

An extended length graded lumber fabrication system features a number of fabrication stages along a substantially continuous fabrication path providing high through put fabrication of graded lumber of extended length from low quality raw lumber. The fabrication stages include reject recognition stages, a supply lumber grading stage, a finger jointing stage and a final grading stage for the extended length lumber. The fabrication system is configured in conjunction with the particularities of low quality raw lumber to minimize grade fluctuations, increase grade bandwidth and minimize raw lumber waste during fabrication of extended length graded lumber, which may be used in wooden truss joists. The use of low quality raw lumber cut from small diameter tree trunks is environmentally beneficial. It contributes to preserve old growth and to use lighter and environmentally less invasive timber harvesting machinery and techniques.

Increasing memory operating frequency

A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates.

Receptacle

Programmable chalcogenide fuse within a semiconductor device

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Sheet metal web stiffener and chord nailing restrictor for wooden i-joist

A chord nailing restricting device features a chord plate combined with a wooden volume structure configured for lateral attachment to the web of a wooden I-joist. The chord plate is positioned on the bottom of the volume structure and features a nail restricting hole having a diameter that corresponds to a predetermined diameter of a chord nail as defined by wooden I-joist manufacturers. The volume structure has a chord nailing access cavity in an surrounding vicinity of the nail restricting hole. Once the device is attached to the web above the bearing rest, the nail restricting hole restricts chord nailing position and nail shaft diameter to manufacturer defined limits. Two devices may be combined by a web front bridge plate for simultaneous attachment of two opposite devices along an I-joist

Multifunction reaction washer and stack accessed by slim reaction socket

Electronically controlled process line

A method and assembly for synchronizing machine operations, the assembly comprising a reference generator for generating a speed reference signal and a position reference signal, a plurality of slave units, each slave unit including, a mechanical device, a separate motor linked to and driving the mechanical device and a separate unit controller for controlling the unit motor, the unit controller receiving and using the reference signals to control motor operation and a synchronizer receiving the reference signals from the control signal source and simultaneously providing the reference signals to each of the slave unit controllers for use in controlling operation of the motors in a synchronized fashion.