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Применить Всего найдено 5. Отображено 4.
15-02-2018 дата публикации

Array substrate manufacturing method and array substrate

Номер: US20180047764A1
Автор: Si Deng
Принадлежит: Wuhan China Star Optoelectronics Technology Co Ltd

The present invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method of the present invention uses an organic photoresist material to form a passivation protection layer ( 90 ) for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer ( 90 ) and a planarization layer ( 70 ) to exposure and development so as to obtain a third via ( 91 ) that is located above the first drain electrode ( 62 ) and a fourth via ( 92 ) that is located above the second drain electrode ( 64 ) and, thus, compared the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate of the present invention has a simple structure and low manufacturing cost and possesses excellent electrical performance.

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Номер записи: 1
08-03-2018 дата публикации

MANUFACTURE METHOD OF LOW TEMPERATURE POLY-SILICON ARRAY SUBSTRATE

Номер: US20180067351A1
Автор: Deng Si, Guo Yuan
Принадлежит:

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property. 1. A manufacture method of a Low Temperature Poly-silicon array substrate , comprising steps of:step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon ...

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Номер записи: 2
20-12-2018 дата публикации

ARRAY SUBSTRATE MANUFACTURING METHOD AND ARRAY SUBSTRATE

Номер: US20180366498A1
Автор: Deng Si
Принадлежит:

An array substrate manufacturing method and an array substrate are provided. The array substrate manufacturing method uses an organic photoresist material to form a passivation protection layer for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer and a planarization layer to exposure and development so as to obtain a third via that is located above the first drain electrode and a fourth via that is located above the second drain electrode and, thus, compared to the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate so manufactured has a simple structure and a low manufacturing cost and possesses excellent electrical performance. 1. An array substrate , comprising a base plate , a light shielding layer located on the base plate , a buffer layer located on the light shielding layer and the base plate , a first poly silicon section and a second poly silicon section located on the buffer layer , a first gate insulation layer and a second gate insulation layer respectively located on middle areas of the first poly silicon section and the second poly silicon section , a first gate electrode and a second gate electrode respectively located on the first gate insulation layer and the second gate insulation layer and in alignment with the first and second gate insulation layers , an interlayer insulation layer located on the first gate electrode , the second gate electrode , the first poly silicon section , the second poly silicon section , and the buffer layer , a first source electrode , a first drain electrode , a second source electrode , and a second drain electrode located on the interlayer insulation layer , a planarization layer located on the first source electrode , the first drain electrode , the second source ...

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Номер записи: 3
27-12-2018 дата публикации

MANUFACTURE METHOD OF LOW TEMPERATURE POLY-SILICON ARRAY SUBSTRATE

Номер: US20180373076A1
Автор: Deng Si, Guo Yuan
Принадлежит:

A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property. 1. A manufacture method of a low temperature poly-silicon array substrate , comprising steps of:step 1, providing a substrate, and defining a negative-channel metal-oxide-semiconductor (NMOS) region and a positive-channel metal-oxide-semiconductor (PMOS) region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;step 3, coating a photoresist layer on the polysilicon layer, wherein after a halftone mask is employed to implement exposure and development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in a middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;employing the first photoresist layer and the second ...

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Номер записи: 4