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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 69. Отображено 69.
20-03-2013 дата публикации

Non-volatile memory devices and systems including multi-level cells methods of operating the same

Номер: CN102982844A
Принадлежит:

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

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11-08-2011 дата публикации

Nonvolatile Memory Devices Having Improved Read Reliability

Номер: US20110194347A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.

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03-05-2016 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009330770B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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18-08-2011 дата публикации

NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20110199833A1
Принадлежит: Samsung Electronics Co., Ltd.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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02-07-2013 дата публикации

Flash memory devices having multi-bit memory cells therein with improved read reliability

Номер: US0008479083B2

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

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30-01-2018 дата публикации

Nonvolatile memory device, operating method thereof and memory system including the same

Номер: US0009881685B2

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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12-05-2020 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0010650903B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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30-05-2017 дата публикации

Nonvolatile memory devices and driving methods thereof

Номер: US0009666283B2

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

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03-05-2016 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009330769B2

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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06-11-2012 дата публикации

Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage

Номер: US0008305817B2

Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.

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23-04-2013 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0008427878B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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28-06-2016 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009378831B2

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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30-12-2014 дата публикации

Nonvolatile memory devices and operating methods thereof

Номер: US0008923060B2

According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines.

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03-06-2014 дата публикации

Nonvolatile memory devices having improved read reliability

Номер: US0008743604B2

Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.

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23-07-2013 дата публикации

Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

Номер: US0008493789B2

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

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13-07-2021 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0011062784B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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11-08-2011 дата публикации

Flash Memory Devices Having Multi-Bit Memory Cells Therein with Improved Read Reliability

Номер: US20110197015A1
Принадлежит:

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

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13-10-2015 дата публикации

Nonvolatile memory device, operating method thereof and memory system including the same

Номер: US0009159443B2

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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31-10-2013 дата публикации

FLASH MEMORY DEVICES HAVING MULTI-BIT MEMORY CELLS THEREIN WITH IMPROVED READ RELIABILITY

Номер: US20130286732A1
Автор: Donghyuk Chae, Jinman Han
Принадлежит:

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation. 1. An integrated circuit memory device , comprising:an array of nonvolatile N-bit memory cells, where N is an integer greater than one; andmeans, electrically coupled to said array, for determining a value of at least one bit of data stored in a selected N-bit memory cell in said array by decoding at least one hard data value and a plurality of soft data values read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.2. The memory device of claim 1 , wherein said determining means comprises:means for reading the hard data value from the selected N-bit memory cell by applying a read reference voltage to the selected N-bit memory cell; andmeans for reading the plurality of soft data values from the selected N-bit memory cell by applying a plurality of read voltages that are less than or greater than the read reference voltage to the selected N-bit memory cell.3. The memory device of claim 1 , wherein said determining means comprises:means for reading the hard data value from the selected N-bit memory cell by applying a read reference voltage to the selected N-bit memory cell;means for reading a first plurality of soft data values from the selected N-bit memory cell by applying a ...

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13-01-2011 дата публикации

NONVOLATILE MEMORY DEVICES AND PROGRAM METHODS THEREOF IN WHICH A TARGET VERIFY OPERATION AND A PRE-PASS VERIFY OPERATION ARE PERFORMED SIMULTANEOUSLY USING A COMMON VERIFY VOLTAGE

Номер: US20110007571A1
Принадлежит: Samsung Electronics Co., Ltd.

Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.

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18-02-2014 дата публикации

Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

Номер: US0008654587B2

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

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29-08-2017 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009747995B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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25-08-2011 дата публикации

INTERCONNECTION STRUCTURE OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Номер: US20110204420A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.

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23-09-2021 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20210295895A1
Принадлежит: Samsung Electronics Co., Ltd.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. A nonvolatile memory device , comprising:substrate;a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substate;a plurality of bit lines;a read and write circuit connected to the columns of the plurality of memory cell groups through the plurality of bit lines respectively; anda plurality of word lines connected to the plurality of memory cells of each memory cell group, respectively;a wordline driver connected to the rows of the plurality of memory cell groups through the plurality of word lines,the word line driver being configured, during a read operation, to apply a select read voltage to a selected word line among the plurality of word lines and to apply unselected read voltages to unselected word lines among the plurality of word lines,the wordline driver being configured, during the read operation, to apply a first unselect read voltage to a first unselected word line among the plurality of word lines and to apply a second unselect read voltage a second unselected word line among the plurality of word lines, 'the second unselected word line being closer to the substrate than the first unselected word line.', 'the second unselect read voltage being lower than the first unselect read voltage, and'}2. The nonvolatile memory device of claim 1 , whereinthe plurality of word lines are divided into wordline groups,each wordline group ...

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18-04-2017 дата публикации

Nonvolatile memory device, operating method thereof and memory system including the same

Номер: US0009627086B2
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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03-03-2015 дата публикации

Nonvolatile memory devices and driving methods thereof

Номер: US0008971114B2

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

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01-03-2012 дата публикации

NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20120051143A1
Принадлежит:

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. 1. A method of operating a non-volatile memory device , the method comprising:performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block; andverifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.2. The method of claim 1 , wherein verifying the erasing operation to the first memory cells and the second memory cells includes recognizing an erasure pass or an erasure fail from respective memory cells.3. The method of claim 1 , further comprising resetting an SSL count and an erase count prior to the erasing operation.4. The method of claim 3 , further comprising counting up the SSL count when verifying the erasing operation to first memory cells associated with the first SSL passes prior to verifying the erasing operation to second memory cells associated with the second SSL.5. The method of claim 3 , further comprising counting up the erase count when verifying the erasing operation to first memory cells associated with the first SSL fails claim 3 , and adjusting an erase voltage to erase the memory block.6. The method of claim 5 , further comprising performing an error report when the erase count reaches a preset value.7. The method of claim 1 , wherein the memory cells of the non-volatile memory device are stacked in a direction perpendicular with respect to a major axis of a substrate where the ...

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28-07-2011 дата публикации

NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME

Номер: US20110182120A1
Принадлежит: Samsung Electronics Co., Ltd.

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

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23-12-2014 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0008917558B2

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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30-04-2013 дата публикации

Interconnection structure of three-dimensional semiconductor device

Номер: US0008431969B2

A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.

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01-08-2023 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0011715537B2
Принадлежит: Samsung Electronics Co., Ltd.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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26-02-2019 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0010217516B2

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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15-10-2013 дата публикации

Nonvolatile memory device, operating method thereof and memory system including the same

Номер: US0008559235B2

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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29-12-2015 дата публикации

Flash memory devices having multi-bit memory cells therein with improved read reliability

Номер: US0009224489B2

Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

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01-01-2009 дата публикации

NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME

Номер: US20090003057A1
Принадлежит: Samsung Electronics Co., Ltd.

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

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24-02-2015 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0008964476B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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11-08-2011 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20110194357A1
Принадлежит: Samsung Electronics Co., Ltd.

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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11-02-2016 дата публикации

NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF

Номер: US20160042792A1
Принадлежит:

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. 1. A nonvolatile memory device , comprising:a memory cell array including a plurality of cell strings arranged in a first direction and a second direction, the plurality of cell strings being divided into a plurality of groups including a first group and a second group, each of the plurality of cell strings including a selection transistor and a plurality of nonvolatile memory cells connected in series and stacked on or above a substrate in a third direction that is perpendicular to both the first direction and the second direction and perpendicular to the substrate;a word line extending in the first direction, and connected to each of the plurality of cell strings;a selection line extending in the first direction and connected to the selection transistor of each cell string of the first group;a first pass transistor connected to one end of the word line;a second pass transistor connected to one end of the selection line;a third pass transistor connected to the other end of the selection line; anda decoder configured to drive the word line with a word line voltage via only one end of the word line, and to drive the selection line with a selection line voltage via both the one end and the other end of the selection line,wherein the word line voltage is driven through the first pass transistor, andthe selection line voltage is driven through the second pass transistor and the third pass transistor.2. The nonvolatile memory device of claim 1 , wherein the first pass transistor and the second pass transistor are placed at a first side of the memory cell array claim 1 , andthe third pass transistor is placed at a second side of the memory cell array opposite to the first side of the memory cell array.3. ...

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12-07-2016 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009390803B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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24-05-2016 дата публикации

Nonvolatile memory devices and driving methods thereof

Номер: US0009349455B2

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

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14-08-2012 дата публикации

Non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same

Номер: US0008243514B2

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

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05-06-2018 дата публикации

Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

Номер: US000RE46887E1
Принадлежит: Samsung Electronics Co., Ltd.

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

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05-02-2019 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US0010199116B2

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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28-06-2016 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US0009378833B2

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

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16-02-2012 дата публикации

Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same

Номер: US20120039130A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

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03-05-2011 дата публикации

Non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same

Номер: US0007936601B2

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

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13-12-2012 дата публикации

NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ RELIABILITY

Номер: US20120314496A1
Автор: CHAE Donghyuk
Принадлежит:

Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages. 1. A method of programming multi-bit data in a nonvolatile memory cell array , the method comprising:gathering full page data to be stored in selected memory cells in a row of the nonvolatile memory cell array;converting the full page data into converted data having different binary values relative to the full page data; andstoring the full page data in the selected memory cells using the converted data by performing at least two or more program sequences.2. The method of claim 1 , wherein the full page data stored in the selected memory cells is read according to a reading operation with a uniform read latency.3. The method of claim 1 , wherein the full page data has a first state ordering of bit patterns claim 1 , and the converted data has a second state ordering of bit patterns.4. The method of claim 3 , wherein the full page data is stored in the selected memory cells using the converted data having the second state ordering of bit patterns by performing three program sequences.5. The method of claim 4 , further comprising:reading the full page data stored in the selected memory cells ...

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02-05-2013 дата публикации

NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF

Номер: US20130107629A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines. 1. A nonvolatile memory device , comprising:a memory cell array including a plurality of memory cells;a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells respectively and to supply voltages to the plurality of word lines; anda read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells respectively,the read/write circuit being configured to adjust levels of the bias voltages applied to the plurality of bit lines according to a location of a selected word line among the plurality of word lines.2. The nonvolatile memory device of claim 1 , whereinthe plurality of word lines and the plurality of memory cells are stacked on a substrate in a direction perpendicular to the substrate, andthe read/write circuit is configured to adjust the levels of the bias voltages applied to the plurality of bit lines according to a distance between the selected word line and the substrate.3. The nonvolatile memory device of claim 2 , wherein the read/write circuit is configured to sequentially decrease the levels of the bias voltages applied to the plurality of bit lines during a program operation according to an increase in a distance between the selected ...

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19-09-2013 дата публикации

NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20130242667A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. A nonvolatile memory device comprising:a substrate;a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substrate;a plurality of bit lines;a read and write circuit connected to the columns of the plurality of memory cell groups through the plurality of bit lines respectively;a plurality of word lines connected to the plurality of memory cells of each memory cell group, respectively;a wordline driver connected to the rows of the plurality of memory cell groups through the plurality of word lines,the wordline driver being configured, during a program operation, to apply a program voltage to a selected word line among the plurality of word lines and to apply pass voltages to unselected word lines among the plurality of word lines, the second program voltage being lower the first program voltage, and', 'the second word line being closer to the substrate than the first word line,, 'the wordline driver being configured, during the program operation, to apply a first program voltage to a first word line among the plurality of word lines if the first word line is selected and to apply a second program voltage to a second word line among the plurality of word lines if the second word line is selected,'} the second pass voltage being lower than the first pass voltage,', 'the second unselected word line being closer to the substrate than the first ...

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24-10-2013 дата публикации

NONVOLATILE MEMORY DEVICES, CHANNEL BOOSTING METHODS THEREOF, PROGRAMMING METHODS THEREOF, AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20130279262A1
Принадлежит:

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings. 17.-. (canceled)8. A program method of a non-volatile memory device which includes groups of memory cells sequentially provided in a direction vertical to a substrate and in which at least two strings are connected to one bit line , the program method comprising:performing a bit line setup operation together with a channel boosting operation; andperforming a program execution operation by applying a program voltage to a selected word line.9. The program method of claim 8 , wherein the performing a bit line setup operation includes claim 8 , during a first bit line setup period claim 8 ,applying a power supply voltage to unselected bit lines,floating all strings of a selected memory block, andapplying a pass voltage to the selected word line and unselected word lines.10. The program method of claim 9 , wherein the floating of the strings of the selected memory block includes applying a ground voltage to a ground selection line and to all string selection lines.11. The program method of claim 10 , wherein the performing a bit line setup operation includes claim 10 , during a second bit line setup period claim 10 ,setting a channel of a selected string to a ground voltage by applying a power supply voltage to a selected string selection line of the string selection lines.12. The program method of claim 11 , wherein the performing a program execution operation includes applying the program voltage to the selected word line following the second bit line setup period.13. The program method of claim 8 , wherein the performing a bit line setup operation includes claim 8 , during a first bit line setup period ...

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03-04-2014 дата публикации

NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20140092685A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. 1. (canceled)2. A method of operating a non-volatile memory device including a plurality of cell strings connected to a bit line , each cell string having at least one ground selection transistor , a plurality of memory cells and at least one string selection transistor stacked sequentially from a substrate in a direction perpendicular to the substrate , ground selection transistors of the plurality of cell strings being connected to a ground selection line in common , string selection transistors of the plurality of cell strings being connected to a plurality of string selection lines respectively , and memory cells having the same height from the substrate being connected to a word line in common , the method comprising:performing an erasing operation to memory cells of the plurality of cell strings;verifying first memory cells associated with a first string selection line of the plurality of string selection lines; andverifying second memory cells associated with a second string selection line of the plurality of string selection lines subsequent to verifying the first memory cells.3. The method of claim 2 , wherein verifying the first memory cells and the second memory cells includes recognizing an erasure pass or an erasure fail from respective memory cells.4. The method of claim 2 , further comprising resetting an SSL count and an erase count prior to performing the erasing operation.5. The method of claim 4 , further comprising counting up the SSL count when verifying the first memory cells passes.6. The method of claim 4 , further ...

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24-03-2022 дата публикации

NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20220093195A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. An apparatus , comprising:a plurality of memory cells arranged in NAND strings in a memory block, the NAND strings including a blocking insulation layer, and a thickness of a first part of the blocking insulation layer being different from a thickness of a second part of the blocking insulation; anda controller configured to determine a first program voltage which is applied to memory cells in a first portion of the memory block, during programming of a selected memory cell in the first portion of the memory block, and configured to determine an initial program voltage for programming of memory cells in a second portion of the memory block based on the first program voltage and a location of the memory cells of the second portion of the memory block.2. The apparatus of claim 1 , wherein the controller is configured to determine the first program voltage claim 1 , which is applied to the memory cells in the first portion of the memory block claim 1 , during programming of the selected memory cell in the first portion of the memory block claim 1 , when threshold voltages of the memory cells in the first portion of the memory block exceed a reference voltage.3. The apparatus of claim 1 , wherein the memory cells in first portion of the memory block are in NAND strings that are a first distance from an edge of the block claim 1 , andthe memory cells of the second portion of the memory block are in NAND strings that are a second distance, which is different from the first ...

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28-03-2019 дата публикации

NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20190096495A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. (canceled)2. A method of programming a nonvolatile memory device including a plurality of memory cells stacked on a substrate in a direction vertical to the substrate , each of the plurality of memory cells coupled to corresponding word line among a plurality of word lines stacked along the plurality of memory cells , and the plurality of memory cells being divided into a first portion and a second portion , the second portion being stacked over the first portion , the method comprising:applying a first program voltage on a first word line located in the first portion;applying a first pass voltage on a third word line located in the first portion while applying the first program voltage on the first word line;applying a second program voltage on a second word line located in the first portion; andapplying a second pass voltage on the third word line located in the first portion while applying the second program voltage on the first word line,wherein the second word line being located farther from the substrate than the first word line and adjacent to the first word line, the third word line being located farther from the substrate than the second word line and adjacent to the second word line, and the level of the second pass voltage is higher than the level of the first pass voltage.3. The method of claim 2 , wherein the method further comprising:applying a third pass voltage on a fourth word line while applying the first and second program voltages on the first and ...

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30-04-2015 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US20150117118A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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28-04-2016 дата публикации

NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20160118133A1
Принадлежит:

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. 1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings , the plurality of memory cell strings including first memory cell strings and second memory cell strings , the method comprising:performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate;performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; andperforming a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells,wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, andone of the first memory cell strings and one of the second memory cell strings are connected to a bit-line.2. The method of claim 1 , further including performing a second erasure operation to the first memory cells and the second memory cells.3. The method of claim 2 , further including determining whether the second erasure verification operation is to be performed to the second memory cells ...

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21-05-2015 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20150138882A1
Автор: CHAE Donghyuk, Han Jinman
Принадлежит:

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. 120.-. (canceled)21. An operating method of a nonvolatile memory device including at least first through fourth strings on a substrate , each string including a plurality of memory cells and at least one select transistor sequentially stacked on the substrate in a direction perpendicular to the substrate , the operating method comprising:erasing first memory cells of a first portion of the first through fourth strings and preventing erasures of second memory cells of a second portion of the first through fourth strings,select transistors of the first and second strings being connected to a first select line, select transistors of the third and fourth strings being connected to a second select line, select transistors of the first and third strings being connected to a first bit line, and select transistors of the second and fourth strings being connected to a second bit line.22. The operating method of claim 21 , whereinthe first portion includes strings among the first through fourth strings that are connected to one of the first and second select lines, andthe second portion includes strings among the first through fourth strings that are connected to an other of the first and second select lines.23. The operating method of claim 21 , wherein the erasing includes:supplying a high voltage to first channels of the first memory cells of the first portion;preventing the high voltage from being supplied to second channels of the second memory cells of the second portion; andapplying a low voltage to word lines connected to the first and second memory cells of the first and second portions. ...

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21-05-2015 дата публикации

NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF

Номер: US20150138890A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. 1. A nonvolatile memory device , comprising:a memory cell array including a plurality of cell strings formed in a direction perpendicular to a substrate layer, each of the plurality of cell strings is connected between the substrate layer and a corresponding bit line, at least one string selection transistor connected to a string selection line;', 'a plurality of cell transistors, each of cell transistors is connected in common with a word line of a corresponding layer; and', 'at least one ground selection transistor connected to a ground selection line for connecting the plurality of cell transistors to the substrate layer;, 'wherein each of the plurality of cell strings comprisesa decoder configured to drive at least one of the string selection line and the ground selection line in at least two directions.2. The nonvolatile memory device of claim 1 , wherein the decoder comprises:a first gating circuit configured to provide at least one of a string selection signal to the string selection line, a ground selection signal to the ground selection line, and word line voltages to the plurality of word lines associated with the plurality of cell transistors on a first side of the memory cell array, anda second gating circuit configured to provide at least one of the string selection signal to the string selection line, the ground selection signal to the ground selection line on a second side of the memory cell array.3. The nonvolatile memory device of claim 2 , wherein the first gating circuit and the second gating circuit are configured to provide the string selection signal to the string selection line on the first side and the second side of the memory cell array concurrently.4. The nonvolatile memory ...

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06-07-2017 дата публикации

NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20170194058A1
Принадлежит:

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. 1. A method of erasing a three dimensional (3D) nonvolatile memory device which includes a first memory cell strings and a second memory cell strings , the first memory cell strings and the second memory cell strings including first memory cells and second memory cells respectively , each of the first and the second memory cells being connected in series and stacked in a direction substantially perpendicular to a substrate , the first memory cell strings being connected to a first string selection line and the second memory cell strings being connected to a second string selection line , at least one of the first memory cells and at least one of the second memory cells being connected to a word line and one of the first memory cell strings and one of the second memory cell strings being connected to a bit-line , the method comprising:performing a first erasure operation to first memory cells and the second memory cells by applying a first word line erasure voltage on the word line and applying a first erasure voltage to the substrate;performing a first erasure verification operation to the first memory cells after the performing the first erasure operation by applying a first erasure verification voltage on the word line;determining whether the first erasure verification passed or failed after the first erasure verification operation; andif the first erasure verification is determined to be passed, performing a second erasure verification operation to the second memory cells by applying a second erasure verification voltage on the word line, ...

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01-09-2016 дата публикации

NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF

Номер: US20160254054A1
Принадлежит:

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. 1. A nonvolatile memory device , comprising:a plurality of cell strings formed in a direction perpendicular to a substrate layer, each of the plurality of cell strings is connected between the substrate layer and a corresponding bit line, each of the plurality of cell strings includes a plurality of cell transistors connected serially to each other;a first gate line connected to at least one cell transistor of a first layer;a second gate line connected to at least one cell transistor of a second layer;a first and second pass transistors connected to both end side of the first gate line to transmit a first driving signal; anda third pass transistor connected to one end side of the second gate line to transmit a second driving signal,wherein the first layer is the uppermost layer of the plurality of cell strings, and the second layer is one of a plurality of layers formed below the first layer.2. The nonvolatile memory device of claim 1 , wherein the first pass transistor claim 1 , the second pass transistor claim 1 , and the third pass transistor are turned on in response to a block selection signal.3. The nonvolatile memory device of claim 1 , wherein a radius of a first cell transistor connected to the first gate line is larger than a radius of a second cell transistor connected to the second gate line claim 1 ,wherein the first cell transistor and the second cell transistor are included in same cell string.4. The nonvolatile memory device of claim 1 , wherein the at least one cell transistor of the first layer is string selection transistor of corresponding cell string.5. The nonvolatile memory device of claim 4 , wherein the first gate line is a string selection line of the plurality of cell ...

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23-07-2020 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US20200234782A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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29-09-2016 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20160284416A1
Автор: CHAE Donghyuk, Han Jinman
Принадлежит:

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. 1. (canceled)2. An operating method of a nonvolatile memory device comprising a plurality of memory blocks , each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines , each cell string comprising a string selection transistor connected to a string selection line and a plurality of memory cells connected to the plurality of word lines respectively , the method comprising:erasing first memory cells of first cell strings connected to at least one first string selection line and preventing an erasure of second memory cells of second cell strings connected to at least one second string selection line in a selected memory block,wherein, in the plurality of cell strings of each memory block, memory cells having a same order from string selection transistors are connected to a common word line among the plurality of word lines.3. The operating method of claim 2 , wherein each cell string further comprises a ground selection transistor connected to a ground selection line.4. The operating method of claim 3 , wherein erasing the first memory cells comprises:applying an erase voltage to the substrate;applying word line erase voltages to the plurality of word lines; andfloating the at least one first string selection line and at least one first ground selection line connected to the first cell strings.5. The operating method of claim 4 , wherein preventing the erasure of the second memory cells comprises:applying an erasure prohibition ...

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29-09-2016 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20160284419A1
Принадлежит:

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. (canceled)2. A method of programming a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string , the first memory cell string including a plurality of serially-connected nonvolatile memory cells , the method comprising:programming each of the plurality of serially-connected nonvolatile memory cells by an incremental step pulse program (ISPP) method that uses a program voltage including an initial program voltage and an increment, a level of the program voltage increasing by the increment from a level of the initial program voltage; andverifying each of the plurality of serially-connected nonvolatile memory cells,wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate, andthe level of the initial program voltage of the program voltage that is applied to a corresponding one of the plurality of serially-connected nonvolatile memory cells is related with a distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate.3. The method of claim 2 , wherein the level of the initial program voltage of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cells is higher as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes ...

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22-10-2015 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20150302927A1
Автор: CHAE Donghyuk, Han Jinman
Принадлежит:

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. 1. (canceled)2. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string , the first memory cell string including a first string selection transistor connected to a bit-line , a first ground selection transistor and a first plurality of nonvolatile memory cells , the first plurality of memory cells being connected in series between the first string selection transistor and the first ground selection transistor , the plurality of memory cell strings being connected to a common source line , the method comprising:applying to a substrate an erase voltage that has a first level;applying a first voltage to a first ground selection line connected to the first ground selection transistor that is included in the first memory cell string and is connected to the first plurality of memory cells, the first ground selection transistor being formed on the substrate, the first plurality of memory cells being stacked on or above the substrate at a direction that is substantially vertical to the substrate;increasing the erase voltage from the first level to a second level higher than the first level during the applying the first voltage to the first ground selection line;floating the first ground selection line after a level of the erase voltage reaches to the second level; andincreasing the erase voltage from the second level to a third level higher than the second level during the floating the first ground selection line,wherein the first memory cell string includes a first dummy cell disposed between the first ground ...

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16-11-2017 дата публикации

NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20170330632A1
Принадлежит:

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. 1. (canceled)2. A method of operating a nonvolatile memory device including a plurality of memory cell strings , each of the plurality of memory cell strings including a plurality of memory cells stacked on a substrate in a direction vertical to the substrate , the plurality of memory cells being divided into a first portion and a second portion , the second portion being stacked over the first portion , the method comprising:programming a first selected memory cell located in the first portion by applying a first initial program voltage on the first selected memory cell, the level of the first initial program voltage being higher as the distance between the first selected memory cell and the substrate being longer;verifying the first selected memory cell to determine programming pass or programming fail;programming a second selected memory cell located in the second portion by applying a second initial program voltage on the second selected memory cell, the level of the second initial program voltage being higher as the distance between the second selected memory cell and the substrate being longer; andverifying the second selected memory cell to determine programming pass or programming fail;wherein, the level of the first initial program voltage applied to the first selected memory cell located at top of the first portion is higher than the level of the second initial program voltage applied to the second selected memory cell located at bottom of the second portion.3. ...

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03-12-2015 дата публикации

NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20150348637A1
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Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. 1. A methodof erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a first string selection transistor connected to a bit-line, a first ground selection transistor and a first plurality of memory cells, the first plurality of memory cells being connected in series between the first string selection transistor and the first ground selection transistor, the plurality of memory cell strings being connected to a common source line, the method comprising:applying to a substrate an erase voltage that has a first level;applying a first voltage to a first ground selection line connected to the first ground selection transistor that is included in the first memory cell string and is connected to the first plurality of memory cells, the first ground selection transistor being formed on the substrate, the first plurality of memory cells being stacked on or above the substrate at a direction that is substantially vertical to the substrate;increasing the erase voltage from the first level to a second level higher than the first level during the applying the first voltage to the first ground selection line;floating the first ground selection line after a level of the erase voltage reaches to the second level;increasing the erase voltage from the second level to a third level higher than the second level during the floating the first ground selection line; andapplying a plurality of word-line voltages to a plurality of word-lines connected to the first plurality of memory cells while the erase ...

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31-12-2015 дата публикации

Non-volatile memory devices, operating methods thereof and memory systems including the same

Номер: US20150380093A1
Принадлежит: Individual

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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01-09-2011 дата публикации

3次元半導体装置の配線構造体

Номер: JP2011171735A
Принадлежит: SAMSUNG ELECTRONICS CO LTD

【課題】集積度及び信頼性を共に向上させた3次元半導体装置を提供する。 【解決手段】3次元半導体装置の配線構造が提供される。3次元半導体装置は3次元基板上に2次元的に配列された積層構造体、第1配線を含み、積層構造体の上部に配置される第1配線層及び第2配線を含み、第1配線層の上部に配置される第2配線層を含み、積層構造体各々は順次に積層された複数の下部ワードラインを含む下部構造体及び順次に積層された複数の上部ワードラインを含み、下部構造体の上部に配置される上部構造体を含み、第1配線各々は下部ワードラインの内の何れか1つに連結し、第2配線各々は上部ワードラインの内の何れか1つに連結する。 【選択図】 図10

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24-08-2023 дата публикации

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Номер: US20230268017A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

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17-04-2018 дата публикации

Nonvolatile memory device, operating method thereof and memory system including the same

Номер: US09947416B2
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

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