Non-linear control for voltage regulator

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

LOW POWER ANALOG TO DIGITAL CONVERTER

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Low power analog to digital converter

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Apparatus and method to reduce power losses in an integrated voltage regulator

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

LOW POWER ANALOG TO DIGITAL CONVERTER

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAGE REGULATOR

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR. 1. An apparatus comprising:a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; anda second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.2. The apparatus of comprises:a first current sensor to sense current of the first power domain; anda second current sensor to sense current of the second power domain.3. The apparatus of comprises a controller to calculate powers of the first and second domains claim 2 , respectively claim 2 , and total power of a chip having the first and second VRs.4. The apparatus of claim 3 , wherein the controller is to adjust the non-zero phase angle offset according to the powers of the first and second domains claim 3 , respectively claim 3 , and the total power.5. The apparatus of claim 3 , wherein the controller is to adjust the non-zero phase angle offset according to the powers of the first and second domains claim 3 , respectively claim 3 , and the total power at runtime during operation of a chip having the first and second power domains.6. The apparatus of claim 1 , wherein the first one or more inductors are at least ...

Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

LOW POWER ANALOG TO DIGITAL CONVERTER

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. 1. An apparatus comprising:a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; andone or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.2. The apparatus of further comprises:another sigma-delta modulator to receive the analog signal, the other sigma-delta modulator operable to perform chopping to cancel common-mode noise, the other sigma-delta modulator and the sigma-delta modulator for generating a pseudo-differential signal corresponding to the analog signal.3. The apparatus of claim 1 , wherein the sigma-delta modulator is operable to perform chopping by switching between at least two clock signal phases for at least two switches of the sigma-delta modulator.4. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an integrator including a cascode inverter amplifier.5. The apparatus of claim 4 , wherein the sigma-delta modulator is operable to perform auto-zeroing operation to cancel DC offset of the cascode inverter amplifier.6. The apparatus of claim 1 , wherein the sigma-delta modulator comprises a switch including:at least two p-type transistors coupled together in series and controllable by a common signal, the at least two p-type transistors having their bulk terminals coupled to a common terminal of the at least two p-type transistors; andat least two n-type transistors coupled together in series and controllable by an inverse of the common signal, the at least two n-type transistors having their bulk terminals coupled to a non-ground common terminal of the at least ...

APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAGE REGULATOR

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR. 1. (canceled)2. An apparatus comprising:a first one or more inductors which are associated with a first power domain; anda second one or more inductors, wherein at least one of the inductors of the first one or more inductors is inductively coupled to at least one of the inductors of the second one or more inductors, and wherein the second one or more inductors are associated with a second power domain separate from the first power domain.3. The apparatus of comprises a first voltage generator coupled to the first one or more inductors.4. The apparatus of comprises a second voltage generator coupled to the second one or more inductors.5. The apparatus of claim 4 , wherein the first voltage generator has a first clock claim 4 , wherein the second voltage generator has a second clock claim 4 , and wherein the first clock has a phase offset from a phase of the second clock.6. The apparatus of claim 4 , wherein the first voltage generator has a first switching frequency claim 4 , wherein the second voltage generator has a second switching frequency claim 4 , and wherein the first switching frequency is different from second switching frequency.7. The apparatus of claim 2 , wherein the first and second power domains are independent power domains.8. The apparatus of claim 2 , wherein the first and second one or more inductors are at least one of:air core inductors (ACIs); ormagnetic core inductors (MCIs).9. An apparatus comprising:a system ...

Voltage regulator circuitry including module for switching frequency self-optimization

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

NON-LINEAR CONTROL FOR VOLTAGE REGULATOR

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load. 1. An apparatus comprising:a first inductor for coupling to a load;a capacitor, coupled to the first inductor, and for coupling to the load;a first high-side switch coupled to the first inductor;a first low-side switch coupled to the first inductor;a bridge controller to control when to turn on and off the first high-side and first low-side switches; anda non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.2. The apparatus of further comprises a logic unit operable to override output of a comparator to control the bridge controller.3. The apparatus of further comprises:a second inductor or resistor, coupled to the capacitor, and for coupling to the load;a second high-side switch coupled to the second inductor or resistor; anda clamp controller to control when to turn on and off the second high-side switch.4. The apparatus of further comprises:a second low-side switch coupled to the second inductor.5. The apparatus of claim 3 , wherein the second inductor claim 3 , second high-side switch claim 3 , second low-side switch claim 3 , and clamp controller are smaller in size than the first inductor claim 3 ...

Spread-spectrum apparatus for voltage regulator

Described is an apparatus for providing spread-spectrum to a clock signal. The apparatus comprises: an oscillator to generate an output clock signal, the oscillator to receive an adjustable reference signal to adjust frequency of the output clock signal; a first circuit to provide a first signal indicative of a center frequency of the output clock signal; a second circuit to generate a switching waveform to provide spread-spectrum for the output clock signal; and a third circuit, coupled to the first and second circuits, to provide the adjustable reference signal according to the first signal and the switching waveform.

Method and apparatus to control temperature of a semiconductor die in a computer system

Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.

Single crystal turbine blade lifing process and system

A system and methods for lifing a single crystal turbine blade of a gas turbine engine is disclosed. The system and methods determine the anisotropic strain of the single crystal turbine blade caused by fatigue and creep by resolving the shear stresses on each of the primary slip systems of the single crystal turbine blade. The system and methods use a ductility exhaustion method to combine the anisotropic fatigue and creep strains to determine the operating life of the single crystal turbine blade.

Nichtlineare steuerung für einen spannungsregler

Beschrieben ist eine Vorrichtung, die eine nichtlineare Steuerung zum Management des Leistungsversorgungsabfalls an einem Ausgang eines Spannungsreglers aufweist. Die Vorrichtung umfasst: eine erste Induktivität zum Koppeln mit einer Last; einen mit der ersten Induktivität gekoppelten Kondensator und zum Koppeln mit der Last; einen ersten mit der ersten Induktivität gekoppelten High-Side-Schalter; einen ersten mit der ersten Induktivität gekoppelten Low-Side-Schalter; eine Brückensteuerung zum Steuern, wann der erste High-Side-Schalter und der erste Low-Side-Schalter ein- und auszuschalten sind; und eine nicht lineare Steuerungseinheit (NLC) zum Überwachen der Ausgangsspannung an der Last und zum Veranlassen, dass die Brückensteuerung den ersten High-Side-Schalter einschaltet und den ersten Low-Side-Schalter ausschaltet, wenn ein Spannungsabfall an der Last detektiert wird.

Method and apparatus for multi-thread pipelined instruction decoder

A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining at the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.

Strom-Digital-Analog-Wandler

Strom-Digital-Analog-Wandler, DAC (1900), der Folgendes aufweist: eine Vielzahl von n-Bauelementen, deren Gate-Anschlüsse mit einer ersten Vorspannung gekoppelt sind, wobei der Source-Anschluss jedes der n-Bauelemente mit Masse gekoppelt ist; eine erste Vielzahl von Schaltern, die so betreibbar sind, dass sie die Drain-Anschlüsse einiger oder aller n-Typ-Vorrichtungen miteinander koppeln, um einen ersten Ausgangsstrom zu erzeugen, dessen Größe von der Anzahl der elektrisch miteinander gekoppelten n-Typ-Vorrichtungen abhängt, eine Mehrzahl von Transistor-Vorrichtungen, deren Gate-Anschlüsse mit einer zweiten Vorspannung gekoppelt sind; und eine zweite Vielzahl von Schaltern, die so betreibbar sind, dass sie die Drain-Anschlüsse einiger oder aller Transistor-Vorrichtungen miteinander koppeln, um einen zweiten Ausgangsstrom zu erzeugen, dessen Größe von der Anzahl der elektrisch miteinander gekoppelten Transistor-Vorrichtungenabhängt.

Device, method and system to mitigate a voltage overshoot event

Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

Vorrichtung, Verfahren und System zum Abschwächen eines Spannungsüberschreitungsereignisses

Techniken und Mechanismen zum Abschwächen einer Überschreitung einer Versorgungsspannung, die mit einem Spannungsregler (Voltage Regulator; VR) bereitgestellt wird. In einer Ausführungsform wird Abwärtswandlerfunktionalität eines VR mit erster Schaltungsanordnung bereitgestellt, die einen ersten Induktor und erste Schalterstromkreise umfasst, die unterschiedlich damit gekoppelt sind. Zweite Schaltungsanordnung des VR umfasst einen zweiten Induktor und zweite Schalterstromkreise, die unterschiedlich damit gekoppelt sind. In Reaktion auf eine Angabe eines Spannungsüberschreitungszustands sind jeweilige Zustände der ersten Schalterstromkreise und der zweiten Schalterstromkreise dafür ausgelegt, eine Leiterbahn zum Ableiten von Energie mit dem ersten Induktor, dem zweiten Induktor und unterschiedlichen einen der ersten Schalterstromkreise und der zweiten Schalterstromkreise zu aktivieren. In einer anderen Ausführungsform umfasst Abschwächen des Spannungsüberschreitungszustands alternierendes Hin- und Herschalten zwischen zwei unterschiedlichen Konfigurationen der zweiten Schalterstromkreise.

Device, method and system to mitigate a voltage overshoot event

Method and apparatus for multi-thread pipelined instruction decoder

A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining at the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.

Verfahren und vorrichtung zum steuern der temperatur eines halbleiterchips in einem computersystem

Schaltung zum Aufbringen von Wärme auf einen Chip, während die Chip-Übergangstemperatur unter einer minimalen Chip-Übergangstemperatur eines Betriebstemperaturbereichs für den Chip liegt wird gestellt. Die Schaltung, um einen Systemstartfehler zu vermeiden, wenn die Chip-Sperrschichttemperatur unter dem Betriebs-Die-Sperrschichttemperaturbereich des Chips liegt.

Verfahren und Einrichtung für einen pipeline-verschachtelten Multi-Thread-Befehlsdecodierer

Pipelined instruction decoder for multi-threaded processors

A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline. The pipeline controller may invalidate an entire thread of instructions, squeeze out invalid instructions, and/or conserve power by selectively stopping the clocking of pipestages.

Method and apparatus for multi-thread pipelined instruction decoder

多線程流水線指令解碼器裝置及方法

Method and apparatus for multi-thread pipelined instruction decoder

Method and apparatus for multi-thread pipelined instruction decoder

Event signature apparatus, systems, and methods

Stromausgleich, Stromsensor und Phasen-Ausgleich-Vorrichtung und Verfahren für einen Spannungsregulator

Beschrieben sind Vorrichtungen und Verfahren zum Stromausgleich, Stromabtastung und Phasenausgleich, Versatzeliminierung, Digital-zu-Analog-Stromwandlung mit monotoner Ausgabe unter Nutzung von binärkodierten Eingaben (ohne einen Binär-zu-Thermometer-Decoder), Kompensator für einen Spannungsregulator (VR), etc. In einem Beispiel umfasst die Vorrichtung: mehrere Induktivitäten, die an einen Kondensator und eine Last koppeln, mehrere Brücken, wovon jede gekoppelt ist an eine entsprechende Induktivität von den mehreren Induktivitäten; und mehrere Stromsensoren, wovon jeder gekoppelt ist an eine Brücke zum Abtasten eines Stromes durch einen Transistor der Brücke.

Event signature apparatus, systems, and methods

Power indication circuit for a processor

According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.