CONTROLLABLE ELECTRONIC CIRCUIT

ELECTRONIC CIRCUIT WITH A SECRET ONE SUBMODUL

IC TEST PROCEDURE AND DEVICES

IC-TESTVERFAHREN UND VORRICHTUNGEN

METHOD FOR TESTING A TESTABLE ELECTRONIC DEVICE

A method for testing a testable electronic device having a first and a second plurality of test arrangements, e.g. scan chains, is disclosed. A first shift register (110) is used in parallel with a second shift register (130) to time-multiplex a first test vector (102) and a second test vector (104) into a number of smaller test vectors (102a-c; 104a-c) for provision to the first and second plurality of test arrangements. By varying the size of the first shift register (110) and the second shift register (130) a trade-off between the number of pins of the electronic device to be contacted and the required test time can be made. Preferably, first shift register (110) is coupled to a first buffer register (120) and second shift register (130) is coupled to a second buffer register (140) for enhanced test data stability. First shift register (110) and second shift register (130) can be partitions of a larger shift register, e.g. a boundary scan chain. The method can also be used in a reverse ...

Testable electronic circuit, test method and tester

An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). Thetest ...

PRÜFBARE ELEKTRONISCHE SCHALTUNG

Testable Electronic Circuit

An electronic circuit contains groups of flip-flops ( 12 a-c), coupled to data terminals ( 11 a-c) of the circuit and to a functional circuit ( 10 ). Each group ( 12 a-c) has a clock input for clocking the flip-flops of the group. Each group ( 12 a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit ( 10 ) and/or receive signals from the functional circuit ( 10 ) respectively. A test control circuit ( 16 ) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit ( 16 ) is coupled to the groups of flip-flops ( 12 a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit ( 15 a-c, 18 ) has inputs coupled to the data terminals ( 11 a-c) and outputs coupled to clock inputs of ...

Method of manufacturing a system in package

A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package 10 can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

ELEKTRONISCHE SCHALTUNG MIT EINEM GEHEIMEN SUBMODUL

METHOD OF MANUFACTURING A SYSTEM IN PACKAGE

A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has bee mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

ELECTRONIC CIRCUIT COMPRISING A SECRET SUB-MODULE

The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including:- a secret sub-module (4) for performing a function, and comprising scan chains,- a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit. © KIPO & WIPO 2007 ...

IC testing methods and apparatus

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated ...

Testable electronic circuit

An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test ...

Electronic circuit comprising a secret sub-module

The invention relates to an electronic circuit including a sub-module assembly ( 2 ) connected to the rest of the circuit, the sub-module assembly including:-a secret sub-module ( 4 ) for performing a function, and comprising scan chains,-a built-in self test circuit including a pattern generator ( 5 ) to apply input signals to the scan chains, and a signature register ( 6 ) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

IC testing methods and apparatus

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated ...

Method of manufacturing a system in package

A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Electronic circuit comprising a secret sub-module

Electronic circuit comprising a secret sub-module

The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

IC testing methods and apparatus

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated ...

Method of manufacturing a system in package

Testable electronic circuit

Low pin count, high-speed boundary scan testing

In a method for testing a testable electronic device having a first and a second plurality of test a arrangements a first shift register ( 110 ) is used in parallel with a second shift register ( 130 ) to time-multiplex a first test vector ( 102 ) and a second test vector ( 104 ) into a number of smaller test vectors ( 102 a–c; 104 a–c ) for provision to the first and second plurality of test arrangements. By varying the size of the first shift register ( 110 ) and the second shift register ( 130 ) a trade-off between the number of pins of the electronic device to be contacted and the required test time can be made. The first shift register ( 110 ) may be coupled to a first buffer register ( 120 ) and second shift register ( 130 ) may be coupled to a second buffer register ( 140 ) for enhanced test data stability. First shift register ( 110 ) and second shift register ( 130 ) can be partitions of a larger shift register. The method can also be used in a reverse way by time-demultiplexing test result vectors into a single vector at the output side of the testable electronic device.

METHOD FOR TREATING HUMAN IMMUNODEFICIENCY VIRUS INFECTION

La présente invention est relative à une composition comprenant plusieurs peptides comprenant des épitopes proviraux et son utilisation pour le traitement d'une infection par le virus de l'immunodéficience humaine. The present invention relates to a composition comprising several peptides comprising proviral epitopes and its use for the treatment of an infection with the human immunodeficiency virus.

Ic Testing Methods and Apparatus

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit ( 44 ) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock ( 40 ) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated by on-chip PLLs and divider circuits for the test mode.

Method of manufacturing a system in package

A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Testable electronic circuit

An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (l la-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.

SYSTEM AND METHOD FOR DETECTING AN ALARM FOLLOWING DETECTION OF THE USE OF A METAL DETECTOR

Ic testing methods and apparatus

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated by on-chip PLLs and divider circuits for the test mode.

System for triggering alarm following detection of use of metal detector for monitoring metal objects e.g. coins, buried in ground, has alarm center to relay alarm signal from magnetic field detector to alarm management equipment

The system has a magnetic field detector for detecting a magnetic field (D) generated by a metal detector (DM), and an alarm center (CA) to relay an alarm signal from the magnetic field detector to alarm management equipment (EQ), where the magnetic field detector is one of remote magnetic field detector (DL) and close magnetic field detector (DP). A microcontroller detects interference of communication between the alarm center and the detector, where communication between the alarm center and the alarm management equipment and between the detector and the alarm center are encrypted. An independent claim is also included for a method for triggering an alarm following detection of use of a metal detector.

Prüfbare elektronische schaltung

Elektronische schaltung mit einem geheimen submodul

Ic-testverfahren und vorrichtungen

Elektronische schaltung mit einem geheimen submodul

Electronic circuit comprising a secret sub-module

The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.