MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. 1. A process comprising: receiving a first instruction that separates memory load instructions into older loads , the older loads being older than the first instruction , and newer loads , the newer loads being newer than the first instruction; allocating a load buffer in a memory ordering unit to the first instruction; stalling dispatches of newer loads from a memory subsystem; retiring the older loads from the memory subsystem; and dispatching the first instruction from the load buffer to a cache controller after all older loads from the memory subsystem are retired.2. The process of wherein the cache controller is the closest cache controller to a processor.3. The process of further comprising: retiring the load fencing instruction from the cache controller.4. The process of wherein the retirement of the older loads from the memory subsystem is via the cache controller.5. The process of wherein the retirement of the older loads from the memory subsystem is via the memory ordering unit.6. The process of wherein the retirement of the older loads from the memory subsystem is indicated by a reorder buffer retirement pointer and a load buffer tail pointer pointing to the load buffer.7. An apparatus comprising: a memory unit; a cache controller; and a memory ordering unit comprising: at least one load buffer claim 5 , the memory ordering unit being operative to receive a first instruction to separate memory load instructions that access the ...

Method and apparatus for a zero voltage processor sleep state

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Method And Apparatus For A Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Detection Of Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

Method and apparatus for a zero voltage processor sleep state

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Method and apparatus for a non-deterministic random bit generator (NRBG)

A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.

MFENCE and LFENCE micro-architectural implementation method and system

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Method and apparatus for a zero voltage processor sleep state

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Method for booting a heterogeneous system and presenting a symmetric core view

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method And Apparatus For A Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A system comprising:at least one processor comprising a first core and a second core;voltage regulation circuitry to regulate an operational voltage of the first core and the second core;an interconnect to couple one of the at least one processor to one or more system components; anda system memory coupled to one of the at least one processor, the first core to execute sequences of instructions;', 'the second core to execute sequences of instructions;', 'a shared cache accessible by both the first core and the second core;', 'power management logic to cause the first core to be powered down while the second core remains in an active state;', 'wherein power to the shared cache is to be maintained to enable access by the second core; and', 'wherein data associated with the first core is to be preserved when the first core is powered down., 'one of the at least one processor comprising2. The system of claim 1 , wherein at least one instruction of the sequences of instructions is a sleep instruction.3. The system of claim 2 , wherein the sleep instruction is to cause certain portions of the at least one processor to be powered down.4. The system of claim 2 , wherein the sleep instruction is to cause certain clocks to be gated.5. The system of claim 1 , wherein the system memory comprises a random access memory.6. The system of claim 1 , further comprising:at least one communication device coupled to the at least one processor.7. The ...

Detection of return oriented programming attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

MFENCE and LFENCE Micro-Architectural Implementation Method and System

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. 1. A process comprising:receiving a load fencing instruction that separates memory load instructions into older loads and newer loads;allocating a load buffer in a memory ordering unit to the load fencing instruction;stalling dispatches of newer loads from a memory subsystem;retiring older loads from the memory subsystem;dispatching the load fencing instruction from the load buffer to a cache controller when all older loads from the memory subsystem are retired.2. The process of wherein the cache controller is the closest cache controller to a processor.3. The process of further comprising:retiring the load fencing instruction from the cache controller.4. The process of wherein the retirement of all older loads from the memory subsystem is via the cache controller.5. The process of wherein the retirement of all older loads from the memory subsystem is via the memory ordering unit.6. The process of wherein the retirement of all older loads from the memory subsystem is indicated when a reorder buffer retirement pointer and a load buffer tail pointer point to the load buffer.7. A computer architecture comprising:a computer readable memory;a cache controller;a memory ordering unit with at least one load buffer wherein the memory unit receives a load fencing instruction that separates memory load instructions that access the computer readable memory into older memory loads and newer memory loads, allocates the load buffer the load fencing ...

METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1a voltage regulator interface to specify an operational voltage to a voltage regulator that provides said operational voltage to said processor;zero voltage entry/exit circuitry to transition said processor to a zero voltage power management state, wherein said operational voltage is reduced to approximately zero volts, said zero voltage entry/exit circuitry to transition said processor from said zero voltage power management state, wherein said operational voltage is higher than the approximately zero volts;a memory interface to write state variables of the processor to a memory as part of transitioning said processor to said zero voltage power management state, and to read said state variables from said memory as part of transitioning said processor from said zero voltage power management state.. A processor, comprising: This application is continuation of U.S. patent application Ser. No. 13/220,413, filed on Aug. 29, 2011, which is a continuation of U.S. patent application Ser. No. 12/706,631, filed on Feb. 16, 2010, which is a continuation of U.S. patent application Ser. No. 11/323,254, filed on Dec. 30, 2005, now U.S. Pat. No. 7,664,970, Issued on Feb. 16, 2010, all of which are hereby incorporated by reference in its entirety into this application.This application is related to U.S. application Ser. No. 10/931,565 filed Aug. 31, 2004 by inventors Kurts et al., assigned to Intel Corporation; U.S. application Ser. No. 10/934, ...

Mfence and lfence micro-architectural implementation method and system

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Mfence and lfence micro-architectural implementation method and system

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Tackifiers For Composite Articles

A composite article comprises a plurality of lignocellulosic pieces and an adhesive system disposed on the plurality of lignocellulosic pieces for bonding the plurality of lignocellulosic pieces. The adhesive system comprises a binder component and a tackifier component. The tackifier component comprises an acrylic or a styrene-butadiene polymer. The tackifier component is useful for maintaining orientation of the plurality of lignocellulosic pieces during manufacture of the composite article. The composite article may be various engineered lignocellulosic composites, such as particleboard. 1. A composite article comprising:a plurality of lignocellulosic pieces; andan adhesive system disposed on said plurality of lignocellulosic pieces for bonding said plurality of lignocellulosic pieces; a binder component, and', 'a tackifier component comprising an acrylic or a styrene-butadiene polymer for maintaining orientation of said plurality of lignocellulosic pieces during manufacture of said composite article., 'wherein said adhesive system comprises'}2. A composite article as set forth in wherein said polymer is a styrene-acrylic polymer.3. A composite article as set forth in wherein said adhesive system is formed from said binder and said tackifier components.4. A composite article as set forth in wherein said polymer comprises;{'sub': 1', '20, 'i) a Cto Calkyl (meth)acrylate,'}ii) an ethylenically unsaturated carboxylic acid,iii) a vinyl aromatic group,{'sub': 2', '13, 'iv) a vinyl ester of a Cto Calkyl carboxylic acid ester,'}{'sub': 2', '8, 'v) a Cto Chydroxyalkyl (meth)acrylate,'}vi) an ethylenically unsaturated nitrile,vii) an α,β-ethylenically unsaturated amide-group-containing compound,viii) a reactive vinyl cross-linker, orix) combinations thereof.5. A composite article as set forth in wherein said polymer comprises said i) Cto Calkyl (meth)acrylate which is selected from the group of methyl (meth)acrylate claim 4 , ethyl (meth)acrylate claim 4 , propyl (meth) ...

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. 1. A processor comprising:an instruction fetch unit to fetch a load fence instruction that does not have a data operand; anda portion of the processor responsive to the load fence instruction to prevent newer memory load instructions occurring after the load fence instruction in program order from being globally visible before older memory load instructions occurring before the load fence instruction in the program order are globally visible without causing the processor to stall dispatch of a newer memory store instruction occurring after the load fence instruction in the program order.2. The processor of claim 1 , wherein the load fence instruction is treated as a non-operation (NOP) by the processor after being dispatched once the older memory load instructions are globally visible claim 1 , and wherein the older memory load instructions are globally visible but not necessarily completed.3. The processor of claim 1 , wherein the load fence instruction comprises a macroinstruction.4. The processor of claim 1 , wherein the load fence instruction does not have a data operand.5. The processor of claim 1 , wherein the instruction fetch unit is further to fetch a memory fence instruction that does not have a data operand claim 1 , the memory fence instruction operable to cause the processor to ensure that all older memory load instructions and all older memory store instructions claim 1 , which are each older than the memory fence instruction ...

Method and apparatus for establishing safe processor operating points

A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Protection Against Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system. 1. A processor comprising:at least one execution unit; anda Return Oriented Programming (ROP) logic coupled to the at least one execution unit, the ROP logic to validate a return pointer stored on a call stack based on a secret ROP value, wherein the secret ROP value is only accessible to an operating system.2. The processor of claim 1 , wherein the ROP logic is to generate the secret ROP value under control of an operating system.3. The processor of claim 2 , wherein the ROP logic is to generate the secret ROP value using a random number.4. The processor of claim 1 , wherein the ROP logic is to generate a check value based on the secret ROP value.5. The processor of claim 4 , wherein the ROP logic is further to store the check value on the call stack after the return pointer.6. The processor of claim 4 , wherein the ROP logic is to generate the check value by encryption of the secret ROP value with the return pointer.7. The processor of claim 4 , wherein the ROP logic is to generate the check value by encryption of the secret ROP value with a stack pointer.8. The processor of claim 5 , wherein the ROP logic is further to remove the check value and the return pointer from the call stack claim 5 , and to generate a validation check value.9. The processor of claim 8 , wherein the ROP logic is to determine that the return pointer is valid when the validation check value matches the check value removed from the call stack.10. The processor of claim 9 , wherein the ROP logic is further to execute a return to a first routine via the return pointer if the return pointer is valid.11. A processor comprising: pop a return pointer and ...

Protection Against Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system. 1. A processor comprising: obtain a secret ROP value and a check value, wherein the secret ROP value is only accessible to an operating system; and', 'determine whether a return pointer is valid based on the secret ROP value and the check value., 'a plurality of cores each to execute instructions, each of the plurality of cores including a Return Oriented Programming (ROP) logic to2. The processor of claim 1 , wherein the ROP logic is to generate the secret ROP value under control of an operating system.3. The processor of claim 1 , wherein the ROP logic is to generate the secret ROP value based on random number.4. The processor of claim 1 , wherein the ROP logic is to generate the check value using the secret ROP value.5. The processor of claim 1 , wherein the ROP logic is to store the check value on the call stack following the return pointer.6. The processor of claim 1 , wherein the ROP logic is to generate the check value by encryption of the secret ROP value with the return pointer.7. The processor of claim 1 , wherein the ROP logic is to generate the check value by encryption of the secret ROP value with a stack pointer.8. The processor of claim 1 , wherein the ROP logic is further to remove the check value and the return pointer from the call stack claim 1 , and to generate a validation check value based on the secret ROP value.9. The processor of claim 8 , wherein the ROP logic is to determine that the return pointer is valid when the validation check value matches the check value removed from the call stack.10. The processor of claim 1 , wherein the ROP logic is to execute a return to a first routine via the return ...

Method And Apparatus For A Zero Voltage Processor

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. (canceled)2. A processor comprising:a first processor core to save at least a portion of a state of the first processor core to a cache memory and to enter a mode in which the first processor core is powered off;a second processor core to save at least a portion of a state of the second processor core to the cache memory and to enter a mode in which the second processor core is powered off; andthe cache memory, wherein the cache memory is to be powered when the first and second processor cores are to be powered off, and the saved state of the first processor core and the saved state of the second processor core are to be restored when the first processor core and the second processor core transition to a mode in which the first processor core and the second processor core are to be powered on, respectively.3. The processor of claim 2 , wherein the first processor core is to save the state of the first processor core in the cache memory.4. The processor of claim 2 , wherein the first processor core is to enter the mode in which the first processor core is to be powered off in response to execution of an instruction by the first processor core.5. The processor of claim 4 , wherein the second processor core is to enter the mode in which the second processor core is to be powered off in response to execution of an instruction by the second processor core.6. The processor of claim 2 , wherein the first processor core is to restore ...

Protection Against Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system. 1. A processor comprising: generate a check value based on a secret value responsive to a first instruction of an instruction set architecture (ISA);', 'push the check value onto a call stack associated with a return pointer;', 'pop the return pointer and the check value off the call stack responsive to a second instruction of the ISA; and', 'determine whether the check value is valid based on a comparison to a validation check value., 'a core including a fetch unit to fetch instructions, a decode unit to decode the fetched instructions, at least one execution unit to execute one or more of the decoded instructions and a first logic comprising at least one hardware circuit coupled to the at least one execution unit, the first logic to2. The processor of claim 1 , wherein the secret value is only accessible to an operating system claim 1 , the secret value to be generated at a beginning of a session and stored in a secure location.3. The processor of claim 2 , wherein the secret value corresponds to a salt value based on a ROP security level.4. The processor of claim 1 , wherein claim 1 , in response to determination that the check value is valid claim 1 , the processor is to resume execution at a location specified by the return pointer claim 1 , and otherwise indicate a possible Return Oriented Programming (ROP) attack.5. The processor of claim 1 , further comprising a control register including at least one bit to indicate whether the first logic is enabled.6. The processor of claim 1 , wherein the first logic is to generate the secret value under control of an operating system claim 1 , responsive to a third instruction ...

DETECTION OF RETURN ORIENTED PROGRAMMING ATTACKS

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification. 1. A processor comprising:at least one execution unit; and determine a ROP metric based on a plurality of control transfer events,', 'determine whether the ROP metric exceeds a threshold, and in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification., 'a Return Oriented Programming (ROP) detection logic to2. The processor of claim 1 , wherein the ROP detection logic is to determine the ROP metric based on a count claim 1 , wherein the count is based on the plurality of control transfer events.3. The processor of claim 2 , wherein the ROP detection logic is to increment the count based on an instance of a subroutine return instruction.4. The processor of claim 3 , wherein the ROP detection logic is to decrement the count based on an instance of a subroutine call instruction.5. The processor of claim 2 , wherein the ROP detection logic is to increment the count based on a return misprediction.6. The processor of claim 2 , wherein the ROP detection logic is to increment the count based on an instance of a control transfer instruction associated with a stack pop instruction.7. The processor of claim 2 , wherein the ROP detection logic is to increment the count based on an instance of a control transfer instruction associated with an increase in a stack pointer.8. The processor of claim 1 , wherein the ROP attack notification is to trigger a protection application to take one or more actions to address the ROP attack.9. The processor of claim 1 , wherein the ROP detection logic ...

Detection Of Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

Method And Apparatus For A Zero Voltage Processor

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A system comprising:a graphics processor;a wireless communication module;a memory controller; and a first processor core, the first processor core to save a state of the first processor core and to enter a mode in which the first processor core is powered off;', 'a second processor core, the second processor core to save a state of the second processor core and to enter a mode in which the second processor core is powered off; and', 'a cache memory, the cache memory to be powered when the first processor core is powered off;, 'a multi-core processor, the multi-core processor includingwherein the first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered, and the second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.2. The system of claim 1 , wherein the first processor core is to save the state of the first processor core in the cache memory.3. The system of claim 1 , wherein the first processor core is to enter the mode in which the first processor core is powered off in response to execution of an instruction by the first processor core.4. The system of claim 3 , wherein the second processor core is to enter the mode in which the second processor core is powered ...

METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (NRBG)

A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction. 1. A processor , comprising:a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings; andan execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.2. The processor of claim 1 , further comprising a flag register to store a flag set by the execution unit to indicate whether the NRB string stored in the destination register is valid.3. The processor of claim 1 , wherein the execution unit is configured claim 1 , in response to a second instruction to read a random number claim 1 , to retrieve one of the DRB strings from the DRNG and to store the DRB in a destination register specified by the second instruction.4. The processor of claim 3 , wherein the DRNG comprises:a conditioner to condition the entropy data provided by the entropy source to generate conditioned entropy (CE) data;a DRB generator (DRBG) coupled to the conditioner to generate the DRB strings based on the CE data; andan NRB generator (NRBG) coupled to the conditioner and the DRBG to generate the NRB strings based on the DRB strings and the CE data.5. The processor of claim 4 , wherein ...

Method And Apparatus For A Zero Voltage Processor

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A mobile system comprising:a mass storage device to store an operating system;a battery;a graphics processor;a wireless communication module;a memory controller; and a first processor core, the first processor core to save a state of the first processor core and to enter a mode in which the first processor core is powered off;', 'a second processor core, the second processor core to save a state of the second processor core and to enter a mode in which the second processor core is powered off; and', 'a cache memory, the cache memory to be powered when the first processor core is powered off;, 'a multi-core processor, the multi-core processor includingwherein the first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered, and the second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.2. The mobile system of claim 1 , wherein the first processor core is to save the state of the first processor core in the cache memory.3. The mobile system of claim 1 , wherein the first processor core is to enter the mode in which the first processor core is powered off in response to execution of an instruction by the first processor core.4. The mobile system of claim 3 , wherein the ...

METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface. 1. A processor comprising:a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level;a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level the first and second cores being in a dynamic multi-core unit; anda virtual-to-physical (V-P) mapping circuit coupled to the first and second physical cores, to map the first physical core to a system firmware interface via a virtual core and to hide the second processor core from the system firmware interface.2. The processor as in further comprising a third physical core having the first instruction set and the first power consumption level claim 1 , wherein the V-P mapping circuit is to map a first virtual core to the first physical core and to map a second virtual core to the third physical core claim 1 , to allow a set of threads to be executed in parallel across the first and third physical processor cores.3. The processor as in wherein the V-P mapping logic is to map the second virtual core to the second physical core transparently to the firmware interface in response to detected characteristics associated with the set of threads being executed.4. The processor as in wherein the first power consumption level is lower than the second power ...

Detection Of Return Oriented Programming Attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification. 1. A processor comprising: adjust a count in a first direction in response to detection of one or more control transfer events of a first type and adjust the count in a second direction in response to detection of one or more control transfer events of a second type; and', 'in response to a determination that the count exceeds a threshold, notify a protection agent of a possible Return Oriented Programming (ROP) attack., 'a core including a fetch unit to fetch instructions, a decode unit to decode the fetched instructions, at least one execution unit to execute one or more of the decoded instructions and a first logic comprising at least one hardware circuit coupled to the at least one execution unit, the first logic to2. The processor of claim 1 , wherein the first logic comprises an accumulator to store the count.3. The processor of claim 1 , wherein the first logic is to increment the count in response to an instance of a subroutine return instruction claim 1 , wherein the subroutine return instruction is a control transfer event of the first type.4. The processor of claim 3 , wherein the first logic is to decrement the count in response to an instance of a subroutine call instruction claim 3 , wherein the subroutine call instruction is a control transfer event of the second type.5. The processor of claim 3 , wherein the first logic is further to increment the count in response to a return misprediction.6. The processor of claim 3 , wherein the first logic is further to increment the count in response to an instance of ...

Method and apparatus for a zero voltage processor sleep state

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Method And Apparatus For A Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A multi-core processor comprising:a memory to store a voltage identification value;a plurality of phase-locked loops; anda first processor core and a second processor core coupled to the memory and the plurality of phase-locked loops;wherein the first processor core and the second processor core each support a core C6 (CC6) state in which a core state of a corresponding processor core is saved to a cache memory; andwherein the multi-core processor supports a package sleep state (C6) in which the phase-locked loops (PLLs) are powered down and a voltage level provided to the multi-core processor is transitioned to a value corresponding to the voltage identification value after the first processor core and the second processor core have entered the core C6 (CC6) state.2. The multi-core processor as in further comprising:power management logic to cause the second core to remain in an active state when the first core enters the CC6 state and to maintain power to the cache memory to be accessed by the second core and to preserve data associate with the first core when the first core is placed in the CC6 state.3. A mobile system comprising:an operating system;a battery;a wireless communication module; anda multi-core processor to include a first processor core and a second processor core;the first processor core to save a state of the first processor core in a memory and to enter a mode in which the first processor core is powered off; ...

Method And Apparatus For A Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A system , comprising:a memory controller;an I/O controller;a clock generator; and a shared L2 cache memory;', 'a memory to store a voltage identification value;', 'a first processor core; and', 'a second processor core;, 'a multi-core processor, the multi-core processor comprisingwherein the first processor core and the second processor core each support a core C6 (CC6) state in which a core state of a corresponding processor core is saved to a cache memory; andwherein the multi-core processor supports a package sleep state (C6) in which phase-locked loops (PLLs) are to be powered down and a voltage level provided to the multi-core processor is to be transitioned to a value corresponding to the voltage identification value after the first processor core and the second processor core enter the core C6 (CC6) state.2. The system of claim 1 , wherein the memory to store the voltage identification value includes a register.3. The system of claim 1 , wherein the first processor core is to enter the CC6 state and wait for the second processor core to enter the CC6 state before the multi-core processor enters the C6 state.4. A multi-core processor comprising:a memory to store a voltage identification value;a plurality of phase-locked loops; anda first processor core and a second processor core coupled to the memory and the plurality of phase-locked loops;wherein the first processor core and the second processor core each support a core ...

METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface. 1. A processor comprising:a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level;a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level the first and second cores being in a dynamic multi-core unit; anda virtual-to-physical (V-P) mapping circuit coupled to the first and second physical cores, to map the first physical core to a system firmware interface via a virtual core and to hide the second processor core from the system firmware interface.2. The processor as in further comprising a third physical core having the first instruction set and the first power consumption level claim 1 , wherein the V-P mapping circuit is to map a first virtual core to the first physical core and to map a second virtual core to the third physical core claim 1 , to allow a set of threads to be executed in parallel across the first and third physical processor cores.3. The processor as in wherein the V-P mapping logic is to map the second virtual core to the second physical core transparently to the firmware interface in response to detected characteristics associated with the set of threads being executed.4. The processor as in wherein the first power consumption level is lower than the second power ...

STACK PIVOT DETECTION SYSTEMS AND METHODS

The present disclosure is directed to systems and methods for detecting stack-pivot attacks in a processor-based device. Processor circuitry executes one or more applications via sequential execution of instructions on a stack. Stack pivot attacks occur when an attacker takes control of the stack and uses the stack to execute a series of code sections referred to as “gadgets.” A stack-pivot attack detector establishes an allowable processor stack offset change value associated with an application and monitors a processor stack offset change value responsive to an occurrence of a processor stack exchange instruction. A stack-pivot attack is detected when the processor offset change value exceeds the allowable processor stack offset change value. Upon detecting a stack-pivot attack, the stack-pivot detection circuitry causes the selective termination of the application. 1. A system to detect processor stack-pivot attacks , the system comprising:processor circuitry;a memory communicably coupled to the processor circuitry; and determine an allowable processor stack offset change value for an application executed by the processor circuitry;', 'detect an occurrence of a processor stack exchange instruction and a processor stack update in the application executed by the processor circuitry;', 'determine a processor stack offset change value for the application responsive to detection of the processor stack exchange instruction and the resultant processor stack update;', 'compare the determined processor stack offset change value to the determined allowable processor stack offset change value for the application; and', 'cause a selective termination of the application responsive to a detected stack-pivot indicated by the determined processor stack offset change value exceeding the determined allowable processor stack offset change value., 'a storage device that includes instructions that, when executed by the processor circuitry causes the processor circuitry to2. The ...

Composicion de resina de resistencia en humedo.

Aqueous thickener composition and process for making same

A water retention aid/thickener composition containing: (a) from about 40 to about 75% by weight of a C1-C8 alkyl acrylate; (b) from about 60 to about 25% by weight of methacrylic acid; and (c) from about 0.1 to about 5% by weight of an alkoxylated acrylate or methacrylate monomer containing at least three vinyl moieties, all weights being based on the weight of the composition.

Polymeric thickeners for aqueous compositions

Latexes are thickened by compounds of the formula ##STR1## wherein R 1 is an aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical having a valence of from 2 to 8; each of B 1 -B 8 is independently an ester, amide, amine, ether, sulfide, disulfide, thiocarbamate, urea, thiourea, urethane, sulfate, phosphate, carbonyl, methylene, thioamide, carbonate, or imide linkage; each of X 1 -X 8 is independently --A 1 --R 2 --A 2 -- or --A 1 -- wherein each of A 1 and A 2 is independently an ester, amide, amine, ether, sulfide, disulfide, urethane, thiocarbamate, urea, thiourea, sulfate, phosphate, carbonyl, methylene, thioamide, carbonate, or imide linkage and R 2 is a divalent aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical with the proviso that only one of B 1 -B 8 is urethane and that when one of B 1 -B 8 is urethane, one of A 1 and A 2 is not urethane; each of d, g, j, m, p, s, v, y is independently 0 or 1, each of c, f, i, l, o, r, u, x is independently any integer or non-integer from 0 to about 200; each of J, K, L, M, N, P, Q, S is 0 or 1; each of e, h, k, n, q, t, w, z is independently any integer or non-integer from 0 to about 200; each of R 3 -R 10 is independently an aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical having from 1 to about 50 carbon atoms; each of AG and AO is independently an ethyleneoxy, 1,2-propyleneoxy, 1,2-butyleneoxy unit or combinations thereof.

Polymeric thickeners for aqueous compositions

Wet strength resin composition and methods of making the same

Wet-strength resins and methods of making the same by reacting a polyamine, polyaminoamide or alkylated derivative thereof with a cross-linking agent selected from diepoxides, piperazine dichlorohydrin, methylene bis-acrylamide, chloroacetyl chloride and maleic anhydride.

Method of thickening aqueous formulations

A composition for thickening aqueous based personal care products is comprised of a cosolvent selected from the group consisting of a diol, the mono alkyl ether of a diol, a salt of a sulfated ethoxylated alcohol, a salt of a sulfated ethoxylated alkyl phenol, and a complex organic phosphate ester; water; a nonionic surfactant and, a complex ester.

Process for repulping wet strength paper

Process for repulping wet strength paper containing at least one wet strength resin in which the initial breakdown of the paper is conducted at a first pH and the substantial completion of the conversion to fibers is conducted at a second pH which is higher than the first pH.

Aqueous dispersions of polyamides

A process is provided for preparing a dispersion of a polyamide in water, said process comprising: forming a solution of a polyamide having an acid value of greater than about 2 in an organic solvent to form a solution of said polyamide in said solvent, said polyamide and said solvent being at a temperature below the softening point of said polyamide during said dissolving, said solution further comprising a surfactant, wherein at least a portion of the acid value of said polyamide is neutralized, adding sufficient water to said solution with mixing to form an oil-in-water dispersion, the temperature of said solution and said water being below the softening point of said polyamide during said adding, and removing at least a major amount of said organic solvent from said oil-in-water dispersion. The resulting dispersion is useful in preparing a coating of the polyamide, which coating is useful as an adhesive.

Wet strength resin blend, as well as process for preparing the blend

En amin-epiklorhydrin-har.piks fremstilles i et vann-polyol-løsemiddel for lettere gjennomfø-ring av polymerisasjons- og tverrbindings-reaksjonen. Reaksjonsproduktet er anvendbart som våtstyrke-harpiksblanding som har et flammepunkt som er høyt nok til at blandingen kan anvendes ved kommersiell papirfremstilling.

Aqueous thickener composition and process for preparing the same

Tertiary amine derivatives as components of polymer forming systems

Curable systems for the preparation of polymeric products in which the curable system comprises an epoxy resin or an isocyanate, wherein the system contains a condensation reaction product of a) a polyamine having only one primary amino group and only one tertiary amino group, and a non-cyclic backbone containing from 1 to 18 carbon atoms; and b) at least one of urea, guanidine, guanylurea, thiourea, and a mono-N,N' alkyl substituted urea or thiourea having from 1 to 3 carbon atoms in the alkyl moieties.

Wet strength resin composition and method of making same

2114722 9303222 PCTABS00019 A wet strength resin composition is comprised of an aminopolyamide-epichlorohydrin acid salt resin having a total organically bound chlorine of up to 0.7 % by weight of the resin. The amount of total organically bound chlorine present is controlled by the process parameters.

An apparatus for performing multiply-add operations on packed data

A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first (810), second (811), third (812), and fourth multiplier (813), wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810, 811), and second adder (851) coupled to the third and fourth multipliers (812, 813). A third storage area (871) is coupled to the adders (850, 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850, 851), respectively, as first and second data elements of a third packed data.

AQUEOUS THICKENER COMPOSITION AND METHOD FOR THE PRODUCTION THEREOF

Antistatic composition and process for making same

Improved alkyl polyglycosides

Polymeric thickeners for aqueous compositions

Latexes are thickened by compounds of the formula ##STR1## wherein R 1 is an aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical having a valence of from 2 to 8; each of B 1 -B 8 is independently an ester, amide, amine, ether, sulfide, disulfide, thiocarbamate, urea, thiourea, urethane, sulfate, phosphate, carbonyl, methylene, thioamide, carbonate, or imide linkage; each of X 1 -X 8 is independently -A 1 -R 2 -A 2 - or -A 1 - wherein each of A 1 and A 2 is independently an ester, amide, amine, ether, sulfide, disulfide, urethane, thiocarbamate, urea, thiourea, sulfate, phosphate, carbonyl, methylene, thioamide, carbonate, or imide linkage and R 2 is a divalent aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical with the proviso that only one of B 1 -B 8 is urethane and that when one of B 1 -B 8 is urethane, one of A 1 and A 2 is not urethane; each of d, g, j, m, p, s, v, y is independently 0 or 1, each of c, f, i, l, o, r, u, x is independently any integer or non-integer from 0 to about 200; each of J, K, L, M, N, P, Q, S is 0 or 1; each of e, h, k, n, q, t, w, z is independently any integer or non-integer from 0 to about 200; each of R 3 -R 10 is independently an aliphatic, substituted aliphatic, aromatic, or substituted aromatic radical having from 1 to about 50 carbon atoms; each of AG and AO is independently an ethyleneoxy, 1,2-propyleneoxy, 1,2-butyleneoxy unit or combinations thereof.

An apparatus for performing multiply-add operations on packed data

A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first (810), second (811), third (812), and fourth multiplier (813), wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810, 811), and second adder (851) coupled to the third and fourth multipliers (812, 813). A third storage area (871) is coupled to the adders (850, 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850, 851), respectively, as first and second data elements of a third packed data.

Process for repulping wet strength paper

Process for repulping wet strength paper containing at least one wet strength resin in which initial breakdown of the paper is conducted at a first pH and the substantial completion of the conversion to fibers is conducted at a second pH which is higher than the first pH.

Thickener for aqueous compositions

A composition for thickening aqueous based personal care products is comprised of a cosolvent selected from the group consisting of a diol, the mono alkyl ether of a diol, a salt of a sulfated ethoxylated alcohol, a salt of a sulfated ethoxylated alkyl phenol, and a complex organic phosphate ester; water; a nonionic surfactant and, a complex ester.

Processor unique processor number feature with a user controllable disable capability

Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features

A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Aqueous dispersions of polyamides

A process is provided for preparing a dispersion of a polyamide in water, said process comprising: dissolving a polyamide having an amine value of greater than about 2 in an organic solvent to form a solution of said polyamide in said solvent, said polyamide and said solvent being at a temperature below the softening point of said polyamide during said dissolving, said solution further comprising a surfactant and an inorganic alkaline material; adding sufficient water containing an acid to said solution with mixing to form an oil-in-water dispersion, the temperature of said solution and said water being below the softening point of said polyamide during said adding, the amount of said acid being sufficient to neutralize a portion of said inorganic alkaline material, but insufficient to coagulate said polyamide from the resulting oil-in-water dispersion; and removing at least a major amount of said organic solvent from said oil-in-water dispersion. The resulting dispersion is useful in preparing a coating of the polyamide, which coating is useful as an adhesive.

Aqueous dispersions of polymers

A method for formulating an aqueous dispersion of a polymer includes dissolving a polymer such as an acrylic polyol in a solvent to form a polymer solution. A surfactant is added to the polymer solution, and water is then added with mixing sufficient to dispersed the polymer in the water. The resulting aqueous dispersion can be mixed with a water dispersible polyisocyanate to produce coating materials which can be cured to form tough films and coatings.

Process of preparing a polyamide dispersion in water and material composition

Method of booting a heterogeneous system and presenting a symmetric core view

Prozessor, der Folgendes umfasst:einen ersten physischen Kern (PCO oder PC1 oder PC2 oder PC3) mit einem ersten Instruktionssatz und einem ersten Stromverbrauchpegel zum Ausführen eines Threads auf einem ersten Leistungspegel;einen zweiten physischen Kern (PC4) mit einem zweiten Instruktionssatz und einem zweiten Stromverbrauchpegel zum Ausführen eines Threads auf einem zweiten Leistungspegel, wobei sich der erste (PCO oder PC1 oder PC2 oder PC3) und der zweite Kern (PC4) in einer dynamischen Mehrkerneinheit befinden; undeinen Virtuell-zu-physisch (V-P)-Abbildungsschaltkreis (1130), der mit dem ersten (PCO oder PC1 oder PC2 oder PC3) und dem zweiten physischen Kern (PC4) gekoppelt ist, zum Abbilden des ersten physischen Kerns (PCO oder PC1 oder PC2 oder PC3) auf eine System-Firmware-Schnittstelle über einen virtuellen Kern (VC0 oder VC1 oder VC2 oder VC3) und zum Verbergen des zweiten physischen Kerns (PC4) vor der System-Firmware-Schnittstelle. A processor comprising:a first physical core (PCO or PC1 or PC2 or PC3) having a first instruction set and a first power consumption level for executing a thread at a first performance level;a second physical core (PC4) having a second instruction set and a second power consumption level for executing a thread at a second performance level, the first (PCO or PC1 or PC2 or PC3) and the second core (PC4) being in a dynamic multi-core unit; anda virtual-to-physical (V-P) mapping circuit (1130) coupled to the first (PCO or PC1 or PC2 or PC3) and the second physical core (PC4) for mapping the first physical core (PCO or PC1 or PC2 or PC3) to a system firmware interface via a virtual core (VC0 or VC1 or VC2 or VC3) and to hide the second physical core (PC4) from the system firmware interface.

Surface Coating Composition

A coating composition with improved adhesion to a hydrophobic paint primer substrate consisting of a waterborne zwitterionic copolymer coating composition that is biocide-free and zero volatile organic compounds that improves the environmental and sustainability issues of today's toxic marine antifouling coatings.

Wässrige dispersionen von polyamiden

Surface coating composition

A coating composition with improved adhesion to a hydrophobic paint primer substrate consisting of a waterborne zwitterionic copolymer coating composition that is biocide-free and zero volatile organic compounds that improves the environmental and sustainability issues of today's toxic marine antifouling coatings.

Cache line flush micro-architectural implementation method and system

Nassfeste harzzusammensetzung mit niedrigem organischem chlorgehalt und verfahren zur herstellung

Nassfeste harzzusammensetzung und verfahren für ihre herstellung

Method and apparatus for a non-deterministic random bit generator (nrbg)

A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.

Aqueous polyamide dispersion composition

Aluminum trihydroxide deliquoring with anionic polymers

Treating substrates to reduce electrostatic charge

Aluminum trihydroxide deliquoring with anionic polymers

Detection of return oriented programming attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.