Reducing thermal runaway in inverter devices

An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2 nd stage first and second FET devices, each 2 nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

REDUCING THERMAL RUNAWAY IN INVERTER DEVICES

An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2 nd stage first and second FET devices, each 2 nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

ON-CHIP SENSOR FOR MONITORING ACTIVE CIRCUITS ON INTEGRATED CIRCUIT (IC) CHIPS

A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response. 1. A sensor for monitoring for the effects of operating conditions , said sensor comprising:a multi-fingered driver associated with a monitored circuit on an integrated circuit (IC) chip, said monitored circuit having known parameter sensitivities, said multi-fingered driver being sensitive to one or more of said known parameter sensitivities;a load driven by said multi-fingered driver; andsense and control logic circuit providing a drive signal selectively driving said multi-fingered driver, and selectively monitoring said load for an expected multi-fingered driver response.2. A sensor as in claim 1 , wherein said IC chip is a CMOS IC chip and said multi-fingered driver is a CMOS driver including at least two field effect transistors (FETs) comprising a p-type FET (PFET) and an n-type FET (NFET).3. A sensor as in claim 2 , wherein said CMOS driver is a multi-fingered inverter claim 2 , said NFET is a fingered NFET and said PFET is a fingered NFET claim 2 , the gate of said fingered NFET and the gate of said fingered PFET being selectively driven from said sense and control logic circuit.4. A sensor as in claim 3 , wherein said the gate of said fingered NFET and the gate of said fingered PFET are selectively independently driven from said sense and control logic circuit.5. A sensor as in claim 2 , wherein said sense and control logic circuit comprises:control logic receiving select signals and providing said drive signal responsive to ...

Method for an Efficient Modeling of the Impact of Device-Level Self-Heating on Electromigration Limited Current Specifications

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Semiconductor device having diffusion barrier to reduce back channel leakage

A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Stress-generating structure for semiconductor-on-insulator devices

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region. 1. A semiconductor structure comprising:a semiconductor-on-insulator (SOI) substrate including a handle substrate, at least one buried insulator portion abutting said handle substrate, and at least one top semiconductor portion abutting said at least one buried insulator portion;a trench extending from a top surface of said at least one top semiconductor portion to a depth below a top surface of said at least one buried insulator portion; anda stack of an insulator stressor plug and a silicon oxide plug located in said trench, wherein said insulator stressor plug abuts a bottom surface of said trench and said silicon oxide plug is substantially coplanar with said top surface of said at least one top semiconductor portion, wherein an interface between said insulator stressor plug and said silicon oxide plug is located between a top surface of said at least one buried insulator portion and said bottom surface of said at least one buried insulator portion, or at said bottom surface of said at least one buried insulator portion, or the interface between said insulator ...

SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE

A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough. 1. A method of fabricating a semiconductor device , comprising:implanting impurities within an active semiconductor layer formed on a buried insulator layer of a semiconductor-on-insulator (SOI) substrate;forming a diffusion barrier layer in the active semiconductor layer, the diffusion barrier layer formed between the impurities and an upper surface of the active semiconductor layer; andannealing the diffusion barrier layer to form a diffusion barrier layer that prevents the impurities from diffusing therethrough.2. The method of claim 1 , further comprising:forming a source region in a first area of the SOI substrate;forming a drain region in a second area of the SOI substrate; andforming a channel region between the source and drain regions, the channel region including the impurities and the diffusion barrier layer.3. The method of claim 2 , further comprising:forming at least one trench storage element in the SOI substrate and adjacent the channel region; andforming at least one trench isolation element in the SOI substrate and in contact with the trench storage element.4. The method of claim 3 , further comprising forming a transistor device on the channel region to selectively control operation of the trench storage element.5. The method of claim 1 , wherein the impurities to increase back channel threshold voltage comprise atoms selected from a group including boron claim 1 , boron difluoride claim 1 , indium claim 1 , gallium claim 1 , arsenic and ...

SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE

A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough. 1. A method of fabricating a semiconductor device , comprising:implanting impurities within an active semiconductor layer formed on a buried insulator layer of a semiconductor-on-insulator (SOI) substrate;forming a diffusion barrier layer in the active semiconductor layer, the diffusion barrier layer formed between the impurities and an upper surface of the active semiconductor layer; andannealing the diffusion barrier layer to form a diffusion barrier layer that prevents the impurities from diffusing therethrough.2. The method of claim 1 , further comprising:forming a source region in a first area of the SOI substrate;forming a drain region in a second area of the SOI substrate; andforming a channel region between the source and drain regions, the channel region including the impurities and the diffusion barrier layer.3. The method of claim 2 , further comprising:forming at least one trench storage element in the SOI substrate and adjacent the channel region; andforming at least one trench isolation element in the SOI substrate and in contact with the trench storage element.4. The method of claim 3 , further comprising forming a transistor device on the channel region to selectively control operation of the trench storage element.5. The method of claim 1 , wherein the impurities to increase back channel threshold voltage comprise atoms selected from a group including boron claim 1 , boron difluoride claim 1 , indium claim 1 , gallium claim 1 , arsenic and ...

FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. 1. A semiconductor structure comprising:a trench located in a single crystalline semiconductor material layer;a graded-doping semiconductor material portion located on sidewalls and a bottom surface of said trench and epitaxially aligned to said single crystalline semiconductor material layer, said graded-doping semiconductor material portion including a faceted surface that adjoins a topmost portion of a vertical sidewall of said trench at an edge and having a gradient in a dopant concentration; anda doped semiconductor material portion located on said graded-doping semiconductor material portion and protruding above said trench and epitaxially aligned to said graded-doping semiconductor material portion, wherein said doped semiconductor material portion is spaced from said single crystalline semiconductor material layer by said graded-doping semiconductor material portion.2. The semiconductor structure of claim 1 , wherein said graded-doping semiconductor material portion includes a tapered region including said faceted surface claim 1 , a uniform-width vertical ...

FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. 1. A method of forming a semiconductor structure comprising:forming a trench having a vertical sidewall in a semiconductor substrate, wherein said vertical sidewall extends downward from a top surface of said semiconductor substrate;depositing a stress-generating semiconductor material in said trench by a first selective epitaxy process, wherein a faceted surface of said stress-generating semiconductor material and said vertical sidewall are adjoined at an edge; anddepositing a doped semiconductor material by an in-situ doped selective epitaxy process, wherein said trench is filled with said stress-generating semiconductor material and said doped semiconductor material.2. The method of claim 1 , further comprisingforming a gate stack on said semiconductor substrate; andforming a gate spacer around said gate stack, wherein said trench is formed by etching an exposed portion of said semiconductor substrate employing said gate stack and said gate spacer as an etch mask.3. The method of claim 2 , wherein said faceted surface of said stress-generating semiconductor ...

Modulation of the morphology of epitaxial semiconductor material

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Creating increased mobility in a bipolar device

The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.

Tuneable semiconductor device

Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

Bipolar device having non-uniform depth base-emitter junction

A non-uniform depth base-emitter junction, with deeper junction at the lateral portions of the emitter, preferably coupled with a recessed and raised extrinsic base, bipolar transistor, and a method of making the same. The bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a recessed and raised extrinsic base layer formed on the silicon germanium layer, and a silicon pedestal on which an emitter layer is formed. The emitter has non-uniform depths into the base layer.

Bipolar transistor with isolation and direct contacts

A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved f T , Fmax and drive current.

Bipolar structure with two base-emitter junctions in the same circuit

Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has lower ramp rate.

Bipolar transistor with collector having an epitaxial Si:C region

A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic C CB .

Sram cells with asymmetric floating-body pass-gate transistors

The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.

BiCMOS integration scheme with raised extrinsic base

A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

Stress-generating structure for semiconductor-on-insulator devices

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border

The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Method of creating asymmetric field-effect-transistors

The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

Semiconductor device having diffusion barrier to reduce back channel leakage

A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

BiCMOS integration scheme with raised extrinsic base

Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors

A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

Methods to improve the SiGe heterojunction bipolar device performance

Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

材料の酸化速度の違いを利用して形成した自己整合マスク

【課題】異なる材料の酸化速度の差を利用して形成される自己整合酸化物マスクを提供する。 【解決手段】能動領域の単結晶Ｓｉ52（Ｓｉ／ＳｉＧｅ）およびフィールド上の多結晶Ｓｉ51（Ｓｉ／ＳｉＧｅ）を含むＣＶＤ成長ベースＮＰＮベース層上に自己整合酸化物マスクを形成する。この自己整合マスクは、多結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）が単結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）よりも速く酸化することを利用して作製される。熱酸化法を用いて多結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）上に厚い酸化層を形成し、単結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）上に薄い酸化層を形成することによって、多結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）および単結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）の両方の上に酸化膜を形成し、次いで酸化物のエッチングを制御して、多結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）上に自己整合酸化物マスク層を残しながら、単結晶Ｓｉ（Ｓｉ／ＳｉＧｅ）上の薄い酸化層を除去する。 【選択図】図５

Methods of modulating the morphology of epitaxial semiconductor material

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.