FIELD EFFECT TRANSISTORS

MANUFACTURE OF INTEGRATED CIRCUITS

Method of making an integrated circuit

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

METHOD OF MAKING AN INTEGRATED CIRCUIT

Field effect transistors

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Manufacture of integrated circuits

A VLSI device is formed on monocrystalline silicon and comprises FET's (G, S, D) and diffused connections 101 surrounded by field oxide and polysilicon interconnections 102. First oxide and nitride layers are formed (for the gate insulator) and doped polysilicon is applied, oxidised to a second oxide layer and covered with a second nitride layer which is oxidised to an oxynitride layer. The last two layers are masked and etched except where polysilicon contacts 103 are required. A third silicon nitride layer is applied and oxidised to an oxynitride layer and these layers are masked and etched to define the polysilicon connection 102 including gate electrodes G. Then the exposed second nitride with its oxynitride and then polysilicon are removed. The first nitride and its oxynitride are masked and etched to define the FET areas 405 and diffused line contact areas 406. Batch etching steps are followed by doping the diffused and polysilicon lines 101, 102 thereby exposed. More batch etching ...

Semiconductor Structure

... 1,155,722. Semi-conductor devices. NORTH AMERICAN ROCKWELL CORP. 20 June, 1966, No. 27496/66. Heading H1K. A monolithic structure suitable for the manufacture of solid circuits consists of a series of mutually insulated monocrystalline semi-conductor bodies of opposite conductivity types. A typical structure is formed by grooving a uniform resistivity N-type silicon wafer, oxidizing or nitriding the grooved surface and then burying the grooves in vapour deposited silicon, beryllia or alumina. The ungrooved face is next lapped down to the grooves to isolate the regions of the wafer defined thereby and holes cut through other regions of the assembly. One face of a corresponding oxidized P-type silicon wafer provided with mesas to mate with the holes, is fitted to the N-type wafer and silicon deposited in the holes to form the monolithic structure shown in section in Fig. 8. The back face of the P wafer 35 is then lapped to leave the mesas as oxide coated islands and to reexpose the N-type ...

MANUFACTURE OF INTEGRATED CIRCUITS

Manufacture of integrated circuits

A VLSI device is manufactured on monocrystalline silicon and comprises FET's (S,G,D), polysilicon connections 102 and diffused connections 101. The silicon is oxidized to form a first oxide layer which is covered with a first nitride layer. The latter is selectively removed to leave FET and diffused connection areas 100, 101 masked. Unmasked areas are oxidized to field oxide and doped polysilicon is applied and oxidized to a second oxide layer which is covered with a second nitride layer. This is oxidized to an oxynitride layer which is doped. Masking and etching steps remove the oxynitride and second nitride except where there are to be polysilicon contacts 103 and remove the polysilicon except for the lines 102 including the gate electrodes G and then remove the first nitride and oxide except for the FET area 405 and diffused connection contact area 406. The device is completed by batch removal steps and applying conducting lines to the polysilicon and diffused contact areas Pc, Nc. The ...

Method of Making Semiconductor Structure

... 1,155,723. Semi-conductor devices. NORTH AMERICAN ROCKWELL CORP. 20 June, 1966, No. 59788/68. Heading H1K. The subject-matter of this Specification is included in Specification 1,155,722, but the claims relate to a process for joining semiconductor segments derived from two wafers of opposite conductivity types in a monolithic structure. One process involves producing a pattern of holes and a corresponding pattern of mesas in wafers respectively of opposite conductivity types, joining the wafers by engaging the mesas in the holes and depositing crystalline insulating material around the mesas, removing part of the mesad wafer to expose the insulating material and isolate the mesas and, as a separate operation, isolating segments of the apertured wafer by forming isolating channels, filling them with isolating material and then removing material from the face opposite the channels down to the isolating material therein. In an alternative process PN junctions or P + or N + diffused zones ...