High tilt angle plus twist drain extension implant for CHC lifetime improvement

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Polycrystalline silicon efuse and resistor fabrication in a metal replacement gate process

A method of fabricating an integrated circuit is disclosed (FIGS. 1 - 2 ). The method comprises providing a substrate ( 200 ) having an isolation region ( 202 ) and etching a trench in the isolation region. A first conductive layer ( 214 ) is formed within the trench. A first transistor having a first conductivity type (n-channel) is formed at a face of the substrate. The first transistor has a gate ( 216 ) formed of the first conductive layer. A second transistor having a second conductivity type (p-channel) is formed at the face of the substrate. The second transistor has a gate ( 224 ) formed of the first conductive layer. The method further comprises replacing the first conductive layer of the first transistor with a first metal gate ( 132 ) and replacing the first conductive layer of the second transistor with a second metal gate ( 134 ).

Partially disposed gate layer into the trenches

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

High tilt angle plus twist drain extension implant for chc lifetime improvement

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Transistors with dual wells

In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

Three Dimensional Three Semiconductor High-Voltage Capacitors

An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.

High tilt angle plus twist drain extension implant for chc lifetime improvement

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Transistors with dual wells

In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

Integrated circuit including vertical capacitors

In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Partially disposed gate layer into the trenches

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

Integrated circuit including vertical capacitors

In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

Selective deposition of doped silion-germanium alloy on semiconductor substrate

Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

Nitrogen based implants for defect reduction in strained silicon

A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

Nitrogen based implants for defect reduction in strained silicon

A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

High performance cmos transistors using pmd linear stress

Method for transistor gate dielectric layer with uniform nitrogen concentration

The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N 2 O which redistributes the incorporated species to produce a uniform nitrogen concentration.

Drive current improvement from recessed SiGe incorporation close to gate

A method ( 100 ) of forming a transistor includes forming a gate structure ( 106, 108 ) over a semiconductor body and forming recesses ( 112 ) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown ( 114 ) in the recesses, followed by forming sidewall spacers ( 118 ) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body ( 120 ) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

Transistors with dual wells

In some examples, a transistor (100') includes a first well (110) doped with a first-type dopant having a first concentration. The transistor (100') also includes: a gate oxide layer (170) on a portion of the first well (110); a gate layer (160) on the gate oxide layer (170); and a first segment (120) of a second well doped with the first-type dopant having a second concentration. The first segment (120) underlaps a first portion (121) of the gate layer (160). The transistor (100') also includes a source region (140) doped with a second-type dopant having a third concentration. The source region (140) is in the first segment (120). The transistor (100') further includes a drain region (150) doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

Transistors with dual wells

In some examples, a transistor includes a semiconductor layer having a first conductivity type and a first dopant concentration. A gate dielectric layer is between a gate electrode and the semiconductor layer. A first source/drain region is adjacent a first sidewall of the gate electrode and a second source/drain region is adjacent an opposite second sidewall of the gate electrode, the first and second source/drain regions having an opposite second conductivity type. A well region is located in the semiconductor layer and has the first conductivity type and a greater second dopant concentration. The well region underlies the first sidewall and the semiconductor layer extends to the gate electrode under the second sidewall of the gate electrode.

Method of fabricating semiconductors

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Integrated circuit including vertical capacitors

In some examples, an integrated circuit includes a first plate (167), a second plate (168), and a dielectric layer (262) disposed between the first plate (167) and the second plate (168). The first plate (167), the second plate (168) and the dielectric layer (262) are disposed on an isolation region (250) of the integrated circuit, and they form a vertical capacitor (252).

トランジスタゲートを製造する方法

(57)【要約】 【課題】 トランジスタゲートの重なり容量を減少する ため、ゲートに切欠を形成するのに、現在の方法は制御 性、再現性、信頼性が充分でない。従って、制御性、再 現性、信頼性に優れたトランジスタゲートの製造方法を 提供することが要望される。 【解決手段】 互いに酸化率の異なる第１、第２の層を 含む多層のゲート構造を形成し、熱酸化処理により第１ の層に切欠が形成されるようにして、切欠のあるトラン ジスタゲートを製造する。

Method of fabricating semiconductors

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Method of fabricating semiconductors

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.