SYSTEMS, METHODS, AND APPARATUS FOR INTEGRATED TUNING CAPACITORS IN CHARGING COIL STRUCTURE

Systems, methods, and apparatus are disclosed for power transfer including a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures, and a tuning capacitance located directly over the ferrite element in the low flux region.

Multi-supply synchronization for wireless charging

Certain aspects of the present disclosure are generally directed to apparatus and techniques for wirelessly charging a device. An exemplary method generally includes receiving, at a first wireless power transfer device, a synchronization signal indicative of a phase for generating a wireless charging field, determining an adjusted phase for generating the wireless charging field based, at least in part, on the received synchronization signal and one or more measurements taken at least one of the first wireless power transfer device or a second wireless power transfer device, wherein the one or more measurements are indicative of a phase difference between the first wireless power transfer device and the second wireless power transfer device, and generating, at the first wireless power transfer device, the wireless charging field with the adjusted phase.

Face living body detection system and method based on rPPG

The invention discloses a human face living body detection system and method based on rPPG, and belongs to the technical field of biological recognition. The method comprises the following steps: S10, acquiring a frame sequence of a facial region of interest; s20, on the basis of the facial region-of-interest frame sequence, predicting a human body facial pulse wave signal through a space-time convolutional network model; s30, performing frequency domain conversion on the predicted human face pulse wave signal and extracting multi-scale long-term frequency spectrum statistical characteristics; and S40, distinguishing the authenticity of the target face through the support vector machine model. According to the method, a lightweight space-time convolutional network is designed, a new learning mode is designed to train the model, a spectrum feature containing rich physiological information is designed and improved, the accuracy and the detection rate of in-vivo detection are greatly improved ...

Image enhancement method and image enhancement device

The invention discloses an image enhancement method and an image enhancement device, and belongs to the technical field of image processing. The image enhancement method comprises the following steps: acquiring a reverse image and enhancement parameters based on an original low-illumination image and brightness characteristics thereof; determining an atmospheric light value and an improved transmission rate based on the inverted image and the enhancement parameter; determining an inverted enhanced image based on the inverted image, the atmospheric light value and the improved transmission rate; and determining a low-illumination enhanced image based on the inverted enhanced image. According to the image enhancement method, enhancement processing of different degrees can be carried out based on the original low-illumination images in different scenes, the method is suitable for any low-illumination environment, the enhancement effect is good, and the universality and the image enhancement ...

Indicating soil additives for improving soil water infiltration and/or modulating soil water repellence

The present invention is related to a method for indicating soil additives for improving soil water infiltration and/or modulating soil water repellence, a corresponding arrangement and the use thereof.

Dicing mechanism for fruit and vegetable dicing machine and fruit and vegetable dicing machine

The invention relates to a dicing mechanism for a fruit and vegetable dicing machine and the fruit and vegetable dicing machine, the dicing mechanism comprises a cutter cylinder capable of rotating around the axis of the cutter cylinder, and the cutter cylinder is of a latticed structure with dicing meshes distributed on the whole; the cutter head is arranged at the end of the cutter cylinder and can rotate along with the cutter cylinder, the cutter head is provided with a slicing knife used for slicing food materials to be processed in the radial direction of the cutter head, and a flaky food material inlet is formed in the position, close to the slicing knife, of the cutter head; the extrusion roller is arranged in the knife cylinder in a mode of rotating around the axis of the extrusion roller, and in the rotating process of the knife cylinder, the peripheral wall of the extrusion roller can be matched with the dicing blade of the knife cylinder in an extrusion mode so that the sheet-shaped ...

Methods and apparatus for wirelessly transferring power

Aspects of this disclosure include an apparatus configured to and methods for the transfer of wireless power. The apparatus comprises a first coil enclosing a first area. The apparatus also comprises a second coil enclosing a second area different than the first area, the second coil positioned to be at least partially coplanar with the first coil. The apparatus further comprises a ferrite material and a third coil and a fourth coil each wound about the ferrite material, the third coil at least partially enclosed by the first coil and the fourth coil at least partially enclosed by the second coil.

Space-time range query method, system and equipment based on materialized view and medium

The invention relates to a spatio-temporal range query method, system and device based on a materialized view and a medium, and the method comprises the steps: obtaining a search request which comprises each piece of first to-be-matched data; according to the search request, searching each node in each hierarchy in the materialized view table for each piece of first storage data matched with each piece of first to-be-matched data as target matched data; wherein the materialized view table is a database for storing first storage data corresponding to a plurality of hierarchies, and each hierarchy corresponds to the first storage data of one category. The problems that current moving track data query is low in efficiency and slow in speed are solved.

Intelligent easel

The invention belongs to the technical field of easel, and relates to an intelligent easel. The drawing board comprises a supporting frame, a drawing board body, a water absorption mechanism and a turn-over mechanism. The drawing board is rotationally installed on the supporting frame through a fixing shaft. And drawing paper is laid on the drawing board. When the first arc-shaped plate slides along the T-shaped guide block, the first arc-shaped plate drives the first rotating roller to move towards the other side of the drawing board, so that the absorbent cotton is gradually lengthened, and in the process, the absorbent cotton is not in contact with the drawing paper, so that ink marks on the drawing paper can be prevented from being scratched by the absorbent cotton. When the end, provided with the first rotating roller, of the first arc-shaped plate is matched with the groove, the water absorption cotton covers the drawing paper, redundant ink on the drawing paper is absorbed, and the ...

Method and system for learning sepsis treatment strategy and storable medium

The invention discloses a sepsis treatment strategy learning method and system and a storable medium, and relates to the field of medical reinforcement learning. The method comprises the following steps: screening medical information of sepsis patients in an intensive care information database; preprocessing the medical information of the sepsis patient, and dividing the medical information of the sepsis patient into a training set and a test set; performing statistical processing on the training set to obtain a mapping relation between a treatment strategy and a healing condition of the sepsis patient; performing weight training on the neural network according to the mapping relation between the treatment strategy and the post-healing condition to obtain a medical treatment model; and optimizing a sepsis treatment scheme based on the medical treatment model to obtain an optimal sepsis treatment strategy. The invention discloses a prediction model capable of possibly guiding liquid treatment ...

SYSTEMS, METHODS, AND APPARATUS FOR INTEGRATED TUNING CAPACITORS IN CHARGING COIL STRUCTURE

Evenly throw wide LED fluorescent tube of angle that shines

The utility model relates to a LED the fluorescent tube, in particular to evenly throw wide LED fluorescent tube of angle that shines. The utility model provides an evenly throw wide LED fluorescent tube of angle that shines through covering 13 departments of (4) bottom surface diameter distance with the illuminating source setting at plastic double -colored PC, has adopted the luminous mode of the LED light source that sinks, and then the invention purpose of the luminous angle of fluorescent tube to 144 that has realized enlarging, has effectively solved side water wave phenomenon, makes the plastic double -colored PC cover surface light -emitting even. The utility model discloses have that the structure integrate degree is high, the electric property stable, the design of nos stroboscopic, radiationless, do not have get an electric shock dangerous, the even angle of light -emitting is big, packaging technology simple, suitable mass production, the sexual valence relative altitude extensively ...

Traditional Chinese medicine composition for treating sepsis and preparation method thereof

The invention belongs to the technical field of traditional Chinese medicines, and provides a traditional Chinese medicine composition for treating sepsis and a preparation method thereof. The traditional Chinese medicine composition for treating sepsis is prepared from the following raw materials in parts by weight: 50 to 60 parts of radix scutellariae, 45 to 55 parts of radix codonopsis, 40 to 50 parts of radix notoginseng, 40 to 50 parts of radix paeoniae rubra, 35 to 45 parts of semen lepidii, 30 to 40 parts of gypsum, 30 to 40 parts of radix et rhizoma rhei, 25 to 35 parts of fructus trichosanthis, 25 to 35 parts of semen armeniacae amarae, 20 to 30 parts of stiff silkworm, 20 to 30 parts of cicada slough, 15 to 25 parts of rhizoma curcumae longae, 15 to 20 parts of cortex moutan, 10 to 15 parts of radix rehmanniae and 8 to 12 parts of rhizoma coptidis. The traditional Chinese medicine composition provided by the invention is safe, reliable, quick in effect, simple in preparation process ...

Machining method for Mecanum roller

The invention discloses a machining method for a Mecanum roller. The machining method comprises the following steps: a) machining to form a hollow roller core; b) coating a polyurethane rubber layer outside the hollow roller core; c) carrying out machining on the polyurethane rubber layer, so as to enable the outer contour line of the polyurethane rubber to be consistent with the outer contour line of the roller core. The machining method for the Mecanum roller provided by the invention coats the polyurethane rubber layer outside the roller core through a manner of rubber coating; moreover, the roller core and the rubber layer are cut and processed respectively; the shape curve of the roller is similar to that of the roller core, so that the thickness of the rubber layer is uniform; when the roller moves under heavy shock loads, the stress exerted on the roller is uniform and the elastic deformation of the rubber layer is also stable and uniform, therefore, the service life of the roller ...

METHODS AND APPARATUS FOR THERMAL DISSIPATION IN VEHICLE PADS FOR WIRELESS POWER TRANSFER APPLICATIONS

Methods and apparatuses for thermal dissipation in vehicle pads for wireless power transfer applications are provided. In some implementations, an apparatus for wirelessly receiving charging power is provided. The apparatus comprises at least one receive coil configured to wirelessly receive the charging power. The apparatus further comprises a plurality of electrical components configured to convert the charging power to a direct current. The apparatus further comprises a primary heat sink comprising a plurality of fins configured to dissipate heat generated by the plurality of electrical components. The plurality of fins are disposed adjacent to the plurality of electrical components. The apparatus further comprises at least one thermally conductive structure configured to physically connect at least some of the plurality of electrical components to the primary heat sink. 1. An apparatus for wirelessly receiving charging power , the apparatus comprising:at least one receive coil configured to wirelessly receive the charging power;a plurality of electrical components configured to convert the charging power to a direct current;a primary heat sink comprising a plurality of fins configured to dissipate heat generated by the plurality of electrical components, the plurality of fins disposed adjacent to the plurality of electrical components; andat least one thermally conductive structure configured to physically connect at least some of the plurality of electrical components to the primary heat sink.2. The apparatus of claim 1 , wherein the primary heat sink comprises a recessed portion configured to support the plurality of electrical components.3. The apparatus of claim 2 , further comprising a secondary heat sink configured to cover the recessed portion and thermally connect the at least one thermally conductive structure to the primary heat sink.4. The apparatus of claim 2 , wherein the recessed portion defines a hole configured to accommodate a termination socket ...

INDICATING SOIL ADDITIVES FOR IMPROVING SOIL WATER INFILTRATION AND/OR MODULATING SOIL WATER REPELLENCE

The present invention is related to a method for indicating soil additives for improving soil water infiltration and/or modulating soil water repellence, a corresponding arrangement and the use thereof.

Intelligent food processor and control method thereof

The invention relates to an intelligent food processor and a control method thereof. The food processor comprises a machine body; the at least two functional modules are used for processing food materials, and each functional module can be detachably placed on the machine body and taken down from the machine body; the recognition device is used for recognizing whether the corresponding function module is placed in place on the machine body or not; and the controller is electrically connected with the recognition device and can be configured to control the food processor to be switched to an operation mode matched with the function module according to the received position signal that the corresponding function module is placed in place on the machine body. After different functional modules are placed on the machine body, the recognition device on the machine body can recognize whether the functional modules are placed in place or not and the models of the functional modules, so that the ...

Carbon-clad spinel lithium titanate material, production method and application thereof

The invention relates to a carbon-clad spinel lithium titanate Li4MxTiyO12 material used as a lithium ion battery cathode material, a production method and an application thereof. The cathode material is spinel type Li4MxTiyO12 or a mono or multiple other metallic element-doped compound Li4MxTiyO12. A synthetic method comprises the following steps: mixing an organic titanium solution and lithium salt liquid to prepare sol; aging the sol to obtain a lithium titanate gel predecessor; calcining the gel predecessor, and being conversed to the spinel lithium titanate material with nano size; or comprises the following steps: dispersing the prepared lithium titanate in a carbon source organic solution, removing the solution, and calcining to obtain the spinel lithium titanate/carbon composite material with nano size. Compared with lithium titanate Li4Ti5O12 prepared by a conventional method, the spinel lithium titanate material has better multiplying power characteristic, when the spinel lithium ...

Grey fault detection positioning method and system based on hybrid in-band network telemetering

The invention provides a gray fault detection positioning method and system based on hybrid in-band network telemetering, and relates to the field of fault detection. Comprising the following steps: a server collects hop-by-hop telemetry information of a passive INT detection packet, carries out primary detection on whether a fault exists, and sends a secondary detection instruction of a fault path to a controller of a virtual SDN network; the controller sends an active INT detection packet to the server, and secondary detection is carried out on the path with the fault in the primary detection; the source server reroutes the data traffic of the path information which really has the fault; the controller sets priorities for all path information with real faults, and compares the paths according to the priorities to obtain fault positions; and the controller feeds back the fault position to the server, and the server searches all paths related to the fault position and ages in advance. According ...

Method and device for processing image in video

The invention provides a method and a device for processing an image in a video, which can reduce the brightness flicker of each frame of image contained in the video. The method comprises the steps that after brightness adjustment is carried out on each frame of image included in a video, a reference frame and a to-be-processed target frame in each frame of image are determined based on the shooting moment of each frame of image, and the shooting moment of the reference frame is earlier than the shooting moment of the target frame; determining first brightness of the reference frame and second brightness of the target frame; determining the type of the target frame based on the first brightness and the second brightness; and if the type of the target frame is the exposure abnormal frame, brightness adjustment processing is performed on the exposure abnormal frame, and the brightness adjustment processing comprises brightness correction processing and image enhancement processing.

Systems, methods, and apparatus for integrated tuning capacitors in charging coil structure

Systems, methods, and apparatus are disclosed for power transfer including a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures, and a tuning capacitance located directly over the ferrite element in the low flux region.

Computing power distribution method, system and equipment for sensor network and medium

The invention discloses a computing power distribution method, system and device for a sensor network and a medium, and relates to the technical field of ocean observation and monitoring sensor networks, the computing power distribution method comprises the following steps: determining a plurality of available nodes according to a current ocean computing power network, the ocean computing power network comprises a plurality of ocean nodes, and each available node corresponds to one ocean node; task information is obtained, and a task time delay model corresponding to the task information is determined according to the data volume corresponding to the task information and the computing power information corresponding to each available node; the task time delay model is used for determining a total time delay for executing the task information according to an unloading scheme determined by a data volume corresponding to the task information; the task time delay model is solved, a target unloading ...

Hybrid in-band network telemetering task transmission method and system

The invention relates to a hybrid in-band network telemetering task transmission method and system. The hybrid in-band network telemetering task transmission method comprises the following steps: acquiring a link topological graph; according to the historical communication task, determining a plurality of first target nodes from each task node and a first target link corresponding to each first target node; taking any one first target node as a first current node, and if the first current node cannot be communicated with other first target nodes except the first current node, determining a second target link from the links according to each first target node and each link; determining a transmitting probe and a receiving probe according to the network telemetering task; and determining a data transmission path between the transmitting probe and the receiving probe according to the transmitting probe, the receiving probe, each first target node, each first target link and each second target ...

De-solvent method with hot water subsiding

A process for desolventization of high-molecular polymer features that the solution of high-molecular polymer is added to hot water containing trace quantity of the same polymer powder. During hot water subsiding, said polymer forms uniform powdery particles and solvent is removed.

Encrypted malicious flow identification method and device based on spatial-temporal characteristics and attention mechanism

The invention relates to an encrypted malicious flow identification method and device based on spatial-temporal characteristics and an attention mechanism, and the method comprises the steps: carrying out the data preprocessing of an original data flow, and obtaining an initial data flow; establishing a traffic trajectory topological graph according to the initial data stream; key node features are extracted from the flow trajectory diagram, and a key node feature set is obtained; establishing a node-level spatial attention feature map by using the key node feature set; extracting spatial features from the node-level spatial attention feature map to obtain a spatial feature set; extracting time features of the spatial feature set from the spatial feature set to obtain a time feature set; fusing the space feature set and the time feature set to obtain a space-time feature set; carrying out weight distribution on the space-time feature set to obtain a model training feature set; and training ...

Wind power boosting ship model test device and optimal rotating speed auxiliary decision-making method

The invention discloses a wind power boosting ship model test device and an optimal rotating speed auxiliary decision-making method, the test device comprises a fan, a ship model, a wind power boosting rotor and a connecting firmware, and the connecting firmware is used for connecting the wind power boosting rotor with the ship model; the wind power boosting rotor comprises an upper rotor and a lower connecting structure, the connecting firmware is provided with a fixing structure corresponding to the lower connecting structure, and the wind power boosting rotor is connected with a driving motor and a sensor for collecting lift force and resistance. The optimal rotating speed auxiliary decision-making method of the wind power boosting rotor developed by the device can provide rotating speed auxiliary decision-making for the wind power boosting rotor under different navigational speed and wind speed conditions, and the energy-saving effect of the ship wind power boosting device is utilized ...

Pipeline structure matched with flow redox battery

The invention provides a pipeline structure matched with a flow redox battery. The flow redox battery comprises a galvanic pile, a positive liquid tank, a negative liquid tank, a positive main loop and a negative main loop, wherein the positive liquid tank is connected with the galvanic pile through the positive main loop, and the negative liquid tank is connected with the galvanic pile through the negative main loop. The pipeline structure matched with the flow redox battery further comprises a galvanic pile SOC (System On Chip) monitoring bypass, wherein the galvanic pile SOC monitoring bypass comprises a potentiostat and two adjusting valves, wherein two ends of the potentiostat are respectively connected with the positive main loop and the negative main loop through the adjusting valves. According to the technical scheme provided by the invention, a characteristic of multiple functions of the pipeline structure is provided specific to the defects of poor technology, single function ...

Method for large-area shellfish replacement of quay crane by intelligent port horizontal transport vehicle

The invention discloses a method for large-area shellfish replacement of a quay crane by an intelligent port horizontal transport vehicle, which belongs to the technical field of ports and comprises the following steps: receiving movement information sent by the quay crane and used for indicating the movement direction and distance of the quay crane; determining the current position of the quay crane according to the movement information and the original position of the quay crane; according to the current position of the quay crane, determining a loading and unloading position for parking the horizontal transport vehicle; a driving instruction is sent to the horizontal transport vehicle, and a signal instruction is sent to the quay crane; receiving feedback information sent by the horizontal transport vehicle, wherein the feedback information comprises a receiving signal received by a signal receiving device carried on the horizontal transport vehicle; and when it is detected that the ...

Production process for intelligent duct piece of subway shield tunnel

The invention belongs to the field of rail transit shield segments, and particularly discloses a subway shield tunnel intelligent segment production process. Comprising the following steps: S1, cleaning, assembling and checking a mold; s2, a release agent is brushed, and a pre-embedded sliding groove is installed; s3, putting the steel reinforcement framework into a mold; s4, junction box installation and cable laying; s5, carrying out hidden acceptance; s6, pipe piece pouring; s7, statically maintaining the duct pieces; s8, segment natural curing or segment steam curing; s9, duct piece demolding and duct piece marking are conducted; s10, segment water curing and spraying curing are carried out; s11, performing segment type inspection; the flexible earth pressure gauge is installed in two steps, an embedded part for fixing the flexible earth pressure gauge is installed before the duct piece is poured, and the flexible earth pressure gauge is installed before the duct piece leaves the factory ...

Encrypted malicious traffic identification method and system for multi-class unbalanced data characteristics

The invention discloses an encrypted malicious traffic identification method and system for multi-class unbalanced data characteristics, and the method comprises the steps: carrying out the preprocessing of network malicious traffic data, and obtaining a feature image of the malicious traffic; a malicious traffic sample is obtained through the feature image of the malicious traffic and a trained malicious traffic sample generation model, self-attention modules are added to a generator and a discriminator of the malicious traffic sample generation model, and the self-attention modules take the feature image output by the convolutional layer as input to generate a malicious traffic sample; obtaining an attention map of the feature map input into the self-attention module, determining a self-attention feature map according to the attention map, carrying out weighted summation on the self-attention feature map and the feature map input into the self-attention module to obtain a feature map ...

Determining method of net hanging position at working face retracement stage under mine high-intensity exploiting

The invention provides a determining method of a net hanging position at a working face retracement stage under mine high-intensity exploiting. By analyzing basic parameters such as working face periodic weighting step pitch and weighting position prediction parameters and flexible net length, three different computing expressions are established, according to the comparing results of the average periodic weighting step pitch, the weighting persistence length, the flexible net length and the minimum net hanging position, the average periodic weighting step pitch and the distance between a next periodic weighting starting position and a main retracement channel are put into a corresponding computing expression, and reasonable hanging net length is computed. According to the method, scientific and reasonable determining of the hanging net position is achieved, the fact that large weighting does not exist during fully-mechanized coal mining working face net hanging is guaranteed, the fact ...

Dicing mechanism for fruit and vegetable dicing machine and fruit and vegetable dicing machine

The invention relates to a dicing mechanism for a fruit and vegetable dicing machine and the fruit and vegetable dicing machine, and the dicing mechanism comprises a dicing knife cylinder which is arranged on a machine body in a manner of rotating around the axis of the dicing knife cylinder; the extrusion roller is located outside the dicing knife cylinder and can be arranged on the machine body in the mode of rotating around the axis of the extrusion roller, the axial direction of the extrusion roller is basically parallel to the axial direction of the dicing knife cylinder, and the extrusion roller can extrude the sheet-shaped food materials towards the interior of the dicing knife cylinder in the rotating process so that the diced food materials can be formed in the dicing knife cylinder. When falling between the dicing knife cylinder and the extrusion roller, sheet-shaped food materials can be extruded in time to form diced food materials, material accumulation is not prone to occurring ...

MULTI-SUPPLY SYNCHRONIZATION FOR WIRELESS CHARGING

Certain aspects of the present disclosure are generally directed to apparatus and techniques for wirelessly charging a device. An exemplary method generally includes receiving, at a first wireless power transfer device, a synchronization signal indicative of a phase for generating a wireless charging field, determining an adjusted phase for generating the wireless charging field based, at least in part, on the received synchronization signal and one or more measurements taken at least one of the first wireless power transfer device or a second wireless power transfer device, wherein the one or more measurements are indicative of a phase difference between the first wireless power transfer device and the second wireless power transfer device, and generating, at the first wireless power transfer device, the wireless charging field with the adjusted phase.

Traditional Chinese medicine composition for treating olfactory and/or gustatory abnormality caused by viral respiratory tract infection as well as preparation method and application of traditional Chinese medicine composition

The invention provides a traditional Chinese medicine composition for treating olfactory and/or gustation abnormality caused by viral respiratory tract infection and a preparation method and application thereof, and belongs to the technical field of traditional Chinese medicines. The traditional Chinese medicine composition for treating olfactory and/or gustation abnormality caused by viral respiratory tract infection is prepared from the following medicines in parts by weight: 9-12 parts of almond, 9-15 parts of burdock, 9-15 parts of platycodon grandiflorum and 9-15 parts of cicada slough. The traditional Chinese medicine composition disclosed by the invention can effectively relieve olfaction and/or taste abnormality caused by viral respiratory tract infection, and is quick in effect and remarkable in curative effect. By improving olfaction and taste functions of a patient, the appetite of the patient can be effectively improved, the immunity of the patient is enhanced, the virus resistance ...

Design method of nonlinear dynamic controller for trajectory tracking of manipulator system

The invention discloses a nonlinear dynamic controller design method for manipulator system trajectory tracking, comprising a manipulator system and a Beckhoff controller, and the manipulator system comprises a motion control unit, a servo drive unit and a mechanical structure unit. The controller developed in the invention is simple in structure, free of excessive control parameters, convenient to adjust and easy to develop, and compared with the existing method, the method has two large differences, one is designed under a nonlinear control framework, and it is ensured that control output can track an expected speed within a short time; and 2, a self-adaptive bandwidth adjustment mechanism is adopted, and the most suitable bandwidth value can be automatically derived through calculation of a mathematical formula according to the speed deviation value instead of selection by experience, so that the adaptability of the controller is improved, and the problem of excessive energy consumption ...

Malicious traffic identification method and system based on data enhancement and feature fusion

The invention provides a malicious traffic identification method and system based on data enhancement and feature fusion, and relates to the field of network security, and the method comprises the steps: carrying out the preprocessing, feature selection and traffic balance of an original traffic data set, and obtaining a training set after data enhancement; based on multi-head attention, constructing a malicious traffic classification model for feature extraction and feature fusion; obtaining a final malicious traffic classification model through parameter optimization and model training; inputting to-be-identified traffic into the malicious traffic classification model, and outputting a classification result; a malicious traffic classification model capable of identifying network traffic, automatically extracting features and solving the problem of insufficient data availability is designed, redundant features are accurately filtered out by using a feature selection method, various traffic ...

Social perception caching method and system suitable for wireless network

The invention provides a social perception caching method and system suitable for a wireless network, and relates to the technical field of wireless communication, and the method comprises the steps: dividing users and equipment into different groups according to a physical graph and a social relation graph in an edge user network region, and obtaining a social perception communication graph; judging a potential connection object in an area where the terminal user is located through the social perception communication graph, screening a user set of trusted users through a trust delivery mechanism, and taking the user set of the trusted users as a cache node to obtain cache content; after the cached content is obtained, a cached content recommendation model based on federal element learning and deep learning predicts the user content preference, the prediction result is cached on the selected user used as the cache node, and the cached content is distributed for the preference of the user ...

REDUCING MECHANISM AND HARMONIC DRIVE THEREOF

A harmonic drive includes a circular rigid internal gear, a circular flexible external gear, a wave generator, a cover, and a fan blade. The circular flexible external gear is disposed in the circular rigid internal gear, and the wave generator has at least one through hole and is disposed in the circular flexible external gear. The cover and the fan blade are respectively disposed at two opposite sides of the wave generator, and the cover is located in the circular flexible external gear. The cover and the wave generator form an air chamber together, and the through hole and an air flow opening are respectively in communication with the air chamber. The wave generator operates to drive the fan blade to operate. The fan blade rotates to generate an air flow, thus performing heat dissipation on the harmonic drive. 1. A harmonic drive , having at least one air flow opening , the harmonic drive comprising:a circular rigid internal gear;a circular flexible external gear, disposed in the circular rigid internal gear, wherein the circular flexible external gear is a cup-shaped body, and the circular flexible external gear has a cup bottom end;a wave generator, having at least one through hole, and disposed in the circular flexible external gear;a cover, disposed in the circular flexible external gear, and disposed between the cup bottom end and the wave generator, wherein the cover and the wave generator form an air chamber together, and the through hole and the air flow opening are respectively in communication with the air chamber; anda fan blade, wherein the fan blade and the cover are respectively disposed at two opposite sides of the wave generator;wherein, when an external force drives the wave generator and the fan blade to operate, the wave generator forces the circular flexible external gear to perform elastic deformation to be partially engaged with the circular rigid internal gear, such that a part of the circular rigid internal gear engaged with the circular ...

DATA CENTER

A data center is provided. The data center includes a plurality of racks, a container management network and a container management module. Each of the racks includes a rack management module and a plurality of server modules. The rack management module is used for receiving an operation status of the corresponding server module. The container management network is connected to the rack management module and the server module. The container management module is connected to each rack through container management network to receive the operation status for controlling and managing each rack according to the operation status. 1. A data center , comprising:a plurality of racks each of which comprises at least one rack management module and a plurality of server modules, wherein the rack management module is used for receiving an operation status of the server modules;a container management network connected to the rack management modules and the server modules; anda container management module connected to each of the racks through the container management network to receive the operation status for controlling and managing each of the racks according to the operation status.2. The data center of claim 1 , wherein a number of the container management module is at least two which are redundant to each other.3. The data center of claim 1 , wherein the container management module provides a user network management platform.4. The data center of claim 1 , wherein each of the server modules is connected to an external Ethernet network through a working management network which is independent of the rack management network.5. The data center of claim 1 , wherein the container management module is a container management host.6. The data center of claim 1 , wherein a number of the at least one rack management modules of each of the racks is at least two which are redundant to each other.7. The data center of claim 6 , wherein each of the server modules of each of the racks ...

METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR

An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10. 1. A metal gate electrode for a field effect transistor comprising:a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; andan upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.2. The metal gate electrode of claim 1 , wherein the lower portion is substantially U-shaped.3. The metal gate electrode of claim 1 , wherein a ratio of a maximum height of the lower portion to a minimum height of the upper portion is from 0.1 to 0.9.4. The metal gate electrode of claim 1 , wherein the first metal material comprises a material selected from a group of TiN claim 1 , TaN claim 1 , and WN.5. The metal gate electrode of claim 1 , wherein the upper portion is substantially T-shaped.6. The metal gate electrode of claim 1 , wherein the second metal material comprises an N-work-function metal.7. The metal gate electrode of claim 6 , wherein the N-work-function metal comprises a metal selected from a group of Ti claim 6 , ...

Method of forming a self-aligned contact opening in MOSFET

A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter. 1. A method of forming an opening on a semiconductor substrate having a first projecting portion with a first height relative to the semiconductor substrate and a second projecting portion with a second height relative to the semiconductor substrate , wherein the first projecting portion has a first sidewall and a second sidewall , and the second projecting portion has a third sidewall and a fourth sidewall , wherein the second sidewall and the third sidewall are between the first sidewall and the fourth sidewall , the method comprising the steps of:a. forming a first layer over the semiconductor substrate extending over the first projecting portion and the second projecting portion;b. forming a first spacer along the second sidewall and a second spacer along the third sidewall; andc. forming a first opening on the semiconductor substrate between the first projecting portion and the second projecting portion by removing the portion of the first layer between the first spacer and the second spacer, wherein the remaining portion of the first layer along the second sidewall forms a first L-type shape, and the remaining portion the first layer along the third sidewall forms a second L-type shape.2. The method according to claim ...

TRENCH TYPE POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME

The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate. 1. A trench type power transistor device , comprising:a semiconductor substrate of a first conductivity type, having an active region and a peripheral region, and the semiconductor substrate having at least one first trench; a first gate conductive layer, disposed in the first trench;', 'a gate insulating layer, disposed in the first trench and between the first gate conductive layer and the semiconductor substrate;', 'a doped body region of a second conductivity type, disposed in the semiconductor substrate at a side of the first trench; and', 'a doped source region of the first conductivity type, disposed in the doped body region;, 'at least one transistor cell, disposed in the active region, and the transistor cell comprisinga gate metal layer, disposed on the semiconductor substrate in the peripheral region;a source metal layer, disposed on the semiconductor substrate in the active region; anda second gate conductive layer, disposed between the first gate conductive layer and the source metal layer, wherein the second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from ...

SERVER RACK SYSTEM

A server rack system includes a management network switch, servers, a power supply unit, fan units, and an integrated management module (IMM). Management network ports of baseboard management controllers (BMCs) of the servers are connected to the management network switch. A management network port of the power supply unit is connected to the management network switch. Management network ports of the fan units are connected to the management network switch. A management network port of the IMM is connected to the management network switch. The IMM communicates with the BMCs of the servers, the fan units, and the power supply unit through the management network switch, so as to obtain operation states of the servers, the fan units and the power supply unit, or control operations of the servers, the fan units and the power supply unit. 1. A server rack system , comprising:a first network switch, coupled to a management network;multiple servers, each comprising a baseboard management controller (BMC), wherein the BMCs each comprises a management network port, and the management network ports are connected to the first network switch;at least one power supply unit, wherein a management network port of the power supply unit is connected to the first network switch;multiple fan units, each comprising a management network port, wherein the management network ports of the fan units are connected to the first network switch; andan integrated management module (IMM), wherein a management network port of the IMM is connected to the first network switch, the 11M communicates with the BMCs of the servers, the fan units, and the power supply unit through the first network switch, so as to obtain operation states of the servers, the fan units, and the power supply unit, or control operations of the servers, the fan units, and the power supply unit.2. The server rack system according to claim 1 , wherein the first network switch is an Ethernet switch.3. The server rack system ...

Server rack system for managing fan rotation speed

A server rack system for managing a fan rotation speed is provided, and the system includes: at least one first network switch, multiple servers, at least one fan unit, at least one fan control unit and an Integrated Management Module (IMM). Each of the servers has at least one temperature detecting element, and the temperature detecting element detects and obtains temperature information related to multiple servers, in which the temperature information is uploaded to a management network. The fan control unit is connected to the fan unit. The IMM has a management network port connected to the management network, obtains the temperature information through the management network, then generates a control command according to the temperature information, and transmits the control command to the fan control unit through the management network. The fan control unit adjusts the rotation speed of the fan unit according to the control command.

SERVER RACK SYSTEM

A server rack system includes a communication module, multiple internal devices, and an integrated management module (IMM). The internal devices are coupled to the communication module. The IMM is coupled to the communication module and communicates with the internal devices through the communication module. The IMM is pre-stored with a correspondence relationship between marker information, identification information, and asset numbers of the internal devices. In operation of the system, the IMM reads the identification information of the internal devices through the communication module, and obtains a correspondence relationship between the marker information and asset numbers of the internal devices from the correspondence relationship according to the identification information to thereby perform asset management of the internal devices. 1. A server rack system comprising:a communication module;a plurality of internal devices within the rack, the internal devices coupled to the communication module; andan integrated management module (IMM) coupled to the communication module and communicating with the internal devices through the communication module, the IMM being pre-stored with a correspondence relationship between marker information, identification information, and asset numbers of the internal devices, wherein, in operation of the system, the IMM reads the identification information of the internal devices through the communication module, and obtains a correspondence relationship between the marker information and asset numbers of the internal devices from the correspondence relationship pre-stored in the IMM according to the identification information to thereby perform asset management of the internal devices.2. The server rack system according to claim 1 , wherein the identification information comprises serial numbers of the internal devices claim 1 , and the correspondence relationship pre-stored in the IMM is a correspondence relationship between the ...

SERVER RACK SYSTEM

A server rack system includes a network switch, an Integrated Management Module (IMM) and in-rack apparatuses. The in-rack apparatuses and the IMM are connected to ports of the network switch respectively according to a preset correlation between in-rack locations and the ports of the network switch. The IMM pre-stores a correlation between identification information of the in-rack apparatuses, the in-rack locations and the ports. When the system is in operation, the IMM obtains a correlation between Media Access Control (MAC) addresses of the in-rack apparatuses and the ports from the network switch, and obtains a correlation between the identification information, the in-rack locations and the MAC addresses according to the correlation between the identification information, the in-rack locations, and the ports. The IMM obtains an Internet Protocol (IP) address corresponding to an MAC address, and uses the IP address to communicate with an in-rack apparatus in a specific rack location. 1. A server rack system , comprising:a network switch, wherein the network switch is coupled to a management network and comprises a plurality of management network ports;a plurality of in-rack apparatuses, located in different locations in the server rack system respectively and each comprising a management network port, wherein the in-rack apparatuses are connected to the management network ports of the network switch respectively according to a preset correlation between identification information of the in-rack apparatuses, the in-rack locations and the management network ports of the network switch; andan Integrated Management Module (IMM), wherein a management network port of the IMM is connected to the network switch, the IMM pre-stores the correlation between the identification information of the in-rack apparatuses, the in-rack locations and the management network ports of the network switch; when the system is in operation, the IMM obtains a correlation, which is generated ...

ENTRUSTED MANAGEMENT METHOD FOR A PLURALITY OF RACK SYSTEMS

An entrusted management method for a plurality of rack systems is provided, which includes the following steps. The rack systems are provided, in which each rack system respectively includes an integrated management module (IMM) and a plurality of internal rack devices. The rack systems are distributed into at least one rack group, and one of a plurality of IMMs in each rack group is selected to serve as a primary IMM. The primary IMM is connected to other IMMs through a network, and performs a synchronous configuration procedure to back up a plurality of pieces of configuration information of the other IMMs in the rack group. When an anomaly occurs in a specific IMM or the specific IMM submits an entrustment request, the primary IMM manages, through the network, internal rack devices originally managed by the specific IMM. 1. An entrusted management method for a plurality of rack systems , comprising:providing the rack systems, wherein each rack system respectively comprises an integrated management module (IMM) and a plurality of internal rack devices, and the IMMs respectively manage the internal rack devices through a network;distributing the rack systems into at least one rack group, and selecting one of the IMMs in each rack group to serve as a primary IMM;the primary IMM being connected to other IMMs through the network, and performing a synchronous configuration procedure to back up a plurality of pieces of configuration information of the other IMMs in the rack group; andwhen an anomaly occurs in a specific IMM or the specific IMM submits an entrustment request, the primary IMM managing, through the network, the internal rack devices originally managed by the specific IMM.2. The entrusted management method according to claim 1 , wherein the configuration information comprises a network protocol address of each of the IMMs claim 1 , and a plurality of peripheral addresses and a plurality of pieces of configuration setting information of each of the internal ...

METHOD FOR MONITORING A PLURALITY OF RACK SYSTEMS

A method for monitoring a plurality of rack systems is provided, which includes the following steps. The rack systems are provided, in which each rack system includes an integrated management module (IMM) and a plurality of servers, and the IMM is communicatively connected to the servers and manages and controls the servers. The rack systems are distributed into at least one rack system group, in which each rack system group includes a first rack system and a second rack system, and the first rack system and the second rack system respectively include a first IMM and a second IMM. The first IMM and the second IMM are communicatively connected, monitor each other, and judge whether an anomaly occurs in each other. When the first IMM judges that an anomaly occurs, the first IMM sends a warning message including the anomaly of the second rack system. 1. A method for monitoring a plurality of rack systems , comprising:providing the rack systems, wherein each rack system comprises an integrated management module (IMM) and a plurality of servers, and the IMM is communicatively connected to the servers and manages and controls the servers;distributing the rack systems into at least one rack system group, wherein each rack system group comprises a first rack system and a second rack system, and the first rack system and the second rack system respectively comprise a first IMM and a second IMM;the first IMM and the second IMM being communicatively connected, monitoring each other, and judging whether an anomaly occurs in each other; andwhen the first IMM judges that an anomaly occurs, sending a warning message comprising the anomaly of the second rack system.2. The monitoring method according to claim 1 , further comprising:when the first IMM judges that the anomaly occurs, the first IMM detecting a communication link from the first IMM to the second IMM to generate a detection result.3. The monitoring method according to claim 2 , wherein in the first rack system claim 2 , ...

METHOD FOR MONITORING A PLURALITY OF RACK SYSTEMS

A method for monitoring a plurality of rack systems is provided, which includes the following steps. The rack systems are provided, in which each rack system includes an integrated management module (IMM) and a plurality of servers. The IMM is communicatively connected to the servers in each rack system and manages and controls the servers. The rack systems are distributed into at least one rack group, and one of the IMMs in each rack group is selected to serve as a primary IMM, in which the IMMs in each rack group are communicatively connected to each other. The primary IMM monitors other IMMs than the primary IMM in the corresponding rack group. When an anomaly occurs in one of the other IMMs, the primary IMM sends a warning message including the abnormal IMM. 1. A method for monitoring a plurality of rack systems , comprising:providing the rack systems, wherein each rack system comprises an integrated management module (IMM) and a plurality of servers, and the IMM is communicatively connected to the servers and manages and controls the servers;distributing the rack systems into at least one rack group, and selecting one of the IMMs in each rack group to serve as a primary IMM, wherein the IMMs in each rack group are communicatively connected to each other;the primary IMM monitoring other IMMs than the primary IMM in the corresponding rack group; andwhen an anomaly occurs in one of the other IMMs, the primary IMM sending a warning message comprising the abnormal IMM.2. The monitoring method according to claim 1 , further comprising:selecting another of the IMMs in each rack group to serve as a secondary IMM;the secondary IMM monitoring other IMMs than the secondary IMM in the corresponding rack group; andwhen an anomaly occurs in one of the other IMMs, the secondary IMM sending the warning message comprising the abnormal IMM.3. The monitoring method according to claim 2 , further comprising:if the abnormal IMM detected by the secondary IMM is the primary IMM, ...

COMPUTER SYSTEM

A computer system including a central processing unit (CPU), a chipset connected to the CPU, a baseboard management controller (BMC) connected to the chipset, and a basic input/output system (BIOS) unit connected to the BMC is provided. The BMC switches a connection mode which the BMC connecting to the BIOS unit between a local mode and a bypass mode. The BIOS unit communicates with the chipset directly when the connection mode is switched to the bypass mode. When reading a BIOS information of the BIOS unit is needed, the BMC switches the connection mode to the local mode, communicates with the BIOS unit directly and read the BIOS information directly. 1. A computer system , comprising:a central processing unit;a chipset, connected to the central processing unit;a baseboard management controller, connected to the chipset; anda basic input/output system unit, connected to the baseboard management controller,wherein the baseboard management controller switches a connection mode of the baseboard management controller with the basic input/output system unit between a local mode and a bypass mode, andwhen in the bypass mode, the basic input/output system unit communicates with the chipset directly, andwhen reading a basic input/output system information is needed, the baseboard management controller communicates with the basic input/output system unit directly and directly reads the basic input/output system information from the basic input/output system unit.2. The computer system according to claim 1 , wherein when finish reading the basic input/output system information claim 1 , the baseboard management controller switches the connection mode with the basic input/output system unit to the bypass mode.3. The computer system according to claim 1 , wherein the basic input/output system unit is a flash memory.4. The computer system according to claim 1 , wherein a process of the baseboard management controller switching between the local mode and the bypass mode and ...

COMPUTER SYSTEM AND METHOD FOR UPDATING BASIC INPUT/OUTPUT SYSTEM THEREOF

A computer system including a central processing unit (CPU), a chipset connected to the CPU, a baseboard management controller (BMC) connected to the chipset, and a basic input/output system (BIOS) unit connected to the BMC is provided. The BMC switches a connection mode which the BMC connecting to the BIOS unit between a local mode and a bypass mode. The BIOS unit communicates with the chipset directly, when the connection mode is switched to the bypass mode. The BMC switches the connection mode from the bypass mode to the local mode, when the BIOS unit should be updated. Then, the BMC communicates with the BIOS unit directly, and the BIOS updating file is written into the BIOS unit. 1. A computer system , comprising:a central processing unit;a chipset, connected to the central processing unit;a baseboard management controller, connected to the chipset; anda basic input/output system unit, connected to the baseboard management controller,wherein the baseboard management controller switches a connection mode of the baseboard management controller with the basic input/output system unit between a local mode and a bypass mode, when in the bypass mode, the basic input/output system unit communicates with the chipset directly, andwhen the basic input/output system unit is needed to be updated, the baseboard management controller switches the connection mode from the bypass mode to the local mode, the baseboard management controller communicates with the basic input/output system unit directly and directly writes a basic input/output system updating file into the basic input/output system unit.2. The computer system according to claim 1 , wherein after the basic input/output system updating file is written completely claim 1 , the baseboard management controller switches the connection mode of the basic input/output system unit to the bypass mode before the central processing unit is powered on next time claim 1 , and when the central processing unit is powered on next ...

SERVER RACK SYSTEM

A server rack system includes a first network switch, a second network switch, servers, a rack internal device, and an integrated management module (IMM). Management network ports of baseboard management controllers (BMCs) of the servers are connected to the first network switch. A management network port of the rack internal device is connected to the second network switch. A first management network port and a second management network port of the IMM are respectively connected to the first network switch and the second network switch. The IMM communicates with the BMCs of the servers through the first network switch, so as to obtain operation states of the servers, or control operations of the servers. The IMM communicates with the rack internal device through the second network switch, so as to obtain an operation state of the rack internal device, or control an operation of the rack internal device. 1. A server rack system , comprising:a first network switch, coupled to a management network;a second network switch;multiple servers, each comprising a baseboard management controller (BMC), wherein the BMCs each comprises a management network port, and the management network ports are connected to the first network switch;at least one rack internal device, wherein a management network port of the rack internal device is connected to the second network switch; andan integrated management module (IMM), wherein the IMM has a first management network port and a second management network port; the first management network port of the IMM is connected to the first network switch; the second management network port of the IMM is connected to the second network switch; the IMM communicates with the BMCs of the servers through the first network switch, so as to obtain operation states of the servers or control operations of the servers; and the IMM communicates with the rack internal device through the second network switch, so as to obtain an operation state of the rack ...

SERVER RACK SYSTEM FOR MANAGING POWER SUPPLY

A server rack system for managing power supply is provided. The system includes: a first LAN switch, a plurality of servers, at least one power supply unit, and an IMM. The first LAN switch is coupled to a management network. Each of the servers has a BMC. The BMC has a management network port connected to the management network. The power supply unit supplies electric power to the server rack system and has a management network port connected to the management network. The IMM has a management network port connected to the management network, visits the BMCs through the management network to acquire a power consumption value of the servers, generates a control command according to the power consumption value of the servers, and transmits the control command through the management network to the power supply unit. The power supply unit adjusts electric power output according to the control command. 1. A server rack system , comprising:a first local area network (LAN) switch, coupled to a management network;a plurality of servers, each having a board management controller (BMC), wherein each of the BMCs has a management network port connected to the management network;at least one power supply unit, for supplying electric power to the server rack system, and having a management network port connected to the management network; andan integrated management module (IMM), having a management network port connected to the management network, and used for visiting the BMCs through the management network to acquire a power consumption value of the servers,wherein the IMM generates a control command according to the power consumption value of the servers, the IMM transmits the control command through the management network to the power supply unit, and the power supply unit adjusts electric power output according to the control command.2. The server rack system according to claim 1 , wherein the power supply unit at least comprises:at least one power supply device; anda ...

RACK SYSTEM

A rack system is provided. The rack system includes a first rack apparatus and a second rack apparatus. The first rack apparatus includes multiple first rack internal devices and a first Integrated Management Module (IMM). The first IMM manages the first rack internal devices via a network. The second rack apparatus includes multiple second rack internal devices and a second IMM. The second IMM manages the second rack internal devices via the network. The first IMM and the second IMM are connected via the network and implement a synchronous configuration process. When the second IMM goes abnormal, the first IMM manages the first rack internal devices and the second rack internal devices via the network at the same time. 1. A rack system , comprising:a first rack apparatus, comprising multiple first rack internal devices and a first Integrated Management Module (IMM), wherein the first IMM manages the first rack internal devices via a network; anda second rack apparatus, comprising multiple second rack internal devices and a second IMM, wherein the second IMM manages the second rack internal devices via the network, and the first IMM and the second IMM are connected via the network and implement a synchronous configuration process,wherein when the second IMM goes abnormal, the first IMM manages the first rack internal devices and the second rack internal devices via the network at the same time.2. The rack system according to claim 1 , wherein when implementing the synchronous configuration process claim 1 , the first IMM backs up a piece of first configuration information of the first rack apparatus to the second rack apparatus claim 1 , and the second IMM backs up a piece of second configuration information of the second rack apparatus to the first rack apparatus.3. The rack system according to claim 2 , wherein the first configuration information comprises a network protocol address of the first IMM and multiple device addresses and multiple pieces of ...

SERVER RACK SYSTEM

A server rack system module is provided. Each rack internal device at least includes a control chip, and the rack internal devices include a plurality of servers. An integrated management module (IMM) is respectively coupled to the control chips, where the IMM stores integrated management firmware, and the integrated management firmware has latest version firmware of the control chip integrated therein and records latest version serial numbers of the latest version firmware. When the server rack system is started, the IMM reads a current version serial number of currently installed firmware of each control chip, and compares the current version serial number with the corresponding latest version serial number, so as to determine whether to update the currently installed firmware. 1. A server rack system , comprising:a plurality of rack internal devices, wherein each rack internal device at least comprises a control chip, and the rack internal devices comprise a plurality of servers; andan integrated management module (IMM), respectively coupled to the control chips, wherein the IMM stores integrated management firmware, and the integrated management firmware has latest version firmware of the control chips integrated therein, and records latest version serial numbers of the latest version firmware,wherein when the server rack system is started, the IMM reads a current version serial number of currently installed firmware of each control chip, and compares the current version serial number with the latest version serial number, so as to determine whether to update the currently installed firmware.2. The server rack system according to claim 1 , further comprising:a management switch, coupled to the control chips and the IMM,wherein the IMM assigns a network address for each of the control chips through the management switch.3. The server rack system according to claim 2 , wherein a rack management terminal is coupled to the management switch claim 2 , and the rack ...

Computer system and detecting-alarming method thereof

A computer system and a detecting-alarming method thereof are provided. The computer system includes a device and a basic input/output system (BIOS) unit. The BIOS unit has a current device table. The BIOS unit detects the device of the computer system to obtain a detecting result in a start procedure, and compares the detecting result with the current device table. If the detecting result does not match the current device table, the BIOS unit gives an alarm.

COMPUTER SYSTEM

A computer system including a configuration unit and a plurality of computers is provided. The configuration unit sends login information and key information to a basic input/output system (BIOS) setting unit in each of the computers to simultaneously configure and check the BIOS settings of the computers. 1. A computer system , comprising: a basic input/output system (BIOS) unit; and', 'a BIOS setting unit, having configuration information of the corresponding BIOS unit and the corresponding computer, wherein the configuration information is corresponding to a setting interface, and the setting interface comprises a plurality of setting options;, 'a plurality of computers, wherein each of the computers comprisesa configuration unit, communicatively connected with the BIOS setting units of the computers, sending a login information to the BIOS setting units to log into the setting interfaces, sending a key information to the BIOS setting units to select the setting options, and sending a key information to the BIOS setting units to set set-up values of the setting options.2. The computer system according to claim 1 , wherein the BIOS setting units are respectively connected to a serial port claim 1 , and the configuration unit sends the key information to the BIOS setting units via the serial ports.3. The computer system according to claim 1 , wherein the computers respectively comprises a baseboard management controller claim 1 , the BIOS setting units respectively communicate with the baseboard management controllers via a serial port circuit claim 1 , the baseboard management controllers are connected with the configuration unit through a network claim 1 , the configuration unit sends network signals containing key information to the baseboard management controllers via the network claim 1 , and the baseboard management controllers convert the network signals into serial port signals and send the serial port signals to the BIOS setting units.4. The computer ...

DISPLAY PANEL

A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly. 1. A display panel comprising:a substrate comprising an active area, herein the active area comprises a plurality of pixel blocks;a plurality of first signal lines disposed parallel to each other on the substrate;a plurality of second signal lines disposed parallel to each other on the substrate, and crossing over the first signal lines to define the pixel blocks, wherein there are more of the second signal lines than the first signal lines;a plurality of pixel units respectively disposed within the pixel blocks, and respectively electrically connected to the first signal lines and respectively electrically connected to the second signal lines;a plurality of transmission lines disposed parallel to each other on the substrate, respectively electrically connected to the second signal lines, crossing through two opposite sides of the active area, and parallel to the first signal lines; and a plurality of first pins electrically connected to the first signal lines;', 'a plurality of second pins electrically connected to the transmission lines; and', 'a driver circuit configured to generate a first signal and a second signal, and to respectively transmit the first signal and the second signal to the first pins and ...

BONDING STRUCTURE

A bonding structure includes a substrate, multiple first pads, multiple second pads, an insulation layer and a patterned conductive layer. The substrate has a bonding region and a predetermined-to-be-cut region. The first pads are disposed on the substrate and within the bonding region. The second pads are disposed on the substrate and within the predetermined-to-be-cut region. The insulation layer is disposed on the substrate and covers the first and second pads. The insulation layer has multiple first and second openings respectively exposing parts of the first and second pads. The patterned conductive layer is disposed on the substrate and covers the insulation layer and the parts of the first and second pads exposed out by the first and second openings, in which the patterned conductive layer is electrically connected to the first and second pads via the first and second openings. 1. A bonding structure , comprising:a substrate, having a bonding region and a predetermined-to-be-cut region;a plurality of first pads, disposed on the substrate and located within the bonding region;a plurality of second pads, disposed on the substrate and located within the predetermined-to-be-cut region, wherein the first pads and the second pads are not connected to each other;an insulation layer, disposed on the substrate and covering the first pads and the second pads, wherein the insulation layer has a plurality of first openings and a plurality of second openings, the first openings respectively expose out parts of the first pads and the second openings respectively expose out parts of the second pads; anda patterned conductive layer, disposed on the substrate and covering the insulation layer and the parts of the first pads and the parts of the second pads exposed out by the first openings and the second openings respectively, wherein the patterned conductive layer is electrically connected to the first pads and the second pads via the first openings and the second openings.2 ...

Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors

Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first insulating material over a workpiece;forming a conductive chemical compound material over the first insulating material;patterning the conductive chemical compound material to form a resistor;forming a second insulating material over the resistor;patterning the second insulating material; andfilling the patterned second insulating material with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor, the second end being different from the first end.2. The method according to claim 1 , wherein each of forming the conductive chemical compound material and patterning the conductive chemical compound material comprise middle-of-line (MEOL) processes performed after a front-end-of line (FEOL) process and before a back-end-of-line (BEOL) process.3. The method according to claim 1 , wherein each of forming the conductive chemical compound material and patterning the conductive chemical compound material comprise back-end-of-line (BEOL) processes performed after a front-end-of line (FEOL) process.4. The method according to claim 1 , wherein the method further comprises forming a third ...

METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE

A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2being less than W, 2being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings. 1. A method , for use with an integrated circuit device including a stack of dielectric/conductive layers , for forming interlayer connectors extending from a surface of the device to the conductive layers , the method comprising:creating spaced apart contact openings in a contact region of the integrated circuit through a dielectric layer with dielectric layer material separating each of the contact openings, the contact openings overlying an electrical conductor for each of W conductive layers;the contact openings creating step comprising creating a first contact opening down to a first conductive layer;{'sup': N−1', 'N, 'using a set of N etch masks with 2being less than W and 2being greater than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected contact openings;'}etching, using the N etch masks, the stack of dielectric/conductive layers only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers;{'sup': 'n−1', 'the etching step comprising etching 2conductive layers for up to half of the contact openings for each etch mask n=1, 2 . . . N;'}the etching step being carried out ...

Phase Shift Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same

A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an AgO absorber layer disposed over the reflective multilayer coating, and a tantalum-containing absorber layer disposed over the AgO absorber layer. The tantalum-containing absorber layer is disposed over the AgO absorber layer outside a mask image region of the mask, such that the mask image region of the mask is free of the tantalum-containing absorber layer. In an example, the tantalum-containing absorber layer is disposed over the AgO absorber layer adjacent to the mask image region. 1. A mask comprising:a substrate;a reflective multilayer coating disposed over the substrate;{'sub': '2', 'an AgO absorber layer disposed over the reflective multilayer coating; and'}{'sub': '2', 'a tantalum-containing absorber layer disposed over the AgO absorber layer adjacent to a mask image region.'}2. The mask of wherein the tantalum-containing absorber layer is a TaBN layer.3. The mask of wherein the substrate includes a low thermal expansion material (LTEM).4. The mask of further including a ruthenium-containing buffer layer disposed between the reflective multilayer coating and the AgO absorber layer.5. The mask of further including a silicon-containing capping layer disposed between the reflective multilayer coating and the ruthenium-containing buffer layer.6. The mask of claim 5 , further including a conductive layer disposed over the substrate claim 5 , wherein the reflective multilayer coating is disposed over a first surface of the substrate and the conductive layer is disposed over a second surface of the substrate claim 5 , the second surface being opposite the first surface.7. The mask of wherein the reflective multilayer coating includes a plurality of molybdenum-silicon (Mo—Si) film pairs.8. A phase shift mask comprising:a low thermal expansion material (LTEM) substrate;a reflective multilayer coating ...

RACK SERVER SYSTEM AND METHOD FOR AUTOMATICALLY MANAGING RACK CONFIGURATION INFORMATION

A rack server system and a method for automatically managing rack configuration information are disclosed herein. The rack server system includes a plurality of servers, plurality of fan modules, a plurality of fan control boards, and a rack management controller. The rack management controller is connected to the fan control boards, detects rack configuration information stored in the fan control boards during the operation of the rack server system, configured to update local rack configuration information stored in the rack management controller with the rack configuration information stored in the fan controllers when the local rack configuration information stored in the rack management controller is different from the rack configuration information stored in the fan control boards. 1. A rack server system , comprising:a plurality of servers, divided into a plurality of groups of servers;a plurality of fan modules, wherein each fan module dissipates the heat of one of the groups of servers corresponding thereto;a plurality of fan control boards, wherein each fan control board controls the operation of one of the fan modules corresponding thereto, and communicates with one of the group of servers corresponding to one of the fan modules; anda rack management controller connected to the fan control boards, detecting rack configuration information stored in the fan control boards during the operation of the rack server system, configured to update local rack configuration information stored in the rack management controller with the rack configuration information stored in the fan control boards when the local rack configuration information stored in the rack management controller is different from the rack configuration information stored in the fan control boards.2. The rack server system as claimed in claim 1 , wherein the rack management controller receives external input rack configuration information via a human machine interface claim 1 , and stores the ...

Rack Server System and Operating Method Thereof

A rack server system and an operating method thereof are disclosed herein. The rack server system includes a rack, a rack management controller, a plurality of servers, a plurality of fan modules, and a plurality of fan controllers. The rack management controller includes a plurality of different first bus ports, and the fan controllers are connected to the first bus ports separately. Each of the fan controllers includes a plurality of different second bus ports, and the servers are connected to the second bus ports separately. The rack management controller identifies the fan controllers through the first bus port, and acquires server general positions of the servers inside the rack through the difference between the first bus ports and the difference between the second bus ports. 1. A rack server system , comprising:a rack;a rack management controller comprising a plurality of different first bus ports;a plurality of server groups, each server group comprising a plurality of servers;a plurality of fan modules, each fan module operative to dissipate heat for one of the server groups; anda plurality of fan controllers, each fan controller collecting running information of servers in a corresponding one of the server groups and controlling an operation of a corresponding one of the fan modules accordingly, and each fan controller comprising a plurality of different second bus ports;wherein in each of the server groups, each of the servers is connected to one of the second bus ports of a corresponding fan controller through one of second buses, the servers communicating with the corresponding fan controller using a same second bus address, each of the second bus ports corresponds to a different server position in the rack, wherein the fan controllers communicate with the servers through the second bus ports and acquire server local positions in the rack of the servers in the server group by a difference between the second bus ports through which the communication data ...

THREE-DIMENSIONAL VERTICAL GATE NAND FLASH MEMORY INCLUDING DUAL-POLARITY SOURCE PADS

A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad. The source line pad includes at least one n-type region and at least one p-type region. The memory includes word lines coupled to the plurality of strips in the plurality of levels. The memory includes data storage elements between the word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines. The memory also includes circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strips extending from the source line pad and one of the n-type region and the p-type region. 1. A memory comprising:a strip of semiconductor material extending between a bit line pad and a source line pad, the source line pad including at least one n-type region and at least one p-type region;a gate coupled to the strip;a data storage element between the gate and the strip, whereby a memory cell is disposed at a cross-point of the strip and the gate; andcircuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strip through one of the n-type region and the p-type region.2. The memory of claim 1 , including a plurality of gates coupled to the strip between the bit line pad and the source line pad claim 1 , wherein the strip is more lightly doped than the n-type region and the p-type region at least in the cross-points between the strip and the plurality of gates.3. The memory of claim 2 , wherein the strip acts as channel regions for a NAND string of memory cells.4. The memory of claim 1 , including:a string select gate coupled to the strip between the gate and the bit line pad, and configured to control ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor. 1. A semiconductor structure , comprising:a stack of memory cells, anda CMOS structure, located below the stack of memory cells, wherein the CMOS structure comprises a source line transistor and a bit line transistor.2. The semiconductor structure according to claim 1 , wherein the source line transistor is adjacent to the bit line transistor.3. The semiconductor structure according to claim 1 , wherein the stack of memory cells does not overlap the source line transistor and the bit line transistor.4. The semiconductor structure according to claim 1 , further comprising:a local bit line, located above the stack of memory cells, anda first pillar element, located between the local bit line and the bit line transistor, wherein the local bit line is electrically connected to the bit line transistor through the first pillar element.5. The semiconductor structure according to claim 4 , further comprising:an insulating stack, adjacent to the stack of memory cells,wherein the first pillar element penetrates the insulating stack, and the first pillar element transmits a signal in the local bit line to the bit line transistor.6. The semiconductor structure according to claim 1 , further comprising:a first metal layer, located above the bit line transistor,a second pillar element, located above the first metal layer, anda global bit line, located above the stack of memory cells,wherein the bit line transistor is electrically connected to the global bit line through the first metal layer and the second pillar element.7. The semiconductor structure according to claim 6 , further comprising:a second metal layer, located between the first metal layer and the second pillar element, wherein the bit line transistor is electrically connected to the global bit ...

ARRAY ARRANGEMENT INCLUDING CARRIER SOURCE

A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions. 1. A memory comprising:a diode having first and second terminals;a series arrangement including a plurality of memory cells, the series arrangement coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to the first terminal of the diode;first and second supply lines connected to the first and second terminals, respectively, of the diode;a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; andcircuitry coupled to the plurality of word lines and to the first and second supply lines configured to bias the first and second supply lines with different bias conditions.2. The memory of claim 1 , wherein the circuitry is configured to apply an erase bias arrangement that induces hole tunneling claim 1 , the erase bias arrangement including a source side bias on the second supply line which forward biases the diode claim 1 , while the first supply line remains floating claim 1 , and erase voltages on the plurality of word lines that induce hole tunneling.3. The memory of claim 1 , wherein the circuitry is configured to apply a program bias arrangement that induces electron tunneling claim 1 , the program bias arrangement including a source ...

STABILIZED INTERFACES OF INORGANIC RADIATION PATTERNING COMPOSITIONS ON SUBSTRATES

A method is described for stabilizing organometallic coating interfaces through the use of multilayer structures that incorporate an underlayer coating. The underlayer is composed of an organic polymer that has crosslinking and adhesion-promoting functional groups. The underlayer composition may include photoacid generators. Multilayer structures for patterning are described based on organometallic radiation sensitive patterning compositions, such as alkyl tin oxo hydroxo compositions, which are placed over a polymer underlayer. 1. A multilayer structure comprising:a substrate with a surface, an underlayer coating over at least a portion of the substrate surface, and an organometallic resist coating that is radiation sensitive, over at least a portion of the underlayer coating, wherein the underlayer coating comprises a polymer composition with crosslinking moieties and/or adhesion-promoting moieties.2. The multilayer structure of wherein the adhesion between the underlayer coating and the organometallic resist coating is sensitive to radiation.3. The multilayer structure of wherein the polymer composition comprises repeat units with side-chain crosslinking moieties and/or polymers with end-chain crosslinking moieties claim 1 , wherein the repeat units include functionalized acrylates claim 1 , functionalized vinyl ketones claim 1 , functionalized acrylamides claim 1 , other functionalized vinyl or non-vinyl repeat units claim 1 , or mixtures thereof claim 1 , wherein the crosslinking moieties may be terminally functionalized with a hydroxide claim 1 , an ether claim 1 , a glycidyl claim 1 , an epoxide claim 1 , a methoxymethyl urea claim 1 , an acrylate claim 1 , or combinations thereof claim 1 , and wherein the polymer composition has suitable film forming properties from solution.4. The multilayer structure of wherein the repeat units have a structure of formula (1) wherein Ris a hydrogen atom claim 3 , a fluorine atom claim 3 , a methyl group claim 3 , or a ...

METHOD FOR NON-FLUORESCENCE HIGHER HARMONIC GENERATION GROUND STATE DEPLETION SUPER-RESOLUTION MICROSCOPY

The present invention discloses a method for non-fluorescence higher harmonic generation ground state depletion super-resolution microscopy, it includes the following steps: providing an organic material unit, focusing excitation light and ground state depletion light, generating a higher harmonic signal, performing ground state depletion and performing microscopic imaging. With the implementation of the present invention, the stimulated electrons of the organic material remains majorly on the singlet (S) state or the triplet (T) state, instead of the ground (S) state, to provide modulation of the spatial distribution of the non-fluorescence signal, and make STED microscopy applicable to non-fluorescence signals to promote the resolution of the images. 1. A method for non-fluorescence higher harmonic generation ground state depletion ultra-resolution microscopy , comprising the steps of:providing an organic material unit, wherein the organic material unit comprises a plurality of molecules, each said molecule has a plurality of electrons, and each said electron has an energy band with energy of hv such that, when excited by hv, the electrons jump from a ground state to a singlet state and undergo inter-system crossing from the singlet state to a triplet state, with h being the Planck constant (equal to 6.626×10̂−34) and v being a frequency expressed in hertz (Hz);focusing excitation light and ground state depletion light by collimating the excitation light, projected by a long-wavelength ultrafast pulse laser, and the ground state depletion light, projected by a short-wavelength continuous-wave laser; combining the collimated excitation light with the collimated ground state depletion light; and focusing the combined light onto a plurality of test positions of the organic material unit sequentially;generating a higher harmonic signal by irradiating and exciting the test positions of the organic material unit with the focused excitation light such that the electrons ...

ELECTRONIC PAPER DISPLAY DEVICE

An electronic paper display device includes a substrate, a protection sheet, an e-ink (electronic-ink) layer, a first electrode layer, and a second electrode layer. The e-ink layer is located between the substrate and the protection sheet. The e-ink layer has a display area and a surrounding area. The display area is surrounded by the surrounding area. The first electrode layer is located between the e-ink layer and the substrate, and the first electrode layer is corresponding to the display area in position. The second electrode layer is located between the e-ink layer and the substrate, and the second electrode layer is corresponding to the surrounding area in position.

SEMICONDUCTOR STRUCTURE

A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip. 1. A semiconductor structure , comprising:a conductive strip;a conductive layer;a first dielectric layer between the conductive strip and the conductive layer arranged in a crisscross manner; anda second dielectric layer different from the first dielectric layer, wherein the second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip.2. The semiconductor structure according to claim 1 , comprising a plurality of the first dielectric layers separated from each other by the second dielectric layer.3. The semiconductor structure according to claim 1 , comprising a plurality of the conductive strips and a plurality of the conductive layers claim 1 , wherein the second dielectric layer is between adjacent two of the conductive strips and between adjacent two of the conductive layers.4. The semiconductor structure according to claim 1 , wherein the conductive strip has a first conductive portion and a second conductive portion adjoined with the first conductive portion claim 1 , the first dielectric layer is adjoined with the first conductive portion claim 1 , the second dielectric layer is adjoined with the second conductive portion claim 1 , a width of the first conductive portion is different from a width of the second conductive portion.5. The semiconductor structure according to claim 1 , wherein the first dielectric layer and the second ...

Capacitor With 3D NAND Memory

An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other. 2. The computer readable medium of claim 1 , wherein the stack of conductive strips is at least one of: transistor channels in the 3D NAND memory array claim 1 , conductors routing signals that select memory cells in the 3D NAND memory array claim 1 , and conductors routing output from the 3D NAND memory array.3. The computer readable medium of claim 1 , wherein the 3D NAND memory array is a vertical gate memory array claim 1 , and the conductive strips in the stack are NAND transistor channels in the vertical gate memory array.4. The computer readable medium of claim 1 , wherein the 3D NAND memory array is a vertical channel memory array claim 1 , and the conductive strips in the stack of conductive strips are word lines in the vertical channel memory array.5. The computer readable medium of claim 1 , wherein the stack of capacitor terminal strips includes a first plurality of capacitor terminal strips alternating with a second plurality of capacitor terminal strips claim 1 , the first plurality of capacitor terminal strips electrically connected together and the second plurality of capacitor terminal ...

METHODS OF DEFECT INSPECTION

Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate. 1. A method of inspecting defects , comprising:forming openings in a underlying layer by using a patterned photoresist layer as an etching mask, the patterned photoresist layer including at least one defective pattern;forming a filling material layer in the openings and over an upper surface of the underlying layer;performing a planarization operation such that the upper surface of the underlying layer is exposed and the filling material layer remains in the opening; andperforming an inspection operation to find a defective pattern in the underlying layer using an optical inspection tool.2. The method of claim 1 , wherein the planarization operation includes a chemical mechanical polishing (CMP) operation.3. The method of claim 2 , wherein the filling material comprises an organic bottom anti-reflective coating (BARC) material.4. The method of claim 3 , wherein the forming the filling material layer comprises spin coating the BARC material over the underlying layer.5. The method of claim 2 , wherein the underlying layer comprises at least one of amorphous silicon claim 2 , silicon nitride claim 2 , aluminum oxide or hafnium oxide.6. The method of claim 1 , wherein the filling material comprises at least one of silicon oxide claim 1 , amorphous silicon claim 1 , silicon nitride claim 1 , aluminum oxide or hafnium oxide.7. The method of claim 6 , wherein the underlying layer includes a conductive material layer.8. The method of claim 6 , wherein the filling material is formed by one of an atomic layer deposition (ALD) ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure has a second portion with an appendage on one side of the second portion and extruding along the longitudinal direction of the second portion. Moreover the semiconductor structure also has a gate line longitudinally parallel to the second portion, wherein the length of the gate line equals to the longitudinal length of the second portion. 1. A semiconductor structure with a gate layer , the gate layer comprising:A second portion with an appendage on one side of the second portion and extruding along the longitudinal direction of the second portion; anda first portion comprising a gate line longitudinally parallel to the second portion, wherein the length of the gate line equals to the to longitudinal length of the second portion.2. The semiconductor structure according to claim 1 , wherein the second portion comprises two appendages and the appendages are separately located on opposite side of the second portion claim 1 , and extrude along is the longitudinal direction of the second portion.3. The semiconductor structure according to claim 1 , wherein the width of the second portion is greater than the width of the gate line.4. The semiconductor structure according to claim 1 , wherein the difference between the width of the second portion and the width of the appendage is an integral multiple of the width of the gate line.5. The semiconductor structure according to claim 1 , wherein the second portion is a GSL or a SSL.6. A semiconductor structure with a gate layer claim 1 , the gate layer comprising:at least two second portions, each second portion comprising at least an appendage on one side of each second portion and extruding along the longitudinal direction of the second portion; anda first portion located between the second portions and longitudinally parallel to the second portion, wherein the first portion comprises a plurality of gate lines with a same spacing and arranged in an array manner, and the length of each gate line ...

METHOD AND APPARATUS FOR ULTRAVIOLET (UV) PATTERNING WITH REDUCED OUTGASSING

A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus. 1. An ultraviolet (UV) lithography apparatus comprising:a stage for receiving thereon a substrate to be patterned;an ultraviolet (UV) light source that directs UV light onto a substrate disposed on said stage;a gas delivery source that causes an inert gas to flow across and in close proximity to a surface of said substrate disposed on said stage; andan exhaust system with exhaust ports capable of exhausting said inert gas.2. The UV lithography apparatus as in claim 1 , wherein said UV light source comprises an extreme ultraviolet (EUV) light source that emits EUV light having a wavelength of about 13.5 nm.3. The UV lithography apparatus as in claim 2 , wherein said EUV light source further comprises at least one reflective member capable of directing said EUV light onto said substrate and a further gas source that causes an inert gas to flow across and in close proximity to a surface of said at least one reflective member.4. The UV lithography apparatus as in claim 2 , wherein said gas delivery source comprises a plurality of gas delivery tubes positioned parallel to said surface of said substrate claim 2 , each said gas delivery tube having an associated gas delivery port claim 2 , and wherein said gas delivery ports surround and face said substrate.5. The UV lithography ...

SERVER SYSTEM AND MESSAGE PROCESSING METHOD THEREOF

A server system and a message processing method thereof are provided. The server system mentioned above includes a baseboard management controller (BMC) and a mainboard system. Output messages are received from the mainboard system by the BMC and are stored into a buffer in the BMC. When a command is received from a remote device, the corresponding output messages are acquired from the buffer according to the received command, and are transmitted to the remote device. 1. A message processing method for a server system , which is suitable for a baseboard management controller , wherein the server system comprises the baseboard management controller and a mainboard system having a serial port connected with the baseboard management controller , and the method comprises:a preliminary step:creating a buffer in the memory of the baseboard management controller;executing steps:receiving multiple output messages by the baseboard management controller from the serial port of the mainboard system;performing a first mode by the baseboard management controller to store the output messages into the buffer;performing a second mode by the baseboard management controller according to a switching command to stop storing the output messages into the buffer and enable a remote device to access the serial port through a network to exchange data with the mainboard system;receiving a command from the remote device through the network and acquiring corresponding output messages from the buffer according to the command; andtransmitting the corresponding output messages to the remote device.2. The message processing method of claim 1 , wherein after the step of receiving the output messages from the serial port of the mainboard system claim 1 , the message processing method further comprises:recording a receiving time when the output messages are received from the mainboard system into the buffer.3. The message processing method of claim 2 , wherein the command comprises a specified time ...

DISPLAY PANEL

A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes. 1. A display panel comprising:a substrate comprising a display region and a non-display region;a peripheral circuit, wherein at least a portion of the peripheral circuit is located on the display region;a plurality of pixel electrodes located on the display region; andan insulating layer located between the peripheral circuit and the pixel electrodes;wherein the peripheral circuit comprises an electrostatic discharge (ESD) protection circuit, at least a portion of the ESD protection circuit is located on the display region.2. The display panel as claimed in claim 1 , wherein the ESD protection circuit is configured to electrically connect to a scan line or a data line.3. The display panel as claimed in claim 1 , further comprising:a plurality of switches respectively and electrically connected to the pixel electrodes, wherein the switches are configured to be switched on according to a plurality of scan signals respectively, so as to transmit a plurality of data signals to the pixel electrodes.4. The display panel as claimed in claim 3 , wherein the peripheral circuit comprises an amorphous silicon array driver ( ...

MEMORY WITH SUB-BLOCK ERASE ARCHITECTURE

A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block. 1. A memory device , comprising:a plurality of blocks of memory cells, bit lines, word lines and sub-block reference lines;each block in the plurality being operably coupled to a set of X bit lines BL(x), a set of Z word lines WL(z), and a set of Y sub-block reference lines RL(y), where Y is two or more, and each block including:an array of NAND strings including a plurality of rows and a plurality of columns of NAND strings, each NAND string in the array including memory cells coupled to each word line WL(z) in the set of Z word lines, the NAND strings in the array having respective first select switches and second select switches; a reference select line RSL coupled to gates of the second select switches of all the NAND strings in the array, the reference select line RSL configured to control the second switches in the array for connection of NAND strings in Y sub-blocks of the array to corresponding reference lines RL(y) in the set of Y sub-block reference lines, the NAND strings in a same row connected to two or more reference lines RL(y) in the set of Y sub-block reference lines; and', 'a controller and bias circuitry coupled to the plurality of blocks, responsive to a command to erase a selected sub-block in a selected block, to apply an erase bias arrangement including a first bias on the reference select line of the selected block, a second bias on a selected one of the Y sub- ...

CALIBRATION METHOD FOR TOOL CENTER POINT, TEACHING METHOD FOR ROBOTIC ARM AND ROBOTIC ARM SYSTEM USING THE SAME

Firstly, a robotic arm drives a projection point of tool projected on test plane to perform relative movement relative to a reference point of a test plane. Then, conversion relationship is established according to the relative movement. Then, a tool axis vector relative to an installation surface reference coordinate system of the robotic arm is obtained. Then, calibration point information group obtaining step is performed, wherein the calibration point information group obtaining step includes: (a1) the robotic arm drives a tool center point to coincide with a reference point of the test plane and records calibration point information group; (a2) the robotic arm drives the tool to change angle of the tool; and (a3) steps (a1) and (a2) are repeated to obtain several calibration point information groups. Then, tool center point coordinate relative to the installation surface reference coordinate system is obtained according to the calibration point information groups. 1. A calibration method for tool center point , comprising: driving, by a robotic arm, a projection point of a tool axis of a tool projected on a test plane to perform a relative movement relative to a reference point of the test plane; and', 'establishing the first conversion relationship according to the relative movement;, 'performing a step of establishing a first conversion relationship between a robotic arm reference coordinate system and a camera reference coordinate system, comprisingobtaining a tool axis vector relative to an installation surface reference coordinate system of the robotic arm; (a1) driving, by the robotic arm, a tool center point to coincide with the reference point of the test plane, and recording a calibration point information group of the robotic arm;', '(a2) driving, by the robotic arm, the tool to change an angle of the tool axis; and', '(a3) repeating steps (a1) and (a2) to obtain a plurality of the calibration point information groups; and, 'performing a calibration ...

PREPOLYMERIZED RESIN, PREPARATION METHOD THEREOF, RESIN COMPOSITION COMPRISING THE SAME, AND ARTICLE MADE THEREFROM

A prepolymerized resin prepared by subjecting a composition to a pre-reaction in the presence of a polymerization inhibitor. The composition at least includes bis(vinylphenyl)ethane and polybutadiene. The polybutadiene has a 1,2-vinyl content of 85% or above and a number average molecular weight of less than 3000, wherein the pre-reaction has a conversion rate of between 30% and 90%. During the pre-reaction, components in the composition are partially crosslinked to leave residual vinyl groups. The composition further includes vinyl-containing polyphenylene ether and has a number average molecular weight of between 4,000 and 12,000. 1. A prepolymerized resin prepared by subjecting a composition to a pre-reaction in the presence of a polymerization inhibitor , the composition at least comprising bis(vinylphenyl)ethane and polybutadiene , wherein the polybutadiene has a 1 ,2-vinyl content of 85% or above and a number average molecular weight of less than 3000 , wherein the pre-reaction has a conversion rate of between 30% and 90% , and wherein , during the pre-reaction , components in the composition are partially crosslinked to leave residual vinyl groups.2. The prepolymerized resin of claim 1 , wherein the composition further comprises vinyl-containing polyphenylene ether.3. The prepolymerized resin of claim 1 , which has a number average molecular weight of between 4 claim 1 ,000 and 12 claim 1 ,000. This application is a Continuation of co-pending application Ser. No. 15/985,445 filed on May 21, 2018, for which priority is claimed under 35 U.S.C. § 120; and this application claims priority of Application No. 107110250, filed in Taiwan, R.O.C. on Mar. 26, 2018 under 35 U.S.C. § 119; the entire contents of all of which are hereby incorporated by reference.Disclosed is a prepolymerized resin, a preparation method thereof, a resin composition comprising the same, and an article made therefrom.Conventionally, polyphenylene ether resins are widely used for making low ...

INFERENCE OPERATION METHOD AND CONTROLLING CIRCUIT OF 3D NAND ARTIFICIAL INTELLIGENCE ACCELERATOR

An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched. 1. An inference operation method of a 3D NAND artificial intelligence accelerator , wherein the 3D NAND artificial intelligence accelerator includes a plurality of memory cells , a plurality of bit lines , a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line , a plurality of filters are stored in the memory cells that are selected by the word lines , the string selecting lines and the bit lines when being read , a plurality of patterns are inputted to the bit lines for performing a Multiply-Accumulation (MAC) operation , and the inference operation method comprises:inputting the patterns to the bit lines;switching the word lines to switch the filters; andswitching the string selecting line groups to switch the filters;wherein in a word line pioneering scheme and a string selecting line group pioneering scheme; when the patterns inputted to each of the bit lines are switched; any one of the word lines is not switched and any one of the string selecting line groups is not switched.2. The inference operation method according to claim 1 , wherein in the word ...

MEMORY DEVICE

A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION

Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height. 1. A method , comprising:measuring a first topographical height at a first coordinate on a substrate;measuring a second topographical height at a second coordinate on the substrate;providing the measured first and second topographical heights as a wafer map; and using a first focal point when exposing the first coordinate on the substrate, wherein the first focal point is determined using the first topographical height; and', 'using a second focal point when exposing the second coordinate on the substrate, wherein the second focal point is determined using the second topographical height., 'performing an exposure process on the substrate using the wafer map, wherein the exposure process includes2. The method of claim 1 , wherein the measuring the first and second topographical heights are performed concurrently using a multi-tip atomic force microscopy (AFM) tool.3. The method of claim 1 , wherein the measuring the second topographical height is performed substantially concurrently with the exposing of the first coordinate.4. The method of claim 1 , wherein the wafer map is generated by determining an offset value between the first topographical height and a third height associated with the first coordinate.5. The ...

TEACHING APPARATUS FOR MANIPULATOR

A teaching apparatus for a manipulator is provided, including: a fixing member for fixing to the manipulator; a main body connected to the fixing member; and a handle connected to the main body. The main body includes a plurality of sensors and an operation display member, wherein at least one of the sensors is disposed on one side of the main body adjacent the fixing member and configured for sensing a force, a stress or a torque applied to the main body, and the operation display member is disposed on the other side of the main body and includes a plurality of function keys and a display screen disposed thereon. The teaching apparatus allows the path-teaching process for a manipulator to be completed quickly and easily. 1. A teaching apparatus for a manipulator , comprising:a fixing member configured to be fixed to the manipulator; anda main body connected to the fixing member and comprising a plurality of sensors and an operation display member, wherein at least one of the sensors are disposed on one side of the main body adjacent the fixing member and configured to sense a force, a stress or a torque applied to the main body, and the operation display member is disposed on the other side of the main body and comprises a plurality of function keys and a display screen disposed thereon.2. The teaching apparatus of claim 1 , further comprising a handle connected to the main body.3. The teaching apparatus of claim 1 , wherein the sensors surround the main body with a same angle.4. The teaching apparatus of claim 1 , wherein the sensors surround the main body with a same interval.5. The teaching apparatus of claim 1 , wherein at least one of the sensors is configured to be electrically connected to a controller of the manipulator.6. The teaching apparatus of claim 5 , wherein the operation display member is configured to be electrically connected to the controller of the manipulator.7. The teaching apparatus of claim 5 , wherein at least one of the function keys is ...

MASK CLEANING

A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask. 1. A lithography system comprising:a load lock chamber comprising an opening configured to receive a mask;an exposure module configured to expose a semiconductor wafer to a light source through use of the mask; anda cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.2. The lithography tool of claim 1 , wherein the lithography tool is an Extreme Ultra-Violet (EUV) lithography tool claim 1 , the mask is an EUV mask claim 1 , and the light source is an EUV light source.3. The lithography system of claim 1 , wherein the cleaning module is integrated into the load lock chamber.4. The lithography system of claim I claim 1 , wherein the cleaning module is located within a discrete chamber positioned along a mask path between the load lock chamber and the exposure module.5. The lithography system of claim 1 , wherein the cleaning module is configured to produce hydrogen radicals.6. The lithography system of claim 5 , wherein the cleaning module comprises:a filament configured to be heated to heat to a temperature greater than 1900 degrees Celsius; anda gas source configured to pass hydrogen gas over the filament to produce the hydrogen radicals.7. The lithography system of claim 1 , wherein the cleaning module is configured to produce a plasma gas including at least one of: hydrogen claim 1 , oxygen claim 1 , nitrogen claim 1 , argon claim 1 , helium claim 1 , fluorine claim 1 , and chlorine.8. The lithography system of claim 1 , wherein the cleaning module comprises one of: a laser decomposition cleaning system claim 1 , an ultraviolet ozone cleaning ...

METHOD OF FORMING METAL GATE ELECTRODE

An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of HO, NHOH, HCl, HSOor diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NHOH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material. 1. A method , comprising:partially filling an opening in a dielectric material with a high-dielectric-constant material;partially filling the opening with a first metal material over the high-dielectric-constant material;filling a remaining portion of the opening with a capping layer over the first metal material;partially removing the first metal material and the capping layer in the opening using a first wet etching process;fully removing the remaining capping layer in the opening using a second wet etching process; anddepositing a second metal material in the opening over the remaining first metal material.2. The method of claim 1 , further comprising:planarizing the capping layer to be coplanar with the high-dielectric-constant material.3. The method of claim 1 , wherein the second metal material is deposited having a bottom portion and sidewall portions claim 1 , the bottom portion is formed having a first thickness in a first direction claim 1 , the sidewall portions are formed having a second thickness in a second direction different from the first direction claim 1 , and the second ...

METHOD OF DYNAMIC FREQUENCY SELECTION AND AN ELECTRONIC DEVICE EMPLOYING THE SAME

A method of dynamic frequency selection includes receiving setting information of a WI-FI unit input by an input unit, controlling the WI-FI unit in a STA working mode to switch different channels to scan an available access point AP with dynamic frequency selection within one channel when receiving the setting information of setting the WI-FI unit to work in an AP working mode and the STA working mode simultaneously, controlling the WI-FI unit in the AP working mode to switch to the channel within which the WI-FI unit in the STA working mode scans the available access point AP when the WI-FI unit in the STA working mode scans the available access point AP, and controlling the WI-FI unit in the AP working mode to communicate with a terminal device via the switched access point AP. 1. An electronic device with dynamic frequency selection , comprising:an input unit; a WI-FI unit coupled to the at least one processor configured to work in an AP working mode and a STA working mode;', receive setting information of the WI-FI unit input by the input unit;', 'control the WI-FI unit in the STA working mode to switch different channels to scan an available access point AP within one channel when receiving the setting information of setting the WI-FI unit to work in the AP working mode and the STA working mode simultaneously;', 'when the WI-FI unit in the STA working mode scans the available access point AP, control the WI-FI unit in the STA working mode to communicate with the scanned access point AP via the channel within which the available access point AP is scanned;', 'control the WI-FI unit in the AP working mode to switch to the channel within which the WI-FI unit in the STA working mode scans the available access point AP; and', 'control the WI-FI unit in the AP working mode to communicate with a terminal device via the switched access point AP., 'a non-transitory storage medium coupled to the at least one processor and configured to store a plurality of instructions, ...

METHODS OF DEFECT INSPECTION

Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate. 1. A method of inspecting defects after a photolithography process , comprising:etching a structure layer under a patterned photoresist layer to transform pattern features from the patterned photoresist layer to the structure layer, wherein the structure layer comprises a first material;filling the pattern features in the structure layer with a dummy filling material, wherein the first material and the dummy filling material have dissimilar optical properties, and the dummy filling material is to be removed from the pattern feature;exposing a top surface of the structure layer containing the first material and the pattern features containing the dummy filling material; andinspecting the top surface for defective pattern features using an inspection tool.2. The method of claim 1 , wherein the dummy filling material comprises a bottom anti-reflective coating (BARC) material.3. The method of claim 2 , wherein filling the pattern features comprises spin coating the dummy filling material over the structure layer.4. The method of claim 1 , wherein removing excess dummy filling material comprises etching the dummy filling material using a plasma of oxygen.5. The method of claim 3 , wherein the first material comprises silicon oxide claim 3 , and the BARC material is an organic BARC material.6. The method of claim 1 , wherein the first material comprises silicon oxide claim 1 , and the dummy filling material comprises one of a BARC material claim 1 , a silicon based material claim 1 , a metal oxide claim 1 , a metal nitride ...

FINFET FABRICATION METHODS

A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions. 1. (canceled)2. A method of fabricating a semiconductor device , comprising:etching an interlayer dielectric (ILD) layer to expose source/drain regions of the semiconductor device;after exposing the source/drain regions, performing a spacer deposition and etch process; andafter performing the spacer deposition and etch process, performing a plasma doping process of the source/drain regions.3. The method of claim 2 , further comprising:after performing the plasma doping process of the source/drain regions, forming a silicide layer over, and in contact with, the source/drain regions.4. The method of claim 2 , wherein the plasma doping process includes a boron plasma doping of the source/drain regions.5. The method of claim 2 , wherein the plasma doping process is a self-amorphizing plasma doping process.6. The method of claim 2 , further comprising after performing the plasma doping process claim 2 , performing a laser anneal process.7. The method of claim 3 , further comprising:after performing the spacer deposition and etch process, and before forming the silicide layer, performing a pre-silicide ...

LOAD BALANCING DEVICE FOR ROBOT ARM

A load balancing device for a robot arm including a pneumatic cylinder and a piston rod is provided. The pneumatic cylinder, used to store a gas, includes a first chamber, a second chamber and a communicating passage, wherein the communicating passage connects the first chamber and the second chamber. The piston rod has one end connected to the robot arm and the other end slidably disposed in the pneumatic cylinder. The piston rod adjusts the volume and the pressure of the gas in the first chamber and the second chamber according to a load, wherein the first chamber and the second chamber are coaxially disposed in the axial direction of the pneumatic cylinder. 1. A load balancing device for a robot arm , comprising:a pneumatic cylinder used to store a gas, wherein the pneumatic cylinder further comprising a first chamber, a second chamber, and a communicating passage communicating the first chamber and the second chamber; anda piston rod having one end connected to the robot arm and the other end slidably disposed in the pneumatic cylinder, wherein the piston rod adjusts the volume and the pressure of the gas in the first chamber and the second chamber according to a load, and the first chamber and the second chamber are coaxially disposed in the axial direction of the pneumatic cylinder.2. The load balancing device according to claim 1 , wherein the pneumatic cylinder comprises a first hollow body claim 1 , a second hollow body claim 1 , a fixing base claim 1 , and a plurality of sealing elements sealed in the junction of every adjacent two of the first hollow body claim 1 , the second hollow body claim 1 , the fixing base and the piston rod.3. The load balancing device according to claim 2 , wherein the piston rod is located in the first hollow body claim 2 , and the communicating passage passes through the first hollow body to connect the first hollow body and the second hollow body.4. The load balancing device according to claim 2 , wherein the first hollow body ...

ROTARY EUV COLLECTOR

An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force. 1. A method of operating an extreme ultraviolet (EUV) lithography system , comprising:generating EUV light;using a collector to gather and focus the light onto an optical system that illuminates a reticle and projects an image from the reticle onto a target;rotating the collector to a new position; andagain using the collector to gather and focus the light onto the optical system that illuminates a reticle and projects an image from the reticle onto a target.2. The method of claim 1 , wherein the collector is rotated while the collector is gathering and focusing the light.3. The method of claim 2 , wherein the collector is rotated continuously while the collector is gathering and focusing the light.4. The method of claim 1 , wherein the collector is rotated by applying a mechanical force to the collector.5. The method of claim 1 , wherein the collector is rotated by applying an electromagnetic force to the collector.6. The method of claim 1 , wherein the collector is rotated while within an enclosed chamber of the EUV lithography system.7. The method of claim 1 , wherein the collector is rotated while the EUV lithography system is online.8. The method of claim 6 , further comprising:while rotating the collector, controlling the pressure of gas in a chamber that houses the collector.9. The method of claim 8 , further comprising:while rotating the collector, ...

Methods for Doping High-K Metal Gates for Tuning Threshold Voltages

A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric. 1. A method comprising:forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively;depositing a lanthanum-containing layer comprising a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively;depositing a hard mask comprising a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively, wherein the hard mask is free from both of titanium and tantalum;forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed;removing the second portion of the hard mask and the second portion of the lanthanum-containing layer; andperforming an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.2. The method of further comprising:before the anneal, removing the patterned etching mask; ...

MULTI-LAYER MEMORY ARRAY AND MANUFACTURING METHOD OF THE SAME

A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes. 1. A method for manufacturing a memory array , comprising:forming a multi-layer stack on a surface of a substrate;forming a plurality of first through holes through the multi-layer stack along a vertical direction of the multi-layer stack from a top surface of the multi-layer stack to the surface of the substrate, the first through holes being arranged in equally spaced rows along a first direction along the surface of the substrate, and equally spaced columns along a second direction orthogonal to the first direction;forming a plurality of sacrificial pillars to fill in the first through holes;forming a hard mask layer over the multi-layer stack with the sacrificial pillars, the hard mask layer including a plurality of hard mask through holes exposing regions of the multi-layer stack between neighboring sacrificial pillars in each column of sacrificial pillars;forming a plurality of second through holes through the multi-layer stack along the vertical direction of the multi-layer stack from the top surface of the multi-layer stack to the surface of the substrate, the second through holes being vertically aligned with the hard mask through holes; andremoving the sacrificial pillars filling in the first through holes,wherein the second through holes are connected with the first through holes to form a plurality of trenches extending along the second direction, andthe trenches divide the multi-layer stack into a ...

Germanium Hump Reduction

The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power. 1. A method , comprising:receiving a workpiece comprising a stack of semiconductor layers, the stack comprising a germanium-containing top layer;depositing a first pad oxide layer on the germanium-containing top layer;depositing a second pad oxide layer on the first pad oxide layer;depositing a pad nitride layer on the second pad oxide layer; andpatterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer,wherein the depositing of the first pad oxide layer comprises a first oxygen plasma power,wherein the depositing of the second pad oxide layer comprises a second oxygen plasma power greater than the first oxygen plasma power.2. The method of claim 1 ,wherein a ratio of the second oxygen plasma power to the first oxygen plasma power is between about 2 and about 3.3. The method of claim 1 , wherein a thickness in the first pad oxide layer is identical to a thickness in the second pad oxide layer.4. The method of claim 1 ,wherein the first pad oxide layer comprises a thickness between about 8 Å and about 12 Å,wherein the second pad oxide layer comprises a thickness between about 8 Å and about 12 Å.5. The method of claim 1 , wherein the depositing of the pad ...

Post Gate Dielectric Processing for Semiconductor Device Fabrication

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks. 1. A method of forming a semiconductor device , comprising:forming a semiconductor fin over a substrate;forming spacers over the semiconductor fin, wherein the spacers form a trench over the semiconductor fin;depositing a high-K dielectric layer in the trench;forming a capping layer over the high-K dielectric layer in one processing tool;performing an annealing process to the capping layer;removing the capping layer to expose the high-K dielectric layer; andforming a metal gate electrode over the high-K dielectric layer.2. The method of claim 1 , forming the capping layer over the high-K dielectric layer includes:depositing high-K capping material over the high-K dielectric layer in the processing tool; andpassing a processing gas, in the processing tool, over a top surface of the high-K capping material to form the capping layer.3. The method of claim 2 , wherein the high-K capping material includes titanium nitride (TiN) claim 2 , tantalum nitride (TaN) claim 2 , or tennessine nitride (TsN).4. The method of claim 2 , wherein the processing gas is silane (SiH) and is passed at a pressure of about 4 to 6 torr claim 2 , with a flow rate of about 300 to 500 sccm claim 2 , and for a period of about 100 to 200 seconds.5. The method of claim 1 , wherein a thickness ratio of the capping layer to the high-K ...

DISPLAY PANEL

A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly. 1. A display panel comprising:a plurality of first signal lines disposed parallel to each other;a plurality of second signal lines disposed parallel to each other and crossing over the first signal lines to define a plurality pixel blocks,a plurality of transmission lines disposed parallel to each other and parallel to the first signal lines, and electrically connected to the second signal lines; and a driver circuit configured to generate a first signal and a second signal;', 'a plurality of first pins electrically connected to the first signal lines configured to transmit the first signal to the first signal lines; and', 'a plurality of second pins electrically connected to the transmission lines configured to transmit the second signal to the transmission lines;', 'wherein a first one of the second pins is disposed immediately next to the first one of the first pins, a second one of the second pins is disposed immediately next to the first one of the second pins, and a second one of the first pins is disposed immediately next to the second one of the second pins., 'a driver IC chip comprising2. The display panel as claimed in claim 1 , wherein a third one of the second pins is disposed immediately prior to ...

PNEUMATIC VEHICLE AND PNEUMATIC DRIVING MODULE

A pneumatic driving module is for mounting on and driving a vehicle. The vehicle includes at least one wheel that includes a rim. The pneumatic driving module includes a storage tank, an air delivery unit and an air-driving mechanism. The storage tank is for storing compressed air therein. The air delivery unit includes a tube fluidly communicating with the storage tank for discharging the compressed air stored in the storage tank. The air-driving mechanism fluidly communicates with the tube, and is configured to be mounted directly to the wheel for providing dynamic energy associated with the compressed air to the rim to drive rotation of the wheel. 1. A pneumatic driving module for mounting on and driving a vehicle , the vehicle including at least one wheel that includes a rim , said pneumatic driving module comprising:a storage tank for storing compressed air therein;an air delivery unit including a tube that fluidly communicates with said storage tank for discharging the compressed air stored in said storage tank; andan air-driving mechanism fluidly communicating with said tube of said air delivery unit, and configured to be mounted directly to the wheel for providing dynamic energy associated with the compressed air to the rim of the wheel to drive rotation of the wheel.2. The pneumatic driving module as claimed in claim 1 , the rim of the wheel including a hub and a plurality of blades extending radially and outwardly from the hub claim 1 ,wherein said air-driving mechanism includes an air outlet that fluidly communicates with said tube and that is configured to be disposed adjacent to the hub for guiding the compressed air directly to the blades, and a discharge direction of the compressed air discharged from said air outlet is parallel to an imaginary line tangent to a periphery of the wheel.3. The pneumatic driving module as claimed in claim 1 ,wherein said air delivery unit further includes a control valve mounted between said storage tank and said tube, ...

SYSTEM AND METHOD FOR CALIBRATING TOOL CENTER POINT OF ROBOT

A system for calibrating tool center point of robot is provided, which may include a first image sensor, a second image sensor, and a controller. The first image sensor may have a first image central axis. The second image sensor may have a second image central axis not parallel to the first image central axis, and intersect the first image central axis at an intersection point. The controller may control a robot to repeatedly move a tool center point thereof between the first and the second image central axis. The controller may record a calibration point including the coordinates of the joints of the robot when the tool center point overlaps the intersection point, and then move the tool center point and repeat the above steps to generate several calibration points, whereby the controller may calculate the coordinate of the tool center point according to the calibration points. 1. A system for calibrating tool center point of robot , comprising:a first image sensor, comprising a first image central axis;a second image sensor, comprising a second image central axis intersecting the first image axis at an intersection point; anda controller, configured to control a robot to repeatedly move a tool center point of a tool thereof between the first image central axis and the second image central axis until the tool center point overlaps the intersection point;wherein the controller is configured to record a calibration point including coordinates of joints of the robot when the tool center point overlaps the intersection point, and the controller is configured to move the tool center point and repeat the above steps to generate a plurality of the calibration points in order to calculate a coordinate of the tool center point according to the calibration points.2. The system for calibrating tool center point of robot of claim 1 , wherein the controller controls the robot according to a first transformation relation between a coordinate system of the first image sensor and ...

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING AND OPERATING THE SAME

An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork architecture comprises a handle portion and prong portions extending from the handle portion. The fork architecture comprises a stacked structure and a dielectric layer. The dielectric layer is between the first conductive structure and the handle portion of the stacked structure. 1. An integrated circuit , comprising:a fork architecture comprising a handle portion and prong portions extending from the handle portion, and comprising a stacked structure and a dielectric layer; anda first conductive structure, wherein the dielectric layer is between the first conductive structure and the handle portion of the stacked structure.2. The integrated circuit according to claim 1 , wherein an upper surface of the first conductive structure is higher than or as high as an upper surface of the fork architecture.3. The integrated circuit according to claim 1 , wherein the first conductive structure a first conductive portion and a second conductive portion adjacent to the first conductive portion claim 1 , the first conductive portion and the second conductive portion are respectively away from and adjacent to the prong portions of the fork architecture.4. The integrated circuit according to claim 3 , wherein an upper surface of the first conductive portion is higher than the fork architecture claim 3 , an upper surface of the second conductive portion is as high as an upper surface of the fork architecture.5. The integrated circuit according to claim 1 , further comprising a second conductive structure claim 1 , wherein the dielectric layer is between the second conductive structure and the prong portion of the stacked structure.6. The integrated circuit according to claim 1 , further comprising second conductive structures respectively on the different prong portions.7. The integrated circuit ...

3D VERTICAL CHANNEL TRI-GATE NAND MEMORY WITH TILTED HEMI-CYLINDRICAL STRUCTURE

A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips. 1. A memory device , comprising:a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction;a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction; anddata storage structures on sidewalls of the conductive strips; andthe hemi-cylindrical vertical channel structures comprising semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.2. The memory device of claim 1 , wherein the major axis is tilted at an angle relative to the first direction claim 1 , the angle having a range between 30 degrees and 80 degrees.3. The memory device of claim 1 , wherein the conductive strips in the stack of conductive strips act as tri-gates in contact with the hemi-cylindrical vertical channel structures.4. The memory device of claim 1 , comprising:a second stack of conductive strips, the conductive strips in the second stack extending in the first direction; andan isolation block separating the first-mentioned ...

TRANSPORT VEHICLE, CHARGING SYSTEM AND ELECTRICITY-GENERATING TIRE

A transport vehicle includes a driving unit, a wheel and a charging system. The charging system includes an electricity-generating tire and a converting unit. The electricity-generating tire has a tire body mounted on the wheel, and a piezoelectricity generating unit disposed at the tire body and configured to output electricity when the piezoelectricity generating unit is subjected to mechanical forces attributed to movement of the tire body on a ground surface. The converting unit operates to convert the electricity outputted by the piezoelectricity generating unit into a form of energy for storage in an energy storing unit. 3. The transport vehicle according to claim 1 , wherein the piezoelectricity generating unit includes a plurality of piezoelectric sub-units electrically coupled in parallel claim 1 , each of the piezoelectric sub-units including a plurality of piezoelectric elements electrically coupled in series.4. The transport vehicle according to claim 3 , wherein the piezoelectric sub-units include a plurality of first piezoelectric sub-units that operate at a first frequency claim 3 , and a plurality of second piezoelectric sub-units that operate at a second frequency different from the first frequency.5. The transport vehicle according to claim 4 , wherein the piezoelectric sub-units further include a plurality of third piezoelectric sub-units that operate at a third frequency that is different from the first frequency and the second frequency.6. The transport vehicle according to claim 5 , wherein each of the first piezoelectric sub-units is disposed between an adjacent pair of the second piezoelectric sub-units and an adjacent pair of the third piezoelectric sub-units claim 5 , each of the second piezoelectric sub-units is disposed between an adjacent pair of the first piezoelectric sub-units and an adjacent pair of the third piezoelectric sub-units claim 5 , and each of the third piezoelectric sub-units is disposed between an adjacent pair of the ...

ELECTROPHORETIC DISPLAY APPARATUS

An electrophoretic display apparatus is suitable for being electrically connected to an external circuit and includes a drive array substrate, an electrophoretic display film and a first optical adhesive layer. The electrophoretic display film is disposed on the drive array substrate and includes a flexible substrate and a display medium layer. The flexible substrate has a disposed region and a bonding region. The external circuit is disposed between the flexible substrate and the drive array substrate, located in the bonding region and extends outside the drive array substrate. The display medium layer is disposed between the flexible substrate and the drive array substrate and located in the disposed region. The first optical adhesive layer is disposed between the display medium layer and the drive array substrate. A thickness of the external circuit is substantially a sum of that of the display medium layer and the first optical adhesive layer. 1. An electrophoretic display apparatus suitable for electrically connecting with an external circuit , the electrophoretic display apparatus comprising:a drive array substrate; a flexible substrate having a disposed region and a bonding region, wherein the disposed region surrounds the bonding region, the external circuit is disposed between the flexible substrate and the drive array substrate, and the external circuit is located in the bonding region and extends outside the drive array substrate; and', 'a display medium layer disposed between the flexible substrate and the drive array substrate and located in the disposed region, and, 'an electrophoretic display film disposed on the drive array substrate, the electrophoretic display film comprisinga first optical adhesive layer disposed between the display medium layer and the drive array substrate, wherein a thickness of the external circuit is substantially a sum of a thickness of the medium layer and a thickness of the first optical adhesive layer.2. The ...

Mask Cleaning

A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module. 1. A lithography system comprising:a first load lock chamber configured to receive a mask;a cleaning module configured to clean the mask;a second load lock chamber configured to receive a wafer; andan exposure module configured to expose the wafer to a light source through use of the cleaned mask,wherein a direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.2. The lithography system of claim 1 , wherein the cleaning module is configured to clean a carbon buildup on the mask through chemical reaction.3. The lithography system of claim 1 , further comprising:a mask inspection module configured to inspect the cleaned mask.4. The lithography system of claim 3 , wherein a side path is shared by the cleaning module and the mask inspection module to couple to the direct path.5. The lithography system of claim 1 , wherein the lithography system is an Extreme Ultra-Violet (EUV) lithography system claim 1 , the mask is an EUV mask claim 1 , and the light source is an EUV light source.6. The lithography system of claim 1 , wherein the cleaning module is configured to produce radicals to clean the mask through chemical reaction.7. The lithography system of claim 6 , wherein the radicals are hydrogen radicals.8. The lithography system of claim 1 , wherein the cleaning module is configured to produce a plasma gas including at least one of: hydrogen ...

MEMORY DEVICE

A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction. 1. A memory device , comprising:a stacked structure in a memory array region and a staircase contact region, the stacked structure comprising first conductive layers and a second conductive layer arranged in a longitudinal direction, wherein the memory array region and the staircase contact region are arranged in a first lateral direction; andat least one first element structure passing through the first conductive layers and the second conductive layer along the longitudinal direction; wherein:the first conductive layers surround a side wall surface of the at least one first element structure; andthe second conductive layer comprises conductive portions arranged in a second lateral direction, the conductive portions are completely separated from each other by the at least one first element structure, the first lateral direction is different from the second lateral direction.2. The memory device according to claim 1 , wherein the at least one first element structure comprises an insulating wall claim 1 , the insulating wall has an enclosed rectangular shape. ...

SYSTEMS, METHODS, AND APPARATUS FOR INTEGRATED TUNING CAPACITORS IN CHARGING COIL STRUCTURE

Systems, methods, and apparatus are disclosed for power transfer including a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures, and a tuning capacitance located directly over the ferrite element in the low flux region. 1. A device for power transfer , comprising:a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures; anda tuning capacitance located directly over the ferrite element in the low flux region.2. The device of claim 1 , wherein the plurality of coil structures are “D” shaped.3. The device of claim 1 , wherein the plurality of coil structures comprise multiple vertically stacked coils.4. The device of claim 1 , wherein the low flux region is dependent on an amount of current present in the plurality of coil structures.5. The device of claim 1 , wherein the tuning capacitance comprises a plurality of surface mount capacitors located on a printed circuit board located between the plurality of coil structures directly over the ferrite element in the low flux region.6. The device of claim 1 , wherein an electrical characteristic of the high flux region defines an electrical characteristic of the low flux region.7. The device of claim 1 , wherein the high flux region is formed by a plurality of high flux regions in the absence of a charging-receiving structure.8. The device of claim 1 , wherein the high flux region is formed by a plurality of high flux regions in the presence of a charging-receiving structure.9. A method for power transfer claim 1 , comprising:locating a plurality of coil structures over a ferrite element;generating a high flux region and a low flux region, the low flux region being ...

STAIR CONTACT STRUCTURE, MANUFACTURING METHOD OF STAIR CONTACT STRUCTURE, AND MEMORY STRUCTURE

A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages. 1. A stair contact structure , comprising:a plurality of layers of stacking structures, wherein each stacking structure comprises a conductive layer and an insulating layer, and the conductive layers and the insulating layers are interlaced; anda first etch stop layer penetrating through the stacking structures vertically and extending along a first horizontal direction, wherein the conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages, wherein a length along the first horizontal direction of one of the conductive layers of said each stacking structure is smaller than a length along the first horizontal direction of one of the insulating layers positioned on and directly contacting said one of the conductive layers of said each stacking structure.2. The stair contact structure according to claim 1 , wherein the first etch stop layer has a first length along the first horizontal direction claim 1 , the stacking structures have a second length along the first horizontal direction claim 1 , and the second length is larger ...

IN-MEMORY COMPUTING DEVICE

An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results. 1. An in-memory computing device , comprising:a plurality of memory cell arrays, respectively receiving a plurality of input signals, wherein the input signals are divided into a plurality of groups, the groups respectively have at least one partial input signal, the at least one partial input signal of each of the groups has a same value, and numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ratio of 2; anda plurality of sensing amplifiers, respectively coupled to the memory cell arrays,wherein the memory cell arrays respectively provide a plurality of weightings, and respectively perform multiply-add operations according to the received input signals and the provided weightings to generate a plurality of computation results, and the sensing amplifiers respectively generate a plurality of sensing results according to the computation results.2. The in-memory computing device as claimed in claim 1 , wherein the computation results are signals of an analog format.3. The in-memory computing device as claimed in claim 1 , wherein each of the ...

THREE DIMENSIONAL MEMORY DEVICE

A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region. 1. A three-dimensional (3D) memory device , comprising:a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure, wherein the multi-layer stacked structure comprises a stair region and an non-stair region, the stair region comprises a plurality of steps, each step comprises an immediately-adjacent pair of the conductive layers and insulating layers;a plurality of memory structures disposed in the non-stair region and each memory structure passing through the conductive layers and the insulating layers; anda fishbone dielectric structure comprises a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.2. The 3D memory device of claim 1 , wherein the fishbone dielectric structure is a dielectric structure without electrically-conductive materials.3. The 3D memory device of claim 1 , wherein each side bone extends along a sidewall of a corresponding step of the stair region.4. The 3D memory device of claim 1 , wherein each side bone is in contact with a sidewall of a corresponding step of the stair region.5. The 3D memory device of claim 1 , further ...

PATTERNED ORGANOMETALLIC PHOTORESISTS AND METHODS OF PATTERNING

A rinse process is described for processing an initially patterned structure formed with an organometallic radiation sensitive material, in which the rinse process can remove portions of the composition remaining after pattern development to make the patterned structure more uniform such that a greater fraction of patterned structures can meet specifications. The radiation sensitive material can comprise alkyl tin oxide hydroxide compositions. The rinsing process can be effectively used to improve patterning of fine structures using extreme ultraviolet light. 1. A method for forming a pattern in a radiation sensitive organometallic resist film on a surface of a substrate , the method comprising rinsing an initial patterned structure with a rinse solution to remove a portion of developed photoresist to control pattern dimensions and to form an adjusted patterned structure ,wherein the initial patterned structure was formed by (i) coating the surface of the substrate with an organometallic radiation sensitive resist material to form the radiation sensitive resist film, (ii) exposing the radiation sensitive resist film to patterned radiation to form an exposed film with exposed portions and unexposed portions, and (iii) contacting the exposed film with a developing solution to form a developed photoresist wherein either the exposed portions or the unexposed portions are selectively soluble in the developing solution.2. The method of wherein the rinse solution comprises aqueous quaternary ammonium hydroxide and the developing solution comprises an organic solvent.3. The method of wherein the developing solution comprises aqueous quaternary ammonium hydroxide and the rinse solution comprises an organic solvent.4. The method of wherein the rinse solution is about 0.5 to 30 weight percent aqueous tetramethyl ammonium hydroxide (TMAH).5. The method of wherein the organometallic radiation sensitive resist material comprises an alkyltin oxide hydroxide approximately ...

METAL GATE CAP

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer. 1. A semiconductor device , comprising:a first plurality of channel members being vertically stacked;a second plurality of channel members being vertically stacked;an n-type work function layer wrapping around each of the first plurality of channel members;a first p-type work function layer over the n-type work function layer and wrapping around each of the first plurality of channel members;a second p-type work function layer wrapping around each of the second plurality of channel members;a third p-type work function layer over the second p-type work function layer and wrapping around each of the second plurality of channel members; anda gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.2. The semiconductor device of claim 1 , wherein the n-type work function layer comprises Ti claim 1 , Al claim 1 , Ag claim 1 , Mn claim 1 , Zr claim 1 , TiAl claim 1 , ...

Methods for Doping High-K Metal Gates for Tuning Threshold Voltages

A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric. 1. A method comprising:depositing a doping-metal-containing layer comprising a first portion over a first gate dielectric;depositing a hard mask comprising a first portion over and contacting the first portion of the doping-metal-containing layer, wherein an entirety of the hard mask is formed of a homogenous material;forming an etching mask comprising a first portion over and contacting the first portion of the hard mask;performing an anneal process to drive a dopant in the doping-metal-containing layer into the first gate dielectric; andremoving the doping-metal-containing layer.2. The method of claim 1 , wherein the forming the etching mask comprises dispensing a photoresist over and contacting the hard mask claim 1 , with the photoresist and the hard mask being in contact with each other claim 1 , and wherein a contact angle between the photoresist and the hard mask is smaller than about 10 degrees.3. The method of further comprising removing the etching mask before the anneal process.4. The method of further ...

Forming Low-Resistance Capping Layer Over Metal Gate Electrode

A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction. 1. A device , comprising:a plurality of active region structures that each protrude upwards in a vertical direction, wherein the active region structures each extend in a first horizontal direction, and wherein the active region structures are separated from one another in a second horizontal direction different from the first horizontal direction;a gate structure disposed over the active region structures, wherein the gate structure extends in the second horizontal direction, and wherein the gate structure partially wraps around each of the active region structures;a conductive capping layer disposed over the gate structure; anda gate via disposed over the conductive capping layer, wherein a dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.2. The device of claim 1 , wherein the dimension of the conductive capping layer measured in the second horizontal direction is at least multiple times greater than the maximum dimension of the gate via measured in the second horizontal ...

SEMICONDUCTOR ISOLATION STRUCTURE AND METHOD FOR MAKING THE SEMICONDUCTOR ISOLATION STRUCTURE

A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer. 1. A semiconductor isolation structure comprising:a handle layer;a buried insulation layer that is disposed on the handle layer;a semiconductor layer that is disposed on the buried insulation layer and that has a first doping type, the semiconductor layer having a functional area in which doped regions of a semiconductor device are to be formed;a deep trench isolation structure that penetrates the semiconductor layer and the buried insulation layer, and that surrounds the functional area; anda first heavy doping region that is formed in the semiconductor layer, that is disposed between the functional area and the deep trench isolation structure, and that is surrounded by the deep trench isolation structure, the first heavy doping region having the first doping type, a doping concentration of the first heavy doping region being higher than that of the semiconductor layer.2. The semiconductor isolation structure as claimed in claim 1 , wherein:the deep trench isolation structure has a first side wall that faces the functional area; andthe first heavy doping region ...

FIELD EFFECT TRANSISTOR INCLUDING A DOWNWARD-PROTRUDING GATE ELECTRODE AND METHODS FOR FORMING THE SAME

A field effect transistor contains a semiconductor material layer including a source-side doped well, a source region, and a drain region. A shallow trench isolation structure is embedded in the semiconductor material layer and extends between the source region and the drain region. Agate dielectric layer overlies the semiconductor material layer. A horizontally-extending portion of a gate electrode overlies the gate dielectric layer, and at least one downward-protruding portion of the gate electrode extends downward from a bottom surface of the horizontally-extending portion into an upper region of the shallow trench isolation structure. The gate electrode is vertically spaced from a bottom surface of the shallow trench isolation structure modifies electrical field in a semiconductor channel to reduce hot carrier injection. 1. A field effect transistor comprising:a semiconductor material layer including a source-side doped well having a doping of a first conductivity type, a source region having a doping of a second conductivity type that is an opposite of the first conductivity type and embedded in the source-side doped well, and a drain region having a doping of the second conductivity type and laterally spaced from the source region;a shallow trench isolation structure embedded in the semiconductor material layer and comprising a portion located between the source region and the drain region;a gate dielectric layer overlying the semiconductor material layer; anda gate electrode comprising a horizontally-extending portion that overlies the gate dielectric layer and at least one downward-protruding portion that extends downward from a bottom surface of the horizontally-extending portion into an upper region of the shallow trench isolation structure and vertically spaced from a bottom surface of the shallow trench isolation structure.2. The field effect transistor of claim 1 , further comprising an intermediate doped well located between the source-side doped well ...

AUTOMATED CALIBRATION SYSTEM AND METHOD FOR A WORKPIECE COORDINATE FRAME OF A ROBOT

An automated calibration system for a workpiece coordinate frame of a robot includes a physical image sensor having a first image central axis, and a controller for controlling the physical image sensor adapted on a robot to rotate by an angle to set up a virtual image sensor having a second image central axis. The first and the second image central axes are intersected at an intersection point. The controller controls the robot to repeatedly move back and forth a characteristic point on the workpiece between these two axes until the characteristic point overlaps the intersection point. The controller records a calibration point including coordinates of joints of the robot, then the controller moves another characteristic point and repeats the foregoing movement to generate several other calibration points. According to the calibration points, the controller calculates relative coordinates of a virtual tool center point and the workpiece to the robot. 2. The automated calibration system for a workpiece coordinate frame of a robot of claim 1 , wherein the controller controls the robot to move according to a coordinate system of the robot with respect to a transformation relationship of another coordinate system of the physical image sensor and the virtual image sensor claim 1 , and a plurality of images of the physical image sensor and the virtual image sensor.3. The automated calibration system for a workpiece coordinate frame of a robot of claim 1 , wherein each of the plurality of calibration points includes rotational angles of the plurality of joints with respect to a preset point.4. The automated calibration system for a workpiece coordinate frame of a robot of claim 3 , wherein the controller calculates coordinates of the virtual tool center point according to the plurality of calibration points and a Denavit-Hartenberg parameter of the robot.5. The automated calibration system for a workpiece coordinate frame of a robot of claim 1 , wherein a quantity of the ...

RESIN COMPOSITION AND ARTICLE MADE THEREFROM

A resin composition includes a vinyl-containing polyphenylene ether resin and a prepolymer, wherein the prepolymer is prepared by prepolymerization of a mixture which at least includes a divinylbenzene, a triallyl compound and a diallyl isophthalate. An article made from the resin composition is also provided, which includes a prepreg, a resin film, a laminate or a printed circuit board. The article achieves improvements in at least one properties of glass transition temperature, copper foil peeling strength, dissipation factor, inner resin flow, melt viscosity, minimum dynamic viscosity, resin filling property in open area, and water resistance. 1. A resin composition comprising a vinyl-containing polyphenylene ether resin and a prepolymer , wherein the prepolymer is prepared by prepolymerization of a mixture which at least comprises a divinylbenzene , a triallyl compound and a diallyl isophthalate.2. The resin composition of claim 1 , wherein the vinyl-containing polyphenylene ether resin comprises a vinylbenzyl-containing polyphenylene ether resin claim 1 , a methacrylate-containing polyphenylene ether resin claim 1 , an allyl-containing polyphenylene ether resin claim 1 , a vinylbenzyl-modified bisphenol A polyphenylene ether resin claim 1 , a chain-extended vinyl-containing polyphenylene ether resin or a combination thereof.3. The resin composition of claim 1 , wherein the triallyl compound comprises triallyl isocyanurate claim 1 , triallyl cyanurate or a combination thereof.4. The resin composition of claim 1 , comprising 90 parts by weight of the vinyl-containing polyphenylene ether resin and 7 to 35 parts by weight of the prepolymer.5. The resin composition of claim 1 , comprising 90 parts by weight of the vinyl-containing polyphenylene ether resin and 10 to 30 parts by weight of the prepolymer.6. The resin composition of claim 1 , wherein the divinylbenzene claim 1 , the triallyl compound and the diallyl isophthalate are present in a weight ratio of 10-20: ...

FORMING MEMORY USING DOPED OXIDE

A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip. 1. A method for manufacturing a memory device , comprising:forming a strip of semiconductor material having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region;forming a memory layer on surfaces of the strip in the memory region;forming a plurality of memory cells over the memory region of the strip;depositing a doped insulating material over a portion of the strip between the contact landing area region and the memory region; andcausing diffusion of dopant from the doped insulating material into the strip in said portion of the strip.2. The method of claim 1 , including a conductor in contact with the strip at an end of the strip opposite the contact landing area region claim 1 , and an end region between said conductor and the memory region of the strip claim 1 , and including depositing the doped insulating material over the end region.3. The method of claim 1 , including a second contact landing area region in the strip at an end opposite the first mentioned contact landing area region claim 1 , and an end region between said second contact landing area region and the memory region of the strip claim 1 , and including depositing the doped insulating material over the end region.4. The method of claim 1 , ...

HETEROGENEOUS ENERGY SUPPLY SYSTEM

A heterogeneous energy supply system includes an electric power management unit controlled by a control unit to output electric power. An electricity supply unit is powered by the electric power management unit, and is controlled by the control unit to regulate the electric power so as to provide an electricity output. An air supply unit is powered by the electric power management unit, and is controlled by the control unit to generate an air output. A hydrogen supply unit is powered by the electric power management unit, and is controlled by the control unit to generate a hydrogen gas output. 1. A heterogeneous energy supply system comprising:a control unit;an electric power management unit electrically connected to and controlled by said control unit to output electric power;an electricity supply unit electrically connected to said electric power management unit for receiving the electric power therefrom, and electrically connected to and controlled by said control unit to regulate the electric power so as to provide an electricity output;an air supply unit electrically connected to said electric power management unit for receiving the electric power therefrom, and electrically connected to and controlled by said control unit to generate an air output; anda hydrogen supply unit electrically connected to said electric power management unit for receiving the electric power therefrom, and electrically connected to and controlled by said control unit to generate a hydrogen gas output.2. The heterogeneous energy supply system as claimed in claim 1 , further comprising a solar energy converter that is electrically connected to said electric power management unit claim 1 , and that is operable to convert solar energy into electric energy to be provided to said electric power management unit.3. The heterogeneous energy supply system as claimed in claim 2 , wherein said electric power management unit includes:a boost converter that is electrically connected to said solar ...

Method and Structure to Improve Process Window for Lithography

The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process

3-D IC Device with Enhanced Contact Area

A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors. 1. A device comprising:a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;a stack of alternating active and insulating layers overlying the recess;each of a plurality of said active layers having a lower portion extending along a lower plane over and generally parallel to the bottom;each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers; anda plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers.2. The device of claim 1 , wherein:the stack of alternating active and insulating layers also overlies the upper surface of the substrate and the recess; andeach of the plurality of active layers also has an upper portion extending ...

MAGNETIC FORCE GENERATING DEVICE AND COLLISION PREVENTION SYSTEM INCLUDING THE SAME

A magnetic force generating device is provided for application to a first object that is movable relative to a second object providing a first magnetic force, and includes a coil disposed on the first object, a sensing module disposed on the first object adjacent to the coil for sensing a distance between the first and second objects, and a processor. When the sensed distance is shorter than a threshold value, the processor enables provision to the coil of a driving current having a magnitude negatively correlated to the sensed distance, so that the coil generates a second magnetic force, which is repulsive to the first magnetic force, in response to the driving current. 1. A magnetic force generating device for application to a first object that is movable relative to a second object , the second object providing a first magnetic force , said magnetic force generating device comprising:a controllable power source;a coil to be disposed on the first object, and configured to receive electrical power from said controllable power source;a sensing module to be disposed on the first object adjacent to said coil, and configured to sense a distance between the first object and the second object;a switch module configured to make or break electrical connection between said controllable power source and said coil; anda processor coupled to said controllable power source, said sensing module and said switch module;wherein, when the distance sensed by said sensing module is shorter than a threshold value, said processor is configured to control said controllable power source to generate a driving current having a magnitude negatively correlated to the distance sensed by said sensing module, and to control said switch module to make electrical connection so that the driving current generated by said controllable power source is provided to said coil, said coil generating a second magnetic force in response to the driving current, the second magnetic force being repulsive to the ...

3-D IC Device with Enhanced Contact Area

A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors. 1. A device comprising:a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;a stack of alternating active and insulating layers overlying the upper surface of the substrate and the recess;each of a plurality of said active layers having an upper portion extending along an upper plane over and generally parallel to the upper surface and a lower portion extending along a lower plane over and generally parallel to the bottom;each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers; anda plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers.2. The device of claim 1 , wherein the plurality of conductive strips comprise sidewall ...

NETWORK SERVICE SYSTEM AND NETWORK SERVICE METHOD

The network service system includes a transmission controller and an authentication server. The transmission controller determines whether a service request belongs to a service of a proprietary network registered with the mobile edge computing platform and comprises an authentication request. The service request is from an electronic device. When the transmission controller determines that the service request belongs to a service of the proprietary network and comprises an authentication request, the authentication server executes an authentication mechanism according to packet information that corresponds to the service request, and the authentication mechanism triggers a permission server to confirm the identity information and permission information of the electronic device. 1. A network service system , suitable for use in a mobile edge computing platform , the network service system comprising:a transmission controller, configured to determine whether a service request belongs to a service of a proprietary network registered with the mobile edge computing platform and comprises an authentication request, wherein the service request is from an electronic device; andan authentication server, wherein when the transmission controller determines that the service request belongs to the service of the proprietary network and comprises the authentication request, the authentication server executing an authentication mechanism according to a packet information that corresponds to the service request, the authentication mechanism triggers a permission server to confirm and return an identity information and a permission information of the electronic device.2. The network service system of claim 1 , further comprising:an identity management controller, wherein when the permission server successfully confirms the identity information and the permission information of the electronic device, the identity management controller establishes a correspondence of the identity ...

SYSTEM AND METHOD FOR ESTABLISHING A JUNCTION TRACE OF AN ASSEMBLY

A system for establishing a junction trace of an assembly includes a surface model creating module, a processing module, and a material inspection module. The assembly includes a first part and a second part assembled with each other. The surface model creating module scans the first part and the second part to separately establish first surface model data and second surface model data. The processing module establishes assembled surface model data according to the first surface model data and the second surface model data, determines a junction region from the assembled surface model data, and determines inspection points mapped on the assembly according to the junction region. The material inspection module inspects materials of the assembly at the inspection points. The processing module establishes a junction trace of the first part and the second part in the assembly according to a material inspection result.

PIXEL ARRAY

A pixel array including first and second signal lines, an active device, a pixel electrode and selection lines is provided. The second signal lines are intersected with the first signal lines to drive the active device, and the pixel electrode is connected to the active device. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines, where at least one selective line is disposed between the adjacent two second signal lines. An amount ratio of the first signal lines and the selection lines is a/a, where a≦a, and when a and a are mutually prime numbers, the selection lines are divided into a plurality of groups, and each group includes a selection lines electrically connected to the first signal lines, and (a−a) selection lines not electrically connected to the first signal lines. 1. A pixel array , comprising:a plurality of first signal lines;a plurality of second signal lines, electrically insulated to the first signal lines, and intersected with the first signal lines to define a plurality of pixel regions;a plurality of active devices, located in the pixel regions, and each of the active devices being electrically connected to the corresponding first signal line and the second signal line;a plurality of pixel electrodes, disposed corresponding to the pixel regions, and electrically connected to the active devices; and{'b': 1', '2', '1', '2', '1', '2', '1', '2', '1, 'a plurality of selection lines, electrically insulated to the second signal lines and intersected with the first signal lines, and at least one selection line being disposed between the two neighbouring second signal lines, wherein an amount ratio of the first signal lines and the selection lines is a/a, where a≦a, and when a and a are mutually prime numbers, the selection lines are divided into a plurality of groups, and each group comprises a selection lines electrically connected to the first signal lines, and (a−a) selection lines not ...

MOBILE EDGE PLATFORM SERVERS AND USER EQUIPMENT CONTEXT MIGRATION MANAGEMENT METHODS THEREOF

A user equipment (UE) context migration management method applied to a mobile edge platform for managing a UE context of a mobile communication device is provided. An embodiment of the UE context migration management method includes: receiving at least one migration request for the UE context; calculating a first difference data corresponding to the UE context in response to the at least one migration request, wherein the first difference data represents a difference between the UE contexts obtained in two consecutive UE context retrieving operations corresponding to the at least one migration request; and transmitting the first difference data to the neighboring mobile edge platform to request the neighboring mobile edge platform to perform a migration operation of the UE context based on the first difference data. 1. A user equipment (UE) context migration management method applied to a mobile edge platform for managing a UE context of a mobile communication device , the method comprising:receiving at least one migration request of the UE context;calculating a first difference data corresponding to the UE context in response to the at least one migration request, wherein the first difference data represents a difference between the UE contexts obtained in two consecutive UE context retrieving operations corresponding to the at least one migration request; andtransmitting the first difference data to at least one neighboring mobile edge platform to request the neighboring mobile edge platform to perform a migration operation of the UE context based on the first difference data,wherein the mobile edge platform connects to the neighboring mobile edge platform and wirelessly connects to the mobile communication device.2. The UE context migration management method as claimed in claim 1 , further comprising:receiving a first UE context from the neighboring mobile edge platform;receiving a second difference data from the neighboring mobile edge platform;generating a ...

ARTIFICIAL INTELLIGENCE ACCELERATOR AND OPERATION THEREOF

An artificial intelligence accelerator receives a binary input data set and a selected layer of layers of overall weight pattern. The artificial intelligence accelerator includes processing tiles and a summation output circuit. Each processing tile receives one of input data subsets of the input data set and performs a convolution operation on weight blocks of each sub weight pattern of the overall weight pattern to obtain weight operation values and then obtains a weight output value expected from a direct convolution operation on the input data subset with the sub weight pattern through performing a multistage shifting and adding operation on the weight operation values. The summation output circuit sums up the plurality of weight output values through a multistage shifting and adding operation, so as to obtain a sum value expected from a direct convolution operation performed on the input data set with the overall weight pattern. 1. An artificial intelligence accelerator , configured to receive a binary input data set and a selected layer of a plurality of layers of an overall weight pattern to perform a convolution operation , wherein the input data set is divided into a plurality of data subsets , and the artificial intelligence accelerator comprises: a receive-end component, configured to receive one of the data subsets;', 'a weight storage unit, configured to store a part of the overall weight pattern, wherein the partial weight storage unit comprises a plurality of weight blocks, and each of the weight blocks stores a block part of the partial weight pattern in order of bits, wherein a cell array structure of the weight storage unit, with respect to a corresponding one of the data sets, configured to perform a convolution operation on the data subset with each block part respectively to obtain a plurality of sequential weight operation values; and', 'a block-wise output circuit, comprising a plurality of shifters and a plurality of adders, and configured to ...

SPIKING NEURAL NETWORKS CIRCUIT AND OPERATION METHOD THEREOF

A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse. 1. A spiking neural networks (SNN) circuit , comprising: a plurality of page buffers, providing a plurality of data signals;', 'a plurality of bit line transistors, each of which is electrically connected to one of the page buffers;', 'a plurality of bit lines, each of which is electrically connected to one of the bit line transistor for receiving one of the data signals;', 'a plurality of memory cells, each of which is electrically connected to one of the bit lines;', 'one word line, electrically connected to the memory cells;', 'a plurality of source lines, each of which is electrically connected to one of the memory cells; and', 'a plurality of source line transistors, each of which is electrically connected to one of the source lines, wherein the source line transistors are connected together; and, 'a bit-line input synapse array, includinga neuron circuit, for outputting a feedback pulse.2. The spiking neural networks circuit according to claim 1 , wherein the bit line transistors and the bit lines form a presynaptic zone claim 1 , the memory cells and the word line form a synaptic zone claim 1 , and the source line transistors and the source lines form a postsynaptic zone.3. The spiking neural networks circuit according to claim 1 , wherein ...

DUMMY VERTICAL STRUCTURES FOR ETCHING IN 3D NAND MEMORY AND OTHER CIRCUITS

A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad. 1. A memory device , comprising:a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad;an array of vertical pillars extending through the stack of patterned conductor layers wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers, the array having an array boundary proximal to the pad;a first set of isolation blocks extending through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad; anda second set of isolation blocks inside the array boundary and extending through the plurality of patterned conductor layers isolating the other strips from the pad.2. The memory device of claim 1 , wherein the second set of isolation blocks include isolation blocks connecting a pair of adjacent isolation blocks in the first set of isolation blocks.3. The memory device of claim 1 , wherein some of the vertical pillars between the pad and the other strips isolated from the pad are penetrated by the isolation blocks in the second set of ...

Method for FinFET LDD Doping

A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus. 1. A semiconductor device , comprising:a substrate;an isolation structure over the substrate;a fin over the substrate and the isolation structure;a gate structure engaging a first portion of the fin;first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;source/drain (S/D) features adjacent to the first sidewall spacers; andsecond sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride, wherein the second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.2. The semiconductor device of claim 1 , wherein the fin includes silicon or silicon germanium.3. The semiconductor device of claim 1 , wherein the fin includes multiple layers of semiconductor materials.4. The semiconductor device of claim 1 , wherein each of the first sidewall spacers includes multiple layers of dielectric materials claim 1 , and each of second sidewall spacers includes multiple layers of dielectric materials.5. The semiconductor device of claim 1 , wherein the first portion of the fin has a first height above a top surface of the isolation structure claim 1 , the second sidewall ...

TRANSMISSION DEVICE AND ROBOTIC ARM

A transmission device is provided, including a first housing, a second housing connected to the first housing, a third housing axially connected to the second housing, an adapter disposed on the third housing, a first power shaft actuating the first housing and the second housing to rotate, a second power shaft actuating the third housing to rotate, and a third power shaft actuating the adapter to rotate. The second and third power shafts are a coaxial structure. The first power shaft is an independent rod. Therefore, a motor loaded with a smaller rotation inertia and being thus cheaper can be used to drive the first power shaft, and the transmission device can have a reduced cost. 1. A transmission device , comprising:a first housing having a first end portion and a second end portion opposing each other;a second housing connected to the first end portion of the first housing;a first speed reducer disposed between the first end portion of the first housing and the second housing; anda first power shaft for actuating the first speed reducer to drive the second housing to rotate.2. The transmission device of claim 1 , wherein the first power shaft actuates the first speed reducer through a first transmission mechanism.3. The transmission device of claim 2 , further comprising a first motor for driving the first power shaft.4. The transmission device of claim 3 , wherein the first motor drives the first power shaft through a bevel gear set.5. The transmission device of claim 2 , wherein the first transmission mechanism is a gear set and transfers power of the first transmission mechanism through a connection structure to the first speed reducer claim 2 , and wherein the connection structure is a pipe.6. The transmission device of claim 2 , further comprising:a third housing axially connected to the second housing, wherein the first power shaft actuates the first speed reducer through the first transmission mechanism to drive the second housing and the third housing to ...

Semiconductor Device and Method

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer. 1. A method comprising:forming a dummy gate dielectric over a semiconductor substrate;forming a dummy gate electrode over the dummy gate dielectric;depositing a gate spacer adjacent the dummy gate electrode and the dummy gate dielectric;removing the dummy gate electrode to form a recess;implanting an impurity in a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, a second region of the gate spacer remaining unmodified by the implanting;removing the dummy gate dielectric and the first region of the gate spacer; andforming a replacement gate in the recess, the replacement gate contacting the second region of the gate spacer.2. The method of claim 1 , wherein the impurity is oxygen claim 1 , and implanting the impurity in the first region of the gate spacer comprises:flowing a gas source comprising an oxygen source precursor gas and a carrier gas over the semiconductor substrate;generating a plasma from the gas source, the plasma comprising oxygen ions and oxygen radicals; andaccelerating the oxygen ions in the plasma towards the gate spacer in a non-directional manner.3. The method of claim 2 , wherein the plasma comprises from 0.1% to 1% oxygen ions and from 90% to 99.9% oxygen radials.4. The method of claim 2 , wherein the plasma is generated at a temperature in a range of 20° C. to 500° C. claim 2 , at a pressure in a range of 200 ...

Multiple Threshold Voltage Implementation Through Lanthanum Incorporation

A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon. 1. A method comprising:forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively;depositing a first lanthanum-containing layer overlapping the first gate dielectric;depositing a second lanthanum-containing layer overlapping the second gate dielectric, wherein the second lanthanum-containing layer is thinner than the first lanthanum-containing layer; andperforming an anneal process to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively, wherein during the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.2. The method of claim 1 , wherein the depositing the second lanthanum-containing layer comprises:depositing a first blanket lanthanum-containing layer overlapping the first gate dielectric, the second gate dielectric, and the third gate dielectric;removing the first blanket lanthanum-containing layer from a first region overlying the second ...

Method for FinFET LDD Doping

A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench. 1. A method , comprising:providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;performing a first implantation process to implant a dopant into the fin adjacent to the gate structure;forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;after the first etching process, performing a second implantation process to implant the dopant into the fin and the fin sidewall spacers;after the second implantation process, performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers; andepitaxially growing a semiconductor material in the trench.2. The method of claim 1 , wherein the first implantation process dopes the dopant into the fin up to a ...

Method for Integrated Circuit Patterning

Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern. 1. A method of forming a pattern for an integrated circuit (IC) , the method comprising:forming a first material layer over a substrate, wherein the first material layer has a first etch rate;forming a resist layer over the first material layer;exposing the resist layer to a radiation for patterning the resist layer, wherein the radiation reaches the first material layer and alters the first material layer to have a second etch rate, different from the first etch rate;developing the resist layer thereby forming a patterned resist layer; andetching the first material layer with the patterned resist layer as an etch mask thereby forming a patterned first material layer.2. The method of claim 1 , wherein the substrate includes a hard mask layer over which the first material layer is formed.3. The method of claim 1 , wherein:the first material layer is configured such that the second etch rate is less than the first etch rate; andthe resist layer is a positive resist.4. The method of claim 3 , wherein the first material layer includes a polymerization of Ethyl(α-hydroxy)acrylate (EHMA) and methacryl acid (MAA).5. The method of claim 1 , wherein:the first material layer is configured such that the ...

SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION

Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height. 1. A method , comprising:measuring a first topographical height at a first coordinate on a substrate;measuring a second topographical height at a second coordinate on the substrate;providing the measured first and second topographical heights as a wafer map; and using a first focal point when exposing the first coordinate on the substrate, wherein the first focal point is determined using the first topographical height; and', 'using a second focal point when exposing the second coordinate on the substrate, wherein the second focal point is determined using the second topographical height., 'performing an exposure process on the substrate using the wafer map, wherein the exposure process includes2. The method of claim 1 , wherein the measuring the first and second topographical heights are performed concurrently using a multi-tip atomic force microscopy (AFM) tool.3. The method of claim 1 , wherein the measuring the second topographical height is performed substantially concurrently with the exposing of the first coordinate.4. The method of claim 1 , wherein the wafer map is generated by determining an offset value between the first topographical height and a third height associated with the first coordinate.5. The ...