Method and apparatus for power management in handover between heterogeneous networks

A method for power management in handover between heterogeneous networks comprising: an MIH layer obtains power information and provides it for an MIH user layer; the MIH user layer determines the handover policy according to the power information. In various embodiments of the disclosure, the MIH layer triggers an event so that the MIH user layer can obtain power information, and select a lower-layer network connection automatically according to the current power status, thus implementing handover; the MIH user layer sends a query request to the MIH layer to obtain power consumption parameters from the network, and selects a lower-layer network connection according to the power consumption and the current power status, thus implementing handover and making more accurate and effective decisions in the handover.

Multilayered printed circuit board, solder resist composition, and semiconductor device

The present invention is to provide a multilayered printed circuit board free from cracks attributed to thermal expansion difference between a solder resist layer and another part and a multilayered printed circuit board of the present invention comprises a conductor circuit and a resin insulating layer serially formed on a substrate in an alternate fashion and in repetition and a solder resist layer formed as an outermost layer, and the solder resist layer contains an inorganic filler.

Method And System For Radio Network Environment Detection And Reporting, And Media Independent Handover Apparatus

A method and a system for radio network environment detection and reporting in a network handover and a media independent handover (MIH) apparatus are provided. The method includes the following: an MIH function (MIHF) at a terminal side initiates a network scan, and generates a parameter report on a radio network environment around the terminal including dynamic information and static information of a scanned point of access (PoA) after the scan is completed; the MIHF at the terminal side sends the parameter report on the radio network environment to an upper layer at the terminal side or to an MIHF at a network side. The method and system support homogeneous and heterogeneous network environments at the same time.

Phase inversion pore-forming agent and pore-forming method for fly ash-based ceramic flat membrane support

The present disclosure provides a phase inversion pore-forming agent and a pore-forming method for a fly ash-based ceramic flat membrane support. The phase inversion pore-forming agent includes poly(oxyphenylene sulfone) and N-methylpyrrolidone (NMP), and is used in a preparation process of the fly ash-based ceramic flat membrane support. Pores can be formed through phase inversion, forming straight-through pores with gradient distribution inside the ceramic flat membrane support, thus avoiding a low porosity, a poor water flux, and uneven pore formation of the existing fly ash-based ceramic flat membrane support.

Regulation of autonomic control of bladder voiding after a complete spinal cord injury

In various embodiments methods and devices are provided for regulating bladder function in a subject after a spinal cord and/or brain injury. In certain embodiments the methods comprise applying a pattern of electrical stimulation to the Lumbosacral spinal cord at a frequency and intensity sufficient to initiate micturition and/or to improve the amount of bladder emptying. In certain embodiments the electrical stimulation is at a frequency and intensity sufficient to improve the amount of bladder emptying (e.g., to provide at least 30% emptying or at least 40% emptying, or at least 50% emptying, or at least 60% emptying, or at least 70% emptying, or at least 80% emptying, or at least 90% emptying, or at least 95% emptying.

REGULATION OF AUTONOMIC CONTROL OF BLADDER VOIDING AFTER A COMPLETE SPINAL CORD INJURY

In various embodiments methods and devices are provided for regulating bladder function in a subject after a spinal cord and/or brain injury. In certain embodiments the methods comprise applying a pattern of electrical stimulation to the Lumbosacral spinal cord at a frequency and intensity sufficient to initiate micturition and/or to improve the amount of bladder emptying. In certain embodiments the electrical stimulation is at a frequency and intensity sufficient to improve the amount of bladder emptying (e.g., to provide at least 30% emptying or at least 40% emptying, or at least 50% emptying, or at least 60% emptying, or at least 70% emptying, or at least 80% emptying, or at least 90% emptying, or at least 95% emptying.

Method and system for radio network environment detection and reporting, and media independent handover apparatus

A method and a system for radio network environment detection and reporting in a network handover and a media independent handover (MIH) apparatus are provided. The method includes the following: an MIH function (MIHF) at a terminal side initiates a network scan, and generates a parameter report on a radio network environment around the terminal including dynamic information and static information of a scanned point of access (PoA) after the scan is completed; the MIHF at the terminal side sends the parameter report on the radio network environment to an upper layer at the terminal side or to an MIHF at a network side. The method and system support homogeneous and heterogeneous network environments at the same time.

Gateway system and method for implementing access to various media

A gateway system for implementing access to various media is provided in the invention, and the gateway system includes: a communication media access module, for establishing a communication link with the corresponding media access network; a Media Independent Handover Functions module, for seamless handover between accesses to various media; and a handover decision module, for selecting a target network for the seamless handover. The gateway system may also include an authentication module, for sharing the authentication information of the User Equipment. Two methods for implementing access to various media are further disclosed in the invention. By the provided gateway system and methods, the User Equipment can access various media via the gateway system, seamlessly hand over between accesses to various media and achieve the access to a service network using the shared authentication information.

MULTILAYERED PRINTED CIRCUIT BOARD

The present invention is to provide a multilayered printed circuit board free from cracks attributed to thermal expansion difference between a solder resist layer and another part and a multilayered printed circuit board of the present invention comprises a conductor circuit and a resin insulating layer serially formed on a substrate in an alternate fashion and in repetition and a solder resist layer formed as an outermost layer, and the solder resist layer contains an inorganic filler.

Flat display

A flat display is disclosed, which includes a backlight module, a display panel, a flexible printed circuit board physically connected to the display panel, and a shielding double-sided tape for fastening the flexible printed circuit board on the backlight module. The shielding double-sided tape includes a frame shielding portion adhered to a front surface of the backlight module, and an extending portion extended from the frame shielding portion. A surface of at least one part of the extending portion is adhered to a back surface of the backlight module, and another surface of the least one part of the extending portion is adhered to the flexible printed circuit board.

Multilayered printed circuit board

The present invention is to provide a multilayered printed circuit board free from cracks attributed to thermal expansion difference between a solder resist layer and another part and a multilayered printed circuit board of the present invention comprises a conductor circuit and a resin insulating layer serially formed on a substrate in an alternate fashion and in repetition and a solder resist layer formed as an outermost layer, and the solder resist layer contains an inorganic filler.

Method and apparatus for real-time transmission in a field broadband bus architecture over an industrial internet

The disclosure relates to a method and apparatus for real-time transmission in a field broadband bus architecture over an industrial internet, where the field broadband bus architecture over an industrial internet includes: a bus controller, at least one bus terminal, and a two-wire bus over which the bus controller and the bus terminal are connected to constitute a network, the bus controller communicates with any one bus terminal, and the respective bus terminals communicate with each other, using the Orthogonal Frequency Division Multiplexing technology, and sub-carriers occupied by the respective bus terminals do not interfere with each other; and the method includes: the bus controller receives a fixed-rate service transmitted by the bus terminal in an uplink subframe over pre-allocated fixed-rate service resource blocks; and allocates resource blocks for a variable-rate service of the bus terminal in a real-time manner among variable-rate service resource blocks.

Method and Media Player for Playing Images Synchronously with Audio File

A method and a media player for playing images synchronously with an audio file are provided. The method includes the following steps. Audio file associated parameters are read according to a preset time interval when an audio file is played. Stereoscopic image associated parameters corresponding to the read audio file associated parameters are generated according to a preset first corresponding relation between the audio file associated parameters and the stereoscopic image associated parameters. Stereoscopic images corresponding to the audio file are generated according to the stereoscopic image associated parameters, and the stereoscopic images are played. Through the method and media player, stereoscopic images can be played synchronously when an audio file is played.

Contrast imaging method based on wide beam and method for extracting perfusion time-intensity curve

A contrast imaging method based on a wide beam and a method for extracting a perfusion time-intensity curve (TIC) are provided to increase contrast-to-tissue ratio (CTR) through the contrast imaging method based on the wide beam via a pulse inversion microbubble wavelet transform sum squared differences decorrelation (PIWSSD). An auto adaptive analysis method about rapidly and accurately extracting a TIC tendency of the contrast imaging method based on the wide beam is also provided to overcome limitations of a decrease in the CTR of the contrast imaging based on the wide beam and a decrease in SCR of the perfusion TIC. The present invention plays an important role in effectively reducing an ultrasound contrast imaging acoustic power and a contrast microbubble perfusion concentration, reducing potential threat to human body, acquiring a contrast image with the high CTR, and accurately evaluating and diagnosing blood perfusion.

Method And Apparatus For Power Management In Handover Between Heterogeneous Networks

A method for power management in handover between heterogeneous networks comprising: an MIH layer obtains power information and provides it for an MIH user layer; the MIH user layer determines the handover policy according to the power information. In various embodiments of the disclosure, the MIH layer triggers an event so that the MIH user layer can obtain power information, and select a lower-layer network connection automatically according to the current power status, thus implementing handover; the MIH user layer sends a query request to the MIH layer to obtain power consumption parameters from the network, and selects a lower-layer network connection according to the power consumption and the current power status, thus implementing handover and making more accurate and effective decisions in the handover.

Mobile power bank

Synchronization method and apparatus on the basis of a field broadband bus architecture of industrial internet

Embodiments of the disclosure disclose a synchronization method and apparatus on the basis of a field broadband bus architecture of an industrial Internet, where the bus architecture includes a bus controller, at least one bus terminal, and a two-wire bus, and the bus controller and the bus terminal are connected over the two-wire bus to constitute a bus system, the bus system communicating using OFDM technology; and in the method, all the bus terminals refer to the bus controller, and when receiving a signal, and transmitting a signal, they adjust a clock for a received signal, and a signal to be transmitted, adaptively according to the downlink pilot signal so as to synchronize their clocks and symbols with the bus controller, and adjust a transmission time for the signal to be transmitted so that all the devices in the bus system are synchronized.

Method, System and Apparatus for Converting Media Contents

A method, system and apparatus for converting media contents are disclosed. The method includes these steps: a media conversion apparatus receives a media conversion service request from a media application terminal, where the media conversion service request carries a media content ID and playing capability information of the media application terminal; the media conversion apparatus sends a media content transmission request carrying the media content ID to the content source device; and the media conversion apparatus receives a media content identified by the media content ID from the content source device, converts the received media content according to the playing capability information of the media application terminal, and sends the converted media content to the media application terminal.

COMPOUNDS FOR TREATMENT OF HEMOLYSIS-AND INFLAMMASOME-ASSOCIATED DISEASES

Disclosed herein are methods of treating a complication of a hemolysis and/or an inflammasome activation-associated disease comprising administering to a patient in need thereof quinine, or a derivative or salt thereof, or the combination of quinine and hemin. Also disclosed is a method of reducing alloimmunization in chronically transfused subjects, comprising administering to a patient in need thereof a therapeutically effective dose of quinine.

Preparation and selection of cells for producing bispecific antibodies

Provided are compositions and methods for preparing a cell suitable for producing a bispecific antibody. A plurality of eukaryotic cells are incubated with an agent under conditions to allow the cells to arrest at G1/S phase. The agent is then removed from the cells and the cells are transfected with a first vector comprising a sequence encoding a first monovalent antigen-binding unit having specificity to a first antigen and a second vector comprising a sequence encoding a second monovalent antigen-binding unit having specificity to a second antigen. A cell is identified from the plurality of cells that expresses both the first and the second antigen-binding units.

Sagittal Focusing Laue Monochromator

An x-ray focusing device generally includes a slide pivotable about a pivot point defined at a forward end thereof, a rail unit fixed with respect to the pivotable slide, a forward crystal for focusing x-rays disposed at the forward end of the pivotable slide and a rearward crystal for focusing x-rays movably coupled to the pivotable slide and the fixed rail unit at a distance rearward from the forward crystal. The forward and rearward crystals define reciprocal angles of incidence with respect to the pivot point, wherein pivoting of the slide about the pivot point changes the incidence angles of the forward and rearward crystals while simultaneously changing the distance between the forward and rearward crystals.

Sagittal focusing Laue monochromator

An x-ray focusing device generally includes a slide pivotable about a pivot point defined at a forward end thereof, a rail unit fixed with respect to the pivotable slide, a forward crystal for focusing x-rays disposed at the forward end of the pivotable slide and a rearward crystal for focusing x-rays movably coupled to the pivotable slide and the fixed rail unit at a distance rearward from the forward crystal. The forward and rearward crystals define reciprocal angles of incidence with respect to the pivot point, wherein pivoting of the slide about the pivot point changes the incidence angles of the forward and rearward crystals while simultaneously changing the distance between the forward and rearward crystals.

Method for Displaying Plurality of Windows and Electronic Device

A method includes: different window display schemes may be automatically switched based on different scenarios. Specifically, a plurality of windows to be displayed on a display are grouped based on at least one of refresh rates of the plurality of windows, a quantity of the windows, sizes of the windows, locations, and the like, and a lane for transmitting window data is allocated to each window group obtained after grouping, so that window data of each window group can be refreshed, drawn, rendered, and presented based on a refresh rate required by the window data, and there is no need to present all the windows at a highest refresh rate.

Contrast imaging method based on wide beam and method for extracting perfusion time-intensity curve

A contrast imaging method based on a wide beam and a method for extracting a perfusion time-intensity curve (TIC) are provided to increase contrast-to-tissue ratio (CTR) through the contrast imaging method based on the wide beam via a pulse inversion microbubble wavelet transform sum squared differences decorrelation (PIWSSD). An auto adaptive analysis method about rapidly and accurately extracting a TIC tendency of the contrast imaging method based on the wide beam is also provided to overcome limitations of a decrease in the CTR of the contrast imaging based on the wide beam and a decrease in SCR of the perfusion TIC. The present invention plays an important role in effectively reducing an ultrasound contrast imaging acoustic power and a contrast microbubble perfusion concentration, reducing potential threat to human body, acquiring a contrast image with the high CTR, and accurately evaluating and diagnosing blood perfusion.

FLAT DISPLAY

A flat display is disclosed, which includes a backlight module, a display panel, a flexible printed circuit board physically connected to the display panel, and a shielding double-sided tape for fastening the flexible printed circuit board on the backlight module. The shielding double-sided tape includes a frame shielding portion adhered to a front surface of the backlight module, and an extending portion extended from the frame shielding portion. A surface of at least one part of the extending portion is adhered to a back surface of the backlight module, and another surface of the least one part of the extending portion is adhered to the flexible printed circuit board.

INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME

A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell. 1. A method of designing an integrated circuit , the method comprising:deploying an active area in a first standard cell;routing at least one gate electrode overlapping the active area in the first standard cell;routing at least one metallic line structure overlapping the active area in the first standard cell, the at least one metallic line structure being substantially parallel to the gate electrode;routing a first power rail that is substantially orthogonal to the at least one metallic line structure in the first standard cell, the first power rail overlapping the at least one metallic line structure, wherein the first power rail has a flat edge that is adjacent to the at least one metallic line structure; anddeploying a first connection plug at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.2. The method of claim 1 , wherein routing the at least one metallic line structure comprises:routing a first metallic line overlapping the active area in the first standard cell; androuting a second metallic line overlapping the first metallic line and the first power rail in the ...

CASE STRUCTURE

A case structure is disclosed. The case structure includes a plastic panel, a case portion, and a plurality of supporting parts. The case portion includes an assembly part. The assembly part is connected to the plastic panel for assembling. The plurality of supporting parts is connected to the assembly part. The plurality of supporting parts supports the inside of the plastic panel. 1. A case structure comprising:a plastic panel;a case portion comprising:an assembly part connected to the plastic panel for assembling; anda plurality of supporting parts connected to the assembly part; wherein the plurality of supporting parts support an inside of the plastic panel.2. The case structure as claimed in claim 1 , wherein the plurality of supporting parts are a plurality of bending metal elements; the plurality of bending metal elements and the case portion are integrally formed.3. The case structure as claimed in claim 1 , wherein the plurality of supporting parts is a plurality of extension elements; the plurality of extension elements is protruded from the case portion.4. The case structure as claimed in claim 3 , wherein one end of each of the plurality of extension elements is fastened to the case portion; another end of each of the plurality of extension elements supports the inside of the plastic panel.5. The case structure as claimed in claim 1 , wherein the inside of the plastic panel further comprises a chamfer part for matching a shape of the case portion.6. The case structure as claimed in claim 1 , wherein the assembly part comprises four sides claim 1 , the plurality of supporting parts are located on three sides of the assembly part.7. The case structure as claimed in claim 1 , wherein the case structure is a desktop computer case.8. The case structure as claimed in claim 1 , wherein the case is a metal case. 1. Field of the InventionThe present invention relates to a case structure; more particularly, the present invention relates to a case structure which ...

Locking mechanism with easy assembly and electronic device therewith

A locking mechanism includes a lock for passing through an opening of a housing. The lock includes a lock head, a cover whereon a slot is formed, a constraining portion, and a platform structure for contacting against a fastening portion of the housing as the cover passes through the opening. The locking mechanism further includes a tongue piece installed on a side of the cover and rotating with the lock head synchronously. The tongue piece includes a latching portion for latching inside an indentation of a door as the tongue piece rotates to a latching position, and a stopping portion for contacting against an end of the constraining portion as the tongue piece rotates to the latching position. The locking mechanism further includes a jump ring for engaging inside the slot on the cover so as to fix the lock inside the housing.

METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER

A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively. 1. A multiplexing circuit comprising:first and second tri-state inverters coupled to first and second data input nodes, respectively, the first and second tri-state inverters including first and second stacks of transistors, respectively, coupled between power supply and ground nodes, each stack including first and second PMOS transistors and first and second NMOS transistors,wherein the first and second stacks further include first and second dummy transistors, respectively.2. The multiplexing circuit of claim 1 , wherein a source terminal and a drain terminal of each dummy transistor are tied to one another.3. The multiplexing circuit of claim 1 , wherein:the first NMOS and PMOS transistors of the first stack have gate terminals coupled to the first data input node;the first NMOS and PMOS transistors of the second stack have gate terminals coupled to the second data input node;the second PMOS and NMOS transistors of the first stack have gate terminals coupled to a select signal node and a select signal complement node, respectively; andthe second NMOS and PMOS transistors of the second stack have gate terminals coupled to the select signal and select signal complement nodes, respectively.4. The multiplexing circuit of claim 3 , further comprising a CMOS inverter including an input and an output coupled to the select signal and select signal complement nodes claim 3 , respectively.5. The multiplexing circuit of claim 3 , wherein the first dummy transistor is a PMOS transistor and the second dummy transistor is a ...

ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS

An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors. 1. A semiconductor structure comprising:at least one active transistor having an active polysilicon gate;a metal lead coupled to said at least one active polysilicon gate;{'sub': SS', 'SS, 'a diode coupling said metal lead to Vthrough a dummy transistor comprising a dummy polysilicon transistor gate disposed over a gate dielectric disposed over a continuous source/drain dopant impurity region, said diode comprising said metal lead coupled to said continuous source/drain dopant impurity region and said dummy polysilicon transistor gate coupled to said V.'}2. The semiconductor structure as in claim 1 , wherein said at least one active transistor is disposed on a semiconductor substrate claim 1 , said substrate maintained at said Vand wherein said dummy polysilicon transistor gate is coupled to said substrate.3. The semiconductor structure as in claim 2 , wherein said dummy polysilicon transistor gate is coupled to said substrate through a further metal lead.4. The semiconductor structure as in claim 2 , wherein said dummy polysilicon transistor gate is coupled to said substrate through a tie-low cell.5. The semiconductor structure as in claim 2 , wherein said ...

CASE AND ELECTRONIC DEVICE HAVING THE SAME

A case is disclosed. The case includes a main body and a container housing tank. The main body includes a surface, and the container housing tank is located on the surface and used to accommodate a nameplate. The container housing tank includes a main tank and a margin tank, wherein the main tank has a first depth; the margin tank is located on the edge of the main tank and connects with the main tank. The margin tank has a second depth that is greater than the first depth. 1. A case , used to accommodate a nameplate , the case comprising:a main body, including a surface; and a main tank, having a first depth; and', 'a margin tank, located on the edge of the main tank, and connected with the main tank, wherein the margin tank has a second depth that is greater than the first depth., 'a container housing tank, located on the surface of the main body and used to accommodate the nameplate, the container housing tank comprising2. The case as claimed in claim 1 , wherein the margin tank is arranged by surrounding the main tank.3. The case as claimed in claim 2 , wherein the shape of the main tank is the same as the shape of the nameplate.4. The case as claimed in claim 3 , wherein the second depth is greater than the first depth of X mm claim 3 , where 0.1≦X≦0.5.5. An electronic device claim 3 , comprising a case claim 3 , the case comprising:a main body, including a surface;a paint layer, attached to the main body;a nameplate; and a main tank, having a first depth; and', 'a margin tank, located on the edge of the main tank, and connected with the main tank, wherein the margin tank has a second depth that is greater than the first depth., 'a container housing tank, located on the surface of the main body and used to accommodate the nameplate, the container housing tank comprising6. The electronic device as claimed in claim 5 , wherein the margin tank is arranged by surrounding the main tank.7. The electronic device as claimed in claim 6 , wherein the shape of the main ...

PANEL HAVING POSITIONING FUNCTION AND RELATED ELECTRONIC DEVICE

A panel having positioning function is disclosed in the present invention. The panel includes a body covering an opening on an extrusion casing, and a positioning mechanism having at least one position set. The position set includes a first rib disposed on a first side of the body, a first contact portion disposed on the first rib and contacting against an inner surface of the extrusion casing, a second rib disposed on a second side of the body, and a second contact portion disposed on the second rib and contacting against the other inner surface of the extrusion casing. A position of the second rib on the second side is symmetrized to a position of the first rib on the first side, so that the panel can align with the extrusion casing due to deformation of the position set. 1. A panel having positioning function , the panel comprising:a body covering an opening on an extrusion casing, the body comprising a first side, a second side, a third side and a fourth side, the first side being substantially parallel to the second side, and the third side being substantially parallel to the fourth side; and [ a first rib disposed on the first side of the body;', 'a first contact portion disposed on the first rib and contacting against a first inner surface of the extrusion casing in a deformable manner;', 'a second rib disposed on the second side of the body opposite to the first side, a position of the second rib on the second side being symmetrized to a position of the first rib on the first side; and', 'a second contact portion disposed on the second rib and contacting against a second inner surface of the extrusion casing opposite to the first inner surface in the deformable manner, so that the panel aligns with a boundary of the extrusion casing via deformation of the position set;, 'at least one position set disposed on the body, the position set comprising, 'wherein the position set is deformed when the panel is assembled with the extrusion casing, a deformation value ...

SCREW POST

A screw post is detachably screwed with a self-tapping screw. The screw post includes a post body and a rib structure. The post body has an approximately triangular hollow structure formed therein. The approximately triangular hollow structure has three arc-shaped sides. The rib structure protrudes from an outer surface of the post body corresponding to at least one of the three arc-shaped sides in an axially-extending manner. The self-tapping screw is screwed into the approximately triangular hollow structure. 1. A screw post detachably screwed with a self-tapping screw , the screw post comprising:a post body having an approximately triangular hollow structure formed therein, the approximately triangular hollow structure having three arc-shaped sides; anda rib structure protruding from an outer surface of the post body corresponding to at least one of the three arc-shaped sides in an axially-extending manner;wherein the self-tapping screw is screwed into the approximately triangular hollow structure.2. The screw post of claim 1 , wherein the rib structure includes three reinforcement ribs respectively disposed at the outer surface of the post body corresponding to the three arc-shaped sides.3. A screw post detachably screwed with a self-tapping screw claim 1 , the screw post comprising:a post body having an approximately polygon hollow structure formed therein, the approximately polygon hollow structure having at least four arc-shaped sides; anda rib structure protruding from an outer surface of the post body corresponding to at least one of the four arc-shaped sides in an axially-extending manner;wherein the self-tapping screw is screwed into the approximately polygon hollow structure.4. The screw post of claim 3 , wherein a sectional contour of the approximately polygon hollow structure is an approximate quadrangle.5. A screw post detachably screwed with a self-tapping screw claim 3 , the screw post comprising:a post body having an approximately cylindrical ...

Layout Architecture for Performance Improvement

An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact. 1. An integrated circuit , comprising:a first contact disposed over a first source/drain region;a second contact disposed over a second source/drain region;a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact;a first polysilicon contact bridging the polysilicon and the first contact within an active region; andan output structure electrically coupled to the first polysilicon contact.2. The integrated circuit of claim 1 , wherein the output structure is disposed outside the active region.3. The integrated circuit of claim 2 , wherein the output structure is formed from a second polysilicon contact and a via.4. The integrated circuit of claim 3 , wherein the first polysilicon contact and the second polysilicon contact are electrically coupled to each other through the polysilicon disposed over the gate.5. The integrated circuit of claim 2 , wherein the output structure is formed from a via claim 2 , the via electrically coupled to the first polysilicon contact through the first contact disposed over the first source/drain region.6. The integrated circuit of claim 1 , wherein the output structure is disposed at least partially within the active region.7. The integrated circuit of claim 6 , wherein the output structure is formed from a first via electrically coupled to the first contact disposed over the first source/drain region claim 6 , a second via electrically coupled to the polysilicon disposed over the gate claim 6 , and a top metal ...

Latch Mechanism, Electronic Apparatus Having the Same, and Method for Removing a Shell Cover from a Shell Base Using the Same

An electronic apparatus includes a shell base, a shell cover and a latch mechanism including an operating component, a pivot axle and a driving axle. The operating component has an access portion and two support portions extending through the shell cover. The pivot axle extends through the support portions, and has two end parts disposed at opposite lateral sides of the support portions and coupled rotatably to the shell cover. The driving axle extends through the support portions and is received in a limit groove of the shell base. The access portion is pivotable about the pivot axle from a closed position to an open position while the driving axle is positioned in the slide direction, thereby moving the pivot axle and the shell cover relative to the shell base. 1. An electronic apparatus comprising:a shell base defining an internal space and having an abutment portion that is disposed in said internal space and that is formed with a limit groove opening upwardly;a shell cover coupled detachably to said shell base, covering said internal space and slidable relative to said shell base along a slide direction, said shell cover having a through hole aligned with said limit groove of said abutment portion; and an operating component that has an access portion disposed outside said shell cover, and a pair of spaced-apart support portions extending from said access portion into said internal space through said through hole,', 'a pivot axle that is adjacent to said through hole, that extends through said support portions of said operating component, and that has a pair of end parts disposed respectively at opposite lateral sides of said support portions, said end parts being coupled rotatably to said shell cover, and', 'a driving axle that extends through said support portions of said operating component, that is spaced apart from said pivot axle, that is disposed in said internal space and that is received and vertically-movable in said limit groove of said abutment ...

PROTECTIVE STRUCTURE FOR COVERING A CONNECTOR AND ELECTRONIC DEVICE THEREWITH

A protective structure includes a covering body, a protective component, a fixing component and a fastening portion. The covering body is for covering the connector. The protective component is connected to the covering body and for plugging into the connector. The fixing component is connected to a side of the covering body and for plugging into an installation hole on a case of the electronic device. The fixing component includes a shaft for pivoting relative to the case so as to drive the covering body to a position where the covering body does not cover the connector when the protective component does not plug into the connector. The fastening portion is installed on the fixing component and is for contacting against the installation hole after the fixing component is plugged into the installation hole so as to prevent the fixing component from separating from the installation hole. 1. A protective structure for covering a connector of an electronic device , comprising:a covering body for covering the connector;a protective component connected to the covering body and for plugging into the connector;a fixing component connected to a side of the covering body and for plugging into an installation hole on a case of the electronic device, the fixing component comprising a shaft for pivoting relative to the case so as to drive the covering body to a position where the covering body does not cover the connector when the protective component does not plug into the connector; anda fasten portion installed on the fixing component and for contacting against the installation hole after the fixing component is plugged into the installation hole, so as to prevent the fixing component from separating from the installation hole.2. The protective structure of claim 1 , wherein the fixing component further comprises a guiding portion claim 1 , and a hole is formed on the guiding portion whereinto a guiding component is inserted claim 1 , so as to guide the guiding portion to ...

Integrated circuit

An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell.

SIGNAL TESTING SYSTEM OF A HANDHELD DEVICE AND A SIGNAL TESTING METHOD THEREOF

A signal testing system of a handheld device is described in the present invention. The signal testing system comprises a testing apparatus and a computer device. The testing apparatus is connected with the handheld device. The computer device is connected with the handheld device and the testing apparatus, and is configured to control the handheld device accessing a signal testing state and receives a power value corresponding to the signal testing state through the testing apparatus. 1. A signal testing system of a handheld device , comprising:a testing apparatus, connected with the handheld device; anda computer device, connected with the handheld device and the testing apparatus, and configured to control the handheld device accessing a signal testing state and receiving a power value corresponding to the signal testing state through the testing apparatus.2. The signal testing system of a handheld device of claim 1 , further comprising an electric shielding box and a plate antenna claim 1 , wherein the electric shielding box is configured for allocating the handheld device and the plate antenna.3. The signal testing system of a handheld device of claim 1 , wherein the power value is an emitting power value of the handheld device.4. The signal testing system of a handheld device of claim 1 , wherein the power value is a receiving power value of the handheld device.5. The signal testing system of a handheld device of claim 1 , wherein the computer device comprises an USB interface and a communication interface claim 1 , and the computer device is communicated with the handheld device by using the USB interface and is communicated with the testing apparatus by using the communication interface.6. The signal testing system of a handheld device of claim 5 , wherein the computer device further comprises a testing software.7. The signal testing system of a handheld device of claim 5 , wherein the computer device further comprises a storage unit.8. The signal testing ...

Integrated circuit and method of manufacturing same

A method includes positioning a first set of conductive traces in a first direction, manufacturing a second set of conductive traces by a first mask pattern, and electrically coupling, by at least a first via, at least one conductive trace of the first set of conductive traces to at least one conductive trace of the second set of conductive traces. The first set of conductive traces is in a first layer of an integrated circuit. The second set of conductive traces is in a second direction different from the first direction. The second set of conductive traces is in a second layer of the integrated circuit. The second layer is different from the first layer. A conductive trace of the second set of conductive traces is part of a first dummy transistor.

METHOD FOR IMPROVED CUT METAL PATTERNING

A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments. 1. A system for preparing an integrated circuit device design comprising:a first memory configured for storing a plurality of preliminary integrated circuit design files; retrieving a preliminary integrated circuit design file from the first memory;', {'sup': th', 'th', 'th', 'th, 'locating a first vertical abutment between an mdevice cell design and an ndevice cell design from the preliminary integrated circuit design file; Подробнее

INTEGRATED CIRCUIT LAYOUT AND METHOD OF CONFIGURING THE SAME

An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other. 1. An integrated circuit comprising:at least one first active region;at least one second active region adjacent to the first active region, wherein the first active region and the second active region are staggered; anda plurality of third active regions adjacent to the first active region, wherein the third active regions are substantially aligned with each other.2. The integrated circuit of claim 1 , further comprising:at least one fourth active region, wherein the second active region is present between the fourth active region and the first active region, and the fourth active region and the first active region are substantially aligned with each other.3. The integrated circuit of claim 2 , further comprising:at least one fifth active region, wherein the fourth active region is present between the fifth active region and the second active region, and the fifth active region and the second active region are substantially aligned with each other.4. The integrated circuit of claim 3 , further comprising:at least one gate electrode crossing the second active region and the fifth active region.5. The integrated circuit of claim 4 , wherein the gate electrode is partially present on an edge of the fourth active region.6. The integrated circuit of claim 2 , further comprising:at least one gate electrode crossing the first active region and the fourth active region.7. The integrated circuit of claim 6 , wherein the gate electrode is partially present on an edge of the second active region.8. An integrated circuit comprising: a first active region;', 'a first gate electrode crossing ...

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. An circuit cell , comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion of the circuit including a plurality of first fin structures arranged in a plurality of first rows; anda second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell.2. The circuit cell of claim 1 , wherein the circuit cell is optimized for speed based on inclusion of the first circuit component in the first fin portion claim 1 , wherein the first fin portion is a high fin portion.3. The circuit cell of claim 1 , wherein the circuit cell is optimized for power consumption based on inclusion of the second circuit component in the second fin portion claim 1 , wherein the second fin portion is a less fin portion.4. The circuit cell of claim 1 , wherein the circuit cell is arranged in a double height cell layout with the first fin portion and the second fin portion being arranged in adjacent rows.5. The circuit cell of claim 1 , wherein the first ...

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. A method of fabricating an circuit cell , comprising:accessing a logic design for implementing a function of the circuit cell, the logic design including a plurality of logic components; a first circuit structure comprising a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion including a plurality of first fin structures arranged in first rows, and', 'a second circuit structure comprising a second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;, 'accessing a plurality of circuit structures for implementing one or more of the logic components, the plurality of circuit structures including,'}generating a plurality of circuit designs that use different combinations of the plurality of circuit structures that implement the function;filtering the generated circuit designs that do not meet a first circuit criterion; andselecting a remaining circuit design that has an optimum value for a second circuit criterion.2. The method of ...

Semiconductor Device Including a Conductive Feature Over an Active Region

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. 1. A method comprising:forming an active region in a substrate;forming a first gate structure and a second gate structure on the substrate, wherein the second gate structure is adjacent to the first gate structure;forming an insulating layer on the first gate structure and the second gate structure;forming a pair of first spacers on each sidewall of the first gate structure;forming a pair of second spacers on sidewalls of the second gate structure;forming a first conductive feature over the active region;etching a portion of the insulating layer over the first gate structure;etching a portion of the first gate structure; anddepositing a second conductive feature over at least the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the insulating layer remaining over the second gate structure.2. The method of further comprising:forming a third conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the third conductive feature.3. The method of further comprising:forming a fourth conductive feature, wherein the fourth conductive feature is over the first gate structure or the second gate structure.4. The method of claim 3 , wherein the second conductive ...

ODD-FIN HEIGHT CELL REGIONS, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD OF GENERATING A LAYOUT DIAGRAM CORRESPONDING TO THE SAME

A semiconductor device includes fins extending substantially parallel to a first direction, at least one of the fins being a dummy fin; and at least one of the fins being an active fin; and at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; wherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins. In an embodiment, the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; and neither of the first and second edges overlaps any of the fins. 1. A semiconductor device comprising: at least one of the fins being a dummy fin; and', 'at least one of the fins being an active fin; and, 'fins extending substantially parallel to a first direction;'}at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; andwherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins.2. The semiconductor device of claim 1 , wherein:the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; andneither of the first and second edges overlaps any of the fins.3. The semiconductor device of claim 1 , wherein:the cell region includes 5 fins; andthe cell region has a size, in the second direction, of 5 fins.4. The semiconductor device of claim 3 , wherein:at least 2 of the 5 fins are active fins.5. The semiconductor device of claim 4 , wherein:4 of the 5 fins are active fins.6. The semiconductor device of claim 1 , wherein:the cell region, relative to stacking in the second direction, is pan-stackable.7. The semiconductor device of ...

DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE

Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate. 1. A dual transmission gate , comprising:a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor, situated within a first row from among a plurality of rows of an electronic device design real estate, configured to receive a first clocking signal;a first n-type metal-oxide- ...

DOUBLE HEIGHT CELL REGIONS, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD OF GENERATING A LAYOUT DIAGRAM CORRESPONDING TO THE SAME

In at least one cell region, a semiconductor device includes fins and at least one overlying gate structure. The fins (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fins have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region. 1. A semiconductor device comprising: dummy fins;', 'first active fins having a first conductivity type; and', 'second active fins having a second conductivity type; and, 'fins, extending substantially parallel to a first direction, configured to includeat least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction which is substantially perpendicular to the first direction; and the fins and the at least one gate structure are located in at least one cell region; and', a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region;', 'a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and', 'a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region., 'each cell region, relative to the second direction, including], 'wherein2. The semiconductor device of ...

SYNCHRONIZATION METHOD AND APPARATUS ON THE BASIS OF A FIELD BROADBAND BUS ARCHITECTURE OF INDUSTRIAL INTERNET

Embodiments of the disclosure disclose a synchronization method and apparatus on the basis of a field broadband bus architecture of an industrial Internet, where the bus architecture includes a bus controller, at least one bus terminal, and a two-wire bus, and the bus controller and the bus terminal are connected over the two-wire bus to constitute a bus system, the bus system communicating using OFDM technology; and in the method, all the bus terminals refer to the bus controller, and when receiving a signal, and transmitting a signal, they adjust a clock for a received signal, and a signal to be transmitted, adaptively according to the downlink pilot signal so as to synchronize their clocks and symbols with the bus controller, and adjust a transmission time for the signal to be transmitted so that all the devices in the bus system are synchronized. 1. A synchronization method on the basis of a field broadband bus architecture of an industrial Internet , wherein the field broadband bus architecture of an industrial Internet comprises: a bus controller , at least one bus terminal , and a two-wire bus , and the bus controller and the at least one bus terminal are connected over the two-wire bus to constitute a bus system; the bus controller communicates with any of the at least one bus terminal , and the bus terminal communicates with each other , using the Orthogonal Frequency Division Multiplexing (OFDM) technology , and sub-carriers occupied by the bus terminal do not interfere with each other; and the synchronization method applicable to each bus terminal comprises:receiving, by the bus terminal, a downlink pilot signal transmitted by the bus controller in a downlink system subframe, and determining a clock offset and a symbol offset respectively between the bus terminal and the bus controller based upon the received downlink pilot signal;correcting, by the bus terminal, a clock for a received signal based upon the clock offset, and correcting a clock for a ...

METHOD AND APPARATUS FOR REAL-TIME TRANSMISSION IN A FIELD BROADBAND BUS ARCHITECTURE OVER AN INDUSTRIAL INTERNET

The disclosure relates to a method and apparatus for real-time transmission in a field broadband bus architecture over an industrial internet, where the field broadband bus architecture over an industrial internet includes: a bus controller, at least one bus terminal, and a two-wire bus over which the bus controller and the bus terminal are connect to constitute a network, the bus controller communicates with any one bus terminal, and the respective bus terminals communicate with each other, using the OFDM technology, and sub-carriers occupied by the respective bus terminals do not interfere with each other; and the method includes: the bus controller receives a fixed-rate service transmitted by the bus terminal in an uplink subframe over pre-allocated fixed-rate service resource blocks; and allocates resource blocks for a variable-rate service of the bus terminal in a real-time manner among variable-rate service resource blocks. 1. A method for real-time transmission in a field broadband bus architecture over an industrial internet , wherein the field broadband bus architecture over an industrial internet comprises: a bus controller , at least one bus terminal , and a two-wire bus over which the bus controller and the bus terminal are connect to constitute a network , the bus controller communicates with any one bus terminal using an Orthogonal Frequency Division Multiplexing (OFDM) technology , and the respective bus terminals communicate with each other , also using the OFDM technology , and sub-carriers occupied by the respective bus terminals do not interfere with each other; and the method comprises:receiving, by the bus controller, a fixed-rate service transmitted by the bus terminal in an uplink subframe over pre-allocated fixed-rate service resource blocks; andreceiving, by the bus controller, a variable-rate service transmission demand transmitted by the bus terminal in the uplink subframe, allocating resource blocks for a variable-rate service of the bus ...

Fixing mechanism and electronic device capable of assembling and disassembling an expansion card module

A fixing mechanism which is capable of assembling an expansion card module includes a base, a latch and a resilient component. The expansion card module slidably inserts into the base. The latch pivots to an accommodating portion of the base to switch between a first position and a second position. The latch includes a pressing portion and a pushing portion connected with each other. The pressing portion presses a side of the expansion card module since the latch is switched to the first position. The pushing portion pushes an opposite side of the expansion card module since the latch is switched to the second position, so as to upwardly move the expansion card module relative to the base. The resilient component is located inside the accommodating portion to actuate the latch and drives the latch to stay at the second position.

SEMICONDUCTOR STRUCTURE AND LAYOUT METHOD OF A SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch. 1. A semiconductor structure , comprising:a plurality of vias on a semiconductor substrate; anda metal layer, having a plurality of metal lines and at least one transmission gate line region, the metal lines connected to the vias, the at least one transmission gate line region connected to at least one transmission gate corresponding to at least one transmission gate circuit, the transmission gate line region comprising at least one different-net via pair, the different-net via pair having two metal lines and each of the two metal lines connected to a via respectively, the two metal lines extending along a first axis but toward opposite directions, a distance between the two vias of the different-net via pair within about 1.5 poly pitch.2. The semiconductor structure of claim 1 , wherein the distance is between about 0.8-1.5 poly pitch.3. The semiconductor structure of claim 1 , wherein the metal layer further comprises at least one 1-dimension section around the different-net via pair.4. The semiconductor structure of claim 3 , wherein the 1-dimension section comprises at least one upper metal line and at least one lower metal line claim 3 , the upper metal line disposed on an upper position ...

SERVER HOUSING

A server housing includes a housing bottom plate including an engaging hole and a hidden tray device including a tray bottom plate, a switch body, and a handle member. The tray bottom plate includes a receiving opening, a guiding trough, a first surface, and a second surface opposite to the first surface. The receiving opening and guiding trough penetrate through the tray bottom plate. The second surface is near the housing bottom plate. The switch body fastened to the first surface includes an engaging portion. The engaging portion passes through the receiving opening and is in the engaging hole. The handle member includes a handle body, a guiding portion, and a pressing unit. The guiding portion is connected to the handle body and is disposed in the guiding trough. The handle body and the pressing unit are between the tray bottom plate and the housing bottom plate. 1. A server housing comprising:a housing bottom plate comprising an engaging hole; anda hidden tray device comprising:a tray bottom plate comprising a receiving opening, at least a guiding trough, a first surface, and a second surface opposite to the first surface, the receiving opening and the guiding trough penetrating through the tray bottom plate from the first surface to the second surface, the second surface being near the housing bottom plate;a switch body comprising an engaging portion a first plate body, and a second plate body connected to the first plate body, one end of the first plate body of the switch body being fastened to the first surface of the tray bottom plate, the engaging portion protruding from another end of the second plate body of the switch body, the second plate body being bent with respect to the first plate body, the second plate body being biased toward the receiving opening, the engaging portion passing through the receiving opening and being in the engaging hole; anda handle member comprising a handle body, at least a guiding portion, and a pressing unit, the guiding ...

METHOD FOR DESIGNING ANTENNA CELL THAT PREVENTS PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS

An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors. 1. A method for forming a semiconductor structure , said method comprising:providing a semiconductor substrate;defining an antenna cell on a surface of said semiconductor substrate;forming a plurality of substantially parallel polysilicon lines having substantially the same length and extending completely through said cell;forming a dummy transistor using one said polysilicon line as a dummy gate thereof, said dummy transistor including said dummy gate disposed over a gate dielectric disposed over a continuous source/drain dopant impurity region; andforming a metal lead coupled to an active transistor gate and further coupled to a diode formed of said dummy transistor, wherein said dummy gate is coupled to said semiconductor substrate and said metal lead is coupled to said continuous source/drain dopant impurity region.2. The method as in claim 1 , further comprising electrically coupling said semiconductor substrate to a Vvoltage source.3. The method as in claim 2 , wherein said dummy gate is directly coupled to said semiconductor substrate via a further metal lead.4. The method as in claim 2 , wherein said dummy gate is directly coupled to said ...

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor. 1. An integrated circuit , comprising:a first active region and a second active region;a first PODE (poly on OD edge) and a second PODE;a first transistor, on the first active region, including a gate electrode, a source region and a drain region; anda second transistor, on the second active region, including a gate electrode, a source region and a drain region; the first active region and the second active region are adjacent and are electrically disconnected with each other;', 'the first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region;', 'the source region of the first transistor is adjacent the first PODE;', 'the source region of the second transistor is adjacent the second PODE; and', 'the first PODE and the second PODE are sandwiched between the source region of the first transistor and the source region of the second transistor., 'wherein'}2. The integrated circuit of claim 1 , wherein at least one conductive interconnection is located between the first PODE and the second PODE.3. The integrated circuit of claim 1 , wherein ...

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a first and a second active region, a first multi-gate structure, a first and a second rail. The first and second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and is configured to supply a second supply voltage. 1. An integrated circuit structure comprising:a first active region extending in a first direction and being located at a first level;a second active region extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction;a first multi-gate structure extending in the second direction, overlapping the first active region and the second active region, and being located at a second level different from the first level;a first rail extending in the first direction, overlapping a portion of the first active region, being configured to supply a first supply voltage, and being located at a third level different from the first level and the second level; anda second rail extending in the first direction, being located at the third level, being separated from the first rail in the second direction, and being configured to supply a second supply voltage different from the first supply voltage.2. The integrated circuit structure of claim 1 , whereinthe first active region has a first width in the second direction, andthe ...

STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD

A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern. 1. A layout of a standard cell , the layout stored on a non-transitory computer-readable medium and comprising:a first conductive pattern;a second conductive pattern; the first row adjacent the first conductive pattern and comprising a first active area pattern and a second active area pattern among the plurality of active area patterns, and', 'the second row adjacent the second conductive pattern and comprising a third active area pattern and a fourth active area pattern among the plurality of active area patterns; and, 'a plurality of active area patterns isolated from each other and arranged in a first row and a second row between the first and second conductive patterns,'}a first central conductive pattern arranged between the first and second active area patterns, the first central conductive pattern overlapping the first conductive pattern.2. The layout of claim 1 , further comprising:a second central conductive pattern arranged between the third and fourth active area patterns, the second central conductive pattern overlapping the second conductive pattern.3. ...

ROTARY DEVICE CAPABLE OF ADJUSTING POSITION OF A BOX

A rotary device includes a bracket, a first supporting module, a second supporting module and a driving module. The two supporting modules respectively have a pivot end and a connective end. The two pivot ends are pivotally connected to different and adjacent position of the bracket. The driving module is utilized to reversely rotate the first supporting module and the second supporting module, simultaneously. The driving module includes an actuating component, a first rod and a second rod. The first rod is connected between the first connective end and a side of the actuating component. The second rod is connected between the second connective end and an opposite side of the actuating component. When the actuating component rotates at a first direction, the first rod rotates the first supporting module at a second direction, and the second rod rotates the second supporting module at the first direction. 1. A rotary device capable of adjusting position of a box , the rotary device comprising:a bracket;a first supporting module pivoting to the bracket;a second supporting module pivoting to the bracket; and an actuating component;', 'a first rod connected to the first supporting module and a side of the actuating component; and', 'a second rod connected to the second supporting module and the other side of the actuating component, the first rod driving the first supporting module to rotate at a second direction and the second rod driving the second supporting module to rotate at a first direction since the actuating component rotates at the first direction, and the first direction being opposite to the second direction., 'a driving module for reversely rotating the first supporting module and the second supporting module simultaneously, the driving module comprising2. The rotary device of claim 1 , wherein the first supporting module comprises a first pivot end and a first connective end claim 1 , the first pivot end pivots to the bracket claim 1 , and the first rod ...

Structure and method of non-rectangular cell in semiconductor device

A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

SEMICONDUCTOR DEVICE WITH V2V RAIL AND METHODS OF MAKING SAME

A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.

SUPPORTING MECHANISM AND RELATED ELECTRONIC DEVICE CAPABLE OF APPLYING TO ROTATION OF A SIGNAL TRANSMISSION HOLDER

A supporting mechanism and a related electronic device can be adapted to apply to rotation of a signal transmission holder. The rotary supporting mechanism includes a base, a bracket, a first connecting rod, a second connecting rod, a third connecting rod and a actuating component. The signal transmission holder is disposed on the bracket . Two end of the first connecting rod respectively pivot between the base and the bracket. A first end of the second connecting rod pivots to the bracket . Two ends of the third connecting rod respectively pivot to the base and a second end of the second connecting rod. The actuating component is rotatably disposed on the second connecting rod. A contacting portion of the actuating component is movably shifted between a first blocker and a second blocker of the third connecting rod since the second connecting rod rotates relative to the third connecting rod. 1. A supporting mechanism capable of applying to rotation of a signal transmission holder by a four-link assembly , the supporting mechanism comprising:a base, the base comprising a jointing portion;a bracket whereon the signal transmission holder is disposed, a lateral wall stretching from a side of the bracket;a first connecting rod, two ends of the first connecting rod respectively pivoting to the jointing portion and the lateral wall of the bracket;a second connecting rod, a first end of the second connecting rod pivoting to the lateral wall of the bracket;a third connecting rod, the third connecting rod comprising a first blocking portion and a second blocking portion, two ends of the third connecting rod respectively pivoting to the jointing portion and a second end of the second connecting rod; andan actuating component rotatably disposed on the second connecting rod, the second connecting rod being adapted to rotate relative to the third connecting rod to movably shift a contacting portion of the actuating component between the first blocking portion and the second ...

DOOR DEVICE CAPABLE OF SWITCHING STATUSES AND STORAGE EQUIPMENT USING THE SAME

The disclosure discloses a door device including a panel, a pivoting arm module, and a door. The pivoting arm module includes a holder and a panel-pivoting arm. The holder is located in a doorway of the panel and fixed to the panel. The holder has an entrance and an accommodating trough. The panel-pivoting arm is slidably accommodated in the accommodating trough and can present a received status or an ejected status relative to the holder. 1. A door device , comprising:a panel having a doorway;a pivoting arm module comprising a holder and a panel-pivoting arm, the holder located in the doorway and fixed to the panel, the holder having an entrance and an accommodating trough inwardly formed from the entrance, wherein the panel-pivoting arm is slidably accommodated in the accommodating trough from the entrance, and is capable of switching to a received status or an ejected status relative to the holder; anda door pivotally connected to the panel-pivoting arm, wherein when the panel-pivoting arm switches to the received status relative to the holder, the door abuts against the panel and closes the doorway, and an appearance surface of the door is flush with appearance surface of the panel, and when the panel-pivoting arm switches to the ejected status relative to the holder, the door leaves the panel and is capable of rotating relative to the panel-pivoting arm to open the doorway.2. The door device of claim 1 , wherein the panel-pivoting arm has a first through hole claim 1 , the pivoting arm module further comprises a locking lever claim 1 , and the locking lever comprises:a linkage;a biasing block connected to an end of the linkage and engaged in the first through hole, wherein the biasing block has an edge, and the edge deviates from an axis of the linkage and abuts against an inner wall of the first through hole; andan engaging block connected to another end of the linkage and slidably engaged with an inner wall of the accommodating trough.3. The door device of ...

INTERCONNECT STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail. 1. A semiconductor device , comprising:a gate electrode extending in a first direction in a first layer over an active region;a first conductive line extending in the first layer adjacent to the gate electrode;a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer;a second conductive line arranged in a third layer over the second layer; anda conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line, wherein the conductive via is electrically insulated from the first power rail.2. The semiconductor device according to claim 1 , further comprising a spacer layer electrically insulating the conductive via from the first power rail.3. The semiconductor device according to claim 2 , wherein spacer layer extends from the first conductive line to the second conductive line.4. The semiconductor device according to claim 2 , wherein the spacer layer is at least partially laterally surrounded by the first power rail.5. The semiconductor device according to claim 1 , further comprising a second power rail arranged in the second layer and parallel to the first power rail.6. The semiconductor device according to claim 5 , wherein the second power rail is ...

Cell Layout and Structure

A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed. 1. A method of designing a semiconductor device , the method comprising:placing a first cell and a second cell into a first cell row;placing a third cell and a fourth cell into a second cell row adjacent to the first cell row; combining a first via in the first cell and a second via in the third cell into a third via; and', 'removing a fourth via from the first cell without severing an electrical connection., 'performing, using a microprocessor, a post placement treatment after the placing the first cell and the second cell and after the placing the third cell and the fourth cell, wherein the performing the post placement treatment further comprises2. The method of claim 1 , wherein prior to the removing the fourth via the fourth via connects a cell boundary conductor with a ground rail.3. The method of claim 2 , wherein the cell boundary conductor remains electrically connected to the ground rail through a metal zero connection.4. The method of claim 1 , wherein the first cell is an inverter.5. The method of claim 4 , wherein the second cell is an inverter.6. The method of claim 1 , wherein a region at an intersection of the first cell claim 1 , the second cell claim 1 , the third cell claim 1 , and the fourth cell comprises:a first drain region of the first cell;a first source region of the second cell;a second source region of the third cell; anda second drain region of the fourth cell.7. The method of claim 1 , wherein a region at an ...

CELL GRID ARCHITECTURE FOR FINFET TECHNOLOGY

A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid. 1. A layout of a cell grid , comprising:a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged in a first direction and evenly spaced with a first pitch;a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged in a second direction and evenly spaced with a second pitch, wherein the second pitch of the fin-shaped OD regions defines a width of the cell grid; anda plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the plurality of PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in respective ones of the fin-shaped OD regions and their gates connected to respective ones of the POLY lines;wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.2. The cell grid of claim 1 , wherein the second pitch of the fin-shaped OD regions is smaller than the first pitch of the POLY lines.3. The cell grid of claim 1 , wherein the width of the cell grid is determined by the second pitch of ...

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. A integrated circuit cell , comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows; anda second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.2. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is optimized for speed based on inclusion of the first circuit component in the high fin portion.3. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is optimized for power consumption based on inclusion of the second circuit component in the less fin portion.4. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is arranged in a double height cell layout with the high fin portion and the less fin portion being arranged in adjacent rows.5. The integrated circuit cell of claim 1 , wherein the first circuit component is electrically coupled to the second circuit component to form a standard cell for a logic circuit.6. The integrated circuit cell of claim 5 , wherein the logic circuit is a multi- ...

CELL LAYOUT DESIGN AND METHOD

A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell. 1. A method , comprising:dividing a plurality of cells into groups such that each cell in a group includes a common attribute pertaining to a location of one or more boundary pins within the cell;selecting the one or more groups of cells that meet at least one selection guideline that identifies suitable positions for boundary pins within a cell; andstoring the cells of the one or more groups of cells that meet the selection guideline in a non-transient computer readable storage medium to create a cell library,wherein at least one of the dividing, selecting, and storing is performed using a processor.2. The method of claim 1 , further comprising:determining if an initial layout of cells includes a pin access problem, wherein the initial layout of cells includes an arrangement of two or more cells selected from the cell library;if the initial layout includes at least one pin access problem, then adjusting at least one cell of the initial layout to produce a second layout that differs from the initial layout; andstoring one of the initial layout and the second layout as a final layout.3. The method of claim 2 , further comprising:fabricating at least one photolithography mask based on the final layout; andfabricating an integrated circuit using the at least one photolithography mask.4. The method of claim 2 , wherein adjusting at least one cell of the initial layout includes flipping at least one cell of the at least one cell.5. The method of claim 2 , wherein determining if the initial layout of cells includes a pin access problem includes determining if a marker of a first cell overlaps a marker of a second cell.6. The method of claim 2 , wherein claim 2 ...

Rapidly assembling/disassembling device and electronic equipment

The disclosure discloses a rapidly assembling/disassembling device including a fixing frame, partitions, pushing brackets, and a fastening member. The fixing frame includes a first side plate and a second side plate. Fan modules are sequentially arranged between the first and second side plates. The second side plate abuts against a second side of the adjacent fan module. Each of the partitions abuts against the second side of the corresponding fan module. Each of the pushing brackets is pivotally connected in the fixing frame. Each of the pushing brackets includes a pushing arm. The fastening member is disposed on the first side plate. When the fastening member pushes the adjacent pushing bracket to abut against a first side of the adjacent fan module, each of the other pushing brackets is pushed by the corresponding pushing arm to abut against the first side of the corresponding fan module.

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule. 1. A method of forming an integrated circuit , the method comprising: generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction and being located on a first layout level;', 'generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns; and', 'generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature ...

CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES

A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track. 1. A cell on an integrated circuit , comprising:a fin structure;an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; anda first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track, wherein a first power supply terminal is connected to the first intermediate gate connection metal track, wherein the first intermediate gate connection metal track extends in a first direction, and wherein the first intermediate gate connection metal track extends outside the cell and is connected to a power connecting cell, the power connecting cell being a first neighboring cell of the cell in the first direction.2. The cell of claim 1 , further comprising:a plurality of metal tracks disposed in a first metal (M1) layer above the intermediate gate connection metal layer, wherein no power supply terminal is connected to the plurality of metal tracks.3. The cell of claim 2 , wherein the ...

Semiconductor Device and Layout Design Thereof

A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance. 1. A method comprising:forming a first gate and a second gate over a first active region;forming a first conductive segment over the first active region between the first gate and the second gate, wherein a first distance between the first gate and the first conductive segment is different from a second distance between the second gate and the first conductive segment; andforming a first via over and contacting the first conductive segment, wherein a third distance between the first gate and the first via is different than the first distance, and a fourth distance between the second gate and the first via is different than the second distance.2. The method of claim 1 , wherein the first distance is larger than the second distance.3. The method of claim 1 , wherein the third distance is larger than the fourth distance.4. The method of claim 1 , wherein the third distance is equal to the fourth distance.5. The method of claim 1 , wherein the second gate is formed over an edge of the first active region.6. The method of claim 5 , wherein the second gate is a dummy gate.7. The method of claim 1 , further comprising:forming a third gate and a second conductive segment over a second active region, wherein the second active region and the first active region are disposed on opposing sides of the first gate, wherein the second conductive segment is formed between the first gate and the third gate, wherein a fifth distance between the first gate and the second conductive segment is equal to or larger than a sixth distance between the second conductive segment and the third gate; andforming a second via over and contacting the second conductive segment.8. The method of claim ...

LAYOUT OF STANDARD CELLS FOR PREDETERMINED FUNCTION IN INTEGRATED CIRCUITS

An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts. 1. An integrated circuit designing system , comprising: a first set of standard cell layouts and a second set of standard cell layouts both corresponding to a predetermined manufacturing process and being configured to perform a predetermined function,', 'the predetermined manufacturing process having a nominal minimum pitch (T) of metal lines along a predetermined direction,', 'each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) along the predetermined direction wherein the cell height is a non-integral multiple of the nominal minimum pitch; and, 'a non-transitory storage medium, the non-transitory storage medium being encoded with'} 'wherein each standard cell layout of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout in the first set of standard cell layouts.', 'a hardware processor communicatively coupled with the non-transitory storage ...

Buried Metal Track and Methods Forming Same

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track. 1. An integrated circuit comprising:a semiconductor substrate;an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate;a buried conductive track comprising a portion in the isolation region;a dielectric layer comprising a bottom portion directly underlying the buried conductive trace, wherein the bottom portion extends deeper into the semiconductor substrate than the isolation region; anda transistor comprising a source/drain region and a gate electrode, wherein the source/drain region or the gate electrode is connected to the buried conductive track.2. The integrated circuit of claim 1 , wherein the buried conductive track comprises a portion extending lower than the transistor.3. The integrated circuit of claim 1 , wherein the buried conductive track is connected to the gate electrode claim 1 , and the integrated circuit further comprises a via underlying the gate electrode and connected to the gate electrode.4. The integrated circuit of claim 3 , wherein the gate electrode is continuously connected to the via claim 3 , with no interface formed between the gate electrode and the via.5. The integrated circuit of further comprising a source/drain contact plug connected to the buried conductive track.6. The integrated circuit of further comprising an additional via between and connected to the source/drain contact plug and the buried conductive track.7. The integrated circuit of further comprising a dielectric layer comprising:sidewall portions on opposite sides of the buried conductive track, wherein the sidewall portions have slanted top surfaces ...

Electronic apparatus and detachable assembly thereof

A detachable assembly for an electronic apparatus includes a main frame, a tray and at least one button unit. The tray for mounting a storage device is combined detachably with the main frame and includes two lateral boards. Each lateral board extends outward to form an actuation part included a hook part. Each button unit includes a button combined movably with the main frame, and the button includes a protruding part corresponding to the hook part. When the tray is combined with the main body, the tray is locked by the protruding part fixing each hook part. When each button is forced to move toward the main frame along an axis, each protruding part is released from each hook part, and the tray is pushed by each button to move along a plane substantially perpendicular to the axis. Then the tray is detached from the main frame.

METHOD OF FORMING LAYOUT DESIGN

A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch. 1. A method of forming a layout design for fabricating an integrated circuit (IC) , the method comprising:identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; andgenerating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern of the set of layout patterns having a width measurable along the second direction, and the width of the first layout pattern being less than twice the predetermined pitch.2. The method of claim 1 , wherein a second layout pattern of the set of layout patterns has a width measurable along the second direction claim 1 , and the width of the second layout pattern being an integer multiple of the predetermined pitch.3. The method of claim 1 , ...

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage. 1. An integrated circuit structure comprising: a first active region extending in a first direction and being located at a first level;', 'a second active region extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction, and', 'a first gate structure extending in the second direction, overlapping the first active region and the second active region, and being located at a second level different from the first level;, 'a first cell comprisinga first rail extending in the first direction, overlapping the first active region, being configured to supply a first supply voltage, and being located at a third level different from the first level and the second level, anda second rail extending in the first direction, overlapping the second active region, being located at the third level, being separated from the first rail in the second direction, and being configured to supply a second supply voltage different from the first supply voltage.2. The integrated circuit structure of claim 1 , wherein the first cell further ...

SEMICONDUCTOR DEVICE, LAYOUT OF SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment. 1. A semiconductor device , comprising:a substrate having an active area;a gate structure over the active area;a lower conductive layer over and electrically coupled to the active area, the lower conductive layer at least partially co-elevational with the gate structure, and the lower conductive layer comprising first and second conductive segments laterally spaced from each other; andan upper conductive layer overlapping the first and second conductive segments of the lower conductive layer, the upper conductive layer comprising a third conductive segment overlapping the first and second conductive segments, the third conductive segment electrically coupled to the first conductive segment, and the third conductive segment electrically isolated from the second conductive segment.2. The semiconductor device of claim 1 , whereinthe upper conductive layer further comprises a fourth conductive segment overlapping and electrically coupled to the gate structure.3. The semiconductor device of claim 2 , whereinthe fourth conductive segment is in direct electrical contact with the gate structure.4. The semiconductor device of claim 1 , whereinthe third conductive segment is in direct electrical contact with the first conductive segment.5. The semiconductor device of ...

SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD OF USING

A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern. 1. A semiconductor device , comprising an array of Engineering Change Order (ECO) cells , each of the ECO cells in the array comprising:a first metal pattern;a second metal pattern;a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns; anda first central metal pattern overlapping the first metal pattern; anda via electrically connecting the first central metal pattern to the first metal pattern,wherein the plurality of active area patterns is arranged symmetrically about the first central metal pattern.2. The semiconductor device of claim 1 , further comprising claim 1 , for each of the ECO cells claim 1 ,a second central metal pattern aligned with the first central metal pattern and overlapping the second metal pattern, wherein the plurality of active area patterns is arranged symmetrically about the second central metal pattern.3. The semiconductor device of claim 1 , further comprising claim 1 , for each of the plurality of active area patterns in each of the ECO cells claim 1 ,at least one polysilicon pattern overlapping a first active area pattern of the plurality of active area patterns; andtwo additional metal patterns overlapping the first active area pattern and arranged on opposite sides of the ...

ISOLATION CIRCUIT BETWEEN POWER DOMAINS

An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. 1. An integrated circuit comprising:a type-one active zone and a type-two active zone forming two parallel active zones each extending in a first direction;a first type-one transistor in a first portion of the type-one active zone and having a gate configured to have a first supply voltage of a first power supply;a second type-one transistor in a second portion of the type-one active zone and having a semiconductor channel configured to be at a non-conductive state;a first type-two transistor in a first portion of the type-two active zone and having a gate configured to have a second supply voltage of the first power supply;a second type-two transistor in a second portion of the type-two active zone and having a semiconductor channel configured to be at a non-conductive state;a third type-one transistor in the first portion of the type-one active zone and having a gate configured to have the first supply voltage of a second power supply, wherein the third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor; anda fourth type-one transistor in the second portion of ...

METHOD FOR IMPROVED CUT METAL PATTERNING

A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE. 1. A method of preparing an integrated circuit device design comprising:identifying a vertical abutment between a first cell and a second cell in a device layout;identifying a first internal metal cut in the first cell;identifying a second internal metal cut in the second cell;determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the device layout;determining whether the horizontal spacing satisfies a spacing threshold; and 'repeating the determining, evaluating, and shifting operations until the modified device layout satisfies the spacing threshold.', 'if the spacing threshold is not satisfied, shifting the second cell horizontally relative to the first cell by a distance equal to N contacted polysilicon pitch (CPP) to define a modified device layout, wherein N is an integer;'}2. The method according to claim 1 , further comprising:saving the passing device layout as a modified device layout.3. The method according to claim 2 , wherein:N is at least 4.4. The method according to claim 1 , further comprising:retrieving the device layout from a designated memory.5. The method according to claim 1 , further comprising:receiving the device layout from an electronic design automation (EDA) tool.6. The method according to claim 1 , further comprising:generating a tape out file corresponding to the modified device layout.7. The method according to claim 1 , wherein:the first cell includes a designated safe zone; andthe shifting of the ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules. 1. A system for designing an integrated circuit , the system comprises:a non-transitory computer readable medium configured to store executable instructions; anda processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction;', 'placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns;', 'placing a first conductive feature layout pattern on a second layout level different from the first layout ...

Semiconductor Device including a Conductive Feature Over an Active Region

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. 1. A structure comprising:a first active region in a substrate;a second active region in the substrate, the second active region being spaced apart from the first active region;a first gate structure over the first and second active regions;a second gate structure over the first and second active regions;a first source/drain region and a second source/drain region in the first active region on opposing sides of the first gate structure;a first conductive contact connected to the first source/drain region;a second conductive contact connected to the second source/drain region; anda first conductive feature over and connected to the first and second conductive contacts, the first conductive feature extending over the second active region.2. The structure of further comprising:a first insulating layer over the first gate structure, the first insulating layer being interposed between the first gate structure and the first conductive feature.3. The structure of further comprising:a second conductive feature over and electrically coupled to the the first gate structure, the second conductive feature having a top surface level with a top surface of the first insulating layer.4. The structure of claim 3 , wherein the second conductive feature is electrically coupled to the first conductive contact.5. ...

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures. 1. An integrated circuit structure comprising:a first power rail extending in a first direction and being located at a first level;a second power rail extending in the first direction and being located at the first level, the second power rail being separated from the first power rail in a second direction different from the first direction;a first set of conductive structures extending in the second direction, over the first power rail and being located at a second level different than the first level;a second set of conductive structures extending in the second direction, over the second power rail, being located at the second level, and being separated from the first set of conductive structures in the second direction;a first set of vias coupling the first power rail and the first set of conductive structures to each other;a second set of vias coupling the second power rail and the second set of conductive structures to each other;a first conductive structure extending in the second direction, overlapping a first conductive structure of the first set of conductive structures and a ...

Heart-shaped self-locking button

A heart-shaped self-locking button includes one housing and one push rod. The push rod is slidably arranged within the housing. A heart-shaped structure is formed on the push rod. The button includes one pin and one flexible element. One end of the pin is fixed on the housing, while the other end is fitted with the heart-shaped structure. The flexible element is arranged between the housing and the push rod and presses the pin towards the heart-shaped structure to allow the pin to be in constant contact with the heart-shaped structure. The heart-shaped structure is arranged on the push rod. Also, the flexible element between the housing and the push rod is utilized to press the pin towards the heart-shaped structure on the push rod to allow the pin to be in constant contact with the heart-shaped structure when moving.

ENHANCED COMMUNICATION SYSTEM

As disclosed herein a method, executed by a computer, includes monitoring proximate automobiles using a camera, receiving a request to transmit a communication connection request to a selected automobile, and determining observed attributes corresponding to the selected automobile based on images from the camera. The method further includes broadcasting, over a network, the observed attributes to the proximate automobiles, and requesting disclosed attributes and a connection identifier from the proximate automobiles that match the observed attributes, receiving at least one response from the proximate automobiles that match the observed attributes, and determining which response is a best match to the selected automobile. The method further includes transmitting the communication connection request to the selected automobile over the network using the connection identifier corresponding to the best match. A computer program product corresponding to the above method is also disclosed herein. 1. A method comprising:monitoring proximate automobiles using a camera;receiving a request to transmit a communication connection request to a selected automobile;determining observed attributes corresponding to the selected automobile based on images from the camera;broadcasting, over a network, the observed attributes to the proximate automobiles and requesting disclosed attributes and a connection identifier from proximate automobiles that match the observed attributes;receiving at least one response from the proximate automobiles that match the observed attributes;determining which response is a best match to the selected automobile; andtransmitting the communication connection request to the selected automobile over the network using the connection identifier corresponding to the best match.2. The method of claim 1 , wherein the observed attributes comprise at least one of GPS coordinates claim 1 , license plate information claim 1 , automobile make claim 1 , automobile ...

ROTARY MECHANISM AND RELATED ELECTRONIC DEVICE

A rotary mechanism includes an accommodating slot structure, a supporting arm, a pivoting portion and a resilient component. The accommodating slot structure is disposed on the bezel. The accommodating slot structure includes a pivot hole structure and an opening structure, respectively formed on the lateral surface and a bottom of the accommodating slot structure. The supporting arm is disposed on the door. The pivoting portion is disposed on the surface of the supporting arm. The pivoting portion is disposed inside the pivot hole structure, so that the supporting arm is rotatably disposed inside the accommodating slot structure. The resilient component is movably accommodated inside the opening structure. A first end of the resilient component is resiliently connected to the lateral surface of the accommodating slot structure. A second end of the resilient component points the surface of the supporting arm, to prevent the pivoting portion from separation. 1. A rotary mechanism disposed between a door and a panel , the rotary mechanism comprising: a pivot hole structure formed on the first inner lateral wall; and', 'an opening structure formed on the bottom and adjacent to the second inner lateral wall;, 'an accommodating slot structure disposed on the panel, the accommodating slot structure comprising a first inner lateral wall, a second inner lateral wall and a bottom, the first inner lateral wall and the second inner lateral wall being opposite lateral walls, the accommodating slot structure comprisinga supporting arm disposed on the door, the supporting arm comprising a first surface and a second surface, the first surface being opposite to the second surface;a pivoting portion disposed on the first surface of the supporting arm, the pivoting portion inserting into the pivot hole structure so that the supporting arm is rotatably disposed inside the accommodating slot structure; anda resilient component movably disposed inside the opening structure, a first end ...

Electronic device and conductive ground element

An electronic device includes a metallic housing having a front wall with a mounting hole communicating with an interior thereof, and a front cover spaced apart from the front wall and having an access slot corresponding in position to the mounting hole. A circuit module includes a circuit board disposed within the metallic housing and having an extension protruding out of the front wall via the mounting hole, and an electrical connector disposed on the extension. A conductive ground element is disposed pivotally within the metallic housing in proximity to the mounting hole, and abuts against the electrical connector to conduct static electricity of the electrical connector to the metallic housing.

SYSTEM FOR DESIGNING INTEGRATED CIRCUIT LAYOUT AND METHOD OF MAKING THE INTEGRATED CIRCUIT LAYOUT

An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch. 1. An integrated circuit designing system , comprising:a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch; anda hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.2. The integrated circuit designing system of claim 1 , wherein a ratio of the cell height to the nominal minimum pitch ranges from 6 to 16.3. The integrated circuit designing system of claim 2 , wherein the ratio of the cell height to the nominal minimum pitch is 7.5.4. The integrated circuit designing system of claim 1 , wherein a ratio of the cell height to the nominal minimum pitch is p/q claim 1 , and p and q are integers.5. ...

ISOLATION CIRCUIT BETWEEN POWER DOMAINS

An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply. 1. An integrated circuit comprising:a type-one active zone and a type-two active zone forming two parallel active zones each extending in a first direction;a first type-one transistor in a first portion of the type-one active zone and having a gate configured to have a first supply voltage of a first power supply;a second type-one transistor in a second portion of the type-one active zone and having a semiconductor channel configured to be at a non-conductive state;a first type-two transistor in a first portion of the type-two active zone and having a gate configured to have a second supply voltage of the first power supply;a second type-two transistor in a second portion of the type-two active zone and having a semiconductor channel configured to be at a non-conductive state;a third type-one transistor in the first portion of the type-one active zone and having a first active-region conductively connected with an active-region of the first type-one transistor, the third type-one transistor having a second active-region and a gate conductively connected to ...

Preparation and selection of cells for producing bispecific antibodies

Provided are compositions and methods for preparing a cell suitable for producing a bispecific antibody. A plurality of eukaryotic cells are incubated with an agent under conditions to allow the cells to arrest at G1/S phase. The agent is then removed from the cells and the cells are transfected with a first vector comprising a sequence encoding a first monovalent antigen-binding unit having specificity to a first antigen and a second vector comprising a sequence encoding a second monovalent antigen-binding unit having specificity to a second antigen. A cell is identified from the plurality of cells that expresses both the first and the second antigen-binding units.

SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE

A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure. 1. A method for forming a semiconductor device , comprising:forming a fin structure protruding from a substrate of the semiconductor device;forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess;forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; andforming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.2. The method of claim 1 , further comprising:forming a second conductive rail on the first conductive rail; andelectrically connecting the second conductive rail to a reference voltage.3. The method of claim 2 , wherein a portion the first conductive line formed within the first recess is covered by the second conductive rail.4. The method of claim 2 , wherein a portion the ...

System and method of processing cutting layout and example switching circuit

A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion.

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region. 1. An integrated circuit structure comprising: a first active region having a first dopant type, extending in a first direction and being located at a first level;', 'a second active region having a second dopant type, extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction;', 'a first gate structure extending in the second direction, overlapping at least the first active region or the second active region, and being located at a second level different from the first level;', 'a second gate structure extending in the second direction, overlapping at least a first edge of the first active region or the second active region, and being located at the second level; and', 'a third gate structure extending in the second direction, overlapping at least a second edge of the first active region or the second active region, and being located at the second level;, 'a first cell comprisinga first rail extending in the first direction, overlapping a middle portion of the first active region, being ...

STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD

A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the possible values set to be the first pitch; and placing standard spare cells into a logic area of the layout according to the first pitch; wherein at least one of the generating, selecting and placing is executed by a processor of a computer. 1. A method of designing , for a semiconductor device , a layout which includes standard spare cells , the method comprising:generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer;selecting one member of the set of possible values to be the first pitch; andplacing standard spare cells into a logic area of the layout according to the first pitch;wherein at least one of the generating, selecting and placing is executed by a processor of a computer.2. The method of claim 1 , wherein:the generating the set of possible values for the first pitch is also based on a number of masks selected to produce the metallization layer.3. The method of claim 1 , wherein: calculating a first group of candidate positive integers, each candidate positive integer being evenly divisible into the second pitch;', 'calculating a second group of candidate positive integers, each candidate positive integer being evenly divisible by a number of masks selected to produce the metallization layer; and', 'intersecting the first and second groups of candidate integers to form a third group of candidate integers; and, 'the generating the set of possible values for the first pitch includesthe third group represents the set of possible values for the first pitch.4. The method of claim 3 , wherein the selecting one member of the set of possible values to be the first pitch includes: {'br': None ...

Double rule integrated circuit layouts for a dual transmission gate

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided. 1. A semiconductor structure , comprising:a first transistor and a second transistor disposed adjacent to the first transistor, the first transistor and the second transistor being at a first elevation;a first dummy source/drain disposed at the first elevation;a third transistor and a fourth transistor disposed adjacent to the third transistor, the third transistor and the fourth transistor being at a second elevation different from the first elevation; anda second dummy source/drain disposed at the second elevation,wherein the second transistor is vertically aligned with the third transistor, the first dummy source/drain is vertically aligned with a source/drain of the fourth transistor, the second dummy source/drain is vertically aligned with a source/drain of the first transistor, and a gate structure between the second dummy source/drain and a source/drain of the third transistor is absent.2. The semiconductor structure of claim 1 , wherein a gate structure between the first ...

Metal Cut Optimization for Standard Cells

The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut. 1. A method for optimizing metal cuts in standard cells , the method comprising:placing a standard cell in an layout area;inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell; anddisconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut, wherein at least one of the placing, inserting, and disconnecting is performed by a processor.2. The method of claim 1 , wherein placing the standard cell comprises:checking at least one of a setup time and power consumption of one or more critical paths associated with the standard cell; anddetermining whether at least one of the setup time and power consumption exceeds a predetermined criteria.3. The method of claim 2 , wherein inserting the metal cut comprises inserting the metal cut at the location based on the at least one of the setup time and power consumption exceeding the predetermined criteria.4. The method of claim 1 , wherein the location satisfies a spacing rule between the metal cut and a neighboring metal cut.5. The method of claim 4 , wherein the spacing rule is based on a cell poly pitch (CPP) spacing between two active gate structures minus a width of the metal cut.6. The method of claim 5 , further comprising inserting an other metal cut along the metal interconnect claim 5 , wherein a minimum spacing between the metal cut and the other metal cut is about twice the CPP spacing minus the width of the metal ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates. 1. An integrated circuit comprising:a set of active regions in a substrate, the set of active regions extending in a first direction, being located on a first level, and being separated from one another in a second direction different from the first direction;a first set of conductive structures extending in at least the first direction or the second direction, being located on the first level, and being between the set of active regions;a shallow trench isolation (STI) region extending in at least the first direction or the second direction, being located on at least the first level, and being between the set of active regions and the first set of conductive structures;a set of gates extending in the second direction, overlapping at least the first set of conductive structures and being located on a second level different from the first level, each of the gates of the set of gates being separated from an adjacent gate of the set of gates in the first direction by a first pitch; anda set of contacts extending in the second direction, overlapping the first set of conductive structures, and being located on the second level, each of the contacts of the set of contacts being separated from an adjacent contact of the set of ...

Integrated circuit with elongated coupling

An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

INTEGRATED CIRCUIT LAYOUT DESIGN

An integrated circuit layout that includes a first standard cell having a first transistor region and a second transistor region; a second standard cell having a third transistor region and a fourth transistor region. The first and second standard cells adjoin each other at side boundaries thereof and the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous region. 1. An integrated circuit layout comprising:a first standard cell having a first transistor region and a second transistor region; anda second standard cell having a third transistor region and a fourth transistor region,wherein the first and second standard cells adjoin each other at side cell boundaries thereof and the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous region.2. The integrated circuit layout of claim 1 , wherein the first standard cell further comprises:a first gate strip and a second gate strip parallel to each other; andupper and lower cell boundaries on opposite ends of the first standard cell;the side cell boundaries are parallel to the first gate strip and the second gate strip;the first transistor region comprises a first PMOS transistor comprising a first portion of the first gate strip as a first gate, a first source region and a first drain region adjacent to the first gate, andthe second transistor region comprises a first NMOS transistor comprising a second portion of the first gate strip as a second gate, and a second source region and a second drain region adjacent to the second gate.3. The integrated circuit layout of claim 2 , wherein the second standard cell further comprises:a third gate strip parallel to the first gate strip and the second gate strip; andupper and lower ...

ELECTRONIC DEVICE WITH ROTARY POSITIONING FUNCTION

An electronic device includes a bezel, a door and a resilient component. The bezel includes an accommodating portion and a fixing portion. The accommodating portion has a lateral wall whereon a pivot hole is formed. The fixing portion is disposed on the lateral wall. The door is rotatably disposed on the bezel. The door includes a supporting arm, a pivoting portion and at least one engaging portion. The supporting arm is detachably disposed on the accommodating portion. The pivoting portion passes through the pivot hole. The engaging portion is disposed on the pivoting portion. The resilient component is disposed on the bezel by the fixing portion and presses the pivoting portion. The supporting arm rotates relative to the accommodating portion via the pivoting portion to engage the resilient component with the engaging portion, so as to constrain a relatively rotary angle between the door and the bezel. 1. An electronic device with rotary positioning function , the electronic device comprising: an accommodating portion, the accommodating portion comprising a lateral wall whereon a pivot hole is formed; and', 'a fixing portion disposed on the lateral wall;, 'a bezel, the bezel comprising a supporting arm detachably disposed on the accommodating portion;', 'a pivoting portion disposed on an end of the supporting arm and passing through the pivot hole; and', 'at least one engaging portion disposed on the pivoting portion; and, 'a door rotatably disposed on the bezel, the door comprisinga resilient component, a fixing end of the resilient component being disposed on the bezel via the fixing portion, a free end of the resilient component pressing the pivoting portion, the supporting arm rotating relative to the accommodating portion via the pivoting portion, so that the free end is engaged with the at least one engaging portion to constrain a rotary angle of the door relative to the bezel.2. The electronic device of claim 1 , wherein the door further comprises a first ...

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns. 1. A method of fabricating an integrated circuit structure , the method comprising:placing a first set of conductive structure layout patterns on a first layout level, the first set of conductive structure layout patterns corresponding to fabricating a first set of conductive structures of an integrated circuit structure, the first set of conductive structure layout patterns extending in a first direction, each conductive structure layout pattern of the first set of conductive structure layout patterns being separated from each other in a second direction different from the first direction;placing a second set of conductive structure layout patterns on a second layout level different from the first layout level, the second set of conductive structure layout patterns corresponding to fabricating a second set of conductive structures of the integrated circuit structure, the second set of conductive structure layout patterns extending in the second direction, overlapping the first set of conductive structure layout patterns, and each conductive ...

Flip-flop with delineated layout for reduced footprint

In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. 1. A semiconductor device comprising:a substrate having an active region;a first gate structure over a top surface of the substrate;a second gate structure over the top surface of the substrate, wherein the second gate structure is adjacent to the first gate structure;a pair of first spacers on each sidewall of the first gate structure;a pair of second spacers on each sidewall of the second gate structure;an insulating layer over at least the first gate structure;a first conductive feature over the active region; anda second conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.2. The semiconductor device of claim 1 , further comprising a third conductive feature claim 1 , wherein the third conductive feature is over the first gate structure or the second gate structure.3. The semiconductor device of claim 1 , wherein the first conductive feature has a tapered shape.4. The semiconductor device of claim 1 , wherein the second conductive feature has an L-shape or a U-shape.5. The semiconductor device of claim 1 , wherein a portion of the second conductive feature is embedded in the first conductive feature.6. The semiconductor device of claim 1 , wherein the first conductive feature or the ...

LOCK MECHANISM AND BOX-SHAPED APPARATUS THEREOF

A lock mechanism includes a driving arm having an arm portion and a fixing portion and a lock rod having first and second ends and a pivot portion. The pivot portion is pivoted to one of a cover and a casing. The fixing portion is disposed on the one of the cover and the casing so as to make a free end of the arm portion interfere with an interference portion of the lock rod. The arm portion swings to a first position or a second position when receiving force. When the first end or the second end is pressed, the interference portion drives the free end to make the arm portion swing to the first or second position, so as to make the lock rod move to a locking position for fixing the cover on the casing or a releasing position for releasing the cover from the casing. 1. A lock mechanism for detachably fixing a cover on a side of a casing , the lock mechanism comprising:a lock rod having a first end, a second end and a pivot portion between the first end and the second end, the lock rod being pivoted to one of the cover and the casing through the pivot portion so that the first end and the second end could perform a lever movement relative to the pivot portion, and the first end having an interference portion; anda driving arm connected to a side of the lock rod and having a fixing portion and an arm portion connected to the fixing portion, the driving arm being disposed on the one of the cover and the casing through the fixing portion so as to make a free end of the arm portion interfere with the interference portion of the lock rod, and the arm portion swinging to a first swing position when receiving force in a first direction or swinging to a second swing position when receiving force in a second direction opposite to the first direction;wherein the interference portion drives the free end of the arm portion to make the arm portion swing to the first swing position or the second swing position when the first end or the second end is pressed, so as to make the lock ...

MANUFACTURING METHOD OF AN INPUT CIRCUIT OF A FLIP-FLOP

A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip. 1. A manufacturing method of an input circuit of a flip-flop , comprising:depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first gate strip and the second gate strip, a distance between the second gate strip and the third gate strip, and a distance between the third gate strip and the fourth gate strip equal;executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip, wherein the first first gate strip is a gate terminal of a first PMOS, and the second first gate strip is a gate terminal of a first NMOS;executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip, wherein the first third gate strip is a gate terminal of a second PMOS and the second third gate strip is a gate terminal of a second NMOS, anddirecting a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.2. The manufacturing method of claim 1 , further comprising:directing a first voltage to a source terminal of the first PMOS; anddirecting a ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

An integrated circuit includes a first and a second set of conductive traces. The first set of conductive traces is in a first level and extends in a first direction. The second set of conductive traces is in a second level and extends in a second direction. The second set of conductive traces includes a first conductive trace corresponding to a gate terminal of a first p-type transistor and a gate terminal of a first n-type transistor, and a second conductive trace corresponding to a gate terminal of a second n-type transistor and a gate terminal of a second p-type transistor. The first and second conductive trace are separated from each other in the first direction. The first n-type transistor and the second p-type transistor are part of a first transmission gate. The second n-type transistor and the first p-type transistor are part of a second transmission gate. 1. An integrated circuit , comprising:a first set of conductive traces in a first level of the integrated circuit, the first set of conductive traces extending in a first direction; a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor and a gate terminal of a first n-type transistor; and', 'a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a second n-type transistor and a gate terminal of a second p-type transistor;, 'a second set of conductive traces in a second level of the integrated circuit different from the first level, the second set of conductive traces extending in a second direction different from the first direction, the second set of conductive traces includingwherein the first conductive trace of the second set of conductive traces and the second conductive trace of the second set of conductive traces are separated from each other in the first direction;the first n-type transistor and the second p-type transistor being part of a first transmission gate; andthe second n- ...

Integrated circuit layout method, device, and system

A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.

INTEGRATED CIRCUIT, SYSTEM, AND METHOD OF FORMING THE SAME

A method of forming an integrated circuit includes generating a first and a second standard cell layout design, generating a first set of cut feature layout patterns extending in a first direction, and manufacturing the integrated circuit based on the first or second standard cell layout design. Generating the first standard cell layout design includes generating a first set of conductive feature layout patterns extending in the first direction, and overlapping a first set of gridlines extending in the first direction. Generating the second standard cell layout design includes generating a second set of conductive feature layout patterns extending in the first direction and overlapping a second set of gridlines extending in the first direction. A side of a first cut feature layout pattern extending in the first direction is aligned with a first gridline of the first or second set of gridlines. 1. A method of forming an integrated circuit (IC) , the method comprising: 'generating a first set of conductive feature layout patterns extending in a first direction, being located on a first metal level and overlapping a first set of gridlines extending in the first direction;', 'generating, by a processor, a first standard cell layout design of the integrated circuit, wherein the generating the first standard cell layout design comprises 'generating a second set of conductive feature layout patterns extending in the first direction, being located on the first metal level and overlapping a second set of gridlines extending in the first direction, and the second set of gridlines being separated from the first set of gridlines in a second direction different from the first direction;', 'generating a second standard cell layout design of the integrated circuit, the second standard cell layout design abutting the first standard cell layout design in the first direction, wherein the generating the second standard cell layout design comprisesgenerating a first set of cut feature ...

HORIZONTAL FIVE-AXIS PLATE CONVERSION MACHINING CENTER

A horizontal five-axis turning plate type machining center includes a support base, a lathe bed arranged on the support base and a column arranged on the support base, wherein the lathe bed and the column are fixedly connected through a connecting arm, a turning plate device is arranged on the support base, an X-direction sliding plate capable of sliding in an X direction on the lathe bed is arranged on a side, facing the column, of the lathe bed, and a third driving unit capable of driving a workbench to perform position conversion between a turning plate and the X-direction sliding plate is arranged on the turning plate. 1. A horizontal five-axis turning plate type machining center , comprising a support base , a lathe bed arranged on the support base and a column arranged on the support base , wherein the lathe bed and the column are fixedly connected through a connecting arm , the support base is provided with a turning plate device which comprises a turning plate having a lower part hinged to the support base and a first driving unit capable of driving the turning plate to turn over , and an X-direction sliding plate capable of sliding in an X direction on the lathe bed and a second driving unit capable of driving the X-direction sliding plate to slide are arranged on a side , facing the column , of the lathe bed; and a third driving unit capable of driving a workbench to perform position conversion between the turning plate and the X-direction sliding plate is arranged on the turning plate , the X-direction sliding plate is provided with a locking mechanism capable of locking the workbench , the column is provided with a Y-direction sliding plate , the Y-direction sliding plate is provided with a Z-direction ram , and the Z-direction ram is provided with a milling head.2. The horizontal five-axis turning plate type machining center according to claim 1 , wherein the lower part of the turning plate is provided with a first supporting slideway claim 1 , a lower ...

LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT

A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern. 1. A layout of an integrated circuit , comprising:a first layout device;a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit;a conductive path disposed across the boundary of the first layout device and the second layout device; anda cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer;wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.2. The layout of claim 1 , wherein the conductive path is a polysilicon path.3. The layout of wherein the first layout pattern corresponds to an active circuit in the integrated circuit claim 1 , and the second layout pattern corresponds to the redundant circuit in the integrated circuit.4. The layout of claim 1 , wherein the first layout device ...

Securing Mechanism and Electronic Device Case Comprising the Same

A securing mechanism includes a first securing unit fixedly disposed on a first component of an electronic device case, and a second securing unit fixedly disposed on a second component for securing the second component to the first component in a first direction. The first securing unit includes a fixture board, a limiting structure and a biasing structure. When the second securing unit extends in the first direction through an engaging through hole in the fixture board, the biasing structure biases the second securing unit in a second direction opposite to the first direction, and the second securing unit engages the limiting structure. As a result, movement of the second securing unit in a direction toward the engaging through hole is limited. 1. A securing mechanism for use with a first component and a second component , said securing mechanism being configured to removably secure the second component to the first component , said securing mechanism comprising: a fixture board to be fixedly attached to the first component, having a first surface that faces the second component in use and a second surface that is opposite to said first surface, and formed with an engaging through hole that has an insertion part and an engaging part in spatial communication with each other, said engaging part having a width smaller than that of said insertion part,', 'a limiting structure formed on said second surface of said fixture board, and', 'a biasing structure; and, 'a first securing unit to be fixedly disposed on the first component, and including'} an extending part to extend from the second component in a first direction, and having a width that corresponds with that of said engaging part of said engaging through hole, and', 'a head part disposed on a distal end of said extending part and having a width larger than the width of said engaging part and smaller than that of said insertion part;, 'a second securing unit to be fixedly disposed on the second component and ...

INTEGRATED CIRCUIT HAVING ANGLED CONDUCTIVE FEATURE

An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions. 1. An integrated circuit , comprising: a first gate electrode structure having a first portion and a second portion separated in the first direction from each other, and', 'a second gate electrode structure having a third portion and a fourth portion separated in the first direction from each other; and, 'a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction, the plurality of gate electrode structures comprising a first section electrically connected to the second portion, wherein the first section extends in the second direction,', 'a second section electrically connected to the third portion, wherein the second section extends in the second direction, and', 'a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and ...

LAYOUT OF AN INTEGRATED CIRCUIT

A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog. 1. An integrated circuit , comprising:a first metal line for VDD power including a first jog coupling to and being perpendicular to the first metal line, the first metal line and the first jog being formed in a first metal layer;a second metal line for VSS power including a second jog coupling to and being perpendicular to the second metal line, the second metal line and the second jog being formed in the first metal layer;a third metal line extending over and running parallel to the first jog, the third metal line being formed in a second metal layer above the first metal layer;a fourth metal line extending over and running parallel to the second jog, the fourth metal line being formed in the second metal layer;an upper cell boundary and a lower cell boundary in an X direction; anda first cell boundary and a second cell boundary in a Y direction; the upper cell boundary is defined in a portion of the first metal line;', 'the lower cell boundary is defined in a portion of the second metal line; and', 'the first cell boundary is defined in a portion of the first jog and a portion of the second jog., 'wherein'}2. The integrated circuit of claim 1 , wherein the first metal line together ...

METHOD AND SYSTEM OF FORMING LAYOUT DESIGN

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality. 1. A method of forming a layout design for fabricating an integrated circuit , the method comprising:identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the region of the layout design being sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality, K being an integer equal to or greater than two, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch; andplacing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns, k being an order index ranging from 1 to K, andat least one of the above operations being performed by a hardware processor.3. The method of claim 1 , ...

METHOD AND SYSTEM OF FORMING LAYOUT DESIGN

A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout. 1. A method of forming a layout design for fabricating an integrated circuit , the method comprising:placing a first set of layout patterns in a first layout layer, the first set of layout patterns being aligned with one or more grid lines of a first set of grid lines, the first set of layout patterns corresponding to fabricating a first set of components in a first component layer of the integrated circuit, the first set of grid lines extending along a first direction, a first grid line of the first set of grid lines overlapping a first cell boundary of a standard cell layout, and a second grid line of the first set of grid lines overlapping a second cell boundary of the standard cell layout; andplacing a second set of layout patterns in a second layout layer, the second set of layout patterns being aligned with one or more grid lines of a second set of grid lines, the second set of layout patterns corresponding to fabricating a second set of components in a second component layer of the integrated circuit, the second set of grid lines extending along the first direction and having at least two different line pitches, a first grid line of the second set of grid lines overlapping the ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level. 1. An integrated circuit comprising:a first active region and a second active region in a substrate, the first active region and the second active region being separated from each other in a first direction, and being located on a first level;a third active region in the substrate, the third active region being located on the first level and being separated from the second active region in a second direction different from the first direction;a first contact extending in the second direction, overlapping the first active region, and being located on a second level different from the first level; anda second contact extending in the first direction and the second direction, overlapping the first contact and the third active region, being electrically coupled to the first contact, and being located on a third level different from the first level and the second level.2. The integrated circuit of claim 1 , further comprising:a third contact extending in the second direction, overlapping the third active region, being located on the second level, and being electrically coupled to the second contact.3. The integrated circuit of claim 2 , ...

SEMICONDUCTOR DEVICE WITH FILLER CELL REGION, METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME

A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell. 1. A method of manufacturing a semiconductor device , the method comprising , for a layout diagram stored on a non-transitory computer-readable medium and including a first level of metallization (M_1st level) representing a first layer of metallization in the semiconductor device , generating the layout diagram including: [ first and second boundaries relative to the first direction (side boundaries), the second side boundary substantially abutting the filler cell;', 'first wiring patterns extending substantially in the first direction in the M_1st level and representing corresponding first conductors in the first functional cell region; and', 'first and second groups of cut patterns overlying corresponding portions of the first wiring patterns, the first group overlapping the second side boundary;, 'the first functional cell including, 'adjusting, in the first direction, one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of ...

REDUCED AREA STANDARD CELL ABUTMENT CONFIGURATIONS

A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density. 2. The method of designing a semiconductor device according to claim 2 , further comprising:selecting the second cell block from a library of standard cell blocks.3. The method of designing a semiconductor device according to claim 1 , further comprising:selecting a second modified cell block that reduces the mismatch, the second modified cell comprising a second abutment region having a continuous active region along a second axis parallel to the edge of the vertical abutment; andreplacing the second cell block with the second modified cell block to obtain a second modified layout design.4. The method of designing a semiconductor device according to claim 1 , further comprising:selecting the first modified cell block that comprises a second active region arranged parallel to and inwardly from the continuous active region.5. The method of designing a semiconductor device according to claim 1 , further comprising:selecting the first modified cell block that comprises a plurality of active regions arranged parallel to and inwardly from the continuous active region.6. The method of designing a semiconductor device according to claim 5 , further comprising: [{'sub': '1', 'a first discontinuous active region having an average active region length of L; and'}, {'sub': 2', '1', '2, 'a second discontinuous active ...

CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance. 1. A method of modifying an integrated circuit layout , comprising:identifying, in an integrated circuit layout, at least one reverse signal net having a first conductive line at a first position and a second conductive line at a second position;determining whether the first conductive line and the second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold;determining whether to move the first conductive line to a third position in the integrated circuit layout; andadjusting the integrated circuit layout by moving the first conductive line to the third position in the integrated circuit layout in response to determining to move the first conductive line to the third position.2. The method of claim 1 , further comprising inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line to the third position.3. The method of claim 2 , wherein inserting the isolation structure comprises inserting a capacitive isolation structure or additional dielectric material.4. The method of claim 1 , further comprising inserting a capacitive isolation structure at the first position after moving the first conductive line to the third position.5. The method of claim 1 , further comprising inserting at ...

Double rule integrated circuit layouts for a dual transmission gate

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

INTEGRATED CIRCUIT LAYOUTS WITH SOURCE AND DRAIN CONTACTS OF DIFFERENT WIDTHS

A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width. 1. A semiconductor device comprising:an active region in a substrate, wherein the active region extends in a first direction;a gate structure extending in a second direction different from the first direction, wherein the gate structure extends across the active region; anda plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure, wherein a first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.2. The semiconductor device of claim 1 , further comprising a conductive layer extending in the first direction claim 1 , wherein the conductive layer is electrically coupled to the first source/drain contact and the second source/drain contact.3. The semiconductor device of claim 2 , further comprising a first via claim 2 , wherein the first via electrically couples the conductive layer to the first source/drain contact.4. The semiconductor device of claim 3 , further comprising a second via claim 3 , wherein the second via electrically couples the conductive layer to the second ...

Variable width nano-sheet field-effect transistor cell structure

One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS

A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines. 1. A semiconductor device comprising:standard functional cells located in a logic area;standard spare cells arranged in a spare region of the logic area; anda metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; andwherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.2. The semiconductor device of claim 1 , wherein:the first pitch is substantially evenly divisible into the second pitch.3. The semiconductor device of claim 2 , wherein: each candidate integer being a positive integer greater than two; and', 'each candidate integer being substantially evenly divisible into the second pitch;, 'there is a group of candidate integers;'}the first pitch is a member of the group; andthe first pitch is smaller than a largest member of the group.4. The semiconductor device of claim 2 , wherein: each candidate integer being a positive integer greater than two; and', 'each candidate integer being substantially evenly divisible into the second pitch; and, 'there is a group of candidate integers;'}the first pitch is a smallest member of the group.5. The semiconductor device of claim 1 , wherein:the first pitch is also based on a number of masks used to produce the metallization layer.6. The semiconductor device of claim 5 , wherein: each ...

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure. 1. An integrated circuit structure comprising:a set of gate structures located at a first level, each gate of the set of gate structures being separated from one another in a first direction, and extending in a second direction different from the first direction;a first conductive structure extending in the first direction, overlapping the set of gate structures and being located at a second level;a first set of vias between the set of gate structures and the first conductive structure, each via of the first set of vias being located where the first conductive structure overlaps each gate of the set of gates, and the first set of vias coupling the set of gate structures to the first conductive structure;a first set of conductive structures extending in the second direction, overlapping the first conductive structure, being located at a third level, each conductive structure of the first set of conductive structures being separated from each other in the first direction and being positioned between a pair of gates of the set of gate structures; anda second set of vias between the first set of conductive ...