Limited run branch prediction

A branch prediction technique which increase the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that many branches have run lengths that are constant or slowly-varying, i.e. several consecutive runs of 1's are of the same length. The technique uses the history stored for each branch, which history is enhanced by two small counters (102, 113), an up counter (102) and a down counter (113). These counters (102, 113) operate in conjunction with a state machine branch predictor (101) of the prior art for very accurate predictions.

有限游程转移预测方法

... 本发明提供了一种可以提高正确地预测一个条件转移指令的方向的可能性的转移预测技术。本技术基于观察到许多转移都具有恒定的或缓变的游程长度，即几个连续的1的游程的长度是相同的这种事实。本技术利用每个转移的存储历史，两个小计数器(102，113)，一个上计数器(102)和一个下计数器(113)增强了该历史。为了很准确的预测，这两个计数器(102，113)与一个现有技术的状态机转移预测器(101)协同操作。 ...

Limited run branch prediction

Distributed event reporting hierarchy

In one embodiment, an apparatus comprises a plurality of core logic blocks, a plurality of first event blocks, and a second event block. Each of the plurality of core logic blocks is configured to generate one or more indications of one or more events. Each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block. Each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block. Coupled to the plurality of first event blocks, the second event block is configured to initiate one or more actions responsive to one or more events detected in one or more of the plurality of first event blocks.

System zur Ausführung von Gleitkommaoperationen

Stitching parcels

The invention provides a method and system for performing instructions in a microprocessor having a set of registers, in which instructions which operate on portions of a register are recognized, and "stitching" instructions are inserted into the instruction stream to couple the instructions operating on the portions of the register. The "stitching" parcels are serialized along with other instruction parcels, so that instructions which read from or write to portions of a register can proceed independently and out of their original order, while maintaining the results of that out-or-order operation to be the same as if all instructions were performed in the original order. In a preferred embodiment, the choice of stitching parcels is optimized to the Intel x86 architecture and instruction set.

Symbolic store-load bypass

The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, in a preferred embodiment, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.

System and method for determining a global ordering of events using timestamps

A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.

Limited run branch prediction

Limited run branch prediction method

Method and system for expressing the algorithms for the manipulation of hardware state using an abstract language

A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.

Apparatus for detecting and executing traps in a superscalar processor

Limited run branch prediction

SYSTEM AND METHOD TO PROCESS INSTRUCTION FOR PROCESSOR

PROBLEM TO BE SOLVED: To provide a system and a method to process an instruction to reduce a number of required clock and to simplify a process. SOLUTION: This data processing system is provided with an instruction unit to generate a program instruction. The program instruction is received by a purse unit connected with the instruction unit. The purse unit discriminates whether both of a load operation and a store operation are included in the instruction and generates a first and a second parcels for the instruction including both of the load and the store operations. The first and the second parcels are received by a decode unit connected with the purse unit. Discrimination numbers are installed in the first and the second parcels by the decode unit, the discrimination number of the second parcel is determined from the discrimination number of the first parcel. The first and the second parcels are received by an issuing unit connected with the decode unit. The parcels are issued for an ...

FLOATING POINT ARITHMETIC SYSTEM

PROBLEM TO BE SOLVED: To decrease the number of needed clocks and to facilitate floating point exchanging operation by allowing a physical register to hold the same contents for respective exchange instructions. SOLUTION: An instruction server 106 retrieves one or more insurrections from an instruction cache 104. Four parcels are stored in parcel registers 108A to 108D. Each parcel register sends the parcels to corresponding decoders 110A to 110D, which decode the parcels, determine whether or not the parcels have a floating point exchange instruction, and further determine their operand registers. Then the decoded instructions are sent to corresponding logic units 112A to 112D. The logic units 112A to 112D further receive top-of-stack information and also receive current or existing FXCH maps each time a floating point exchange instruction is received. COPYRIGHT: (C)1998,JPO ...

Modeling operating system instances

A method and mechanism for managing operating system instances in a computing system. A computing system is configured to enable users to model and manage operating system instances. One or more defined operating system instances may be created and stored for future use. Each of the defined operating system instances may include a description of required resources. In addition, the definition of desired and/or optimal resources may be specified. In response to an attempt to realize an operating system instance, a determination is made as to whether resources allocated for the operating system instance are adequate. If the allocated resources are inadequate, further resources may be allocated. In addition, a determination may be made as to whether a standby mode is indicated for the operating system instance. If a standby mode is indicated, the operating system instance may be realized but not booted.

Apparatus for detecting and executing traps in supercalar processor