GATE PROTECTION CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal. 1. A gate protection circuit comprising:a clock signal generator configured to generate a plurality of gate clock signals;a gate driver configured to output gate signals based on the plurality of gate clock signals, the gate driver comprising a plurality of cascading gate driving circuits; anda monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator,wherein the clock signal generator is configured to block generation of the plurality of gate clock signals in response to the feedback signal.2. The gate protection circuit of claim 1 , wherein a plurality of gate clock lines corresponding to the plurality of gate clock signals are connected in parallel and are connected to the monitoring line.3. The gate protection circuit of claim 2 , wherein each of the plurality of gate clock lines is connected to a diode configured to prevent reverse current.4. The gate protection circuit of claim 3 , wherein the feedback signal comprises a voltage in which the plurality of gate clock signals overlap each other.5. The gate protection circuit of claim 4 , wherein the gate clock signals have a same cycle and different phases.6. The gate protection circuit of claim 5 , wherein the plurality of gate clock signals comprises n gate clock signals each configured to be phase-shifted by 1/nth of one ...

METHOD OF DRIVING A DISPLAY PANEL AND A DISPLAY APPARATUS PERFORMING THE METHOD

A method of driving a display panel includes driving a first sub area and a second sub area of a pixel part in a two-dimensional (2D) image mode, wherein a first luminance difference exists between the first and second sub areas in the 2D image mode, and driving the first sub area and the second sub area of the pixel part in a three-dimensional (3D) image mode, wherein a second luminance difference exists between the first and second sub areas in the 3D image mode, the second luminance difference being smaller than the first luminance difference. 1. A method of driving a display panel , the method comprising:driving a first sub area and a second sub area of a pixel part in a two-dimensional (2D) image mode, wherein a first luminance difference exists between the first and second sub areas in the 2D image mode; anddriving the first sub area and the second sub area of the pixel part in a three-dimensional (3D) image mode, wherein a second luminance difference exists between the first and second sub areas in the 3D image mode, the second luminance difference being smaller than the first luminance difference.2. The method of claim 1 , wherein in the 3D image mode a luminance value of the first sub area of the pixel part is about equal to a luminance value of the second sub area of the pixel part.3. The method of claim 1 , further comprising:determining that a received image signal is for the 2D image mode or the 3D image mode; andgenerating a first vertical start signal and a second vertical start signal based on the determined image mode.4. The method of claim 3 , wherein driving the first sub area and the second sub area of the pixel part in the 2D image mode comprises:generating a first sub gate signal having a high level and a low level based on the first vertical start signal having the high level and the low level;charging a data voltage into a first liquid crystal (LC) capacitor and a second LC capacitor in response to the first vertical start signal of the high ...

LIQUID CRYSTAL COMPOSITION AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME

A liquid crystal composition according to an exemplary embodiment of the present invention includes a liquid crystal compound represented by a below chemical formula (I) at about 10 wt % to about 15 wt %; and 2. The liquid crystal composition of claim 1 , whereinthe amount of the liquid crystal compound represented by the chemical formula (II) is less than about 5 wt % of the total amount of the liquid crystal composition,the amount of the compound represented by the chemical formula (III) is in a range of about 4 wt % to about 7 wt % of the total amount of the liquid crystal composition, andthe amount of the compound represented by the chemical formula (IV) is in a range of about 3 wt % to about 8 wt % of the total amount of the liquid crystal composition.4. The liquid crystal composition of claim 3 , whereinthe amount of the compound represented by the chemical formula (V) is in a range of about 32 wt % to about 43 wt % of the total amount of the liquid crystal composition,the amount of the compound represented by the chemical formula (VI) is in a range of about 2 wt % to about 13 wt % of the total amount of the liquid crystal composition,the amount of the compound represented by the chemical formula (VII) is in a range of about 8 wt % to about 15 wt % of the total amount of the liquid crystal composition,the amount of the compound represented by the chemical formula (VIII) is in a range of about 10 wt % to about 15 wt % of the total amount of the liquid crystal composition,the amount of the compound represented by the chemical formula (IX) is in a range of about 5 wt % to about 15 wt % of the total amount of the liquid crystal composition, andthe amount of the compound represented by the chemical formula (X) is in a range of about 2 wt % to about 7 wt % of the total amount of the liquid crystal composition.6. The liquid crystal display of claim 5 , whereinthe amount of the liquid crystal compound represented by the chemical formula (II) is less than about 5 wt % ...

SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF

A semiconductor device comprises a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals. 1. A semiconductor device comprising:a plurality of cell blocks activated in response to a plurality of selection signals, respectively;a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode;a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap; anda decision circuit configured to decide whether or not the activated cell blocks are repaired in response to stored repair information and the activated selection signals.2. The semiconductor device of claim 1 , wherein the decision circuit comprises a plurality of fuses corresponding to the selection signals claim 1 , respectively claim 1 , and the decision unit is configured to activate a first signal in response to cut states of fuses corresponding to the activated selection signals.3. The semiconductor device of claim 2 , wherein one of the ...

PARALLEL TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS

A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad. 1. A parallel test circuit of a semiconductor memory apparatus , comprising:a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks,wherein, when a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.2. The parallel test circuit according to claim 1 , wherein the first and second sub banks are both enabled during the test mode.3. The parallel test circuit according to claim 2 , wherein the global line and the test global line of the second sub bank respectively comprise a plurality of lines claim 2 ,and the parallel test circuit further comprises:a compression unit configured to compare data loaded in the plurality of global lines and data loaded in the plurality of global test lines of the second sub bank, compress the comparison result, and output a compression signal based on a compression result; andan output unit configured to generate the test output signal in response to a strobe signal and the compression signal, and output the generated test output signal to the pad.4. The parallel test ...

COLOR CONVERSION SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME

A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter. 1. A color conversion substrate , comprising:a base substrate;a first color filter and a second color filter disposed on a surface of the base substrate;a first partition layer disposed between the first color filter and the second color filter;a second partition layer disposed on the first partition layer;a first wavelength conversion pattern disposed on the first color filter; anda second wavelength conversion pattern disposed on the second color filter,wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.2. The color conversion substrate of claim 1 , wherein the first color filter and the second color filter are spaced apart from each other claim 1 , and the first partition layer further includes a third lower surface disposed on the surface of the base substrate.3. The color conversion substrate of claim 2 , wherein the first partition layer includes a portion of which side surface is inclined from the third lower surface toward ends of the first lower surface and the second lower surface.4. The color conversion substrate of claim 2 , wherein the first lower surface and the second lower surface are parallel to the surface of the base substrate.5. The color conversion substrate of ...

COLOR CONVERSION PANEL AND DISPLAY DEVICE INCLUDING THE SAME

A display device includes: a display panel; and a color conversion panel overlapping with the display panel. The color conversion panel includes: a substrate; a first color conversion pattern on the substrate; a second color conversion pattern on the substrate, and partially overlapping with the first color conversion pattern; a first reflective partition wall between the first color conversion pattern and the second color conversion pattern; a first color filter between the substrate and the first color conversion pattern; and a second color filter between the substrate and the second color conversion pattern. 1. A display device , comprising:a display panel; and{'claim-text': ['a substrate;', 'a first color conversion pattern on the substrate;', 'a second color conversion pattern on the substrate, and partially overlapping with the first color conversion pattern;', 'a first reflective partition wall between the first color conversion pattern and the second color conversion pattern;', 'a first color filter between the substrate and the first color conversion pattern; and', 'a second color filter between the substrate and the second color conversion pattern.'], '#text': 'a color conversion panel overlapping with the display panel, the color conversion panel comprising:'}2. The display device of claim 1 , wherein the first reflective partition wall covers a side of the first color conversion pattern.3. The display device of claim 2 , wherein the second color conversion pattern does not contact the first color conversion pattern.4. The display device of claim 1 , wherein the second color conversion pattern contacts the first color conversion pattern underneath the first reflective partition wall.5. The display device of claim 1 , wherein the color conversion panel further comprises:a light blocking pattern partially overlapping with the first color conversion pattern and the second color conversion pattern between the first color conversion pattern and the second ...

Display device

Provided is a display device. The display device includes a first base portion, a second base portion facing the first base portion, a light emitting layer disposed on one surface of the first base portion and emitting first light, a first wavelength conversion pattern disposed on the light emitting layer and converting the first light into second light having a different wavelength from the first light, a first color filter overlapping the first wavelength conversion pattern on one surface of the second base portion and spaced apart from the first wavelength conversion pattern, and an air layer interposed between the first wavelength conversion pattern and the first color filter.

Method for simulating event-driven switching circuit and saving medium to which circuit simulation program using same is saved

Disclosed is a method of simulating a switching electrical circuit, including one or more reactive elements and one or more switches. The method includes receiving an electrical circuit including one or more reactive elements and one or more switches and a stimulus expressed in a form of a linear combination of one or more basis functions; calculating a response of the electrical circuit before the switching in a form of a linear combination of one or more basis functions, using an s-domain transfer function of the electrical circuit before the switching, initial values of the reactive elements before the switching, and the stimulus expressed in a form of a linear combination of one or more basis functions; and calculating a response of the electrical circuit after the switching in a form of a linear combination of one or more basis functions, using an s-domain transfer function of the electrical circuit after the switching and initial values of the reactive elements after the switching.

LIQUID CRYSTAL COMPOSITION AND A LIQUID CRYSTAL DISPLAY INCLUDING THE SAME

A liquid crystal display including a first substrate, a second substrate disposed opposite the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The liquid crystal layer includes a liquid crystal composition. The liquid crystal composition includes at least one of liquid crystal compounds including a cyclopentadienyl group. 2. The display of claim 1 , wherein the liquid crystal compounds of Formulae 1 to 3 are in an amount of more than about 0% by weight to about 50% by weight with respect to the liquid crystal composition.8. The display of claim 1 , wherein the liquid crystal composition has a negative dielectric anisotropy.10. The display of claim 1 , wherein the liquid crystal layer is driven in a vertical alignment mode.12. The composition of claim 11 , wherein the liquid crystal compounds of Formulae 1 to 3 are in an amount of more than about 0% by weight to about 50% by weight with respect to the liquid crystal composition.18. The composition of claim 11 , wherein the composition has a negative dielectric anisotropy.20. The composition of claim 11 , wherein the composition is used in a vertical alignment mode liquid crystal display. The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0102296, filed on Aug. 11, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.Exemplary embodiments of the present invention relate to a liquid crystal composition, and more particularly to a liquid crystal display including the same.A liquid crystal display may include a first substrate, a second substrate, and a liquid crystal layer. The first substrate may include a plurality of pixel electrodes. The second substrate may include a common electrode. The liquid crystal layer may be disposed between the first substrate and the second substrate. The liquid crystal display may display an image. The ...

DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME

A display panel is provided. A first substrate includes a display area and a peripheral area. The peripheral area surrounds the display area. A second substrate is disposed on the first substrate. The second substrate faces the first substrate along a first direction. A liquid crystal layer is interposed between the first substrate and the second substrate. A multi-layered sealant is disposed on the peripheral area of the first substrate. The multi-layered sealant surrounds the liquid crystal layer. The multi-layered sealant includes a first sealant layer including an acrylate resin having a functional group having at least 3 carbon atoms, and a second sealant layer including an epoxy resin having a (meth)arcylate group. 1. A display panel , comprising:a first substrate including a display area and a peripheral area, the peripheral area surrounding the display area;a second substrate disposed on the first substrate, facing the first substrate along a first direction;a liquid crystal layer interposed between the first substrate and the second substrate; anda multi-layered sealant disposed on the peripheral area of the first substrate and surrounding the liquid crystal layer,wherein the multi-layered sealant includes:a first sealant layer including an acrylate resin having a functional group having at least 3 carbon atoms, anda second sealant layer including an epoxy resin having a (meth)arcylate group.2. The display panel of claim 1 , wherein the multi-layered sealant is about 0.1 mm to about 1.0 mm in width measured in a second direction crossing the first direction claim 1 , and the multi-layered sealant is about 2 μm to about 5 μm in height measured in the first direction.3. The display panel of claim 1 , wherein the multi-layered sealant further includes a third sealant layer claim 1 , wherein the first sealant layer claim 1 , the second sealant layer claim 1 , and the third sealant layer are vertically stacked on each other along the first direction claim 1 , ...

COLOR TRANSFORMATION SUBSTRATE AND DISPLAY DEVICE

A color transformation substrate comprises: a base portion having first and second light-blocking areas and first to third light-transmitting areas, where the light-transmitting areas are successively positioned along a first direction; first to third color filters positioned in the first to third light-transmitting areas, respectively; a light-blocking member positioned in the first light-blocking area, and including part contacting the base portion; a color pattern positioned in the second light-blocking area so as to contact the base portion; a first wavelength conversion pattern positioned on the second color filter so as to wavelength-convert light having a first color into light having a second color; and a second wavelength conversion pattern positioned on the third color filter so as to wavelength-convert light having the first color into light having a third color different from light having the second color. The color pattern and the first color filter comprise the same color material. 1. A color conversion substrate comprising:a base portion in which a first light-blocking area, a second light-blocking area, a first light-transmitting area, a second light-transmitting area, and a third light-transmitting area are defined, wherein the first light-transmitting area, the second light-transmitting area, and the third light-transmitting area are sequentially disposed along a first direction;a first color filter disposed on the base portion and disposed in the first light-transmitting area;a second color filter disposed on the base portion and disposed in the second light-transmitting area;a third color filter disposed on the base portion and disposed in the third light-transmitting area;a light-blocking member including a first light-blocking member which is disposed on the base portion, disposed in the first light-blocking area, and includes a portion in contact with the base portion;a color pattern including a first color pattern which is disposed on the ...

Liquid crystal composition and display device including the same

A liquid crystal composition includes a compound having a structure represented by formula A-1: wherein R A1 is an alkyl group, an alkoxy group, a cyano group, a halogen atom, or a hydrogen atom, R A2 is an alkyl group, a cyano group, a halogen atom, or a hydrogen atom, Z A is *—O—*, *—COO—*, *—OCO—*, *—CF 2 O—*, *—OCF 2 —*, *—CH 2 O—*, *—OCH 2 —*, *—SCH 2 —*, *—CH 2 S—*, *—C 2 F 4 —*, *—CH 2 CF 2 —*, *—CF 2 CH 2 —*, *—(CH 2 ) k —*, *—CH═CH—*, *—CF═CF—*, *—CH═CF—*, *—CF═CH—*, *—C≡C—*, *—CH═CHCH 2 O—*, or a single bond, X is a halogen atom, each of l1 and l2 is independently an integer of 0 to 2, and when l1 is 2 and Z A in a repeating unit defined by l1 are the same or different, wherein k is an integer of 1 to 5 and “*” indicates a point of attachment.

LIQUID CRYSTAL COMPOSITION AND DISPLAY DEVICE INCLUDING THE SAME

A liquid crystal composition includes: at least one liquid crystal compound selected from the group consisting of Chemical Formulas 1-1 to 1-8; at least one self-aligned compound selected from the group consisting of Chemical Formulas 2-1 and 2-2; and at least one reactive mesogen selected from the group consisting of Chemical Formulas 3-1 to 3-5. Compositions and devices constructed therewith are capable of ameliorating liquid crystal drip spots that typically occur in a manufacturing process. In addition, the display devices using the composition do not require an additional alignment layer, which simplifies manufacturing. 2. The liquid crystal composition of claim 1 , wherein:a content of the liquid crystal compound represented by Chemical Formula 1-1 is 0 to 1 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-2 is 0 to 1 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-3 is 3 to 10 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-4 is 3 to 20 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-5 is 3 to 20 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-6 is 3 to 20 wt % of the entire liquid crystal composition,a content of the liquid crystal compound represented by Chemical Formula 1-7 is 10 to 30 wt % of the entire liquid crystal composition, anda content of the liquid crystal compound represented by Chemical Formula 1-8 is 3 to 30 wt % of the entire liquid crystal composition.3. The liquid crystal composition of claim 1 , wherein a content of the self-aligned compound is 0.05 wt % to 3 wt % of the entire liquid crystal composition.4. The liquid crystal composition of claim 1 , wherein a content of the ...

DISTRIBUTING ON CHIP INDUCTORS FOR MONOLITHIC VOLTAGE REGULATION

Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system. 1. A processor , comprising:an integrated voltage regulator comprising a plurality of pairs of inductors implemented on a die of the processor, wherein a respective clock phase assigned to a first inductor of each of the pairs is different than a respective clock phase assigned to a second one of each of the pairs; andthe pairs of inductors configured to regulate voltage as part of a power distribution network (PDN) for different respective portions of the die.2. The processor of claim 1 , wherein the respective clock phase assigned to the first inductor of each of the pairs is opposite the respective clock phase assigned to the second one of each of the pairs.3. The processor of claim 1 , wherein the respective clock phase values assigned to each of the pairs of inductors are interleaved across different ones of the pairs of inductors.4. The processor of claim 1 ,wherein the processor further comprises one or more circuits configured to implement control logic for the integrated voltage regulator comprising the plurality of pairs of inductors;wherein the control logic is configured to enable one or more of the pairs to distribute power in addition to one or more currently enabled pairs; andwherein the enabled one or more of the pairs are assigned to two or more clock phases different than two or more clock phases assigned to the one or more currently enabled pairs.5. The processor of claim 1 , wherein the processor is a multicore processor claim ...

DISPLAY PANEL AND THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDED IN THE SAME

Provided are a display panel and a thin film transistor array substrate. According to one or more exemplary embodiments, a display panel includes: a first substrate including a pixel area and a non-pixel area; a second substrate that faces the first substrate; and a crack guide groove disposed on a surface of at least one of the first substrate and the second substrate. 1. A display panel comprising:a first substrate comprising a pixel area and a non-pixel area;a second substrate that faces the first substrate; anda crack guide groove disposed on a surface of at least one of the first substrate and the second substrate.2. The display panel of claim 1 , wherein the crack guide groove has at least one of a solid line shape and a dotted line shape along a first direction.3. The display panel of claim 1 , wherein crack guide groove portions are disposed in opposite edge portions of the at least one of the first substrate and the second substrate claim 1 ,wherein a first crack guide groove portion and a second crack guide groove portion of the crack guide groove are disposed in the opposite edge portions, respectively, andwherein the first crack guide groove portion and the second crack guide groove portion are separated in a first direction and substantially aligned relative to a second direction substantially perpendicular to the first direction.4. The display panel of claim 1 , wherein a depth of the crack guide groove is equal to or smaller than one tenth of a thickness of the at least one of the first substrate and the second substrate.5. The display panel of claim 1 , wherein a cross section shape of the crack guide groove is selected from a group consisting of a triangle and a rectangle.6. The display panel of claim 1 , wherein the first substrate and the second substrate are substantially flat and the at least one of the first substrate and the second substrate is configured to generate a crack along the crack guide groove when bent more than a threshold bending ...

LIQUID CRYSTAL COMPOSITION AND DISPLAY DEVICE INCLUDING THE SAME

Disclosed is a liquid crystal composition including at least one compound selected from the group consisting of a liquid crystal compound expressed by Formula 1-1 and a liquid crystal compound expressed by Formula 1-2; at least one compound selected from the group consisting of a self-alignment compound expressed by Formula 2-1 and a self-alignment compound expressed by Formula 2-2; and at least one compound selected from the group consisting of a reactive mesogen expressed by Formula 3-1, a reactive mesogen expressed by Formula 3-2, a reactive mesogen expressed by Formula 3-3, a reactive mesogen expressed by Formula 3-4, and a reactive mesogen expressed by Formula 3-5. The liquid crystal composition also has negative dielectric anisotropy. 2. The liquid crystal composition of claim 1 , wherein:a content of the liquid crystal compound expressed by Formula 1-1 is 0.5 wt % to 3 wt % of the liquid crystal composition, anda content of the liquid crystal compound expressed by Formula 1-2 is 0.5 wt % to 3 wt % of the liquid crystal composition.4. The liquid crystal composition of claim 1 , wherein a content of at least one of the self-alignment compound expressed by Formula 2-1 and the self-alignment compound expressed by Formula 2-2 is 0.05 wt % to 3 wt % of the liquid crystal composition.5. The liquid crystal composition of claim 1 , wherein a content of at least one of the reactive mesogen expressed by Formula 3-1 claim 1 , the reactive mesogen expressed by Formula 3-2 claim 1 , the reactive mesogen expressed by Formula 3-3 claim 1 , the reactive mesogen expressed by Formula 3-4 claim 1 , and the reactive mesogen expressed by Formula 3-5 is 0.05 wt % to 3 wt % of the liquid crystal composition.6. The liquid crystal composition of claim 1 , wherein refractive anisotropy of the liquid crystal composition is 0.08 to 0.13 claim 1 , rotation viscosity is 70 to 150 claim 1 , and dielectric anisotropy is −2.8 to −5.5.7. The liquid crystal composition of claim 3 , wherein:the ...

DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME

A display apparatus includes a display panel which displays an image, a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area, a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area, a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal, and a correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data. 1. A display apparatus comprising:a display panel which displays an image;a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area;a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area;a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal; anda correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data.2. The display apparatus of claim 1 , wherein the compensation area is divided into a boundary area adjacent to a boundary between the compensation area and the normal area and a remaining area except for the boundary area claim 1 , andthe compensation coefficient determiner determines a compensation coefficient of the boundary area to gradually increase by a horizontal line.3. The display apparatus of claim 1 , further comprising:a normal look up table which stores a normal compensation data which compensates input data of the normal area.4. The display ...

ADDRESS STORAGE CIRCUIT AND MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation. 1. A memory , comprising:a plurality of word lines wherein one or more memory cells are coupled to individual word lines;an address storage unit suitable for storing an input address corresponding to a first external signal that is received at a random time; anda control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.2. The memory of claim 1 , wherein the one or more target word lines comprise one or more word lines corresponding to the address stored in the address storage unit and one or more word lines adjacent to the word line corresponding to the address stored in the address storage unit.3. The memory of claim 1 , wherein:the first external signal is the active command; andthe address storage unit determines a time at which the input address is stored using a period signal that oscillates in a set cycle and a second external signal that is externally received.4. The memory of claim 3 , wherein the address storage unit comprises:an enable signal generation unit suitable for activating an enable signal when the second external signal is received by a first set number of times or more in a state in which the period signal is a first level, and deactivating the enable signal when the second external signal is ...

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time. 1. A memory comprising:a plurality of word lines coupled to one or more memory cells;a target address generation unit suitable for generating one or more target addresses using a stored address; anda control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command, which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.2. The memory of claim 1 , further comprising an address detection unit suitable for detecting a highly active word line claim 1 , which has been activated a number greater than or equal to a preset number or which has an activation frequency greater than or equal to a preset frequency claim 1 , during a preset period.3. The memory of claim 2 , wherein the target address generation unit stores an address of the highly active word line claim 2 , andwherein the target address corresponds to a target word line adjacent to the highly active word line.4. The memory of claim 1 , wherein the control unit refreshes a target word line corresponding to the target address while the refresh command is inputted N times claim 1 , and changes sequential order in which the target word line is refreshed during N times of input of the refresh commands.5. The memory of claim 1 , further comprising an address counting unit suitable for generating a counting address claim 1 , a value of which is changed whenever a word line is refreshed.6. The memory of claim 5 , wherein the control ...

LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL COMPOSITION INCLUDED THEREIN

A liquid crystal display includes a first base substrate, a second base substrate facing the first base substrate, and an electrode unit disposed on at least one of the first base substrate and the second base substrate. A liquid crystal layer is positioned between the first base substrate and the second base substrate and includes a liquid crystal composition. The liquid crystal composition includes at least one of a liquid crystal compound represented by Chemical Formula 1, at least one of a liquid crystal compound represented by Chemical Formula 2-A, and at least one of a liquid crystal compound represented by Chemical Formula 2-B. The liquid crystal compound of Chemical Formula 2-A includes a cyclohexylene and a phenylene 8. The liquid crystal display of claim 1 , whereinthe liquid crystal composition has negative dielectric anisotropy.11. The liquid crystal display of claim 1 , whereinthe liquid crystal layer is driven in a vertical aligned mode This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0175936 filed in the Korean Intellectual Property Office on Dec. 21, 2016, the disclosure of which is incorporated by reference herein in its entirety.Exemplary embodiments of the present invention relate to a liquid crystal display, and more particularly to a liquid crystal composition included therein.A liquid crystal display generally includes a first substrate having a plurality of pixel electrodes, a second substrate having a common electrode, and a liquid crystal layer disposed between the first substrate and the second substrate. The liquid crystal display may display an image by varying light transmittance of the liquid crystal layer according to an electric field formed between each of the pixel electrodes and the common electrode. The liquid crystal display may include a plurality of pixels, which each include the pixel electrode.An exemplary embodiment of the present invention provides a liquid crystal composition ...

Method for training multichannel data receiver timing

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

DISTRIBUTING ON CHIP INDUCTORS FOR MONOLITHIC VOLTAGE REGULATION

Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system. 120-. (canceled)21. A processor , comprising:an integrated voltage regulator comprising a plurality of pairs of inductors implemented on a die of the processor, wherein the pairs of inductors are evenly distributed amongst different voltage domains, wherein a respective clock phase assigned to a first inductor of each of the pairs is different than a respective clock phase assigned to a second one of each of the pairs, and wherein the different voltage domains are enabled or disabled according to the respective clock phases assigned to the pairs of inductors; andthe pairs of inductors configured to regulate voltage as part of a power distribution network (PDN) for different respective portions of the die.22. The processor of claim 21 , wherein the respective clock phase assigned to the first inductor of each of the pairs is opposite the respective clock phase assigned to the second one of each of the pairs.23. The processor of claim 21 , wherein the respective clock phase values assigned to each of the pairs of inductors are interleaved across different ones of the pairs of inductors.24. The processor of claim 21 ,wherein the processor further comprises one or more circuits configured to implement control logic for the integrated voltage regulator comprising the plurality of pairs of inductors;wherein the control logic is configured to enable one or more of the pairs to distribute power in addition to one or more currently enabled pairs; ...

Display apparatus and method of driving the same

A display apparatus includes a gamma controller configured to determine whether the target pixel unit is driven in both time division method and space division method based on a plurality of comparison values and a reference condition, and an output controller configured to generate normal gamma-data of the target pixel unit using a normal gamma curve if the plurality of comparison values satisfy the reference condition and to generate high gamma-data and low gamma-data of the target pixel unit using a high gamma curve and a low gamma curve in both time division method and space division method if the plurality of comparison values do not satisfy the reference condition.

METHOD FOR TRAINING MULTICHANNEL DATA RECEIVER TIMING

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus. 1. An apparatus , comprising: [ determining, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal; and', 'determining, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal;, 'a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal, including by, 'wherein the control circuit is configured, during an operational phase, to use delays based on the first and second timing relationships to sample data from the second device on the data bus., 'a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus, wherein the first device includes2. The apparatus of claim 1 , wherein the ...

COLOR CONVERSION SUBSTRATE AND DISPLAY DEVICE

A color conversion substrate includes a base on which first to third light outputting regions and a light shielding region surrounding the first to third light outputting regions are defined; first to third color filters on the base in the first to third light outputting regions, respectively; a first light shielding member on the first color filter in the light shielding region; a light transmission pattern on the first color filter; a first wavelength conversion pattern on the second color filter and which converts light of a first color into light of a second color; and a second wavelength conversion pattern on the third color filter and which converts the light of the first color into light of a third color. A first opening located in the light shielding region is defined in at least one of the light transmission pattern and the first and second wavelength conversion patterns. 1. A color conversion substrate comprising:a base on which a first light outputting region, a second light outputting region and a third light outputting region sequentially disposed to be spaced apart from each other along a first direction, and a light shielding region surrounding each of the first to third light outputting regions are defined;a first color filter disposed on the base and disposed in the first light outputting region and the light shielding region;a second color filter disposed on the base and disposed in the second light outputting region;a third color filter disposed on the base and disposed in the third light outputting region;a first light shielding member disposed on the first color filter and disposed in the light shielding region;a light transmission pattern disposed on the first color filter;a first wavelength conversion pattern disposed on the second color filter, wherein the first wavelength conversion pattern converts light of a first color into light of a second color; anda second wavelength conversion pattern disposed on the third color filter, wherein the ...

LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

A liquid crystal display device comprises: a first substrate; an organic layer disposed on the first substrate; a pixel electrode disposed on the organic layer; a plurality of slits defined in the pixel electrode and configured to exposed a surface of the organic layer; a liquid crystal alignment film disposed on a surface of the pixel electrode and on the surface of the organic layer exposed by the plurality of slits; and a plurality of liquid crystal molecules disposed on the liquid crystal alignment film, wherein the liquid crystal alignment film includes a first region overlapping the plurality of slits and a second region overlapping the pixel electrode, wherein the second region has a surface energy different from a surface energy of the first region. 1. A liquid crystal display device comprising:a first substrate;an organic layer disposed on the first substrate;a pixel electrode disposed on the organic layer;a plurality of slit defined in the pixel electrode and configured to expose a surface of the organic layer;a liquid crystal alignment film disposed on a surface of the pixel electrode and on the surface of the organic layer exposed by the plurality of slits; anda plurality of liquid crystal molecules disposed on the liquid crystal alignment film,wherein the liquid crystal alignment film comprises a first region overlapping the plurality of slits and a second region overlapping the pixel electrode, and wherein the second region has a surface energy different from a surface energy of the first region.2. The liquid crystal display device of claim 1 , wherein a portion of the liquid crystal molecules are disposed on the first region and a portion of the liquid crystal molecules are disposed on the second region claim 1 , wherein an average alignment direction of the portion of the liquid crystal molecules on the first region and an average alignment direction of the portion of the liquid crystal molecules on the second region are at different angles with ...

Cosmetic mask kit packed in biodegradable packaging material

Disclosed is a cosmetic mask kit packed in a biodegradable packaging material, wherein the use of the mask kit of the present disclosure can be eco-friendly since the mask kit is designed as a 100% biodegradable product, and the mask kit of the present disclosure can significantly improve the satisfaction of a customer since a mask sheet can implement various feelings of use according to the preference of a user.

Semiconductor memory device capable of controlling drivability of overdriver

A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

Method for training multichannel data receiver timing

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Semiconductor memory device

A semiconductor memory device, including a memory banks and associated local data buses, and a bus connection circuit connected to the local data buses associated with two or more of the memory banks to perform a selective data transfer between a global data bus and those local data buses.

Semiconductor memory device with ZQ calibration

A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal.

Color conversion substrate and display device

A color conversion substrate includes a base on which first to third light outputting regions and a light shielding region surrounding the first to third light outputting regions are defined; first to third color filters on the base in the first to third light outputting regions, respectively; a first light shielding member on the first color filter in the light shielding region; a light transmission pattern on the first color filter; a first wavelength conversion pattern on the second color filter and which converts light of a first color into light of a second color; and a second wavelength conversion pattern on the third color filter and which converts the light of the first color into light of a third color. A first opening located in the light shielding region is defined in at least one of the light transmission pattern and the first and second wavelength conversion patterns.

Test mode control circuit

Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.

Liquid crystal composition and a liquid crystal display including the same

A liquid crystal display including a first substrate, a second substrate disposed opposite the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The liquid crystal layer includes a liquid crystal composition. The liquid crystal composition includes at least one of liquid crystal compounds including a cyclopentadienyl group.

Color converting substrate and display device including same

Provided are a color converting substrate and a display device including same. The color converting substrate includes: a base portion in which a first light transmission area, a first light blocking area, and a second light transmission area, which are sequentially and closely arranged in a first direction, are defined; a first wavelength converting pattern located on the base portion and configured to wavelength-covert a first color light into a second color light; a second wavelength converting pattern located on the base portion and configured to wavelength-convert the first color light into a third color light; and a light transmission pattern located on the base portion and configured to transmit the first color light.

Liquid crystal composition and display device including the same

A liquid crystal composition includes: at least one liquid crystal compound selected from the group consisting of Chemical Formulas 1-1 to 1-8; at least one self-aligned compound selected from the group consisting of Chemical Formulas 2-1 and 2-2; and at least one reactive mesogen selected from the group consisting of Chemical Formulas 3-1 to 3-5. Compositions and devices constructed therewith are capable of ameliorating liquid crystal drip spots that typically occur in a manufacturing process. In addition, the display devices using the composition do not require an additional alignment layer, which simplifies manufacturing.

On die termination device and semiconductor memory device including the same

Apparatus for generating power-up signal

An apparatus, included in a semiconductor memory device, for generating a power-up signal, including a first means for receiving a plurality of divided voltages and outputting a first control signal in response to a circumference temperature; and a signal generator for outputting the power-up signal in response to the first control signal.

Semiconductor memory device capable of controlling drivability of overdriver

A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair of the memory cell array block; a first driver for driving a power supply line of the bit line sense amplifier block to a voltage of a node connected with the first power supply in response to a driving control signal; a plurality of second drivers for driving the node to an overdriving voltage higher than the normal driving voltage; and an overdriving drivability controller for selectively activating the second drivers in response to a test-mode drivability control signal inputted during an activation period of an overdriving signal.

Voltage regulating circuit and method of regulating voltage

Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.

Liquid crystal display device and liquid crystal composition included therein

A liquid crystal display includes a first base substrate, a second base substrate facing the first base substrate, and an electrode unit disposed on at least one of the first base substrate and the second base substrate. A liquid crystal layer is positioned between the first base substrate and the second base substrate and includes a liquid crystal composition. The liquid crystal composition includes at least one of a liquid crystal compound represented by Chemical Formula 1, at least one of a liquid crystal compound represented by Chemical Formula 2-A, and at least one of a liquid crystal compound represented by Chemical Formula 2-B. The liquid crystal compound of Chemical Formula 2-A includes a cyclohexylene and a phenylene

Memory performing target refresh operation and memory system including the same

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

Semiconductor memory device having test mode for data access time

A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the data according to a CAS latency in synchronization with a clock signal at a normal mode or passing the data without synchronization with the clock signal at a test mode based on the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization with the clock signal at the test mode based on the output node control signal.

Display device

Provided is a display device. The display device includes a first base portion, a second base portion facing the first base portion, a light emitting layer disposed on one surface of the first base portion and emitting first light, a first wavelength conversion pattern disposed on the light emitting layer and converting the first light into second light having a different wavelength from the first light, a first color filter overlapping the first wavelength conversion pattern on one surface of the second base portion and spaced apart from the first wavelength conversion pattern, and an air layer interposed between the first wavelength conversion pattern and the first color filter.

Non-aqueous electrolyte and electrochemical device comprising same

The present disclosure relates to a nonaqueous electrolyte having improved stability. The nonaqueous electrolyte includes: a first solvent including a heterocyclic compound having at least one double bond or not, and containing at least one of oxygen and sulfur atoms; a second solvent including at least one of an ether-based compound, an ester-based compound, an amide-based compound and a carbonate-based compound; and a first lithium salt, wherein the first lithium salt includes lithium bis(nonafluorobutanesulfonyl)imide, and the lithium bis(nonafluorobutanesulfonyl)imide is present in an amount of 2-5 wt% based on 100 wt% of the total weight of the nonaqueous electrolyte.

Hardware automatic fastening apparatus

A hardware automatic fastening apparatus includes a magazine having a lever formed on an outer edge to store and supply hardware including any one or more types of a bolt, a nut, and a clip, a rotating part coupled to the magazine to rotate the magazine to position the hardware at a predetermined position, and a torque generating tool provided with an ascending and descending mechanism for ascending the hardware positioned by the rotating part upon ascending, and provided with a torque applying part for applying a torque to the ascended hardware, and the lever has a latch structure.

Display device

Provided is a display device. The display device includes a first base portion, a second base portion facing the first base portion, a light emitting layer disposed on one surface of the first base portion and emitting first light, a first wavelength conversion pattern disposed on the light emitting layer and converting the first light into second light having a different wavelength from the first light, a first color filter overlapping the first wavelength conversion pattern on one surface of the second base portion and spaced apart from the first wavelength conversion pattern, and an air layer interposed between the first wavelength conversion pattern and the first color filter.

Display apparatus

A display apparatus and a driving method thereof, in which the display apparatus includes a temperature sensor detecting a temperature, a first memory, a timing controller that receives an (n−1)th image signal and an nth image signal of consecutive frames, corrects the nth image signal and outputs the nth image signal, wherein the timing controller generates a clock signal whose phase varies according to the detected temperature, writes the nth image signal in the first memory in synchronization with the clock signal, reads the (n−1)th image signal from the first memory, and compares the nth image signal and the (n−1)th image signal with each other to then correct the nth image signal based on the comparison result, a data driver that provides an image-data voltage corresponding to the corrected signal of the nth image signal, and a liquid crystal panel that displays an image corresponding to the image-data voltage.

High voltage generator

High voltage generator

Simplified power-down mode control circuit utilizing active mode operation control signals

Color conversion substrate

A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.

Color conversion substrate and display device including the same

A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.

Liquid crystal display device and method of driving the same

A liquid crystal display device includes; gate lines disposed on a display region, data lines disposed on the display region, wherein the data lines intersect with, and are insulated from, the gate lines, a gate driver which drives the gate lines, a plurality of data drivers which generate a data voltage from an input power source voltage and supply the data voltage to the data lines, and a power source voltage supplying unit which supplies different power source voltages to each of the data drivers according to a distance of each data driver from the gate driver.

Color conversion panel and display device including same

Dynamic comparator with background offset calibration

Color conversion panel with improved light efficiency and display device including the same

A display device includes: a display panel; and a color conversion panel overlapping with the display panel. The color conversion panel includes: a substrate; a first color conversion pattern on the substrate; a second color conversion pattern on the substrate, and partially overlapping with the first color conversion pattern; a first reflective partition wall between the first color conversion pattern and the second color conversion pattern; a first color filter between the substrate and the first color conversion pattern; and a second color filter between the substrate and the second color conversion pattern.

車両部品組立システム及び組立方法

【課題】様々な車両部品を多種の車種に合わせて組み立てできる車両部品組立システム及び組立方法を提供する。【解決手段】本発明による車両部品組立システムは、積載された車両部品及び車両部品が組み立てられる車両の組立箇所を撮影する撮影部と、積載された車両部品をロードし、ロードされた車両部品を車両の組立箇所に移動させ、車両部品を組立箇所に組み立てる組立ロボットと、撮影部の車両部品画像を分析して、組立ロボットが積載された車両部品の同一箇所をロードするように組立ロボットを制御し、車両の組立箇所画像を分析して、組立ロボットが車両の組立箇所に正確に車両部品を組み立てるように制御する制御部と、を含む。【選択図】図１

System und Verfahren zur Montage einer Fahrzeugkomponente

System und Verfahren zur Montage einer Fahrzeugkomponente, wobei das System eine Bilderfassungseinheit (I), die konfiguriert ist, um ein Bild einer montierten Fahrzeugkomponente und ein Bild eines Montagepunktes an einem Fahrzeug, an welchem die Fahrzeugkomponente montiert ist, zu erfassen, einen Montageroboter (R), der konfiguriert ist, um die montierte Fahrzeugkomponente zu laden, die geladene Fahrzeugkomponente zu dem Montagepunkt an dem Fahrzeug zu bewegen und die Fahrzeugkomponente an dem Montagepunkt zu montieren, und eine Steuereinheit (C) aufweist, die konfiguriert ist, um das Bild der Fahrzeugkomponente, das von der Bilderfassungseinheit (I) erfasst wird, zu analysieren, den Montageroboter zu steuern, um zu ermöglichen, dass der Montageroboter die montierte Fahrzeugkomponente an demselben Punkt lädt, das Bild des Montagepunktes an dem Fahrzeug zu analysieren und den Montageroboter zu steuern, um zu ermöglichen, dass der Montageroboter die Fahrzeugkomponente genau an dem Montagepunkt des Fahrzeuges montiert.

System and method for assembling vehicle component

Disclosed are a method and system for assembling a vehicle component, the system including an image capturing unit configured to capture an image of a mounted vehicle component and an image of an assembly point on a vehicle to which the vehicle component is assembled, an assembly robot configured to load the mounted vehicle component, move the loaded vehicle component to the assembly point on the vehicle, and assemble the vehicle component to the assembly point, and a control unit configured to analyze the image of the vehicle component captured by the image capturing unit, control the assembly robot to allow the assembly robot to load the mounted vehicle component at the same point, analyze the image of the assembly point on the vehicle, and control the assembly robot to allow the assembly robot to assemble the vehicle component accurately to the assembly point of the vehicle.

Display device

Clock control circuit and data alignment circuit including the same

Medium composition for dermal papilla cell growth, containing rotenone and albumin as active ingredients

The present invention relates to a culture medium composition obtained by further adding at least one selected from the group consisting of rotenone and albumin to a serum-free medium prepared through a CAMPs technology. It has been ascertained that the proliferation of dermal papilla cells and maintenance of characteristics thereof during culturing can be improved by regulating the concentration of rotenone and albumin, and since the culture medium composition is a serum-free chemical medium comprising no serum, there is no risk of side effects, which can be caused by using a conventional serum medium, during use on the human body.The culture medium composition of the present invention obtained by further adding at least one selected from the group consisting of rotenone and albumin to a serum-free medium, or dermal papilla cells cultured through the composition can be effectively used in the development of therapeutic agents for hair loss prevention and hair growth promotion.

Color conversion panel and display device including same

A display device may include a display panel and a color conversion panel overlapping the display panel, and the color conversion panel may include a substrate, a first color conversion pattern disposed on the substrate, a second color conversion pattern disposed on the substrate and partially overlapping the first color conversion pattern, a first reflective partition wall disposed between the first color conversion pattern and the second color conversion pattern, a first color filter disposed between the substrate and the first color conversion pattern, and a second color filter disposed between the substrate and the second color conversion pattern.

Electrolyte for a lithium-sulfur battery and lithium-sulfur battery comprising the same

The present invention relates to an electrolyte for a lithium-sulfur battery and a lithium-sulfur battery comprising the same.

表示装置

【課題】ニュートラルブラック（Ｎｅｕｔｒａｌ ｂｌａｃｋ）の反射色を実現できる表示装置を提供する。 【解決手段】表示装置は、第１発光領域、第２発光領域、および第３発光領域が定義される第１基板と、前記第１基板と対向する各々の発光領域と重なる各々の透光領域、が定義され、前記第１基板に向かい合う第１面、および前記第１面の反対面である第２面を含む第２基板と、前記第２基板の前記第１面上に対応する各々のカラーフィルタと、前記各々のカラーフィルタ上に位置する各々の波長変換パターンと、を含み、前記第１基板の前記第２面側で照射されたＣ光源に対する反射光は、種々の波長に対応する第１光、第２光、第３光を含み、前記第１カラーフィルタの厚さは前記第２カラーフィルタの厚さより大きく、前記第２カラーフィルタの厚さは前記第３カラーフィルタの厚さより大きい。 【選択図】図１

Semiconductor memory device having test mode for data access time

Semiconductor device and semiconductor memory device

Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Delay locked loop circuit

Self refresh oscillator and oscillation signal generation method of the same

A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.

Medium composition for dermal papilla cell growth, containing rotenone and albumin as active ingredients

The present invention relates to a culture medium composition obtained by further adding at least one selected from the group consisting of rotenone and albumin to a serum-free medium prepared through a CAMPs technology. It has been ascertained that the proliferation of dermal papilla cells and maintenance of characteristics thereof during culturing can be improved by regulating the concentration of rotenone and albumin, and since the culture medium composition is a serum-free chemical medium comprising no serum, there is no risk of side effects, which can be caused by using a conventional serum medium, during use on the human body. The culture medium composition of the present invention obtained by further adding at least one selected from the group consisting of rotenone and albumin to a serum-free medium, or dermal papilla cells cultured through the composition can be effectively used in the development of therapeutic agents for hair loss prevention and hair growth promotion.

Gate protection circuit and display device including the same

Memory device performing write leveling operation

A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit.

Self refresh oscillator and oscillation signal generation method of the same

A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.

Delay locked loop circuit

Distributing on chip inductors for monolithic voltage regulation

Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.

Nonaqueous electrolyte and electrochemical device including the same

The present disclosure relates to a nonaqueous electrolyte having improved stability. The nonaqueous electrolyte includes: a first solvent including a heterocyclic compound having at least one double bond or not, and containing at least one of oxygen and sulfur atoms; a second solvent including at least one of an ether-based compound, an ester-based compound, an amide-based compound and a carbonate-based compound; and a first lithium salt, wherein the first lithium salt includes lithium bis(nonafluorobutanesulfonyl) imide, and the lithium bis(nonafluorobutanesulfonyl) imide is present in an amount of 2-5 wt % based on 100 wt % of the total weight of the nonaqueous electrolyte.

Smart card for performing biometric authentication and method of operating the same

A smart card includes a frequency measurement circuit configured to measure a first clock frequency of an external clock signal, a sensor clock output circuit configured to select a first range from a plurality of first clock ranges based on the first clock frequency and to output a sensor clock signal having a second clock frequency corresponding to the first range, and a sensor circuit configured to output sensing data for biometric authentication based on the sensor clock signal and first compensation image data.

Gate protection circuit and display device including the same

A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal.

Display apparatus and method of driving the same

A display apparatus includes a display panel which displays an image, a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area, a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area, a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal, and a correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data.

Semiconductor devices and semiconductor systems

A semiconductor system and semiconductor device may be provided. The semiconductor system may include a first semiconductor device configured to generate a test mode signal and configured to receive output data. The semiconductor system may include a second semiconductor device configured to enter a test mode, based on the test mode signal, and block the output data of data that is stored in redundancy memory cells connected to unrepaired redundancy word lines which are not used among redundancy word lines provided for replacing failed word lines.

Address storage circuit and memory and memory system including the same

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.