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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 5. Отображено 5.
02-05-2023 дата публикации

Deep learning processor core module based on Winograd

Номер: CN116048782A
Автор: WANG XIAOFENG, LU KUNFENG, ZHOU HUI, XIE YUJIA, ZHAO XIONGBO, GAI YIFAN, JIANG PENGLONG, LI XIAOMIN, LI CHAORAN, WU SONGLING, LIN PING, DONG WENJIE, MI HANGUANG, HUANG LI, WU MIN, ZHAO GUANJIE, LI JIE, LI YANGJUN, WANG SEN, YANG QINGJUN, JIN RUIXI, LIN YUYE, XU TIANYUN
Принадлежит:

The invention belongs to the technical field of artificial intelligence processors, and particularly relates to a Winograd-based deep learning processor core module, which comprises a control module for receiving an instruction transmitted by an external control unit and generating a control signal; the d-Buffer module caches external input characteristics, the d-Buffer module is connected with the control module, and the control module controls the action of the d-Buffer module in each clock period; and the PE array comprises n independent calculation units, each calculation unit is connected with the d-Buffer module, the calculation units calculate the convolution of each output channel, the PE array performs parallel calculation of the n output channels, and the control module controls the action of the PE array in each clock period. Through the Winograd fast convolution method, the problem that the performance of an FPGA-based deep learning processor is generally limited by the number ...

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Номер записи: 1
21-01-2015 дата публикации

Infrared image 9/7 wavelet transformation hardware acceleration circuit

Номер: CN104301740A
Автор: LIU LIANGLIANG, ZHAO XIONGBO, FAN RENHAO, WU SONGLING, YAN ZHIGANG, JIANG PENGLONG, GAO LEI, LI LEI
Принадлежит:

Provided is an infrared image 9/7 wavelet transformation hardware acceleration circuit. A data reading control module firstly reads pixel values of an original infrared image from an image RAM according to the preset sequence and starts a wavelet calculation circuit; the wavelet calculation circuit is started to read nine pixel values from the initial q position, and q is made to equal to the sum of q and 2 each time nine pixel values are read; the wavelet calculation circuit is started to read nine pixel values from the q position again till the pixel values are all read according to the current preset sequence; the wavelet calculation circuit reads the first nine pixel values to conduct wavelet transformation so as to obtain a wavelet transformation result; a data writing control module stores the wavelet transformation result into a temporary RAM according to the transposed position; the data reading control module reads pixel values from the temporary RAM according to the same sequence ...

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Номер записи: 2
19-02-2014 дата публикации

Dual-core PLC (programmable logic controller) system supporting instruction extension of functional blocks of ladder diagram

Номер: CN103593321A
Автор: LIU LIANGLIANG, JIANG PENGLONG, ZHAO XIONGBO, WU SONGLING, CHEN TAO, ZHANG MENG, CHENG RUI
Принадлежит:

Disclosed is a dual-core PLC (programmable logic controller) system supporting instruction extension of functional blocks of a ladder diagram. An instruction extension module, an input module, an instruction analysis module and an output module are arranged in a universal processor; a special ladder diagram processor transmits current instructions of the functional blocks of the ladder diagram to the universal processor and the instruction extension module; the instruction extension module receives the instructions of the functional blocks of the ladder diagram, extends the instructions of the functional blocks of the ladder diagram and transmits the extended instructions to the instruction analysis module; a user transmits the register address of shared data required for corresponding functions of functional block numbers in the instructions of the functional blocks of the ladder diagram and the initial address of shared data blocks to the instruction extension module by using the universal ...

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Номер записи: 3
24-06-2015 дата публикации

FPGA on-chip storage controller compatible with different bit widths and supporting non-aligned access

Номер: CN104731525A
Автор: ZHAO XIONGBO, LIU LIANGLIANG, FAN RENHAO, WU SONGLING, YAN ZHIGANG, JIANG PENGLONG, TIAN TIAN, MENG JING
Принадлежит:

The invention provides an FPGA on-chip storage controller compatible with different bit widths and supporting non-aligned access. The FPGA on-chip storage controller comprises a decoder and 2 storages. The storages independently store and read data, and the decoder conducts combined address coding and decoding control over the 2 storages. When the data are read or stored, the decoder decodes address signals with the bit width being N, low n bits of the address signals form 2 bit storage controller selection signals through the decoder, and the storage where a data start bit is located is selected from the 2 storages. High N-n bits of the address signals form 2 bit storage address bit selection signals through the decoder, the storage address bit of the data start bit in the storage which is selected before is determined, the data start bit is determined, and within a reading or storage period, 2*m bit data are read. The storage controller can remarkably improve storage ...

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Номер записи: 4
27-05-2015 дата публикации

Similarity measurement hardware accelerating method based on rapid normalized cross correlation method

Номер: CN104657553A
Автор: ZHAO XIONGBO, LIU LIANGLIANG, WU SONGLING, FAN RENHAO, YAN ZHIGANG, JIANG PENGLONG, TIAN TIAN, MENG JING
Принадлежит:

The invention provides a similarity measurement hardware accelerating method based on a rapid normalized cross correlation method. The similarity measurement hardware accelerating method comprises the following steps of firstly establishing a mathematic model of correlation coefficients between a real-time image and a template image; then performing a hardware algorithm design by use of a two-layer production line, and calculating the correlation coefficients between the real-time image selected by a search window and the template image; after all the correlation coefficients between the real-time image selected by the search window and the template image are calculated, and finding out the maximal value of the correlation coefficients and the horizontal coordinate and longitudinal coordinate of the top left corner of the corresponding search window in a real-time image coordinate system, wherein the selected region corresponding to the search window is a matched region. According to the ...

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Номер записи: 5