SYSTEMS AND METHODS FOR TRANSMITTING MESSAGES IN A CONTROLLER AREA NETWORK

An integrated circuit includes Controller Area Network (CAN) circuitry, and identifier (ID) filter circuitry coupled to the CAN circuitry and a CAN bus. The ID filter circuitry is configured to determine if a CAN message selected for transmission by the CAN circuitry should be blocked based on an ID of the selected CAN message. In response to determining that the selected message should not be blocked, the CAN circuitry broadcasts the selected message to all CAN nodes coupled to the CAN bus. In response to determining that the selected message should be blocked, the selected message is not transmitted to the CAN bus. 1. An integrated circuit (IC) , comprising:Controller Area Network (CAN) circuitry; andidentifier (ID) filter circuitry coupled to the CAN circuitry and a CAN bus, wherein the ID filter circuitry is configured to determine if a CAN message selected for transmission by the CAN circuitry should be blocked based on an ID of the selected CAN message, wherein, in response to determining that the selected message should not be blocked, the CAN circuitry broadcasting the selected message to all CAN nodes coupled to the CAN bus and in response to determining that the selected message should be blocked, not transmitting the selected message to the CAN bus.2. The IC of claim 1 , wherein the ID filter circuitry comprises an ID table wherein the ID filter circuitry is configured to use the ID table to determine if the CAN message selected for transmission by the CAN circuitry should be blocked.3. The IC of claim 2 , wherein the ID table comprises a plurality of entries claim 2 , wherein each entry is configured to store ID information indicating one or more message IDs that should be blocked and the message IDs indicate a type of information in the CAN message.4. The IC of claim 3 , wherein the identifier filter circuitry comprises comparison circuitry which compares the ID of the selected message to each entry of the ID table to determine if the CAN message ...

Error detector in a cache memory using configurable way redundancy

A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

METHOD AND SYSTEM FOR FAULT COLLECTION AND REACTION IN SYSTEM-ON-CHIP

A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

DEVICES AND METHODS FOR PREVENTING ERRORS AND DETECTING FAULTS WITHIN A MEMORY DEVICE

A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request. The concept can also be used with parity bits on columns of the memory cells and a column decoder that selects bit lines associated with column address lines.

Devices and methods for preventing errors and detecting faults within a memory device

A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request. The concept can also be used with parity bits on columns of the memory cells and a column decoder that selects bit lines associated with column address lines.

DATA PROCESSING SYSTEM HAVING DYNAMIC THREAD CONTROL

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region. 1. A method for managing thread execution in a processing system , the method comprising:setting a first watchpoint;generating a first watchpoint trigger corresponding to the first watchpoint; andin response to the first watchpoint trigger, controlling execution of a first thread in accordance with a value stored in a first control register.2. The method of claim 1 , further comprising generating a second watchpoint trigger corresponding to a second watchpoint claim 1 , and in response to the second watchpoint trigger claim 1 , resuming normal execution of the first thread.3. The method of claim 2 , wherein controlling the first thread further comprises disabling execution of the first thread claim 2 , the disabling execution of the first thread occurring between the first watchpoint trigger and the second watchpoint trigger.4. The method of claim 2 , wherein controlling the first thread further comprises throttling execution of the first thread between the first watchpoint trigger and the second watchpoint trigger.5. The method of claim 1 , further comprising setting a flag in the first control register claim 1 , the flag providing an indication to a second thread that execution of one or more threads is affected by the first watchpoint trigger.6. The method of claim 1 , wherein setting the first watchpoint further comprises setting the first watchpoint during execution of boot code.7. The method of claim 1 , wherein the first watchpoint is ...

System and method for soft error detection in memory devices

A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.

Comparator and clock signal generation circuit

A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.

Device and technique for transistor well biasing

A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Data processing system having dynamic thread control

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

Systems and methods for interrupt distribution

A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

Data processing system having lockstep operation

A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

INTERFACE SYSTEM AND METHOD WITH BACKWARD COMPATIBILITY

An interface including first and second transport protocol circuitry, a memory and a mode controller. The interface includes first and second physical interface types which are both selectively enabled to interface a set of pads. The first transport protocol circuitry is operative with the first type physical interface in a first mode and the second transport protocol circuitry is operative with the second type physical interface in a second mode. The memory stores a mode value indicative of the operating mode. The mode controller enables one of the physical interface types and a corresponding transport protocol based on the mode value. The first mode is the default mode, and the mode controller enables dynamic transition to the second mode. An escape indication may be enabled during the second mode for dynamic transition back to the first mode. Programmable timing values may be used to facilitate mode transitions. 1. An interface , comprising:a physical interface including a first type physical interface and a different second type physical interface which are both selectively enabled to interface a common set of pads;first transport protocol circuitry operative with said first type physical interface in a first operating mode;second transport protocol circuitry operative with said second type physical interface in a second operating mode;a memory which stores a mode value indicative of one of said first and second operating modes; anda mode controller which enables said first type physical interface to operate with said first transport protocol circuitry in said first operating mode upon power up or reset, and which dynamically transitions to said second operating mode by disabling said first type physical interface and enabling said second type physical interface to operate with said second transport protocol circuitry when said second operating mode is indicated by said mode value.2. The interface of claim 1 , wherein said mode controller dynamically transitions ...

Method and system for fault collection and reaction in system-on-chip

A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

Circuitry for checking operation of error correction code (ECC) circuitry

Error detection circuitry is configured to receive raw read data from a memory, perform error detection in accordance with a single-bit error correction and double-bit error detection (SECDEC) error-correction code (ECC) on the raw read data, and provide a single bit correction indicator in response to performing the SECDEC ECC on the raw read data. Error correction circuitry is configured to provide corrected read data corresponding to the raw read data based at least on the single bit correction indicator. ECC checking circuitry is configured to generate a wrong operation indicator based at least on a parity of the raw read data, a parity of the corrected read data, and the single bit correction indicator, wherein the ECC checking circuitry is configured to assert the wrong operation indicator when at least one of the error detection circuitry or the error correction circuitry is not operating correctly.

DEVICE AND TECHNIQUE FOR TRANSISTOR WELL BIASING

A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

COMPARATOR AND CLOCK SIGNAL GENERATION CIRCUIT

A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. 1. A comparator for comparing two input signals and generating an output signal based on the comparison of the input signals , the comparator comprising:a first input transistor arranged to be coupled to one of the input signals;a second input transistor arranged to be coupled to the other one of the input signals;first and second hysteresis transistors coupled between the first input transistor and an output stage of the comparator and between the second input transistor and the output stage of the comparator, respectively, and configured to apply hysteresis to the comparison of the input signals; andfirst and second hysteresis control transistors coupled between the first and second input transistors and the first and second hysteresis transistors, and operable to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal.2. The comparator of claim 1 , further comprising first and second control transistors for coupling the first and second hysteresis transistors in parallel with a first output stage transistor and a second output stage transistor respectively claim 1 , based on the hysteresis enable signal.3. A circuit for generating a clock signal claim 1 , comprising:a comparator for comparing two input signals and generating an output signal based on the comparison of the input signals, the comparator operable in a first mode or a second mode based on a hysteresis enable ...

Safe-stating a system interconnect within a data processing system

A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

SYSTEM AND METHOD FOR SOFT ERROR DETECTION IN MEMORY DEVICES

A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation. 1. A system for detecting a soft error in a memory device during a memory read/write operation , comprising:a latch having a clock input terminal for receiving a first clock signal and a data input terminal for receiving input data corresponding to the memory read/write operation, wherein the latch latches the input data at the beginning of the memory read/write operation in response to a rising edge of the first clock signal and generates a latch output;a master flip-flop having a clock input terminal for receiving a second clock signal and a data input terminal connected to the latch for receiving the latch output, wherein the master flip-flop continuously receives and stores the latch output during the memory read/write operation based on the second clock signal;a slave flip-flop having a clock input terminal for receiving the second clock signal and an input terminal connected to an output of the master flip-flop for receiving the latch output, wherein the slave flip-flop receives and stores the latch output at the end of memory read/write operation based on the second clock signal; anda comparator, having a first input that receives the input data and a second input connected to an output of the slave flip-flop for receiving the ...

SAFE-STATING A SYSTEM INTERCONNECT WITHIN A DATA PROCESSING SYSTEM

A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect. 1. A data processing system , comprising:a system interconnect;a first master; in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed, and', 'after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect., 'wherein the bridge circuit is configured to, 'a bridge circuit coupled between the first master and the system interconnect,'}2. The data processing system of claim 1 , wherein the bridge circuit is configured to complete the one or more outstanding issued write commands by providing dummy data to the system interconnect for each of the one or more outstanding write commands claim 1 , wherein the each dummy data includes a negated strobe signal.3. The data processing system of claim 1 , wherein a protocol of the system interconnect allows write data to be issued by the first master prior to issuing corresponding write commands for the issued write data ...

SYSTEMS AND METHODS FOR INTERRUPT DISTRIBUTION

A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators. 1. A data processing system configured to execute a plurality of threads , comprising:a plurality of domains, wherein the data processing system is configured to execute a plurality of software codes each having data portions that are isolated in a domain of the plurality of domains; an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request;', 'a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads, wherein the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread; and', 'a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the ...

Data processing system having lockstep operation

A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

Safe-stating a system interconnect within a data processing system

A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

Data processing system with tag-based queue management

An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

Data processing system having lockstep operation

Error detector in a cache memory using configurable way redundancy

A data processing system (10) includes a processor (12) having a multi-way cache (60) which has a first (64, 72) and a second (66, 74) way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory (18), where the processor (12), in response to a read address missing in the cache (60), provides the read address to the memory (18). The second way may be dynamically configured to be redundant to the first way during operation of the processor (12) in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache (60), data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

Data processing system with tag-based queue management

An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

在使用可組態方式多餘性之快取記憶體中誤差偵測

Error detector in a cache memory using configurable way redundancy

A data processing system (10) includes a processor (12) having a multi-way cache (60) which has a first (64, 72) and a second (66, 74) way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory (18), where the processor (12), in response to a read address missing in the cache (60), provides the read address to the memory (18). The second way may be dynamically configured to be redundant to the first way during operation of the processor (12) in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache (60), data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

Data processing system with tag-based queue management

An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.