Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels.

Fast arbitration scheme for a bus

A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes

Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.

Internal evict with external request

A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

Source controlled cache allocation

A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

System having interfaces and switch that separates coherent and packet traffic

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Coherent shared memory processing system

A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels. 1. A Network on Chip (NoC) , comprising:a plurality of channels;at least one receiving hardware element; and transmit a valid signal to the at least one receiving hardware element on a channel of the plurality of channels, and', 'transmit a virtual channel (VC) valid signal as a virtual channel indicator for a virtual channel of a plurality of virtual channels designated for transmission of data and transmit the data on the virtual channel designated for the transmission of the data;', 'wherein the at least one receiving hardware element is configured to transmit a VC credit to the at least one transmitting hardware element., 'at least one transmitting hardware element configured to2. The NoC of claim 1 , wherein the at least one transmitting hardware element is configured to not transmit the data packet on the virtual channel until a VC credit is obtained.3. The NoC of claim 1 , wherein the plurality of channels comprises one or more VCs claim 1 , each of the plurality of channels being configurable to be independently controlled for mapping to an interface virtual VCs.4. The NoC of claim 1 , further comprising a virtual interface connected to the NoC for virtual channels to interact with agents of a System on Chip (SoC).5. The NoC of claim 4 , wherein the virtual interface comprises a read channel.6. The NoC of claim 1 , wherein the at least one transmitting element is further configured to:manage VC credits received from one or more of the at least one receiving hardware element; andconduct arbitration based on whether a message destination is associated with a VC ...

System having interfaces, switch, and memory bridge for CC-NUMA operation

A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Bus sampling on one edge of a clock signal and driving on another edge

An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive ...

Page crossing prefetches

Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.

Remote line directory which covers subset of shareable CC-NUMA memory space

A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

System having interfaces, switch, and memory bridge for CC-NUMA operation

A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Addressing scheme supporting variable local addressing and variable global addressing

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Transparent data format within host device supporting differing transaction types

A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager. Each transaction cell has a control tag and data and carrying all or a portion of a packet data transaction or an input/output transaction.

Distributed copies of configuration information using token ring

A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various agents in the data processing system. The interface agent are not required to have target/response logic to respond to internal and external configuration accesses. In and embodiment of the present invention, a node controller, which may comprise a configuration block, is operably connected to a system interconnect bus and a switch. A plurality of interface agents are connected to the switch, with each of the interface agents comprising a configuration space register, a configuration space shadow register and a control and status register (CSR). A token ring connected to the node controller is operable to transmit data from the node controller to a plurality of interface agents connected to the token ring, thereby providing a system ...

Hierarchical asymmetric mesh with virtual routers

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.

System and method for ensuring coherency in trace execution

A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.

System having interfaces and switch that separates coherent and packet traffic

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Hierarchical asymmetric mesh with virtual routers

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.

Interface virtualization and fast path for network on chip

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

System and method for conserving power

A system includes a plurality of processors and a monitor coupled to each of the plurality of processors. The monitor is located in a location separate from the plurality of processors. At least some portions of one or more of the plurality of processors enter a power-conservation mode after the one or more of the plurality of processors request one or more resources. The system further includes a power-management controller. The power-management controller is operative to cause the at least some portions of the one or more of the plurality of processors to enter the power-conservation mode after the one or more of the plurality of processors request the one or more resources.

Command to transfer data from node state agent to memory bridge

A node comprises a first agent, a second agent, and a third agent, all coupled to an interconnect. The first agent is configured to initiate a transaction on the interconnect to transfer a coherency block to the second agent. The third agent is configured to transmit the coherency block on the interconnect during a data portion of the transaction instead of the first agent responsive to a state of the coherency block in the third agent. In some embodiments, the first agent may be designated to store the node state of a remote cache block, and the second agent may be responsible for internode coherency within the node.

System having address-based intranode coherency and data-based internode coherency

A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is transferred responsive to transmission of the address on the interconnect. The system further includes a second interconnect to which the plurality of nodes are coupled, wherein ownership of a coherency block is transferred on the second interconnect responsive to a transmission of the data comprising the coherency block on the second interconnect. A first node of the plurality of nodes issues a coherency command on the second interconnect to fetch the coherency block in response to the transaction on the interconnect within the first node, whereby ownership transfers within the first node prior to ownership transferring from another one of the plurality of nodes to the first node.

Load-linked/store conditional mechanism in a CC-NUMA system

A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.

Cache programmable to partition ways to agents and/or local/remote blocks

A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.

Programmably disabling one or more cache entries

A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

System having interfaces and switch that separates coherent and packet traffic

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.

Virtual core management

A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.

Independent reset of arbiters and agents to allow for delayed agent reset

A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

System on a chip for networking

A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Enhanced page locality in network-on-chip (NoC) architectures

Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.

L2 Cache maintaining local ownership of remote coherency blocks

A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first node is configured to fetch the coherency block from another node. The other node is configured to record a state in which the coherency block is provided to the first node. The first cache is designated to store the state of the coherency block recorded by the first node.

Interface virtualization and fast path for Network on Chip

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Systems using Mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Hypertransport exception detection and processing

In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.

Bus precharge during a phase of a clock signal to eliminate idle clock cycle

A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Direct access mode for a cache

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data. In one embodiment, the cache may alter the state of its ...

Source controlled cache allocation

A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Multiple clock domains in NoC

Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.

Tagging and synchronization for fairness in NOC interconnects

Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication.

Scalable cache coherent distributed shared memory processing system

A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in distributed shared memory systems. The I/O link protocol is adapted to include additional virtual channels that can carry command packets for coherency transactions over the link in a format that is acceptable to the I/O protocol. The coherency transactions support cache coherency between processing nodes interconnected by the link. Each processing node may include processing resources that themselves share memory, such as symmetrical multiprocessor configuration. In this case, coherency will have to be maintained both at the intranode level as well as the internode level. A remote line directory is maintained by each processing node so that it can track the state and location of all of the lines from its local memory that have been provided to other remote nodes. A node controller initiates transactions over the link in response to ...

Bus precharge during a phase of a clock signal to eliminate idle clock cycle

A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

Data pend mechanism

A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.

SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AND RELIABILITY

Methods and example implementations described herein are directed to systems and methods for maintaining network-on-chip (NoC) safety and reliability. An aspect of the present disclosure relates to an network-on-chip (NoC)-based error correction system capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element. The system includes an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers), and a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data. In an aspect, the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure. 1. An network-on-chip (NoC)-based error correction system capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element , the system comprising:an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers);a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data, wherein the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure.2. The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises a transport error detection and correction mechanism.3. The NoC-based error correction system of claim 1 , wherein the error correction circuit comprises an end to end transport error ...

Bridges performing remote reads and writes as uncacheable coherent

A system and method for improving the bandwidth for data read and write operations in a multi-node system by using uncacheable read and write commands to a home node in the multi-node system so that the home node can determine whether the commands needs to enter the coherent memory space. In one embodiment where nodes are connected via HT interfaces, posted commands are used to transmit uncacheable write commands over the HT fabric to a remote home node so that no response is required from the home node. When both cacheable and uncacheable memory operations are mixed in a multi-node system, a producer-consumer software model may be used to require that the data and flag must be co-located in the home node's memory and that the producer write both the data and flag using regular HT I/O commands. In one embodiment, a system for managing data in multiple data processing devices using common data paths comprises a first data processing system comprising a memory, wherein the memory comprises ...

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Internal evict with external request

A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

Random generator

A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A detector circuit detects whether or not the value from the primary circuit is within the desired output range for the random number generator circuit, and selects either the value from the primary circuit or the value from the secondary circuit in response. The second range is the desired output range and the first range encompasses the second range. In one embodiment, the primary circuit has complex harmonics but may generate values outside the desired range. The secondary circuit may have less complex harmonics, but may generate values only within the desired range. In one implementation, the random number generator circuit is used to generate a replacement way for a cache.

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

Internal evict with external request

A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

Ambiguous virtual channels

An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

PAGE CROSSING PREFETCHES

Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests. 1. A system comprising:a plurality of caches; anda prefetcher configured to prefetch cache lines from a first physical memory page into a first cache of the plurality of caches, wherein the cache lines prefetched into the first cache are selected using a prediction determined from a pattern of operations associated with the first cache and also using a first prefetch distance, wherein cache lines in a second physical memory page are selected for prefetching using the pattern and a second prefetch distance that is based on the first prefetch distance.2. The system of wherein the first prefetch distance corresponds to a confidence level associated with the pattern claim 1 , the confidence level comprising a value that increases as the pattern increases in length.3. The system of wherein the confidence level is used with the first prefetch distance to establish the second prefetch distance.4. The system of wherein the prefetcher is further configured to observe the operations and detect the pattern.5. The system of wherein the operations are selected from the group consisting of: cache misses in the cache; and fetches of cache lines to the cache.6. The system of wherein prefetching from the second physical memory page is suspended when the first prefetch distance reaches the end of the first physical memory page until a confirming access request to the second physical memory page is made.7. The system of wherein the prefetcher is further configured to predict a ...

Random generator

A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A detector circuit detects whether or not the value from the primary circuit is within the desired output range for the random number generator circuit, and selects either the value from the primary circuit or the value from the secondary circuit in response. The second range is the desired output range and the first range encompasses the second range. In one embodiment, the primary circuit has complex harmonics but may generate values outside the desired range. The secondary circuit may have less complex harmonics, but may generate values only within the desired range. In one implementation, the random number generator circuit is used to generate a replacement way for a cache.

Deterministic setting of replacement policy in a cache

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Thus, a direct access transaction may be used to provide a deterministic setting to the replacement policy, providing predictability to the entry selected to store a subsequent cache miss. In one embodiment, the replacement policy may be a pseudo-random replacement policy. In one embodiment, a direct access transaction also explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read ...

READ EXCLUSIVE FOR FAST, SIMPLE INVALIDATE

An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.

Method and system for promoting traces in an instruction processing circuit

A method and system for promoting traces in an instruction processing circuit is disclosed. The method and system comprises determining if a current trace is promotable; and adding the current trace to a sequence buffer if the current trace is promotable. The current trace is marked as promoted and the current trace is marked as a first trace of a multi-block trace. The method and system includes determining if a next trace is promotable; adding the next trace to the sequence buffer if the next trace is promotable; and repeating the above until the next trace is not promotable and then adding the next trace to the sequence buffer if the next trace is not promotable.

Addressing scheme supporting variable local addressing and variable global addressing

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

System on a chip for networking

A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Bandwidth weighting mechanism based network-on-chip (NoC) configuration

The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.

Ambiguous virtual channels

An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Read exclusive for fast, simple invalidate

An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.

Addressing scheme supporting fixed local addressing and variable global addressing

A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Promoting and appending traces in an instruction processing circuit based upon a bias value

A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.

CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC CONGESTION

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem. 1. A method , comprising:assigning one or more traffic flows to a plurality of Network on Chip (NoC) layers in an NoC system, based on a load balancing configuration.2. The method of claim 1 , wherein the load balancing configuration comprises a computation of load balancing routes for the traffic flows assigned to each of the plurality of NoC layers.3. The method of claim 1 , further comprising determining a width for at least one channel in at least one of the plurality of NoC layers claim 1 , based on the assigned one or more traffic flows and at least one of a packet size claim 1 , a bandwidth requirement claim 1 , and a channel width constraint.4. The method of claim 1 , further comprising:determining satisfaction of interconnect bandwidth requirements of the NoC system; andallocating additional ones of the NoC layers to the NoC system based on the determined satisfaction of the interconnect bandwidth requirements.5. The method of claim 1 , further comprising providing additional virtual channels to the NoC system by allocating additional NoC layers based on a satisfaction of at least one of deadlock avoidance and a provision of system traffic isolation.6. The method of claim 1 , further comprising providing additional ...

Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit

An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.

System and Method For the Transfer of color and Other Physical Properties to Laminate Composite Materials and Other Articles

A method of transferring a dye to a composite material comprising applying the dye to a transfer media to create a colored transfer media, placing the colored transfer media into contact with the composite material, and applying, using an autoclave, at least one of heat, external pressure, vacuum pressure to infuse the dye to the composite material to create a colored composite material. 1. A method of transferring a dye to a composite material , the method comprising:applying the dye to a transfer media to create a colored transfer media;placing the colored transfer media into contact with the composite material; andapplying, using an autoclave, at least one of heat, external pressure, vacuum pressure to infuse the dye to the composite material to create a colored composite material.2. The method of claim 1 , wherein the transfer media is at least one of transfer paper claim 1 , transfer laminate claim 1 , or transfer film.3. The method of claim 1 , wherein the dye may be applied to the transfer media in the shape of a pattern claim 1 , graphic or logo claim 1 , and wherein the colored composite material is infused with a matching pattern claim 1 , graphic or logo claim 1 , respectively.4. The method of claim 1 , wherein the dye is applied to the transfer media using direct printing. This application is a non-provisional of U.S. Patent Application No. 61/370,448, filed Aug. 3, 2010, and entitled “SYSTEM AND METHOD FOR COLOR TRANSFER TO LAMINATE COMPOSITE MATERIALS AND OTHER ARTICLES”, which is hereby incorporated by reference.In a typical prior art embodiment, laminated reinforced materials are plain in color and not conducive to being dyed or colored. One known technique for adding color to laminated material is to paint the material. However, painting the material has the downside of the paint flaking off through use and fading in sunlight over time. These drawbacks can be very pronounced in flexible laminate material. In another prior art embodiment, laminated ...

IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FOR EVALUATING POTENTIAL PROTOCOL LEVEL DEADLOCKS

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels. 1. A method , comprising: 'manipulating one or more of the multiple interface channels and determining the internal dependency specification based on changes to the one or more of the remaining ones of the multiple interface channels.', 'determining an internal dependency specification of a component in a Network on Chip (NoC), the component having multiple interface channels comprising multiple input interface channels and multiple output interface channels, the determining the internal dependency specification comprising2. The method of claim 1 , wherein the manipulating the one or more of the multiple interface channels comprises blocking the one or more of the multiple interface channels.3. The method of claim 1 , wherein the determining the internal dependency specification based on the changes on the one or more of the multiple interface channels is based on identification of at least one of backpressure and traffic flow variation of the remaining ones of the multiple interface channels.4. The method of claim 3 , further comprising:mapping a dependency of the one or more of ...

HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers. 1. A method , comprising:constructing a plurality of clusters, each of the clusters comprising a single router;for at least one of the plurality of clusters, connecting one or more cores to the single router of the at least one of the plurality of clusters, wherein a number of the one or more cores is based on a radix of the single router; andconnecting said single router of a first one of the plurality of clusters to said single router of a second one of the plurality of clusters.2. The method of claim 1 , further comprising configuring each of the single routers of the plurality of clusters not having any cores with a plurality of directional ports to connect to the single routers of the plurality of clusters.3. The method of claim 1 , wherein the connecting said single router of the first one of the plurality of clusters to said single router of the second one of the plurality of clusters comprises configuring said single router of the first one of the plurality of clusters with at least one directional port.4. The method of claim 3 , wherein the configuring said single router of the first one of the plurality of clusters with at least one directional port is based on a hierarchy of the one or more ...

HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers. 1. A method , comprising:for a network on chip (NOC) configuration comprising a plurality of cores interconnected by a plurality of routers in a mesh arrangement, generating a plurality of virtual routers configured to connect ones of the plurality of routers having one or more unused ports; andconfiguring each of the plurality of virtual routers to connect to an unused port of a router from the ones of the plurality of routers having the one or more unused ports.2. The method of claim 1 , wherein a host is connected to one of the plurality of virtual routers connected to a previously unused port of one of the plurality of routers.3. The method of claim 1 , further comprising configuring each of the plurality of virtual routers with at least one of a register and a flow control logic between a host port and a router port of the each of the plurality of the virtual routers claim 1 , and a pass through logic facilitating a direct connection between the host port and the router port of the each of the plurality of the virtual routers.4. The method of claim 1 , further comprising routing a message through the NOC configuration by using multi-turn based routing in the mesh arrangement.5. The method of claim ...

TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS

Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication. 1. A method , comprising:associating a tag with one or more packets of at least one input channel of a network on chip (NoC), the tag comprising information for one or more arbitration decisions;reading the information of the tag; andconducting an arbitration of the one or more packets for an output channel based on the reading of the information.2. The method of claim 1 , wherein the reading and conducting is performed by a router of the NoC.3. The method of claim 1 , wherein the information for one or more arbitration decisions is an indication of one of a normal packet and a barrier packet claim 1 , and wherein the conducting the arbitration comprises setting the output channel to one of a normal phase and a barrier phase.4. The method of claim 3 , further comprising changing the setting of the output channel based on the tag of subsequently received ones of the one or more packets of the at least one input channel.5. The method of claim 1 , wherein the associating the tag with the one or more packets of the NoC interconnect is based on one or more fairness requirements.6. The method of claim 1 , wherein the associating the tag with the one or more packets of the NoC interconnect is based on an assignment of a weight.7. The method of claim 1 , wherein the associating the tag is conducted when the one or ...

AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT BY CAPTURING INTERNAL DEPENDENCIES OF IP CORES USING HIGH LEVEL SPECIFICATION

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. 1. A method , comprising:capturing one or more dependencies present in a first core based on a processing of a high level specification of the first core.2. The method of claim 1 , wherein the high level specification comprises:dependency information between one or more messages received and transmitted by one or more channels of the first core, wherein the processing of the high level specification comprises converting the dependency information into channel dependencies.3. The method of claim 2 , further comprising:identifying a usability of the first core in a Network on Chip (NoC) system based on the dependency information, anddetermining a placement in the NoC system based on the usability of the first core in the NoC system.4. The method of claim 3 , wherein the identifying comprises determining inter-operability between the first core and at least one core of the NoC system claim 3 , based on the dependency information and a traffic profile of the NoC system.5. The method of claim 3 , further comprising generating an interconnect for the NoC system that is substantially ...

QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS AND USING WEIGHTED ARBITRATION AT NOC NODES

Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations. 1. A method , comprising:computing weights for one or more channels of a Network on Chip (NoC) based on a bandwidth requirement for each of the one or more channels.2. The method of claim 1 , further comprising:assigning the computed weights to the one or more channels of the NoC; andconducting weighted arbitration at nodes of the NoC.3. The method of claim 2 , further comprising:dynamically adjusting at least one of the computed weights assigned to the one or more channels of the NoC, based on flows of the one or more channels.4. The method of claim 3 , wherein the dynamically adjusting the computed weights comprises claim 3 ,monitoring the flows of the one or more channels and determining an activity level of each of the flows over a number of cycles.5. The method of claim 3 , wherein the conducting weighted arbitration at the nodes of the NoC is based on the dynamically adjusted computed weights.6. The method of claim 3 , further comprising:determining at least one of the computed weights to be static and not dynamically adjustable.7. The method of claim 1 , wherein the NoC comprises one of a heterogeneous 2-D mesh claim 1 , heterogeneous 2.5-D mesh claim 1 , heterogeneous 3-D mesh claim 1 , Taurus NoC interconnect and ring NoC ...

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels. 1. A hardware element incorporated into a Network on Chip (NoC) , comprising:a plurality of physical links and virtual links;a queue for transmission of output messages to output ports of the hardware element;an arbiter configured to process input messages to the queue based on a logic scheme;a configurable bypass link between the virtual links, andbypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter.2. The hardware element of claim 1 , wherein the bypass logic is configured to redirect the input messages to the configurable bypass link opportunistically.3. A hardware element incorporated into a System on Chip (SoC) claim 1 , comprising:a plurality of physical links and virtual links;a queue for transmission of output messages to output ports of the hardware element;an arbiter configured to process input messages to the queue based on a logic scheme;a configurable bypass link between the virtual links, andbypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter.4. The hardware element of claim 3 , wherein the bypass logic is configured to redirect the input messages to the configurable bypass link opportunistically. This regular U.S. patent application is a continuation of U.S. patent application Ser. No. 15/829,749, filed on Dec. 1, 2017 which is based on and claims the benefit of priority under 35 U.S.C. 119 from provisional U.S. patent application No. 62/429,695, filed on Dec. 2, 2016, the entire disclosure of which is incorporated by ...

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels. 1. A hardware element incorporated into a Network on Chip (NoC) , comprising:a plurality of physical links and virtual links;a queue for transmission of output messages to output ports of the hardware element;an arbiter configured to process input messages from input ports to the queue based on alogic scheme;bypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter; anda plurality of configurable bypass links bypassing the queue and the arbiter, the plurality of configurable bypass links providing a pathway from the bypass logic to the output ports through the physical links.2. The hardware element of claim 1 , wherein ones of the physical links have different sizes than other ones of the physical links claim 1 , wherein the plurality of configurable bypasses are incorporated on the virtual links within the physical links such that output ones of the virtual links are a same size as input ones of the virtual links.3. The hardware element of claim 1 , wherein the hardware element is a configurable router.4. A hardware element incorporated into a System on Chip (NoC) claim 1 , comprising:a plurality of physical links and virtual links;a queue for transmission of output messages to output ports of the hardware element;an arbiter configured to process input messages from input ports to the queue based on a logic scheme;bypass logic configured to redirect the input messages to the configurable bypass link to bypass the queue and the arbiter; anda plurality of configurable bypass links bypassing the queue and the ...

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels. 1. A method for a Network on Chip (NoC) comprising a plurality of channels , at least one receiving hardware element; and at least one transmitting hardware element , the method comprising:transmitting a valid signal to the at least one receiving hardware element on a channel of the plurality of channels,transmitting a virtual channel (VC) valid signal as a virtual channel indicator for a virtual channel of a plurality of virtual channels designated for transmission of data and transmit the data on the virtual channel designated for the transmission of the data; andtransmitting a VC credit to the at least one transmitting hardware element.2. The method of claim 1 , further comprising not transmitting the data packet on the virtual channel until a VC credit is obtained.3. The method of claim 1 , wherein the plurality of channels comprises one or more virtual channels (VCs) claim 1 , each of the plurality of channels being configurable to be independently controlled for mapping to an interface virtual VCs.4. The method of claim 1 , further comprising:managing virtual channel (VC) credits received from one or more of the at least one receiving hardware element; andconducting arbitration based on whether a message destination is associated with a VC credit from the managed VC credits.5. The method of claim 1 , further comprising:arbitrating messages for transmitting through prioritizing messages that are associated with a VC credit.6. The method of claim 1 , further comprising:providing a reservation for a virtual channel (VC) to one or more of the at least one transmitting ...

Enhanced page locality in network-on-chip (noc) architectures

Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.

BANDWIDTH WEIGHTING MECHANISM BASED NETWORK-ON-CHIP (NOC) CONFIGURATION

The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state. 1. A method for packet routing in a circuit architecture , said method comprising:managing, at a router of the circuit architecture, one or more catch-up bits, said each of the one or more catch-up bits indicating that said router has reset a round of round-robin based packet routing without allowing an agent corresponding to said each of the one or more catch-up bits to complete its respective round;allowing, by said router, said agent to continue its respective round in catch-up state such that upon completion of said respective round, said agent is switched to normal state.2. The method of claim 1 , wherein when an output port of said respective router receives an end-of-round signal from a second agent claim 1 , a first set of agents that are in end-of-round state return to said normal state claim 1 , and a second set of agent that are in normal state are switched to catch-up state.3. The method of claim 1 , wherein arbiter of said respective router allocates highest priority to agents that form part of the catch-up state.4. The method of claim 1 , wherein each output port of said respective router is configured as a 2-bit state machine.5. The method of claim 1 , wherein when said router transmits an end-of round ...

Panel attachment system and a method of using the same

A panel attachment system comprises a panel and a casing. The panel has one fixed mount bracket, and at least one sliding mount bracket. The casing has one fixed mount boss, and at least one sliding mount boss. When the panel attachment system is in use, the fixed mount bracket is fixedly secured to the fixed mount boss, and the or each sliding mount bracket is slidingly engaged with a corresponding respective one of the or each sliding mount boss. This enables the panel to be detachably connected to the casing, such that any relative in-plane thermal expansion between the panel and the casing is accommodated by corresponding relative movement between the one or more sliding mount brackets and the corresponding one or more sliding mount bosses.

MULTIPLE CLOCK DOMAINS IN NOC

Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning. 1. A Network on Chip (NoC) comprising:a plurality of routers; anda plurality of interconnects;wherein each of the plurality of routers and each of the plurality of interconnects are associated with one or more of a plurality of sections;wherein the plurality of sections operate at clock domains such that at least one of the plurality of sections operates at a different clock domain from another one of the plurality of sections.2. The NoC of claim 1 , wherein ones of the plurality of routers and ones of the plurality of interconnects are configured to operate at multiple clock domains and to facilitate clock domain crossing of communications.3. The NoC of claim 1 , wherein each of the plurality of routers includes a clock architecture comprising an independent core clock and an independent clock for each input port of the each of the plurality of routers.4. The NoC of claim 3 , wherein the clock domain of the independent core clock operates in a synchronous claim 3 , ratio-synchronous claim 3 , mesochronous or asynchronous relationship with at least one of the clock domains of the independent clock for each input port.5. The NoC of claim 3 , wherein ones of the plurality of routers are configured to facilitate clock domain crossing of communications at each input port claim 3 , from a clock domain of each input port to a clock domain of the independent core clock.6. The NoC of claim 1 , wherein each router of the plurality of routers is configured to synchronize incoming data at an ...

Method for testing compressive strength

1,244,490. Cartridge actuated fastenerdriving tools. F. W. ALLEN, Jnr., R. J. KOPF, and R. W. THOMPSON. 4 Sept., 1968 [21 Sept., 1967], No. 42131/68. Heading B4C. [Also in Divisions F3 and G1] Three steel probes such as 30, Fig. 1, may be fired into concrete 32 through three upstanding bosses 33, Fig. 3, in a hardened steel template 31. The housing 10 must be telescoped downwardly over the boss it is engaged with in order that the barrel 11 may be depressed sufficiently to slide a breech block 12 and a cocking rod 19 upwardly, and when this is done the rod engages a depressible pawl 18 extending outwardly from a firing pin 15 and moves the pin back against a spring 16 to the Fig. 1 ready for firing position. A trigger 20 pivoted at 21 may be pulled to push the pawl 18 inwardly and release the firing pin which explodes the powder in the cartridge 22 and fires the probe 30. The opening 34 through which the probe nose passes will not allow the enlarged rear end of the probe to pass through so that the probe cannot go into free flight if the material 32 is very soft.

System having interfaces and switch that separates coherent and packet traffic

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Method and probe for testing the compressive strength of concrete or the like.

Smoking pipe

Concurrent vs. low power branch prediction

An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.

Bus sampling on one edge of a clock signal and driving on another edge

An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge. The sampled signals may be evaluated to determine an arbitration winner, which may drive the bus responsive to the next occurrence of the first edge.

Transfer of color and other physical properties to laminates

A method of transferring a dye to a composite material comprising applying the dye to a transfer media to create a colored transfer media, placing the colored transfer media into contact with the composite material, and applying, using an autoclave, at least one of heat, external pressure, vacuum pressure to infuse the dye to the composite material to create a colored composite material.

Transfer of color and other physical properties to laminates

A method of transferring a dye to a composite material comprising applying the dye to a transfer media to create a colored transfer media, placing the colored transfer media into contact with the composite material, and applying, using an autoclave, at least one of heat, external pressure, vacuum pressure to infuse the dye to the composite material to create a colored composite material.

Data pend mechanism

A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.

Flag optimization of a trace

A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.

Improvements in or relating to Curtain Attachment Means

1,162,201. Suspending curtains. SELECTUS Ltd. 5 Jan., 1967 [11 Jan., 1966], No. 1150/66. Addition to 1,040,144. Heading A4B. Curtain attachment means according to the parent patent is modified by supporting a hooked pile fabric (1) by direct engagement with a runner (4) thereby dispensing with an intermediate suspension hook. 1,162,204. Brackets. HORNE BROS Ltd. 6 April, 1967 [6 April, 1966], No. 15453/66. Heading A4B. A support for a bracket 21 or 22 comprises in combination a channel section upright 1 with inturned flanges 2 supporting outwardly directed flanges 4, grooves 5 to receive panels (10) being defined between adjacent flanges 2 and 4 and a longitudinal gap 3 being defined between opposed flanges 2, a pair of channel section attachment members 11 with limbs 12 embracing the flanges 2, 4, the members 11 being separately inserted in the gap 3 and slid into side-by-side relationship, and screws 14 for anchoring to bracket 21 or 22 and members 11 to the upright 1. Each screw 14 engages a threaded bore 13 formed half in each attachment member 11 to effect a clamping by forcing the members 11 apart, the end of the screw 14 finally engaging the rear wall 17 of the upright 1. A capping plate 18 may be fitted over the members 11 to limit their movement apart. A plastics strip 27 may be fitted in the base of the upright 1 to conceal wall mounting screws. The screws 14 may anchor a shelf bracket 21. Alternatively a fitting to be supported may have bores to receive a pair of oppositely directed prongs 24 carried by a pair of plates 22 secured one to each of two pairs of attachment members 11.

Random number generator

Network circuit

A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Loom for weaving

Hypertransport exception detection and processing

In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.

Internal evict with external request

A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

Programmably disabling one or more cache entries

A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Trace unit with a trace builder

An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.

System having interfaces and a switch that separates coherent and non-cohrent data packet traffic

Eyeshield

Golf-club holder for use with golf carts

Golf-club holder which supplements a normal golf bag and is particularly adapted for use with golf carts. The holder comprises an elongated rigid body which terminates as a spike at one end which is driven into the ground when using the holder. Golf-club retaining means are affixed to the body and spaced from the spike so that the clubs can be retained proximate the upper ends thereof. The retaining means each have a short flexible member affixed at one end to the body and a ring-like retaining member is affixed to the other end. The ring-like member fits over the top of the club to retain same. When the holder is not in use it can readily be stored in the golf bag since it occupies only a small lateral space. In use, the golfer carries the holder and several clubs from the cart to a location remote from the cart where the clubs not used for the shot are retained by the holder. This keeps the clubs clean and dry and prevents clubs from being inadvertently left on the course.

Cache programmable to partition ways to agents and/or local/remote blocks

A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.

Production and treatment of textile fabrics

Memory ordering queue tightly coupled with a versioning cache circuit

An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.

Re-fetching cache memory having coherent re-fetching

A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from some or all of the archive, and the data portion is re-fetched according to the repopulated tag portion. The re-fetching is optionally performed in a cache coherent fashion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Programmably disabling one or more cache entries

A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Network circuit

System including a bus precharging circuit

Processor core subsystem with open-standard network-on-chip ports

Embodiments of apparatuses, methods, and machine-readable mediums for a subsystem with open-standard network-on-chip ports are disclosed. In an embodiment, a machine-readable medium includes a design of an apparatus to be manufactured, the apparatus to include one or more cores, and a network-on-chip having at least one port of a first type and at least one port of a second type. The first type is to communicate with the one or more cores according to a proprietary protocol. The second type is to communicate with an intellectual property block according to an open-standard protocol.

Fernverzeichnis, welches eine Untermenge eines gemeinsamen cc-numa (cache-coherent nonuniform memory access) Speicherraums überdeckt

Fernverzeichnis, welches eine untermenge eines gemeinsamen cc-numa (cache-coherent nonuniform memory access) speicherraums überdeckt

Fernverzeichnis, welches eine Untermenge eines gemeinsamen cc-numa (cache-coherent nonuniform memory access) Speicherraums überdeckt

Textile material manufacture

System mit Busvorladeschaltung

System mit Busvorladeschaltung

Textile material

System mit schnittstellen, einem schalter und einer speicherbrücke mit cc-numa (cache-coherent non-uniform memory access)

Composite yarn

Quellen-aktivierte Transaktionssperrung

Improvements in or relating to process of epoxidizing esters

Textile machinery

System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr

Fastener and attachment for piston-type fastening tool

Fastener and attachment for piston-type fastening tool

Level 2 cache mit lokaler beibehaltung von kohärenzblöcken

Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren

System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz

Synthetic phase isolator

Elastic fabric

Source triggered transaction blocking

A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

Improvements in or relating to process of epoxidizing esters

Improved process forthe production of wool felt capelines, andthe product thereof

Method for testing compressive strength

System mit adressbasierter Intraknotenkohärenz und datenbasierter Interknotenkohärenz

Seitenübergreifende Vorabholung

Eine Vorabholung darf von einer physikalischen Speicherseite zu einer weiteren weitergehen. Insbesondere wenn ein Strom aus Zugriffsanforderungen virtuelle Adressen enthält, die mehr als einer physikalischen Speicherseite zugeordnet sind, dann kann die Vorabholung von einer ersten physikalischen Speicherseite in eine zweite physikalische Speicherseite fortgesetzt werden. Die Vorabholung wird vorteilhafterweise zu der zweiten physikalischen Speicherseite auf der Grundlage des Konfidenzpegels und des Vorabholungsabstands fortgesetzt, die erstellt werden, während die erste physikalische Speicherseite das Ziel der Zugriffsanforderungen war.

Street sweeper hopper dump mechanism

Street sweeper hopper dump mechanism

Synthetic phase isolator

Eye shield

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

Improved process forthe production of wool felt capelines, andthe product thereof

Method for testing compressive strength

Improvements in or relating to fastener members

Textile fabric production

Independent reset of arbiters and agents to allow for delayed agent reset

A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

Unabhängige Initialisierung von Arbitern und Agenten, um verzögerte Agent-Initialisierung zu ermöglichen

Independent reset of arbiters and agents to allow for delayed agent reset

Direct access mode for a cache

A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data. In one embodiment, the cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache.