INDUCTOR STRUCTURE IN A SEMICONDUCTOR DEVICE

An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

FLIP-CHIP EMPLOYING INTEGRATED CAVITY FILTER, AND RELATED COMPONENTS, SYSTEMS, AND METHODS

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer. 1. An integrated circuit (IC) comprising: at least one semiconductor layer;', a first transmission line configured to transmit a first electromagnetic (EM) signal through a first signal transmission aperture; and', 'a second transmission line configured to receive a second EM signal through a second signal transmission aperture; and, 'a plurality of interconnect layers for providing interconnections to the at least one semiconductor layer, at least one of the plurality of interconnect layers comprising], 'a semiconductor die comprising a plurality of die layers, the plurality of die layers comprisinga plurality of conductive elements interconnected to at least one of the plurality of interconnect layers, the plurality of conductive elements and at least one of the plurality of die layers defining an interior resonator cavity;the interior resonator cavity configured to receive the first EM signal from the first transmission line through the first signal transmission aperture, resonate the first EM signal to generate the second EM signal comprising a ...

SUBSTRATE COMPRISING STACKS OF INTERCONNECTS, INTERCONNECT ON SOLDER RESIST LAYER AND INTERCONNECT ON SIDE PORTION OF SUBSTRATE

An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal. 1. An integrated circuit device comprising:a die; and at least one dielectric layer;', 'a first stack of first interconnects in the at least one dielectric layer, the first stack of first interconnects configured to provide a first electrical path for a non-ground reference signal, wherein the first stack of first interconnects is located along at least one side of the package substrate; and', 'a second interconnect formed on at least one side portion of the at least one dielectric layer, wherein the second interconnect is configured to provide a second electrical path for a ground reference signal., 'a package substrate coupled to the die, the package substrate comprising2. The integrated circuit device of claim 1 , wherein the package substrate includes a set of pads on a printed circuit board (PCB) side of the package substrate claim 1 , wherein a majority of the pads from the set of pads are configured to provide a plurality of electrical paths for at least one non-ground reference signal claim 1 , the set of pads includes all the pads located on the PCB side of the package substrate.3. The integrated circuit device of claim 1 , wherein the package substrate includes a set of pads on a die side of the package substrate claim 1 , wherein a majority of the pads from the set of pads are configured to ...

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Inductor structure in a semiconductor device

An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Multi-layer interconnected spiral capacitor

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Multi-layer ground shield structure of interconnected elements

A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate

An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A CAPACITOR IN A SUBSTRATE

Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Device, system and method for detecting overlap of an ophthalmic device by an eyelid

Techniques and mechanisms for sensing an overlap of an ophthalmic device by an eyelid of a user while the ophthalmic device is disposed in or on an eye of the user. In an embodiment, a circuit, disposed in a sealed enclosure of the ophthalmic device, interacts via an electromagnetic field with a film of tear fluid that is formed on the ophthalmic device. Based on the electromagnetic interaction, an oscillation characteristic of the circuit is evaluated. The oscillation characteristic varies with a resistance that is due in part to an eyelid of the user overlapping at least some portion of the ophthalmic device. Based on the evaluated oscillation characteristic, an amount of the eyelid overlap is determined by circuitry of the ophthalmic device. In another embodiment, the amount of eyelid overlap is used to determine one or more characteristics of gazing by the user's eye.

Multi-layer ground shield structure of interconnected elements

A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Multi-antenna wearable device

A multi-antenna device may include a high-frequency antenna, a low-frequency antenna, and a patterned metal ground plane defining channels having capacitors operable a short circuit for the high-frequency antenna and an open-circuit for the low-frequency antenna. The high-frequency antenna, the low-frequency antenna, and the patterned metal ground plane may be coupled to a multi-layer printed circuit board of the multi-antenna device. The channels of the metal ground plane conductor may have dimensions to, themselves, operate as the capacitors. In other aspects, discrete capacitors may be positioned on the metal ground plane proximate to the channels to reduce eddy currents during operation of the low-frequency antenna.

ANTENNA CONFIGURATION FOR COMPACT GLUCOSE MONITOR

A wearable glucose monitor may include a compact having an antenna positioned on a housing of the glucose monitor to allow the size of the antenna to be larger than a printed circuit board of the glucose monitor positioned internal to the housing. The antenna may be communicatively coupled to a wireless communication device, such as a transceiver on the PCB, to transmit glucose level measurements to an external device through low-frequency radio signals. In some aspects, the antenna may be configured to be distributed into multiple sections positioned on different sections of the housing and connected to form a complete antenna. 1. A wearable device , comprising:a device housing;a printed circuit board (“PCB”) disposed in the device housing and communicatively coupled to a glucose sensor, the PCB including a wireless communication device mounted on the PCB; andan antenna communicatively coupled to the wireless communication device, the antenna comprising a coil, the coil disposed on the device housing, wherein an area enclosed by a perimeter of the coil disposed on the device housing is larger than an area of the PCB.2. The wearable device of claim 1 , wherein at least a portion of the coil is positioned on an internal surface of the device housing.3. The wearable device of claim 1 , wherein at least a portion of the coil is positioned on an external surface of the device housing.4. The wearable device of claim 1 , wherein the device housing includes a first housing section and a second housing section claim 1 ,wherein the antenna includes a first antenna section and a second antenna section, the second antenna section physically separate from the first antenna section and coupled to the first antenna section to form the antenna,wherein the first antenna section is positioned on the first housing section and the second antenna section is positioned on the second housing section.5. The wearable device of claim 4 , wherein the first antenna section and the second ...

PATTERNED GROUNDS AND METHODS OF FORMING THE SAME

A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element. 1. An integrated circuit package , comprising:a first body layer;an inductive element positioned above the first body layer;a first ground plane on a top of the first body layer between the first body layer and the inductive element, the first ground plane having conductive lines generally perpendicular to a magnetic field generated by the inductive element; anda second ground plane on a bottom of the first body layer opposite the first ground plane.2. The integrated circuit package of claim 1 , wherein the first body layer is a dielectric substrate and the inductive element is in an integrated circuit.3. The integrated circuit package of claim 1 , wherein the first ground plane is electrically isolated from the second ground plane.4. The integrated circuit package of claim 1 , further comprising one of a via claim 1 , a solder bump claim 1 , a copper pillar claim 1 , or an electrically conductive path extending between the first ground plane and the second ground plane through the first body layer.5. The integrated circuit package of claim 1 , wherein the first ground plane has an area larger than an area of the inductive element.6. The integrated circuit package of claim 1 , wherein the first ground plane ...

DISPLAY MODULE EXCITATION FOR WIRELESS COMMUNICATIONS

According to an aspect, a display device includes a display module including a display panel and a conductive layer, and an enclosure configured to surround the display module, where the enclosure includes a conductive portion. The display device includes an antenna having a structure formed by an air gap disposed between the conductive layer and the conductive portion of the enclosure. The antenna includes an antenna feed located within the air gap. The antenna feed is coupled to the conductive portion of the enclosure and to the conductive layer such that at least a portion of the display module is configured as a radiating element for wireless communication. 1. A display device comprising:a display module including a display panel and a conductive layer;an enclosure configured to surround the display module, the enclosure including a conductive portion; andan antenna having a structure formed by an air gap located between the conductive layer and the conductive portion of the enclosure, the antenna including an antenna feed located within the air gap, the antenna feed being coupled to the conductive portion of the enclosure and to the conductive layer such that at least a portion of the display module is configured as a radiating element for wireless communication.2. The display device of claim 1 , further comprising:a ground wall configured to electrically connect a portion of the display module to the enclosure.3. The display device of claim 1 , wherein the portion of the display module configured as the radiating element is a corner portion of the display module.4. The display device of claim 1 , wherein the portion of the display module configured as the radiating element is a side portion extending from a first edge of the display module to a second edge of the display module.5. The display device of claim 1 , wherein the entire display module is configured as the radiating element.6. The display device of claim 1 , wherein the antenna includes a ground ...

LOW PROFILE PACKAGE WITH PASSIVE DEVICE

Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) having an active face, an integrated passive device (IPD) having a face, and a redistribution layer (RDL) disposed between the IPD and the IC. The IC is embedded in a substrate. The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield. 1. An apparatus , comprising:an integrated circuit having an active face, wherein the integrated circuit is embedded in a substrate;an integrated passive device (IPD) having a face, wherein the active face of the integrated circuit faces the face of the IPD, and at least one contact of the IPD is arranged in an overlapping configuration relative to the integrated circuit; anda redistribution layer (RDL) disposed between the IPD and the integrated circuit, wherein the RDL is configured to electrically couple the IPD and the integrated circuit.2. The apparatus of claim 1 , wherein the IPD includes at least one of a capacitor claim 1 , an inductor claim 1 , a transformer claim 1 , a coil claim 1 , or a combination thereof.3. The apparatus of claim 1 , further comprising:a second integrated circuit embedded in the substrate; andan interposer disposed between the integrated circuit and the second integrated circuit, the interposer electrically coupled to a first portion of the RDL and a second portion of the RDL, wherein the interposer is configured to couple signals between the integrated circuit and the IPD on the first portion of the RDL and the second circuit on the second portion of the RDL.4. The apparatus of ...

SMART CONTACT LENS WITH ANTENNA AND SENSOR

An ophthalmic device includes an enclosure, an antenna, a sensor system, and a first conductive trace. The ophthalmic device is configured to mount on or in an eye of a user and includes a central region surrounded by a peripheral region. The antenna is disposed within the peripheral region between an outer edge of the ophthalmic device and the central region. The sensor system includes a sensor trace disposed within the peripheral region between the antenna and the central region. The first conductive trace is at least partially disposed between at least one of the antenna and the sensor trace or the central region and the sensor trace. 1. An ophthalmic device , comprising:an enclosure configured to mount on or in an eye of a user;a central region surrounded by a peripheral region;an antenna disposed within the peripheral region, wherein the antenna is disposed between an outer edge of the ophthalmic device and the central region;a sensor system including a sensor trace disposed within the peripheral region between the antenna and the central region; anda first conductive trace at least partially disposed between at least one of the antenna and the sensor trace or the central region and the sensor trace.2. The ophthalmic device of claim 1 , further comprising a second conductive trace claim 1 , wherein the first conductive trace and the second conductive trace each extend alongside opposite sides of the sensor trace.3. The ophthalmic device of claim 2 , wherein the first conductive trace and the second conductive trace are positioned proximate to the sensor trace to inhibit electromagnetic coupling between the antenna and the sensor system.4. The ophthalmic device of claim 2 , wherein the first conductive trace is disposed between the central region and the sensor trace claim 2 , and wherein the second conductive trace is disposed between the antenna and the sensor trace.5. The ophthalmic device of claim 2 , further comprising:a first electronic component disposed ...

SYSTEM, APPARATUS, AND METHOD FOR SEMICONDUCTOR PACKAGE GROUNDS

A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via. 1. A semiconductor package , comprising:a semiconductor die attached to a support plate;a first portion of the support plate configured as a signal connection;a first redistribution layer positioned horizontally above the semiconductor die and coupled to the semiconductor die forming a first signal path;a first via extending vertically between the first portion of the support plate and the first redistribution layer coupling the first portion of the support plate to the first redistribution layer;a second portion of the support plate configured as a ground plane;a second redistribution layer positioned horizontally above the semiconductor die and coupled to the semiconductor die forming a second signal path; anda second via extending vertically between the second portion of the support plate and the second redistribution layer coupling the second portion of the support plate to the second redistribution layer.2. The semiconductor package of claim 1 , wherein the first redistribution layer is adjacent to and separate from the second redistribution layer and the first signal path forms a transmission line for a RF signal.3. The semiconductor package of claim 2 , wherein a proximity of the first redistribution layer to the second redistribution layer capacitively couples the first redistribution layer to the second redistribution layer to reduce inductive coupling of the ...

HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE

Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die. 1. An integrated device comprising:a capacitor; and a first metal layer of a printed circuit board (PCB);', 'a set of solder balls coupled to the PCB; and', 'a second metal layer in a die., 'an inductor electrically coupled to the capacitor, wherein the inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device, the inductor comprising2. The integrated device of claim 1 , wherein the capacitor is located in the die.3. The integrated device of claim 1 , wherein the capacitor is one of at least a metal-insulator-metal (MIM) capacitor claim 1 , and/or metal-on-metal (MOM) capacitor.4. The integrated device of claim 1 , wherein the capacitor is a surface mounted passive device on the PCB.5. The integrated device of claim 1 , wherein the first metal layer is a trace on the PCB.6. The integrated device of claim 1 , wherein the second metal layer is an under bump metallization (UBM) layer of the die.7. The integrated device of claim 1 , wherein the inductor further comprises a third metal layer in the die.8. The integrated device of claim 7 , wherein the ...

Multi-layer interconnected spiral capacitor

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

ANTENNA WITH EXTENDED RANGE

Disclosed herein are techniques for improving the radiation efficiency and coverage range of antennas in wireless devices. According to some embodiments, an antenna includes an antenna feed and a radiator, where signals to be transmitted by the antenna are coupled from the antenna feed to the radiator through distributed and coherent coupling, such that the radiations by the antenna feed and the radiator constructively interfere in a far field to achieve a higher radiation efficiency and an increased coverage range, without increasing the power consumption of the antenna. 1. A wireless device comprising:a circuit board;an antenna feed mounted on the circuit board and configured to receive an electrical signal from the circuit board and radiate the electrical signal; anda radiator mounted on the circuit board and adjacent to the antenna feed, the radiator characterized by a perimeter,wherein the antenna feed is positioned in proximity to a portion of the perimeter of the radiator to feed the electrical signal to the radiator by distributed coupling along the portion of the perimeter of the radiator; andwherein the radiator is configured to receive the electrical signal from the antenna feed by the distributed coupling and radiate the received electrical signal.2. The wireless device of claim 1 , wherein the antenna feed and the radiator are configured such that the electrical signal radiated by the antenna feed and the electrical signal radiated by the radiator are coherent and constructively interfere in a far field.3. The wireless device of claim 2 , wherein the electrical signal in the antenna feed and the electrical signal in the radiator are phase-aligned on propagation paths of the electrical signal in the antenna feed and the electrical signal in the radiator.4. The wireless device of claim 1 , wherein the antenna feed extends in a direction along the portion of the perimeter of the radiator.5. The wireless device of claim 1 , wherein the antenna feed includes ...

DEVICE, SYSTEM AND METHOD FOR DETECTING OVERLAP OF AN OPHTHALMIC DEVICE BY AN EYELID

Techniques and mechanisms for sensing an overlap of an ophthalmic device by an eyelid of a user while the ophthalmic device is disposed in or on an eye of the user. In an embodiment, a circuit, disposed in a sealed enclosure of the ophthalmic device, interacts via an electromagnetic field with a film of tear fluid that is formed on the ophthalmic device. Based on the electromagnetic interaction, an oscillation characteristic of the circuit is evaluated. The oscillation characteristic varies with a resistance that is due in part to an eyelid of the user overlapping at least some portion of the ophthalmic device. Based on the evaluated oscillation characteristic, an amount of the eyelid overlap is determined by circuitry of the ophthalmic device. In another embodiment, the amount of eyelid overlap is used to determine one or more characteristics of gazing by the user's eye.

Antenna configuration for compact glucose monitor

A wearable glucose monitor may include a compact having an antenna positioned on a housing of the glucose monitor to allow the size of the antenna to be larger than a printed circuit board of the glucose monitor positioned internal to the housing. The antenna may be communicatively coupled to a wireless communication device, such as a transceiver on the PCB, to transmit glucose level measurements to an external device through low-frequency radio signals. In some aspects, the antenna may be configured to be distributed into multiple sections positioned on different sections of the housing and connected to form a complete antenna.

Antenna configuration for compact glucose monitor

A wearable glucose monitor may include a compact having an antenna positioned on a housing of the glucose monitor to allow the size of the antenna to be larger than a printed circuit board of the glucose monitor positioned internal to the housing. The antenna may be communicatively coupled to a wireless communication device, such as a transceiver on the PCB, to transmit glucose level measurements to an external device through low-frequency radio signals. In some aspects, the antenna may be configured to be distributed into multiple sections positioned on different sections of the housing and connected to form a complete antenna.

Vertical complementarily fractal antenna

Miniaturized multi-layer balun

A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to an unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.

Capacitor structure

Inductor devices

Complementary mirror image embedded planar resistor architecture

A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Miniaturized multi-layer balun

A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to a unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.

High frequency and wide band impedance matching via

Multi-functional substrate structure

Symmetrical capacitor

A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.

Apparatus and method for testing component built in circuit board

High dielectric antenna substrate and antenna thereof

A high dielectric antenna substrate and antenna thereof are provided. The substrate includes a first dielectric layer having a first dielectric constant, and a second dielectric layer having a second dielectric constant. The second dielectric layer is formed on one surface of the first dielectric layer. The second dielectric constant is lower than the first dielectric constant. Furthermore, a first metal layer and a second metal layer are optionally formed on the same surface or two surfaces of the first dielectric layer to compose a capacitor.

Mirror image shielding structure

A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Antenna configuration for compact glucose monitor

A wearable glucose monitor may include a compact having an antenna positioned on a housing of the glucose monitor to allow the size of the antenna to be larger than a printed circuit board of the glucose monitor positioned internal to the housing. The antenna may be communicatively coupled to a wireless communication device, such as a transceiver on the PCB, to transmit glucose level measurements to an external device through low-frequency radio signals. In some aspects, the antenna may be configured to be distributed into multiple sections positioned on different sections of the housing and connected to form a complete antenna.

Smart contact lens with antenna and sensor

An ophthalmic device includes an enclosure, an antenna, a sensor system, and a first conductive trace. The ophthalmic device is configured to mount on or in an eye of a user and includes a central region surrounded by a peripheral region. The antenna is disposed within the peripheral region between an outer edge of the ophthalmic device and the central region. The sensor system includes a sensor trace disposed within the peripheral region between the antenna and the central region. The first conductive trace is at least partially disposed between at least one of the antenna and the sensor trace or the central region and the sensor trace.

Antenna with extended range

Disclosed herein are techniques for improving the radiation efficiency and coverage range of antennas in wireless devices. According to some embodiments, an antenna includes an antenna feed and a radiator, where signals to be transmitted by the antenna are coupled from the antenna feed to the radiator through distributed and coherent coupling, such that the radiations by the antenna feed and the radiator constructively interfere in a far field to achieve a higher radiation efficiency and an increased coverage range, without increasing the power consumption of the antenna.

Test method of embedded capacitor and test system thereof

Multi-layer interconnected spiral capacitor

An upper planar capacitor (204) is spaced above a lower planar capacitor (102) by a dielectric layer (201). A bridged-post inter-layer connector couples the capacitances in parallel, through first posts (210A,C) and second posts (210B,D). The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler (106) extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler (212) extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Antenna excitation through laptop hinge

According to an aspect, a computing device includes a first enclosure, a second enclosure, a hinge coupled to the first enclosure and the second enclosure, and a hinge-based antenna defined by a slot of the hinge and a portion of an air gap disposed between the first enclosure and the second enclosure, where the slot of the hinge is aligned with the portion of the air gap, and the hinge-based antenna includes an antenna feed element disposed within the slot of the hinge and configured to excite the portion of the air gap.

A circuit board with embedded passive components and the manufacturing and measuring method thereof

Low profile package with passive device

Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) (112) having an active face (114), an integrated passive device (IPD) (102) having a face, and a redistribution layer (RDL) (106,108) disposed between the IPD and the IC. The IC is embedded in a substrate (104). The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive "fence" that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Flip chip que emplea un filtro de cavidad integrado y componentes, sistemas y procedimientos relacionados

Un circuito integrado, CI, de flip chip que comprende: un troquel semiconductor (5 14), que comprende: al menos una capa semiconductora (22); una pluralidad de capas metálicas (24) para proporcionar interconexiones a la al menos una capa semiconductora; una capa de apertura (26) que comprende una apertura de transmisión de señal de entrada (30) configurada para pasar una señal de entrada de radiofrecuencia (RF) (38) a través de la misma, y una apertura de transmisión de señal de salida (32) configurada para pasar una señal de RF de salida (42)) a través de la misma; y al menos una capa de interconexión posterior de final de línea (28) dispuesta entre la al menos una capa semiconductora y la capa de apertura, la al menos una capa de interconexión posterior de final de línea, que comprende: una línea de transmisión de entrada (36) configurada para transmitir la señal de RF de entrada a través de la apertura de transmisión de señal de entrada; y una línea de transmisión de salida (40) configurada para recibir la señal de RF de salida a través de la apertura de transmisión de señal de salida; y una pluralidad de protuberancias conductoras (16) interconectadas a al menos una de entre la pluralidad de capas metálicas (24), la pluralidad de protuberancias conductoras y la capa de apertura que definen una cavidad interior del resonador (34); la cavidad del resonador interior configurada para recibir la señal de RF de entrada desde la línea de transmisión de entrada a través de la apertura de transmisión de señal de entrada, hacer resonar la señal de RF de entrada para generar la señal de RF de salida que comprende una señal de RF filtrada de la señal de RF de entrada y acoplar la señal de RF de salida en la línea de transmisión de salida a través de la apertura de transmisión de señal de salida.

Flip-chip employing integrated cavity filter, and related components, systems, and methods

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive "fence" that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Circuito integrado (ic) flip-chip e método para formar um chip de circuito integrado

filtro de cavidade integrado que emprega flip-chip e componentes, sistemas e métodos relacionados. é revelado um flip-chip que emprega um filtro de cavidade integrado que compreende um chip de circuito integrado (ic) que compreende uma matriz semicondutora e uma pluralidade de saliências condutoras. a pluralidade de saliências condutoras é interconectada a pelo menos uma camada de metal da matriz semicondutora para fornecer uma cerca condutora que define uma cavidade de ressonância interna para fornecer um filtro de cavidade integrado no flip-chip. a cavidade de ressonância interna é configurada para receber um sinal de rf de entrada a partir de uma linha de transmissão de entrada através de uma abertura de transmissão de sinal de entrada fornecida em uma camada interna na matriz semicondutora. a cavidade de ressonância interna ressoa o sinal de rf de entrada para gerar o sinal de rf de saída que compreende um sinal de rf filtrado do sinal de rf de entrada, e acopla o sinal de rf de saída em uma linha de transmissão de sinal de saída no flip-chip através de uma abertura de transmissão de saída fornecida na camada de abertura.

Mobile and non-intrusive device for sleep apnea screening and telemedicine

Systems and methods for monitoring sleep using a sleep monitoring system includes a first component and a second component. The first component is configured to be coupled to a chest of the subject and the second component is configured to be concurrently coupled to an abdomen of the subject. Each component includes a housing, a pair of electrode pads mounted on an underside of the respective housing, and an ECG sensor circuit communicatively coupled to the respective pair of electrode pads. The first component further includes a photoplethysmogram sensor that includes at least one light source and at least one photodetector mounted on the underside of the housing of the first component at a location between the first pair of electrode pads.

Smart contact lens with antenna and sensor

An ophthalmic device includes an enclosure, an antenna, a sensor system, and a first conductive trace. The ophthalmic device is configured to mount on or in an eye of a user and includes a central region surrounded by a peripheral region. The antenna is disposed within the peripheral region between an outer edge of the ophthalmic device and the central region. The sensor system includes a sensor trace disposed within the peripheral region between the antenna and the central region. The first conductive trace is at least partially disposed between at least one of the antenna and the sensor trace or the central region and the sensor trace.

Low profile package with passive device

Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) (112) having an active face (114), an integrated passive device (IPD) (102) having a face, and a redistribution layer (RDL) (106,108) disposed between the IPD and the IC. The IC is embedded in a substrate (104). The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

System, apparatus, and method for semiconductor package grounds

A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.

Antenna configuration for compact glucose monitor

A wearable glucose monitor may include a compact having an antenna positioned on a housing of the glucose monitor to allow the size of the antenna to be larger than a printed circuit board of the glucose monitor positioned internal to the housing. The antenna may be communicatively coupled to a wireless communication device, such as a transceiver on the PCB, to transmit glucose level measurements to an external device through low-frequency radio signals. In some aspects, the antenna may be configured to be distributed into multiple sections positioned on different sections of the housing and connected to form a complete antenna.

Multi-layer interconnected spiral capacitor

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Structure and method for a multi-electrode capacitor

Inductor structure in a semiconductor device

An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Inductor structure in a semiconductor device

An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Balanced-to-unbalanced transformer embedded with filter

A balanced-to-unbalanced transformer embedded with a filter, the balanced-to-unbalanced transformer being disposed in a multi-layered substrate and comprising vertically coupled transmission lines designed in different layers in the multi-layer substrate to increase transmission performances. A capacitor and a transmission line are connected to a single-ended I/O port of the balanced-to-unbalanced transformer such that a filter is embedded in the balanced-to-unbalanced transformer.

Multi-antenna wearable device

A multi-antenna device may include a high-frequency antenna, a lowfrequency antenna, and a patterned metal ground plane defining channels having capacitors operable a short circuit for the high-frequency antenna and an opencircuit for the low-frequency antenna. The high-frequency antenna, the lowfrequency antenna, and the patterned metal ground plane may be coupled to a multilayer printed circuit board of the multi-antenna device. The channels of the metal ground plane conductor may have dimensions to, themselves, operate as the capacitors. In other aspects, discrete capacitors may be positioned on the metal ground plane proximate to the channels to reduce eddy currents during operation of the low-frequency antenna.

Multi-antenna wearable device

A multi-antenna device may include a high-frequency antenna, a lowfrequency antenna, and a patterned metal ground plane defining channels having capacitors operable a short circuit for the high-frequency antenna and an opencircuit for the low-frequency antenna. The high-frequency antenna, the lowfrequency antenna, and the patterned metal ground plane may be coupled to a multilayer printed circuit board of the multi-antenna device. The channels of the metal ground plane conductor may have dimensions to, themselves, operate as the capacitors. In other aspects, discrete capacitors may be positioned on the metal ground plane proximate to the channels to reduce eddy currents during operation of the low-frequency antenna.

A balance to unbalance transformer embedded with a filter

A balance to unbalance transformer embedded with a filter

An adjustable resistor embedded in a multi-layer substrate and method for forming the same

substrato compreendendo pilhas de conexões, conexão sobre camada resistente à solda e conexão em parte lateral de substrato

a presente invenção se refere a um dispositivo de circuito integrado que inclui um substrato de acondicionamento e uma matriz acoplada ao substrato de acondicionamento. o substrato de acondicionamento inclui pelo menos uma camada dielétrica, uma primeira pilha de primeiras conexões na pelo menos uma camada dielétrica e uma segunda conexão formada em pelo menos uma parte lateral da pelo menos uma camada dielétrica. a primeira pilha de primeiras conexões é configurada para fornecer um primeiro caminho elétrico para um sinal de referência não terra, onde a primeira pilha de primeiras conexões é localizada ao longo de pelo menos um lado do substrato de acondicionamento. a segunda conexão é configurada para fornecer um segundo caminho elétrico para um sinal de referência terra.

Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate

An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Sustrato que comprende pilas de interconexiones, interconexión sobre la capa protectora contra soldadura e interconexión sobre la porción lateral del sustrato

Un envase que comprende: un molde (304); y un sustrato del envase (302) acoplado al molde, el sustrato del envase que comprende: al menos una capa dieléctrica (320, 322, 324); una primera pila de primeras interconexiones (380) en al menos una capa dieléctrica, la primera pila de primeras interconexiones se configura para proporcionar una primera trayectoria eléctrica para una primera señal de referencia sin conexión a tierra, en la que la primera pila de primeras interconexiones se ubica a lo largo de al menos un lateral del sustrato del envase; una segunda pila de primeras interconexiones (390) en al menos una capa dieléctrica, la segunda pila de primeras interconexiones se configura para proporcionar otra trayectoria eléctrica para una segunda señal de referencia sin conexión a tierra, en la que la segunda pila de primeras interconexiones se ubica a lo largo de al menos un lateral del sustrato del envase; una interconexión lateral (352) que se forma sobre al menos una porción lateral exterior de al menos una capa dieléctrica, en la que la interconexión lateral se configura para proporcionar una segunda trayectoria eléctrica para una señal de referencia de conexión a tierra, en el que la interconexión lateral se configura para aislar al menos parcialmente la primera señal de referencia sin conexión a tierra que pasa a través de la primera pila de primeras interconexiones, de la segunda señal de referencia sin conexión a tierra que pasa a través de la segunda pila de primeras interconexiones, en el que el sustrato del envase incluye un conjunto de almohadillas (334) sobre un lateral de la placa de circuito impreso (PCB) del sustrato del envase, en el que una mayoría de las almohadillas del conjunto de almohadillas se configuran para proporcionar una pluralidad de trayectorias eléctricas para al menos una señal de referencia sin conexión a tierra, el conjunto de almohadillas incluye todas las almohadillas que se ubican sobre el lateral de la PCB del sustrato del ...

Pacote e método para fabricar um substrato de acondicionamento

A presente invenção se refere a um dispositivo de circuito integrado que inclui um substrato de acondicionamento e uma matriz acoplada ao substrato de acondicionamento. O substrato de acondicionamento inclui pelo menos uma camada dielétrica, uma primeira pilha de primeiras conexões na pelo menos uma camada dielétrica e uma segunda conexão formada em pelo menos uma parte lateral da pelo menos uma camada dielétrica. A primeira pilha de primeiras conexões é configurada para fornecer um primeiro caminho elétrico para um sinal de referência não terra, onde a primeira pilha de primeiras conexões é localizada ao longo de pelo menos um lado do substrato de acondicionamento. A segunda conexão é configurada para fornecer um segundo caminho elétrico para um sinal de referência terra.

Photoplethysmogram system and method

Photoplethysmogram system and method are designed for monitoring a user's physiological signals. The system includes a PPG device with a light source, a PPG sensor, and at least one verification sensor. The PPG sensor collects light reflected from a user's fingertip after being emitted by the light source, while the verification sensor determines the position of the fingertip and measures the contact pressure of the PPG device to the user's fingertip. Additionally, the system includes an analysis module that is electrically connected to the PPG device, which is responsible for analyzing and processing a plurality of collected data from the device. There is also a display module that is electrically connected to the analysis module, providing a feedback on the PPG device's performance. The analysis module dynamically adjusts the intensity and sampling rate of light emitted by the light source based on the measured contact pressure.

A multilayer printed circuit board embedded with a filter

Patterned grounds and methods of forming the same

A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.