Double-horizontal axle concrete-mixer

A double-horizontal axle concrete-mixer comprises a material barrel, mixing shafts in the material barrel and mixing blades which are connected with the mixing shaft. The mixing shaft is connected with the revolving mechanism of speed reducer of main motor. Two mixing shafts are installed in parallel in the material barrel. The mixing blades on two mixing shafts have same installation form and opposite installation directions. The mixing blades are distributed with a spiral form along the axial directions of mixing shafts. The middle part of mixing shaft is connected with middle mixing blades. Two ends of mixing shafts are connected with end mixing blades. The blade surface of middle mixing blade has a sickle shape. The blade surface of end mixing blade has a kitchen knife shape. The end of knife handle is provided with screw thread. The knife handle traverses the radial preserved hole passage of mixing shaft. The screw thread at end of knife handle is connected with the nut. The double-horizontal ...

Method for determining intelligent platform management bus (IPMB) addresses of block multiplexer channels (BMC) of blade servers

The invention discloses a method for determining the IPMB addresses of BMCs of blade servers and belongs to the technical field of blade server communication. The method adopts a structure which comprises management module and blade servers, wherein the management module performs data interaction with the BMC of each blade server through an IPMB bus. The structure is characterized in that: each IPMB bus is provided with an electrically programmable read-only-memory (EPROM) for storing the IPMB address of the BMCs of the blade servers; the management module writes the specified IPMB addresses of the BMCs of the blade servers in the EPROMs in the buses when starting for the first time; and when inserted, the blade servers can configure the IPMB addresses of the BMCs of the blade servers by reading the IPMB addresses in the EPROMs. The management module can change the IPMB addresses of the BMCs of the blade servers flexibly according to needs, thereby improving the safety of the IPMB addresses ...

Method for producing electrolytic manganese metal by using ammonia gas instead of aqueous ammonia to neutralize to remove iron

The invention discloses a method for producing electrolytic manganese metal by using ammonia gas instead of aqueous ammonia to neutralize to remove iron, comprising working procedures of leaching chemical combination, purification, electrolysis, post treatment and the like. The working procedure of the leaching chemical combination comprises the steps of fully adding anolyte enabling material to react into a reactor, then adding sulphuric acid, adding manganese carbonate ore and manganese dioxide ore, introducing steam in the feeding process for heating, controlling the temperature at 70-75 DEG C and stirring for 2-2.5 hours in the leaching process, wherein the special point of the leaching process is that: introducing ammonia gas to the inside of feed liquid when fe2+ is less than or equal to 0.001g/l and stopping supplying air until the pH value of the feed liquid reaches 6.2-6.8. The ammonia gas replaces the aqueous ammonia for neutralizing operation, thereby eliminating plenty of industrial ...

Experiment method for pulsed laser single event upset cross section

The invention provides an experiment method for a pulsed laser single event upset cross section. The method comprises the steps of scanning and irradiating an inside of a device according to pulsed laser E of a certain value; obtaining a laser single event upset cross section value under the E according to single event upset frequency, irradiation frequency (stationing number of scanning) of the monitored device; and obtaining a Sigma~E curve of the laser single event upset cross section through changing the pulsed laser with different energy for scanning and irradiating. The invention provides technical support for pre-estimating single event upset resistance of a to-be-tested device and enables easier and more practical research on ground pulsed laser simulation of single event effects in the future.

Implementing method of network security system capable of self-updating letter of representation

Disclosed is an implementation method of a grid security system which can update the proxy certificate automatically; the implementation method is a strategic method and adopts a regular check mechanism to check the proxy certificate of the operation continuously; once the overdue proxy certificate is detected and the proxy is updated automatically to ensure the normal running of the operation. The grid security system which can update the proxy certificate automatically is mainly composed of a grid security system client, a grid security system server, a grid security system certificate updating module and a certificate repository; the proxy updating service uses the function provided by the certificate repository. From the logical viewpoint, the service can be considered as a module of the operation management system; the module records and manages the proxy certificates of the submitted operations and the operations require the proxy to be updated; therefore, the operation maintained ...

Folding arm type cable movement device for offshore platform

The invention discloses a folding arm type cable movement device for an offshore platform. The folding arm type cable movement device consists of a davit, a connection cylinder, a connection pin shaft, cable bridges, a platform upright post and a bracket pedestal. The working manner of the folding arm type cable movement device is that: the davit is arranged on a movable drilling platform; the upright post is arranged on a main deck of a platform; and two sections of cable bridges are connected with the davit and the upright post respectively via a semicircular protective panel, and the cable bridges are connected via the movable pin shaft. A power cable and a signal cable supply power to equipment on the movable drilling platform via the upright post, the cable bridges and the davit. When the drilling platform moves back and forth, or leftwards and rightwards, a cable arranged on the cable bridges can be driven to move by the stretching of the cable bridges at two ends of the movement ...

Petroleum pipeline detecting system

The invention provides a petroleum pipeline detecting system which comprises an excitation device, a detecting device, a mileage wheel, a data processing unit, a pipe internal and external data transmission device based on an ultra-low frequency electromagnetic pulse emitter, a low frequency signal emitter based on 22Hz, a low frequency signal receiver based on 22Hz, a driving device, a speed control device, a receiving sensor array, and a data analyzing unit. The system guarantees the stable running of a petroleum pipeline detector by installing a supporting wheel below the pipe internal andexternal data transmission device based on the ultra-low frequency electromagnetic pulse emitter, reduces the situation that detects of the pipeline are undetected by installing the speed control device, improves the locating precision of the pipeline defects by installing a pipe external defect locating device of the low frequency signal generator based on 22Hz, is beneficial to timely finding out ...

Credible hard disk based on GPS

The invention discloses a credible hard disk based on GPS, comprising a GPS receiver, an external GPS antenna, an IDE interface, a central processing unit, a processing procedure memory, a nonvolatile memory, a hard disk driving logic circuit and a disk body, wherein the central processing unit is respectively connected with the GPS receiver, the IDE interface, the nonvolatile memory, the processing procedure memory, the hard disk driving logic circuit and the disk body; the external GPS antenna is directly connected with the GPS receiver; and the IDE interface is connected with the IDE interface of a general computer. The invention relates to global positioning system (GPS), computer processing technology, information security technology, and the like, adopts a hardware encryption and decryption method, uses geographical position information provided by the GPS as a secret key and is suitable for the hard disk information security of a non-moving computer.

Method for realizing self-adapting on embedded web server

The invention provides a method for realizing language self-adaptation on an embedded type web server. The method comprises the step of achieving the language self-adaptation on the inserted type web server through amending a mini-httpd source code. Compared with the prior art, the method has the advantages that the use is flexible on the embedded type web server, the configuration is simple, the language code of a browser used by a client can be automatically determined to provide a corresponding language web page, so that the service of the wed page is more humanized.

Sand-measuring ionization chamber

The invention discloses a sand-measuring ionization chamber which comprises an upper end tube and a lower end tube connected by a flange and is separated into two separate parts. The upper end tube is internally provided with an amplifier plate, a high-voltage power source frame and a temperature sensor, and a high-voltage power source is mounted in the high-voltage power source frame; the lower end tube is internally provided with an electrode container and filled with high-voltage inert gas; the top end of the lower end tube is provided with an aluminum window; a ceramic insulator is welded on the flange; a lead tube on the electrode container is connected with a high-voltage electrode on the high-voltage power source frame by the ceramic insulator; the other electrode on the high-voltage power source frame is connected with the input end of an amplifying circuit on the amplifier plate; the output end of the amplifying circuit on the amplifier plate is connected with a cable; and the ...

Underwater confining pressure-resistant flexible insulation belt

The invention relates to underwater insulation technology, in particular to an underwater confining pressure-resistant flexible insulation belt which comprises a waterproof external protection layer,insulation coils, a subordinate connection plug-in unit and an air supply pipeline; not less than 5 insulation coils are encapsulated side by side in the middle of the waterproof external protection layer; the air supply pipeline is connected with all the insulation coils through the connection plug-in unit; and all the insulation coils after being woven are connected with each other at a certaindistance. The underwater confining pressure-resistant flexible insulation belt can be used for underwater insulation and can endure greater confining pressure.

Blood vessel diameter measuring method based on digital image processing technology

The invention provides a blood vessel diameter measuring method based on digital image processing technology. The method includes that: (1) Gauss matched filtering method is utilized to enhance a blood vessel image; (2) the image is normalized and binarized; (3) according to related theory of mathematical morphology, the image is refined, and skeleton is extracted; (4) straight line fitting method is used for solving slope of a section of blood vessel, pixel number of blood vessel is detected along the direction vertical to the blood vessel, and then the blood vessel diameter is solved according to dot pitch. The invention is used for measuring medical image blood vessel diameter, computing efficiency is high, requirement on image quality is low, and computation is accurate.

Sand-measuring ionization chamber

The invention discloses a sand-measuring ionization chamber which comprises an upper end tube and a lower end tube connected by a flange and is separated into two separate parts. The upper end tube isinternally provided with an amplifier plate, a high-voltage power source frame and a temperature sensor, and a high-voltage power source is mounted in the high-voltage power source frame; the lower end tube is internally provided with an electrode container and filled with high-voltage inert gas; the top end of the lower end tube is provided with an aluminum window; a ceramic insulator is weldedon the flange; a lead tube on the electrode container is connected with a high-voltage electrode on the high-voltage power source frame by the ceramic insulator; the other electrode on the high-voltage power source frame is connected with the input end of an amplifying circuit on the amplifier plate; the output end of the amplifying circuit on the amplifier plate is connected with a cable; and theother ...

Expansion tank liquid level pressure stabilization device in closed water-cooling circulating system

The invention aims to provide an expansion tank liquid level pressure stabilization system in a closed water-cooling circulating system. The expansion liquid level pressure stabilization system comprises an expansion tank, an outer water replenishing pipeline, an internal water replenishing pipeline and a container which is a funneled container; a sealing cover is arranged on the funneled container; the outer water replenishing pipeline is connected with the funneled container and the internal water replenishing pipeline respectively; the funneled container is connected with the expansion tank which is connected with a main water pipeline and an auxiliary pipeline respectively; and the auxiliary pipeline is connected with a small water storage tank which is communicated with the internal water replenishing pipeline. The equipment of the conventional nitrogen pressure stabilization system is reduced, the expansion tank pressure stabilization system in the closed water-cooling system is simplified ...

ISCSI disc array controller with internal path redundant function

The invention discloses an embedded IOP331 processor, which integrates a master CPU, a DDR2 memory, a dual-gigabit Ethernet, a dual-SATA disk controller and other major chips on a signal mainboard and can realize the single-path access and control of the maximum 16 SATA disks and also supports the dual-path redundancy control of 8 hard drives of a stand-alone. The host end can adopt the standard ISCSI agreement to realize the RAID creation, zoning and other disk operations of the SATA disks. The invention not only realizes the ISCSI disk array controller functions of a single mainboard, but also selectively provides the path redundancy of 8 disks and the path redundancy of the dual-gigabit Ethernet host in the controller based on the provision of 16-bit ISCSI access and RAID operations, so as to greatly improve the reliability of the disk array system under a single controller. The invention achieves high availability and high reliability, on the basis of low cost. At the same time, in ...

Parallel processing-based multi-host interface redundancy SAN controller

The invention relates to a parallel processing-based multi-host interface redundancy SAN controller and belongs to a controller. The structure of the parallel processing-based multi-host interface redundancy SAN controller comprises a controller redundant module A, a controller redundant module B and a backboard module C, wherein the controller redundant module A is connected with the controller redundant module B by a high-speed PCIE bus P1 and is connected with the backboard module C by a non-high speed mutual connection access PA; the controller redundant module B is connected with the backboard module C by a non-high speed mutual connection access PB. Compared with the prior art, the parallel processing-based multi-host interface redundancy SAN controller adopts double controller double DMA channel parallel processing, a structure configured with two redundancy controller modules, and parallel processing of RAID and other data in each controller redundancy module and between the two ...

Method for recognizing print hand Arabic alphabets based on boundary characteristic

Method for oxidizing unsaturated conjugated enol

The invention relates to a method that a compound which contains conjugated unsaturated enol is oxidized into a conjugated unsaturated ketene compound. Ketone or aldehyde is used as an oxidizer, and the compound which contains the conjugated unsaturated enol is oxidized under the action of an alcohol aluminum catalyst. The target products which are obtained by adopting the method have high yield rate, the operation is simple and convenient, and the cost is low. The conjugated double bonds are not damaged, in addition, the chirality which is needed by the obtained products is also ensured.

Soil curing agent and using method thereof

The invention discloses a soil curing agent, which comprises the following components in part by weight: 1 part of fluidized bed fire coal sulphur-fixing ash, 0.1 to 0.3 part of portland cement, 0.2 to 0.6 part of water quenching blast furnace slag, 0.1 to 0.5 part of active mineral admixture, 0.05 to 0.1 part of active exciting agent and 0 to 0.3 part of hydroxides of alkali metals or alkaline-earth metals. By using the curing agent of the invention, soil has high strength, water stability and volume stability, so the curing agent is not inferior to ordinary portland cement under the same condition, and has the characteristics of high early strength, large development potential of long-term strength, convenient construction, high durability and the like; and simultaneously, the curing agent is convenient to prepare, can dissolve industrial waste residues such as sulphur-fixing ash and the like which cannot be recycled at present, reduces the cost and is favorable for protecting environment ...

CACHE method applied to IPSAN

The invention discloses a CACHE method applied to IPSAN, belonging to an SAN technology. IPSAN directly inserts a dedicated network between a host and a storage device; a controller is set between the network and the storage device, and CACHE algorithm is added into the controller. The adding method comprises the following steps: (1) one part of the memory of the controller is separated out to serve as CACHE; (2), tio.c in target software of the controller is added with cache_alloc () function; and (3) inspur_cache_access () function is invoked in the cache_alloc () function to make corresponding operation on data from the network according to the CACHE algorithm. Compared with the prior art, the CACHE method applied to IPSAN of the invention adds the CACHE algorithm into the controller on the basis of open source software (OSS), and thus, the performance of IPSAN is improved.

Implementing method of network security system capable of self-updating letter of representation

Disclosed is an implementation method of a grid security system which can update the proxy certificate automatically; the implementation method is a strategic method and adopts a regular check mechanism to check the proxy certificate of the operation continuously; once the overdue proxy certificate is detected and the proxy is updated automatically to ensure the normal running of the operation. The grid security system which can update the proxy certificate automatically is mainly composed of a grid security system client, a grid security system server, a grid security system certificate updating module and a certificate repository; the proxy updating service uses the function provided by the certificate repository. From the logical viewpoint, the service can be considered as a module of the operation management system; the module records and manages the proxy certificates of the submitted operations and the operations require the proxy to be updated; therefore, the operation maintained ...

Method for producing electrolytic manganese metal by lixiviating sinter ore by adding ferrous sulphate in replacement of manganese carbonate ore

The invention discloses a method for producing electrolytic manganese metal by lixiviating sinter ore by adding ferrous sulphate in replacement of manganese carbonate ore. The method comprises the working procedures of lixiviation and oxidation, neutralization, filtration, purification, electrolyzation and the like, and is characterized in that the process of lixiviation and oxidation is implemented by injecting anolyte enough to lead the material to react into the lixiviation vessel, adding concentrated sulfuric acid, adding sinter ore and finally adding ferrous sulphate for lixiviation for 3-4 hours at 70-75 DEG C; adding ammonia water immediately when Fe2+ in the feed liquid is less than or equal to 0.001g/l so as to carry out neutralization, testing the pH value of the feed liquid several times during the process of neutralization, and stopping adding ammonia water when full-valent Fe up to standard is less than or equal to 0.001g/l and the pH value reaches 6.8-7.2. The invention can ...

Biological preparation method for water-soluble polyvinyl alcohol fibers

The invention particularly relates to a biological preparation method for water-soluble polyvinyl alcohol fibers, which belongs to the field of biochemistry and has the advantages of simple preparation, high product quality and practicability. The invention adopts the following technical scheme that the method comprises the following steps: (1) mixing water-soluble polyvinyl alcohol fibers, sodium alga acid, acrylamide and water, heating the mixture in a water bath for dissolving, and then standing the mixture and cooling the mixture to the normal temperature so as to form water-soluble polyvinyl alcohol fiber solution; (2) mixing enzyme/microbial suspension and the water-soluble polyvinyl alcohol fiber solution in a certain proportion; (3) adding saturated boric acid solution into calcium chloride and N, N'-methylene-bisacrylamide to form cross-linker solution; and (4) dripping the mixed solution prepared in the third step into the cooled cross-linker solution to form white spherical granules ...

Method for enabling management module main chip of blade server to work under low-temperature environment

The invention discloses a method for enabling a management module main chip of a blade server to work under a low-temperature environment, and belongs to the technical field of blade servers. A digital temperature sensor transmits a measured temperature number to a complex programmable logic device (CPLD); when the temperature number read by the CPLD is lower than the temperature number of the working requirement of the management module main chip, the CPLD controls conduction of high-power metal oxide semiconductor (MOS) tubes around the commercial management module main chip; the high-power MOS tubes work to generate a large amount of heat, so that the temperature of the management module main chip is raised; when the temperature reaches the working temperature of the management module main chip, the management module main chip is started and simultaneously sends a work signal to the CPLD; and after detecting the work signal, the CPLD switches off the MOS tubes. Aiming at the wide temperature ...

Dual-section clamping tool for fixing and positioning elbow parts

The invention provides a dual-section clamping tool for fixing and positioning elbow parts. The clamping tool is provided with a flange plate (7), sliding seats (3) and V-shaped blocks, wherein the flange plate (7) can be connected with a machine tool, the sliding seats (3) are fixedly connected to the flange plate, the V-shaped blocks are fixedly connected to the sliding seats (3) and used for clamping the elbow parts, the sliding seats (3) are symmetrically distributed on the central axis of the flange plate, and connected and fixed to a disc (6) through screw pins, a sliding block (2) passes through sliding grooves on the sliding seats (3) and is slidably connected into the sliding grooves, the upper end of the sliding block (2) is parallel to the two translational V-shaped blocks (1) on the plane of the flange plate (7) and does a horizontal axial motion along with the sliding block, and two rotating V-shaped blocks (8) are movably connected to the sliding block through pin holes on ...

Method for determining thickness of single-event sensitive volume of device

The invention relates to a method for determining the thickness of single-event sensitive volume of a device, which belongs to the fields of space radiation effects and reinforcement technology. The method comprises the steps of calculating deposited energy of laser in the sensitive volume, and generating single event effects when deposited charges of the laser in a sensitive volume unit of the device achieve or exceed the critical charges of the device, wherein the critical charges of the single-event effects under different pulsed laser wavelengths are the same; and the laser of a laser simulation system is used for inducing, obtaining energy threshold data of the single-event effects and further obtaining the thickness of the sensitive volume (Sv) of the single-event effects. The method has no radiation injury to the device and laboratory staff, very simple operation, low cost and capability of precisely measuring the thickness of the sensitive volume of the device.

Method for producing electrolytic manganese metal by using ammonia gas instead of aqueous ammonia to neutralize to remove iron

The invention discloses a method for producing electrolytic manganese metal by using ammonia gas instead of aqueous ammonia to neutralize to remove iron, comprising working procedures of leaching chemical combination, purification, electrolysis, post treatment and the like. The working procedure of the leaching chemical combination comprises the steps of fully adding anolyte enabling material to react into a reactor, then adding sulphuric acid, adding manganese carbonate ore and manganese dioxide ore, introducing steam in the feeding process for heating, controlling the temperature at 70-75 DEG C and stirring for 2-2.5 hours in the leaching process, wherein the special point of the leaching process is that: introducing ammonia gas to the inside of feed liquid when fe2+ is less than or equal to 0.001g/l and stopping supplying air until the pH value of the feed liquid reaches 6.2-6.8. The ammonia gas replaces the aqueous ammonia for neutralizing operation, thereby eliminating plenty of industrial ...

Spherical Langmuir probe device for measuring low-density cold plasmas

The invention discloses a spherical Langmuir probe device for measuring low-density cold plasmas, which is used for measuring low-density cold plasmas with the density of between 105 and 108cm-3 and electron energy of between 0.5 and 5eV. The device comprises a hollow gold-plated titanium metal spherical Langmuir probe, a hollow cylindrical titanium metal support, an electrical connection point of the Langmuir probe and a ceramic insulating base of the Langmuir probe. The extraspherical diameter of the hollow gold-plated titanium metal spherical Langmuir probe is not less than 56mm, and the thickness of a shell is between 0.5 and 2mm; and the outer surface of the probe is subjected to gold-plating treatment, and the gold-plating thickness is between 10 and 50nm. The device effectively improves the charge collection of the plasmas and reduces the mass, and the surface gold-plating can play a role in antioxidation. The device is suitable for parameter measurement of spatial on-orbit low-density ...

Method for producing electrolytic manganese metal

The invention relates to a method for producing electrolytic manganese metal. The method has the following characteristics that: silicomanganese slag replacing manganese carbonate ore is leached in multiple stages, that is, in the first stage of leaching, anolyte enough for the reaction of materials is poured into a combination tank, concentrated sulfuric acid and the silicomanganese slag are then added, in the second stage and each of the rest stages of leaching, the filtrate produced by filter pressing in the previous stage of leaching is first poured into the combination tank, the anolyte is then replenished, the concentrated sulfuric acid and the silicomanganese slag are then added, so that Mn 2 plus in the slag can be extracted, the produced manganese sulfate enters solution, and after the manganese concentration required by catalysis is reached, processes, such as deironization, desiliconization, neutralization, purification and electrolysis, are sequentially carried out, so that ...

Aerial photographic and aerial survey timing electronic shutter controller

The invention relates to an aerial photographic and aerial survey timing electronic shutter controller. The controller consists of a shell, and a control circuit and a battery which are arranged in the shell. The front of the shell is provided with a time adjustment button, a switch button and a liquid crystal display. The side edge of the shell is provided with a camera connecting line and a receiver connecting line. The control circuit operates and processes data acquired by a receiver by the setting of the time adjustment button, displays processing results on the liquid crystal display screen and controls a camera to act. The controller controls an electronic shutter by utilizing a singlechip to make the photographic interval of the electronic shutter accurate to 0.001s, can randomly adjust the photographic interval, is simple, easy to use, small in volume, light in weight and high in control accuracy, greatly improves the aerial photographic and aerial survey accuracy, improves the ...

Cooling system of high-power power conversion device used for ship

The invention aims to provide a cooling system of a high-power power conversion device used for a ship. The cooling system comprises a rectifier power module, a direct-current conversion power module, an inverter power module, a main water circulating pump, a heat exchange device, a main water inlet pipe and a main water return pipe which are connected in parallel; the rectifier power module, the direct-current conversion power module and the inverter power module are all provided with water-cooled radiators; the three water-cooled radiators are connected with the heat exchange device through the main water inlet pipe and the main power return pipe to from a cooling loop; and the main water circulating pump is arranged in the main water inlet pipe. The cooling system can effectively save space on the ship, and can realize the high power intensity of the power conversion device. The blockage caused by scaling and microbial growth in the cooling system is avoided, so that the corrosion of ...

Image compression method based on fractional fourier transform

The invention provides an image compression method based on fractional fourier transform, comprising the following steps of: firstly, calculating (0.5, 0), (0, 0.5), (1, 0) and (0, 1) order fractional fourier transform of an image; secondly, calculating fractional fourier second moments of all transform orders according to the relationship of Wigner distribution and the fractional fourier transform; thirdly, finding an optimal transform order according to each second moment value, and transforming the image to an optimal fractional fourier domain to centralize the energy of the image onto fractional fourier coefficients as little as possible; fourthly, ignoring all coefficients with amplitudes smaller than certain threshold, and encoding the other fractional fourier coefficients by adopting an entropy encoding method to realize image compression. The invention has rapid calculation speed and adopts a rapid discrete fractional fourier transform algorithm. The time complexity is only O (N ...

A method for testing line defects of LCD (liquid crystal display) panel, array substrate and drive wires

A method for testing line defects of an LCD panel, an array substrate and drive wires. The LCD panel comprises a plurality of groups of drive wires and a plurality of detection terminals, and each group of the drive wires at least comprises two drive wires, wherein the LCD panel further comprises a plurality of first switches, a plurality of second switches, a first switch control wire used for controlling the plurality of first switches, and a second switch control wire used for controlling the plurality of second switches, and one end of each of the two drive wires of at least one group of the drive wires is connected with one detection terminal through one first switch and one second switch respectively. At least two drive wires share one first detection terminal, so that the using times of probes can be reduced; the distance among the detection terminals are enlarged, and the defect of detection error caused by short circuit of the adjacent probes as soon as the probes are slightly ...

Multilevel converter systems and methods with reduced common mode voltage

Multilevel converters and space vector modulation operating methods are presented in the invention in which fewer than all possible switching states are employed for space vector modulation of rectifier and inverter circuits to promote common mode voltage contribution cancellation or reduction therebetween and by using subsets of possible space vector modulation switching states associated with minimal positive or negative common mode voltages and in some cases using virtual vectors which have zero common mode voltages to eliminate the 3rd order harmonic components in common mode voltage as well as to reduce common mode voltage affects associated with multilevel inverter stages.

SMBUS-based KVM switch with local and remote functions

The invention discloses a system management bus (SMBUS)-based keyboard video mouse (KVM) switch with local and remote functions, which belongs to the field of computers. The switch consists of a remote KVM switch management part and a local KVM switch management part, wherein the remote KVM switch management part performs the switch management on each signal of the KVM by a remote management central processing unit (CPU) through an SMBUS and or input/output signals extended from the SMBUS, and packages data and transmits the packaged data to a remote management machine through an Ethernet; and the local KVM switch part performs the switch management on each signal of the KVM by a switch management microcontroller unit (MCU) through the SMBUS and/or the input/output signals extended from the SMBUS, and provides output interfaces of a local video graphics array (VGA) interface, a universal series bus (USB) interface, a play station 2 (PS2) interface and a component object model (COM) interface ...

Test method of single event effect of pulse width modulator (PWM)

The invention relates to a test method of a single event effect of a pulse width modulator (PWM), belonging to the technical field of space radiation effect and reinforcement. The test method comprises the following steps of: firstly monitoring the output pulse loss phenomenon caused by single event upset in a test; then counting 50MHz pulse signals by taking a PWM output high level as a gate control signal, calculating the time of the high level in the measurement period, and finally calculating the duty ratio output by the PWM by using a microprogrammed control unit (MCU); monitoring an uploading upper computer; comparing an output signal amplitude with an output pulse signal amplitude of the PWM, and uploading a monitoring result to the upper computer; recording the output frequency of the PWM which is not a twice relation with the clock frequency by a counter, transmitting into the MCU for monitoring, and uploading to the upper computer; and counting the pluses in a certain standard ...

Underwater power device and coupling device connected to load

The invention provides a coupled device for connecting an underwater power pack and a load. The device comprises a magnet steel which is arranged on an output shaft of a power plant, a non-conductive housing which is covered outside the output shaft of the power plant and the magnet steel and is connected with a sealing housing of the power plant in a sealing way, a steel column which is fixed on the non-conductive housing and a sleeve which is arranged on the steel column. When the power plant in loading is entwined or blocked by a barrier under water, the device can still work normally, thereby avoiding the damage of the power plant and guaranteeing the service life of the power plant. In the invention, the magnet coupling connection is adopted to solve the problem that the power plant is difficult to seal in water. The power plant and the retarder are arranged in the same sealing box so that the complex moving seal is not needed on the output shaft; and the research, development and ...

Method for implementing redundant management module in compact peripheral component interconnect (CPCI) blade server

The invention provides a method for implementing a redundant management module in a compact peripheral component interconnect (CPCI) blade server. A complex programmable logic device (CPLD) is arranged on a backboard to control and switch red, green and blue (RGB), universal serial bus (USB) and inter-integrated circuit (I2C) signals; and the control principle is that: if a main management module is connected and normally works, the main management module is used for management in spite of the connection of a slave management module; if the main management module fails in the working process, the slave management module can take over the work; and after a new management module is connected to the position of the main management module, if the new management module works normally, the new management module can take over the work again. Compared with the prior art, the method for implementing the redundant management module in the CPCI blade server has the advantages that: the whole process ...

Deepwater underwater oil-storage petroleum production device with a dynamic positioning buoy

The invention relates to a deepwater underwater oil-storage petroleum production device with a dynamic positioning buoy. A complete system comprises an underwater wellhead module, an underwater processing module, an oil-water replacement underwater oil-storage module, a deepwater upright tube, a dynamic positioning buoy and a shuttle tanker, wherein the underwater wellhead module, the underwater processing module and the oil-water replacement underwater oil-storage module are all arranged at the seabed and are connected in series; the dynamic positioning buoy floats on the water surface; one end of the deepwater upright tube is connected with the underwater storage module, and the other end is connected with the dynamic positioning buoy; and the shuttle tanker is tied and parked on the dynamic positioning buoy when the oil is filled. The device can replace a floating production system to develop the offshore oil in the deep sea, basically avoid the ice force, the wind wave force and the ...

Protective circuit for locking single particle

The invention discloses a protection circuit for single event latchup, relates to a single event latchup prevention protection of a CMOS device under a space radiation environment and belongs to the field of radiation electronics. The invention comprises a switch triode, a current sensor, a trigger, a voltage comparator, a resistor and a capacitor. The switch triode is adopted for supplying powerto the device; the current sensor and the voltage comparator are utilized for carrying out the real-time monitoring of the current in a power supply loop; when an abnormal strong current which is different from the normal working current of the device appears in the circuit, the voltage comparator immediately closes an input power supply of the device through a feedback loop; and when the abnormal strong current in the circuit disappears, the feedback loop is disconnected, and the normal power supply of the device is recovered. The protection object of the invention is used by common grounding, ...

Experimental method for single event effects (SEE) of pulse width modulator (PWM)

The invention discloses an experimental method for single event effects (SEE) of a pulse width modulator (PWM) and belongs to the technical field of space radiation effects and hardening. The method comprises the following steps of: numbering test samples; inserting the numbered test samples into a board, wherein a tested circuit board moves in accordance with a movable bracket; performing a power-on test on a test system; starting a radiation source; in a radiating process, monitoring the single event effects of the tested samples in real time by using a monitoring system; monitoring the fluence rate of incident particles in real time by using a beam monitoring system; and recording the number of the single event effects, the electrical parameters of the samples and the radiation time. The method can realize an evaluation test on the anti-SEE performance of a PWM device and obtain a single particle LET threshold or an energy threshold or a sigma-LET or E curve of the PWM device.

Speed control device and speed control method for flux leakage detector of oil pipeline

The invention provides a speed control device and a speed control method for a flux leakage detector of an oil pipeline. The speed control device for the flux leakage detector consists of a tachometer generator, a controller, a fixed disc, a mile wheel, a driving leather cup and solenoid valves, wherein the mile wheel is arranged on the flux leakage detector of the oil pipeline and is connected with one end of the tachometer generator; the other end of the tachometer generator is connected with the controller through a data wire; the controller is connected with the fixed disc through a data wire; eight solenoid valves are arranged on the fixed disc; and the driving leather cup is arranged at the tail end of the flux leakage detector of the oil pipeline and is connected with a flange in the middle of the fixed disc. The speed control device and the speed control method can eliminate the influence on the flux leakage detector of the oil pipeline caused by the unstable flow rate of a liquid ...

Method of storage system with multi-sever to obtain IP address of embedded memory controller

The present invention discloses a method of storage system with multi-sever to obtain IP address of embedded memory controller, belonging to the technical field of system with multi-server and storage controller, wherein a server storage system comprises a storage controller and a management module of a server; the management module manages and controls the storage controller, and the management module is responsible for the management of whole server storage system; the onboard EEPROM of the storage controller acts as a medium for storing the IP address of the storage controller; the storage controller stores the changed IP address into the onboard EEPROM; the interface program of the total management module reads the content of the onboard EEPROM to obtain a new IP address. Compared with the prior art, the method of storage system with multi-sever to obtain IP address of embedded memory controller of the present invention is simple and feasible; besides the IP address, other information ...

Method for improving soft RAID (redundant array of independent disk) performance based on Loongson processor

The invention provides a method for improving soft RAID (redundant array of independent disk) performance based on a Loongson processor. The method structurally comprises a Loongson processor, the method comprises following particular implementation processes: firstly connecting a RAID control card with a PCIE (Peripheral Component Interconnect Express) slot of a North bridge chip; and then connecting at least one SATA (serial at attachment) hard disk on the RAID control card in a hanging way; connecting the North bridge chip with a South bridge chip and the loongson processor so as to realize soft RAID function of the system. Compared with the prior art, the method has a simpler and more convenient overall process, only one level route is required to realize interactive communication with the loognson processor, thus, the storage efficiency for configuring soft RAID can be improved remarkably and the method has good promotion and use values.

Disturbance-prevention small unmanned aerial vehicle

The invention relates to a disturbance-prevention small unmanned aerial vehicle, which comprises wings and ailerons, the ailerons are hinged at the sides of the wings, the connection at the hinged position of the upper planes of the wings and the ailerons adopts a Kevlar connecting belt, the connection at clutching position the lower planes of the wings and the ailerons adopts a semi-cambered surface. In the invention, the wings and the ailerons are connected by Kevlar materials so as to realize seamless connection, reduce the air disturbance phenomenon of the surface of the wings on the fly, and be more stable for the flying status; and the lower planes of the wings and the ailerons are connected by adopting arc or an involuted semi-cambered surface, so that the whole unmanned aerial vehicle has light weight and large connection strength, can be folded more than ten thousands of times, and effectively prolongs the service life.

Petroleum pipeline detecting system

The invention provides a petroleum pipeline detecting system which comprises an excitation device, a detecting device, a mileage wheel, a data processing unit, a pipe internal and external data transmission device based on an ultra-low frequency electromagnetic pulse emitter, a low frequency signal emitter based on 22Hz, a low frequency signal receiver based on 22Hz, a driving device, a speed control device, a receiving sensor array, and a data analyzing unit. The system guarantees the stable running of a petroleum pipeline detector by installing a supporting wheel below the pipe internal andexternal data transmission device based on the ultra-low frequency electromagnetic pulse emitter, reduces the situation that detects of the pipeline are undetected by installing the speed control device, improves the locating precision of the pipeline defects by installing a pipe external defect locating device of the low frequency signal generator based on 22Hz, is beneficial to timely finding out ...

Method for programming serial periphery interface (SPI) FLASH

The invention discloses a method for programming a serial periphery interface (SPI) FLASH, and belongs to the technical field of SPI FLASH. The structure used in the method comprises the SPI FLASH, an SPI programming module and a personal computer (PC), wherein the SPI programming module comprises a field programmable gate array (FPGA) chip and a universal serial bus (USB) buffer; an SPI master controller and a USB slave controller are arranged in the FPGA chip; and the USB buffer of the SPI programming module receives the data transmitted from the PC and transmits the data to the USB slave controller; then the FPGA chip transmits the data received from the USB slave controller to the SPI master controller; and the SPI master controller writes the data into the SPI FLASH. The method for programming the SPI FLASH greatly accelerates the programming speed of the FLASH and saves development time.

Special-purposed cellular composite material used for small unmanned air vehicle

The invention relates to a special-purposed cellular composite material used for a small unmanned air vehicle (UAV). The material is a layered material comprising surface panels and a cellular interlayer, which are bound by a binding agent. The surface panels comprise an outer surface panel and an inner surface panel. The layered composite structure is composed of the outer surface panel, the cellular interlayer and the inner surface panel. The outer surface panel is composed of orderly arranged layers of an epoxy overprint varnish layer, a surface paint layer and an outer glass fiber layer. The inner surface panel is composed of orderly arranged layers of an inner glass fiber layer and a carbon fiber blended fabric layer. The cellular interlayer is fixed between the outer glass fiber layer of the outer surface panel and the inner glass fiber layer of the inner surface panel. The layers are bound by thermosetting resin with a mold. After the materials are solidified, a finished product ...

Modular quickly-spliced unmanned aerial vehicle

The invention relates to a modular quickly-spliced unmanned aerial vehicle. The unmanned aerial vehicle comprises a left wing module, a hatch module, a vertical module, a body module, a parachute cabin module and a right wing module which are connected with one another through uniformly distributed latch devices, wherein each latch device consists of a latch seat and a locking column; and the latch devices are fixedly arranged on interconnected module materials respectively, and one latch device is a locking latch device. The main constituent parts of the unmanned aerial vehicle are subjectedto modular manufacturing, so that smallest volume can be realized for packaging, vehicle-mounted space is increased, and transportation is facilitated; meanwhile, the modular parts are subjected to standardized manufacturing, so that easily damaged parts can be quickly supplemented, installed and used, can be quickly assembled and disassembled and accurately matched when a task is executed, and can ...

Hydraulic lifting straightening guiding device for marine self-elevating platform

The utility model relates to a hydraulic lifting straightening guiding device for marine self-elevating platform, which comprises a platform supporting pole, a platform lifting cylinder, a lifting ring beam, upper and lower hydraulic pins and a lower fixed ring beam; the straightening guiding sleeve is sleeved out of the platform supporting pole; the lifting ring beam is sleeved out of the straightening guiding sleeve and is fixed with the straightening guiding sleeve; the lower fixed ring beam is also sleeved out of the platform supporting pole; the lifting ring beam is connected with the lower fixing ring beam through the platform lifting cylinder; the lower fixed ring beam is fixed to the platform body; the platform supporting pole and the straightening guiding sleeve are provided with matched pin holes; the hydraulic pins are uniformly arranged around the lifting ring beam and the lower fixed ring beam; and a straightening adjusting roller set is mounted out of the straightening guiding ...

Soil curing agent and using method thereof

The invention discloses a soil curing agent, which comprises the following components in part by weight: 1 part of fluidized bed fire coal sulphur-fixing ash, 0.1 to 0.3 part of portland cement, 0.2 to 0.6 part of water quenching blast furnace slag, 0.1 to 0.5 part of active mineral admixture, 0.05 to 0.1 part of active exciting agent and 0 to 0.3 part of hydroxides of alkali metals or alkaline-earth metals. By using the curing agent of the invention, soil has high strength, water stability and volume stability, so the curing agent is not inferior to ordinary portland cement under the same condition, and has the characteristics of high early strength, large development potential of long-term strength, convenient construction, high durability and the like; and simultaneously, the curing agent is convenient to prepare, can dissolve industrial waste residues such as sulphur-fixing ash and the like which cannot be recycled at present, reduces the cost and is favorable for protecting environment ...

Method for transmitting very low frequency signal of oil-vapor pipe magnet leakage detector

The invention provides a method for transmitting the very low frequency signal of an oil-vapor pipe magnet leakage detector. A pipe inner part is driven by a driving device to move at constant speed in an oil-vapor pipe; the magnet leakage data detected by a magnetic sensor detecting unit is sent to a data processing unit to be subjected to classification, compression and defect quantification and then is stored temporarily; the magnet leakage data which is stored temporarily and the mileage wheel count are transmitted to a microcontroller in a SCM at set intervals; after being subjected to power amplification and DA conversion, the magnet leakage data and the mileage wheel count are transmitted into a transmitting coil, and different types of data in the oil-vapor pipe is outputted; the electromagnetic pulse is received by a magnetic-induction receiving antenna set, after the voltage of the electromagnetic pulse is extracted and is sent to a data decompressing unit, the data in the oil-vapor ...

Method for oxidizing unsaturated conjugated enol

The invention relates to a method that a compound which contains conjugated unsaturated enol is oxidized into a conjugated unsaturated ketene compound. Ketone or aldehyde is used as an oxidizer, and the compound which contains the conjugated unsaturated enol is oxidized under the action of an alcohol aluminum catalyst. The target products which are obtained by adopting the method have high yield rate, the operation is simple and convenient, and the cost is low. The conjugated double bonds are not damaged, in addition, the chirality which is needed by the obtained products is also ensured.

Method for producing electrolytic manganese metal

The invention relates to a method for producing electrolytic manganese metal. The method has the following characteristics that: silicomanganese slag replacing manganese carbonate ore is leached in multiple stages, that is, in the first stage of leaching, anolyte enough for the reaction of materials is poured into a combination tank, concentrated sulfuric acid and the silicomanganese slag are then added, in the second stage and each of the rest stages of leaching, the filtrate produced by filter pressing in the previous stage of leaching is first poured into the combination tank, the anolyte is then replenished, the concentrated sulfuric acid and the silicomanganese slag are then added, so that Mn 2 plus in the slag can be extracted, the produced manganese sulfate enters solution, and after the manganese concentration required by catalysis is reached, processes, such as deironization, desiliconization, neutralization, purification and electrolysis, are sequentially carried out, so that ...

Method and structure for collecting tiny dust particles

The invention discloses a method and structure for collecting tiny dust particles and provides a method and structure for collecting tiny dust particles from a spacecraft orbit environment. By adopting the method, the charge-mass ratio of tiny dust particles can be measured quantitatively under the condition of simulating the spacecraft orbit environment, and the national mass in-situ monitoring sensitivity is increased to 1.10*10<-9> to 4.42*10<-9> g/cm<2>; a dust particle charge-mass ratio testing instrument is simple in structural design and mainly comprises a circular grid plate, a hollow cylindrical capacitor and a QCM (Quartz Crystal Microbalances), so that the accuracy of measured data is greatly increased in the testing process and the load using risk of a spacecraft orbit is lowered; in the method, the hollow cylindrical capacitor is used, the design size of the instrument is reduced and a signal acquisition circuit and an assembly box are used, so that the charge-mass ratio of ...

Method for determining thickness of single-event sensitive volume of device

The invention relates to a method for determining the thickness of single-event sensitive volume of a device, which belongs to the fields of space radiation effects and reinforcement technology. The method comprises the steps of calculating deposited energy of laser in the sensitive volume, and generating single event effects when deposited charges of the laser in a sensitive volume unit of the device achieve or exceed the critical charges of the device, wherein the critical charges of the single-event effects under different pulsed laser wavelengths are the same; and the laser of a laser simulation system is used for inducing, obtaining energy threshold data of the single-event effects and further obtaining the thickness of the sensitive volume (Sv) of the single-event effects. The method has no radiation injury to the device and laboratory staff, very simple operation, low cost and capability of precisely measuring the thickness of the sensitive volume of the device.

Overdrive clutch reversing zero energy consumption starting-up pumping unit

The invention provides a starting oil extractor featuring overrunning clutch reversing and zero energy consumption, comprising a base, an electric motor, an overrunning coupling, a drive system, a pin rack, a stander, a switch rod, a reversing system, a guider, a roller mechanism and a suspension system; wherein, the motor, the stander and the drive system are respectively fixed on the chassis; the output end of the motor is connected with the overrunning coupling which is connected with the drive system; the lower part of the switch rod is fixed on the drive system and the upper part thereof is connected with the top of the stander by a lower guider, the reversing system and an upper guider; the roller mechanism is fixed on the top of the stander; the suspension system rounds the roller mechanism. The oil extractor has the advantages that the structure is reasonable, upper and lower travel switches are collided to control the forward and reverse running of the motor to realize stroke reversing ...

Continuous refining separation device and method for coal gasification crude phenol

The invention discloses a continuous rectification separation device and a continuous rectification separation method for coal gasification crude phenol. The device comprises a first-level pretreatment acidifying unit consisting of a film scraping evaporator, a primary acid regulating tank group and a buffer tank, a second-level pretreatment oxidizing unit consisting of a static mixer and a secondary acid regulating tank and a rectifying tower system consisting of a deslagging tower, a dehydrating tower, a phenol refining tower, an o-cresol refining tower and a m, p-cresol refining tower, wherein the first-level pretreatment acidifying unit is connected with the phenol deslagging tower; and the phenol deslagging tower is connected with the second-level pretreatment oxidizing unit and is connected with each rectifying tower system respectively. By the device and the method, the raw material of the coal gasification crude phenol is subjected to decoloration, deodorization, desulfuration, ...

Device for cleaning contaminants on surface of spherical Langmuir probe

The invention discloses a device for cleaning the contaminants on the surface of a spherical Langmuir probe, comprising a hollow spherical Langmuir probe, a cleaning halogen lamp, a ceramic halogen lamp bracket, a coaxial lead for the power supply of the cleaning halogen lamp, a temperature measuring resistor, a coaxial lead for supplying power to the temperature measuring resistor, a hollow columnar spherical Langmuir probe bracket, a ceramic insulating base, a temperature measuring power supply interface and a cleaning halogen lamp power supply interface. One end of coaxial lead for the power supply of the cleaning halogen lamp penetrates through hollow columnar spherical Langmuir probe bracket and the ceramic halogen lamp bracket and is connected with the cleaning halogen lamp, and the other end is connected with the power supply of the cleaning halogen lamp; the temperature measuring resistor is adhered to the surface of the hollow cavity of the spherical Langmuir probe; one end of ...

Speed control device and speed control method for flux leakage detector of oil pipeline

The invention provides a speed control device and a speed control method for a flux leakage detector of an oil pipeline. The speed control device for the flux leakage detector consists of a tachometer generator, a controller, a fixed disc, a mile wheel, a driving leather cup and solenoid valves, wherein the mile wheel is arranged on the flux leakage detector of the oil pipeline and is connected with one end of the tachometer generator; the other end of the tachometer generator is connected with the controller through a data wire; the controller is connected with the fixed disc through a data wire; eight solenoid valves are arranged on the fixed disc; and the driving leather cup is arranged at the tail end of the flux leakage detector of the oil pipeline and is connected with a flange in the middle of the fixed disc. The speed control device and the speed control method can eliminate the influence on the flux leakage detector of the oil pipeline caused by the unstable flow rate of a liquid ...

Test method of single event effect of pulse width modulator (PWM)

The invention relates to a test method of a single event effect of a pulse width modulator (PWM), belonging to the technical field of space radiation effect and reinforcement. The test method comprises the following steps of: firstly monitoring the output pulse loss phenomenon caused by single event upset in a test; then counting 50MHz pulse signals by taking a PWM output high level as a gate control signal, calculating the time of the high level in the measurement period, and finally calculating the duty ratio output by the PWM by using a microprogrammed control unit (MCU); monitoring an uploading upper computer; comparing an output signal amplitude with an output pulse signal amplitude of the PWM, and uploading a monitoring result to the upper computer; recording the output frequency ofthe PWM which is not a twice relation with the clock frequency by a counter, transmitting into the MCU for monitoring, and uploading to the upper computer; and counting the pluses in a certain standard ...

Display window size-adjustable KVM over IP method

The invention discloses a display window size-adjustable KVM over IP method, which belongs to the technical field of remote management control over blade servers. In the method, a display chip, a compression module and a remote personal computer (PC) are structurally involved, wherein the display chip samples red, green and blue (RGB) signals of the server, and finishes the A/D conversion, amplification and reduction of the RGB signals of the server; an operator of the remote PC can set an expected resolution in a WEB server page of the compression module according to the display condition of the used remote PC; the compression module informs the display chip after receiving a control signal of regulating the resolution from the remote PC through the network; and then the display chip amplifies or reduces the resolution of the RGB signals according to the control signal to make the resolution of the RGB signals consistent with the regulated resolution of the remote PC. Compared with the ...

Protective circuit for locking single particle

The invention discloses a protection circuit for single event latchup, relates to a single event latchup prevention protection of a CMOS device under a space radiation environment and belongs to the field of radiation electronics. The invention comprises a switch triode, a current sensor, a trigger, a voltage comparator, a resistor and a capacitor. The switch triode is adopted for supplying power to the device; the current sensor and the voltage comparator are utilized for carrying out the real-time monitoring of the current in a power supply loop; when an abnormal strong current which is different from the normal working current of the device appears in the circuit, the voltage comparator immediately closes an input power supply of the device through a feedback loop; and when the abnormal strong current in the circuit disappears, the feedback loop is disconnected, and the normal power supply of the device is recovered. The protection object of the invention is used by common grounding, ...

Method for transmitting very low frequency signal of oil-vapor pipe magnet leakage detector

The invention provides a method for transmitting the very low frequency signal of an oil-vapor pipe magnet leakage detector. A pipe inner part is driven by a driving device to move at constant speed in an oil-vapor pipe; the magnet leakage data detected by a magnetic sensor detecting unit is sent to a data processing unit to be subjected to classification, compression and defect quantification and then is stored temporarily; the magnet leakage data which is stored temporarily and the mileage wheel count are transmitted to a microcontroller in a SCM at set intervals; after being subjected to power amplification and DA conversion, the magnet leakage data and the mileage wheel count are transmitted into a transmitting coil, and different types of data in the oil-vapor pipe is outputted; the electromagnetic pulse is received by a magnetic-induction receiving antenna set, after the voltage of the electromagnetic pulse is extracted and is sent to a data decompressing unit, the data in the oil-vapor ...

Method for producing electrolytic manganese metal by lixiviating sinter ore by adding ferrous sulphate in replacement of manganese carbonate ore

The invention discloses a method for producing electrolytic manganese metal by lixiviating sinter ore by adding ferrous sulphate in replacement of manganese carbonate ore. The method comprises the working procedures of lixiviation and oxidation, neutralization, filtration, purification, electrolyzation and the like, and is characterized in that the process of lixiviation and oxidation is implemented by injecting anolyte enough to lead the material to react into the lixiviation vessel, adding concentrated sulfuric acid, adding sinter ore and finally adding ferrous sulphate for lixiviation for 3-4 hours at 70-75 DEG C; adding ammonia water immediately when Fe2+ in the feed liquid is less than or equal to 0.001g/l so as to carry out neutralization, testing the pH value of the feed liquid several times during the process of neutralization, and stopping adding ammonia water when full-valent Fe up to standard is less than or equal to 0.001g/l and the pH value reaches 6.8-7.2. The invention can ...

Underwater power device and coupling device connected to load

The invention provides a coupled device for connecting an underwater power pack and a load. The device comprises a magnet steel which is arranged on an output shaft of a power plant, a non-conductive housing which is covered outside the output shaft of the power plant and the magnet steel and is connected with a sealing housing of the power plant in a sealing way, a steel column which is fixed onthe non-conductive housing and a sleeve which is arranged on the steel column. When the power plant in loading is entwined or blocked by a barrier under water, the device can still work normally, thereby avoiding the damage of the power plant and guaranteeing the service life of the power plant. In the invention, the magnet coupling connection is adopted to solve the problem that the power plant is difficult to seal in water. The power plant and the retarder are arranged in the same sealing box so that the complex moving seal is not needed on the output shaft; and the research, development and production ...

Unmanned aerial vehicle power supply device

The invention provides an unmanned aerial vehicle power supply device which is suitable for the field of power supplies. The device comprises a power supply module, a digital steering engine voltage module, two constant voltage output modules and a variable voltage module, wherein the power supply module adopts lithium battery multipath output and independent filtration and respectively provides stable power supply for GPS (Global Positioning System) self-driving equipment and image/data equipment; the digital steering engine voltage module realizes double-path power supply voltage stabilizing filter output by using a double-combined voltage reducing chip and provides working voltage for a digital steering engine; the two constant voltage output modules directly supply power to airborne equipment by a filter circuit; and the variable voltage module provides voltage demands meeting different kinds of airborne equipment by the voltage reducing chip. In the invention, voltage is reduced by ...

NANOPORE-FACILITATED SINGLE MOLECULE DETECTION OF NUCLEIC ACID

The present invention provides a new and improved oligonucleotide detection method based on the nanopore technology with a probe containing a complementary sequence to the target oligonucleotide and a terminal extension at the probe's 3′ terminus, 5′ terminus, or both termini. The improved nanopore sensor with the probe enables sensitive, selective, and direct detection, differentiation and quantification of target oligonucleotides such as miRNAs. The inventive detection method may also be employed as a non-invasive and cost-effective diagnostic method for cancer detection based on miRNA levels in the patient's blood sample. 113-. (canceled)14. A method of detecting an oligonucleotide in a sample with a nanopore system , comprising the steps of:a) mixing a sample suspected of comprising a target oligonucleotide and a probe, said probe comprising a center domain with a complementary sequence to said target oligonucleotide and a terminal extension tagged to at least one of its 3′ and 5′ terminals, to produce a sample mixture wherein said central domain of said probe can hybridize to said target oligonucleotide,b) applying a voltage to said sample mixture in a cis compartment of a dual chamber nanopore system sufficient to drive translocation of said hybridized probe and target oligonucleotide through a nanopore of said system by an unzipping process, andc) analyzing an electrical current pattern in said nanopore system over time, wherein presence of said oligonucleotide in said sample is indicated by at least one signature electrical current block that is distinct from a background electrical current block that occurs with said sample alone or said probe alone.15. The method of claim 14 , wherein said signature electrical current block comprises at least one of a: i) a current block of different duration than a background current block; ii) a different number of distinct current blockade levels than a background current blockiii) a different order of occurrence of ...

Nanopore-Facilitated Single Molecule Detection of Nucleic Acids

The present invention provides a new and improved oligonucleotide detection method based on the nanopore technology with a probe containing a complementary sequence to the target oligonucleotide and a terminal extension at the probe's 3′ terminus, 5′ terminus, or both termini. The improved nanopore sensor with the probe enables sensitive, selective, and direct detection, differentiation and quantification of target oligonucleotides such as miRNAs. The inventive detection method may also be employed as a non-invasive and cost-effective diagnostic method for cancer detection based on miRNA levels in the patient's blood sample. 160-. (canceled)61. A method of detecting one or more target oligonucleotides in a sample with a nanopore system , the method comprising:combining the sample with a probe molecule that comprises a domain and a tag attached to the domain, wherein a sequence of the domain is complementary or partially complementary to a sequence of at least one of the target oligonucleotides, such that the probe molecule and the target oligonucleotide form a probe molecule-target oligonucleotide complex wherein the domain is hybridized to the target oligonucleotide;applying a voltage across a nanopore of the nanopore system to drive a portion of the probe molecule-target oligonucleotide complex at least partially inside the nanopore; andanalyzing an electrical current of the nanopore system over time, wherein a presence of the target oligonucleotide is indicated by a signature electrical current pattern corresponding to:(a) trapping the double-stranded molecule in a trans opening of the nanopore; or(b) detaching the target oligonucleotide from the probe molecule and translocating at least one of the probe molecule or the target oligonucleotide completely through the nanopore,the signature electrical current pattern comprising an electrical current having an amplitude and a duration respectively different from an amplitude and a duration of each of an electrical ...

POWER CONVERTER

A power converter includes a full-bridge conversion circuit. The full-bridge conversion circuit includes a first leg and a second leg. The first leg includes at least two switches coupled to each other at a first node, and the second leg includes at least two switches coupled to each other at a second node. The power converter further includes an AC filter. The AC filter includes a first inductor, a second inductor and a capacitor. The first inductor includes a first end coupled to the first node and a second end could be couple to a grid. The second inductor includes a first end coupled to the second node and a second end could be couple to the grid. The capacitor includes a first end coupled to the second end of the first inductor and a second end coupled to the second leg. The first end of the capacitor is electrically coupled to the second end of the first inductor during a cycle of an AC voltage of the grid. 1. A power converter , comprising: a first leg comprising a first high side switch and a first low side switch coupled to each other at a first node, and', 'a second leg comprising a second high side switch and a second low side switch coupled to each other at a second node; and, 'a full-bridge conversion circuit comprising a first inductor comprising a first end coupled to the first node and a second end coupleable to a grid,', 'a second inductor comprising a first end coupled to the second node and a second end coupleable to the grid, and', 'a capacitor comprising a first end coupled to the second end of the first inductor and a second end coupled to the second leg,, 'an AC filer, comprisingwherein the first end of the capacitor is electrically coupled to the second end of the first inductor during a cycle of an AC voltage of the grid.2. The power converter of claim 1 , wherein the second high side switch and the second low side switch are configured to be turned off during a time window around a zero crossing of the AC voltage claim 1 , and wherein the ...

SYSTEM AND METHOD FOR POWER CONVERSION

A system and a method for power conversion. The system includes a rectifier; an inverter; a DC-link capacitor coupled between the rectifier and the inverter; and a controller. The controller is configured to obtain a current value at an output of the inverter and a voltage value across the DC-link capacitor, determine an average component and a fluctuating component of an output voltage of the inverter based on the obtained current value and the voltage value, and determine a current reference for controlling the rectifier based on the average component and the fluctuating component of the output voltage. 1. A system comprising:a rectifier;an inverter;a DC-link capacitor coupled between the rectifier and the inverter; and obtain a current value at an output of the inverter and a voltage value across the DC-link capacitor,', 'determine an average component and a fluctuating component of an output power of the inverter based on the obtained current and voltage values, and', 'determine a current reference for controlling the rectifier based on the average component and the fluctuating component of the output power., 'a controller configured to2. The system of claim 1 , wherein the controller comprises a de-coupler configured to decouple the average component of the output power from the fluctuating component of the output power.3. The system of claim 2 , wherein the de-coupler comprises:a moving average filter (MAF) configured to output the average component of the output power based on the output power; andan adder coupled to the MAF and configured to output the fluctuating component by decreasing the average component from the output power.4. The system of claim 1 , wherein the controller comprises:a first controller unit configured to determine a first current from the average component of the output power; anda second controller unit configured to determine a second current from the fluctuating component of the output power.5. The system of claim 4 , wherein the ...

MEMORY

A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits. 1. A memory , comprising:a plurality of storage groups, wherein the plurality of storage groups are arranged along a first direction, each one of the storage groups comprises a plurality of banks, the plurality of banks are arranged along a second direction, and the first direction is perpendicular to the second direction;first signal lines extending along the first direction; wherein each one of the first signal lines is arranged correspondingly to more than one of the plurality of banks and is configured to transmit storage data of the more than one of the plurality of banks; andsecond signal lines extending along the first direction, each one of the second signal lines being arranged correspondingly to a respective bank and configured to transmit storage data of the respective bank;wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.2. The memory of claim 1 , wherein the first signal lines comprise a plurality of first metal lines with a same line width claim 1 , and the second signal lines ...

Vesicular adaptor and uses thereof in nucleic acid library construction and sequencing

Provided are a vesicular adaptor and a single-chain cyclic library constructed by using the adaptor. The library can be used for RNA sequencing and other sequencing platforms dependent on a single-stranded cyclic library, and has the advantage of high throughput sequencing, high accuracy and simple operations.

Interleaved Converter

Voltage converter circuits including a first and second branch. The first branch is coupled between a first DC terminal and a second DC terminal and includes a first and second winding around a magnetic core. The first and second winding are coupled to an AC terminal via a common node. The second branch is coupled in parallel to the first branch between the first and second DC terminals and includes a third winding around the magnetic core. The third winding is coupled to the AC terminal such that the first and second branches convert a first voltage into a second voltage. The first, second and third windings are configured to cause magnetic flux generated by a differential mode (DM) component of a first current in the first branch and magnetic flux generated by the DM component of a second current in the second branch to enhance with each other. 1. A voltage converter circuit , comprising:a first branch coupled between a first direct current (DC) terminal and a second DC terminal and including a first winding and a second winding around a magnetic core, the first winding and the second winding coupled to an alternating current (AC) terminal via a common node; anda second branch coupled in parallel to the first branch between the first and second DC terminals and including a third winding around the magnetic core, the third winding coupled to the AC terminal such that the first and second branches are configured to convert a first voltage into a second voltage;wherein the first, second and third windings are configured to cause magnetic flux generated by a differential mode (DM) component of a first current in the first branch and magnetic flux generated by the DM component of a second current in the second branch to enhance with each other.2. The voltage converter circuit of claim 1 , wherein the first claim 1 , second and third windings are configured to reduce magnetic flux caused by a common mode (CM) current to reduce inductance for the CM current.3. The ...

Touch detecting structure, touch display device and touch detecting and manufacturing methods

The invention discloses a touch detecting structure, an organic light emitting touch display device, a method of detecting a touch on a device and a method of manufacturing a device. The touch detecting structure includes: a first signal transmission line arranged on a first substrate of an organic light emitting touch display device; an insulating layer arranged on the first signal transmission line and having a via hole and a protrusion; a second signal transmission line located on the insulating layer and passing the top of the protrusion; a signal transmission terminal arranged on the lateral surface of the protrusion and having one end connected with the first signal transmission line through the via hole and the other end located on the top of the protrusion, and insulated from the second signal transmission line; and a cathode film arranged on a second substrate.

Output circuit and chip

The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limit on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.

Startup Method and Apparatus and Computer System

A startup method and apparatus, and a computer system. When a CPU fails to start a system, receiving, by a startup apparatus, a backup area selection instruction, where the backup area selection instruction is used to instruct the startup apparatus to read a boot loader from a backup area of Nand-Flash; receiving a program read instruction sent by the CPU, where the program read instruction includes a primary area address of the boot loader in the Nand-Flash; acquiring a backup address of the boot loader in the Nand-Flash from a correspondence between primary and backup addresses according to the primary area address; reading the boot loader from the backup address; and sending the boot loader to the CPU, such that the CPU starts the system according to the boot loader. 1. A startup method , comprising:receiving, by a startup apparatus, a backup area selection instruction when a central processing unit (CPU) fails to start a system, wherein the backup area selection instruction is used to instruct the startup apparatus to read a boot loader from a backup area of a memory, and wherein the memory is Nand-Flash;receiving a program read instruction sent by the CPU, wherein the program read instruction comprises a primary area address of the boot loader in the Nand-Flash;acquiring a backup address of the boot loader in the Nand-Flash from a correspondence between primary and backup addresses according to the primary area address, wherein the correspondence between primary and backup addresses comprises a correspondence between the primary area address and the backup address;reading the boot loader from the backup address in the Nand-Flash; andsending the boot loader to the CPU, such that the CPU starts the system according to the boot loader.2. The method according to claim 1 , wherein after acquiring the backup address of the boot loader in the Nand-Flash claim 1 , the method further comprises generating a backup program read instruction according to the backup address ...

Oscillator layout

An oscillator layout includes: a first row layout region constituted by sequentially arranging a second B layout region, second A layout region, third B layout region and third A layout region in parallel; and a second row layout region constituted by sequentially arranging a first A layout region, first B layout region, fourth A layout region and fourth B layout region in parallel. Inputs and outputs of the first A layout region, second A layout region, third A layout region and fourth A layout region constitute a first ring topology, inputs and outputs of the first B layout region and third B layout region constitute a second ring topology, inputs and outputs of the second B layout region and fourth B layout region constitute a third ring topology, the second ring topology and third ring topology are both electrically connected to the first ring topology.

POWER SUPPLY SYSTEM AND METHOD AND CIRCUIT USING THE SAME

A power supply system uses a DC-DC power converter () for supplying an output load. A compensation circuit () is connected between the input to the DC-DC converter and the output of the DC-DC converter and it provides a compensating path in response to a voltage drop at the output of the DC-DC converter caused by a surge in the output load. The power supply system further comprises a low drop out regulator () as the output load, which low drop out regulator () having an input connected to the DC-DC power converter and the compensation circuit, and an output connected to an output terminal (C) for connection to a further output load. This enables the DC-DC power converter to have a low current capability, because a large current demand can be met by the DC supply to the DC-DC converter. 1. A power supply system , comprising:a DC power source for generating a first DC output;a DC-DC power converter for generating a second DC output from the first DC output and providing the second DC output to a supply terminal of the power supply system for supplying an output load; anda compensation circuit connected between the first DC output and the supply terminal, the compensation circuit is adapted to provide power to the supply terminal from the first DC output in response to a voltage drop in the second DC output,wherein the power supply system further comprises a low dropout regulator as the output load, which low dropout regulator having an input connected to the supply terminal and an output connected to an output terminal for connection to a further output load;wherein said compensation circuit comprises:a switch between the first DC output and the supply terminal, and wherein the switch comprises a transistor arrangement having a base connection and an emitter connection which together control the switch state of the transistor, and the emitter connection connects to the supply terminal, and', 'wherein the control circuit comprises a voltage generating circuit which ...

INPUT BUFFER CIRCUIT, INTELLIGENT OPTIMIZATION METHOD, AND SEMICONDUCTOR MEMORY THEREOF

The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode. The single-end CMOS circuit may be configured to a process low-speed data transmission in the single-end CMOS input mode. 1. An input buffer circuit for a chip , comprising:a detection circuit configured to obtain a working frequency of the chip;a mode control circuit connected to the detection circuit and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode or a single-end complementary metal oxide semiconductor (CMOS) input mode;a double-end differential circuit connected to the mode control circuit and configured to process a high-speed data transmission in the double-end differential input mode; anda single-end CMOS circuit connected to the mode control circuit and configured to process a low-speed data transmission in the single-end CMOS input mode.2. The input buffer circuit according to claim 1 , wherein the detection circuit comprises:a first clock counter configured to receive and count a clock signal of the chip;a second clock counter configured to receive and count ...

Base-Pair Specific Inter-Strand Locks for Genetic and Epigenetic Detection

A versatile detection method is disclosed that utilizes a base-pair-specific inter-strand lock for genetic and epigenetic detection. Reagents, devices, etc., for implementing the method have also been discovered and/or developed. In certain embodiments, compounds have been identified to be able to specifically bind certain mismatched base pairs including T-T, U-T, and C-C base pair mismatches using either Hg or Ag. Such binding can strengthen the base-pair hybridization in orders of magnitude, forming a so-called reversible inter-strand lock that can greatly stabilize double-stranded nucleic acid fragments. 1. A method of detecting a thymine-thymine (T-T) base pair mismatch or a uracil-thymine (U-T) base pair mismatch in an at least partially double-stranded oligonucleotide (ds-oligonucleotide) , the method comprising: reversibly binding Hg to the base pair mismatch , thereby increasing the hybridization stability of the ds-oligonucleotide in comparison to its hybridization stability in the absence of Hg reversible binding , wherein the T-T or U-T base pair mismatch is within a contiguous region of at least 10 nucleotides that are hybridized in the ds-oligonucleotide; and detecting the increased hybridization stability of the ds-oligonucleotide , thereby detecting the T-T or U-T base pair mismatch.2. The method of claim 1 , the method comprising: (a) hybridizing a first single-stranded oligonucleotide to a second single stranded oligonucleotide to form the at least partially ds-oligonucleotide comprising the T-T or U-T base pair mismatch and (b) contacting the ds-oligonucleotide with Hg.3. The method of claim 2 , wherein the Hg is provided by the addition of HgCl.4. The method of claim 2 , wherein either the first single-stranded oligonucleotide or the second single-stranded oligonucleotide comprises a tag domain comprising a polydeoxycytosine covalently bound to the 3′-end claim 2 , the 5′-end claim 2 , or both the 3′-end and the 5′-end of the hybridizing region.5. ...

Vehicle and method for activating voice control function of mobile phone

A method for activating a voice control function of a mobile phone communicating with and carried in a vehicle is provided. The method includes the following steps. A sensing unit arranged in the vehicle senses a real-time speed of the vehicle when the vehicle is moving. A processor of the vehicle determines whether a real-time speed of the vehicle exceeds a predefined speed according to the sensed real-time speed of the vehicle. The processor controls the mobile phone to activate the voice control function of the mobile phone if the speed of the vehicle exceeds a predefined speed. A vehicle using the method is also provided by the present disclosure.

APPARATUS FOR CONVERSION BETWEEN AC POWER AND DC POWER

An apparatus for conversion between AC power and DC power. The apparatus includes: a first power conversion circuit having a first AC side and a DC side, at least one second power conversion circuit each having a second AC side and sharing the DC side with the first power conversion circuit, and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein: the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit. Moreover, the choke includes: a first common-mode choke and a first differential-mode choke, wherein: the first common-mode choke and the first differential-mode choke are electrically coupled in series via a first group of coil ends of the first common-mode choke and a first group of coil ends of the first differential-mode choke, and a second group of coil ends of one of the first common-mode choke and the first differential-mode choke are electrically coupled to the first terminal of the choke, and a second group of coil ends of the other are respectively electrically coupled to the second terminal and the at least one third terminal of the choke. The first common-mode choke can help provide high inductance to the high-frequency components of the common-mode current, which flows from the AC power source, since the impedance of the common-mode choke and the differential-mode choke depends on frequency on the same scale as inductance. The advantages of using the common-mode choke is that it provides twice the inductance of separate inductor design due to the coupling effect. Therefore it filters the common-mode current more effectively on the inductance size can be reduced for a given current ripple requirement. 1. An apparatus for conversion ...

POWER SUPPLY CELL AND POWER SUPPLY SYSTEM USING THE SAME

An objective of the present application is to to provide a power supply cell of a power supply system and a power supply system using the same. The power supply cell includes a first power conversion circuit operative to output a first DC voltage across its first output positive terminal and first output negative terminal, a second power conversion circuit operative to output a second DC voltage across its second output positive terminal and second output negative terminal, a first controllable unidirectional semiconductor switch operative to generate a first conduction path from the first output positive terminal of the first power conversion circuit to the second output negative terminal of the second power conversion circuit, a first unidirectional semiconductor switch operative to generate a second conduction path from the first output positive terminal of the first power conversion circuit to the second output positive terminal of the second power conversion circuit, a second unidirectional semiconductor switch operative to generate a third conduction path from the first output negative terminal of the first power conversion circuit to the second output negative terminal of the second power conversion circuit, a first low-pass filter and a controlling unit operative to issue turn-on signal or turn-off signal to the first controllable unidirectional semiconductor switch so that the first power conversion circuit and the second power conversion circuit supply current to the low-pass filter via the first conduction path or both of the second conduction path and the third conduction path. The first low-pass filter can help smooth the power supply cell's output voltage and current in order to achieve a relatively wide linearly constant output power range. By controlling the ration of series and parallel connection in a switching cycle of the switching frequency by the switching arrangement, both the output voltage and current range of the power supply cell can be ...

POWER SUPPLY CELL AND POWER SUPPLY SYSTEM USING THE SAME

An objective of the disclosure is to provide a power supply cell of a power supply system and a power supply system using the same. The power supply cell includes a first power conversion circuit operative to output a first DC voltage across its first positive terminal and first negative terminal, a second power conversion circuit operative to output a second DC voltage across its second positive terminal and second negative terminal, a first controllable unidirectional semiconductor switch operative to generate a first conduction path from the first positive terminal of the first power conversion circuit to the second negative terminal of the second power conversion circuit, a first unidirectional semiconductor switch operative to generate a second conduction path from the first positive terminal of the first power conversion circuit to the second positive terminal of the second power conversion circuit, a second unidirectional semiconductor switch operative to generate a third conduction path from the first negative terminal of the first power conversion circuit to the second negative terminal of the second power conversion circuit, a first low-pass filter, a second low-pass filter, a third low-pass filter and a controlling unit. The controlling unit is operative to: issue turn-on signal to the first controllable unidirectional semiconductor switch so that the first power conversion circuit and the second power conversion circuit supply current to the first low-pass filter via the first conduction path, the second low-pass filter and the third low-pass filter; or issue turn-off signal to the first controllable unidirectional semiconductor switch so that the first power conversion circuit and the second power conversion circuit supply currents to the first low-pass filter in parallel via the second conduction path and the second low-pass filter together with the third conduction path and the third low-pass filter. The first low-pass filter can help smooth an output ...

MULTILEVEL CONVERTER SYSTEMS AND METHODS WITH REDUCED COMMON MODE VOLTAGE

Multilevel converters and space vector modulation operating methods are presented in which fewer than all possible switching states are employed for space vector modulation of rectifier and inverter circuits to promote common mode voltage contribution cancellation or reduction therebetween and by using subsets of possible space vector modulation switching states associated with minimal positive or negative common mode voltages and in some cases using virtual vectors which have zero common mode voltages to eliminate the 3rd order harmonic components in common mode voltage as well as to reduce common mode voltage affects associated with multilevel inverter stages. 1. A power conversion system , comprising:a DC bus circuit comprising first and second DC bus terminals;a rectifier including a plurality of multilevel rectifier converter stages, individual ones of the multilevel rectifier converter stages comprising an AC input terminal adapted to receive AC input power from a corresponding one of a plurality of AC input phases, a pair of DC output terminals individually coupled to a corresponding one of the first and second DC bus terminals of the DC bus circuit, and a multilevel rectifier circuit operable according to a corresponding set of rectifier switching control signals to convert AC input power to provide a DC output voltage at the DC output terminals;an inverter including a plurality of multilevel inverter stages, individual ones of the multilevel inverter stages comprising a pair of DC input terminals individually coupled to a corresponding one of the first and second DC bus terminals of the DC bus circuit, an AC output terminal adapted to provide AC output power directly or indirectly to a corresponding one of a plurality of AC output phases to drive a load, and a multilevel inverter circuit operable according to a corresponding set of inverter switching control signals to convert DC input power from the DC bus circuit to provide an AC output voltage at the AC ...

MODULAR MULTILEVEL CONVERTER AND CHARGING CIRCUIT THEREFOR

Methods and charging apparatus are presented for charging cell capacitors of a multilevel power conversion system, in which an auxiliary charging source is selectively applied across DC bus terminals while one or more selected multilevel converter cells are alternately switched between a first state to bypass the selected cell or cells and a second state to charge the cell capacitor or capacitors of the selected cell via charging current from the auxiliary charging source. 1. A charging system for charging cell capacitors of a multilevel power conversion system , comprising: a charging source operative in a first mode to provide a DC voltage less than a nominal cell capacitor voltage of the multilevel power conversion system, and', 'at least one blocking component coupled in series with the charging source between the first and second DC bus nodes and operative in the first mode to allow charging current to flow from the charging source to cells of the multilevel power conversion system; and, 'a charging circuit coupled with first and second DC bus nodes of a multilevel power conversion system, the charging circuit comprisinga controller operative in the first mode to alternate switching states of at least one selected cell of the multilevel power conversion system between a first state to bypass the at least one selected cell and build up current flow in an inductor of the multilevel power conversion system), and a second state to charge at least one cell capacitor of the at least one selected cell.2. The charging system of claim 1 , wherein the individual cells of the multilevel power conversion system include first and second output terminals for connection with preceding and succeeding cells in a series circuit claim 1 , and wherein the controller is operative in the first mode to alternate the switching states of the at least one selected cell between the first state to bypass the at least one selected cell by coupling the first and second output terminals of ...

CHIP ASSEMBLY AND CHIP

Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units. 1. A chip assembly , comprising: a substrate , a first chip and a second chip stacked on an upper surface of the substrate , wherein the first chip is arranged above the second chip; whereina first pad pair comprising a first reference potential pad and a second reference potential pad are provided at edges of first sides of the first chip and the second chip, and a second pad pair comprising a first reference potential pad and a second reference potential pad are provided at edges of second sides of the first chip and the second chip;the second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units; anda differential between an orientation to the first side of the first chip and an orientation to the first side of the second chip is 180 degrees, and the first pad pair of the first chip corresponds in position to the second pad pair of the second chip.2. The chip assembly according to claim 1 , wherein a first reference potential is a positive electrode of a power source claim 1 , and a second reference potential is a ground potential.3. The chip assembly according to claim 1 , ...

Nanopore-Facilitated Single Molecule Detection of Nucleic Acids

The present invention provides a new and improved oligonucleotide detection method based on the nanopore technology with a probe containing a complementary sequence to the target oligonucleotide and a terminal extension at the probe's 3′ terminus, 5′ terminus, or both termini. The improved nanopore sensor with the probe enables sensitive, selective, and direct detection, differentiation and quantification of target oligonucleotides such as miRNAs. The inventive detection method may also be employed as a non-invasive and cost-effective diagnostic method for cancer detection based on miRNA levels in the patient's blood sample. 160-. (canceled)61. A method of detecting a first target oligonucleotide in a sample , the method comprising:combining the sample with a probe molecule, wherein the probe molecule comprises a terminal extension and a sequence that is fully complementary or partially complementary to the first target oligonucleotide, such that the probe molecule and the target oligonucleotide form a probe/target complex;applying a voltage across a nanopore system while the probe/target complex is on a first side of a partition of the nanopore system, the partition including an opening; andanalyzing an electrical current pattern in the nanopore system over time, wherein a presence of the first target oligonucleotide in the sample is indicated by a signature electrical pattern comprising three sequential levels of electrical current, each level having a duration and a current amplitude different from the other levels of the three sequential levels.62. The method of claim 61 , wherein the three sequential levels of the signature electrical pattern correspond to claim 61 , in sequential order claim 61 , a first level claim 61 , a second level claim 61 , and a third level claim 61 , and the duration of the first level is longer than either the duration of the second level or the duration of the third level.63. The method of claim 62 , wherein the duration of the third ...

METHODS AND SYSTEMS FOR DETERMINING AND USING A CONFIDENCE LEVEL IN SPEECH SYSTEMS

Methods and systems are provided for processing speech inputs for a controlling one or more vehicle systems of a vehicle. In one embodiment, a method includes: receiving speech input from an audio channel; performing, by a processor, speech recognition on the speech input to obtain recognized results; determining, by a processor, an accuracy level of the audio channel based on a comparison of the recognized results and predictive phraseology; determining, by a processor, an integrity level of the audio channel based on situational awareness information; communicating the recognized results, accuracy level, and the integrity level to a vehicle system; and selectively using the recognized results by the vehicle system based on the accuracy level and the integrity level. 1. A method of processing speech inputs for a controlling one or more vehicle systems of a vehicle , comprising:receiving speech input from an audio channel;performing, by a processor, speech recognition on the speech input to obtain recognized results;determining, by a processor, an accuracy level of the audio channel based on a comparison of the recognized results and predictive phraseology;determining, by a processor, an integrity level of the audio channel based on situational awareness information;communicating the recognized results, accuracy level, and the integrity level to a vehicle system; andselectively using the recognized results by the vehicle system based on the accuracy level and the integrity level.2. The method of claim 1 , wherein the determining the integrity level is performed based on the performance of the determining the accuracy level.3. The method of claim 2 , further comprising maintaining the accuracy level while updating the integrity level.4. The method of claim 3 , further associating a descriptive label with the integrity level claim 3 , and wherein the communicating further comprises communicating the descriptive label.5. The method of claim 4 , further comprising ...

Vesicular linker and uses thereof in nucleic acid library construction and sequencing

Provided are a vesicular linker and a single-chain cyclic library constructed by using the linker. The library can be used for RNA sequencing and other sequencing platforms dependent on a single-stranded cyclic library, and has the advantages of high throughput sequencing, high accuracy and simple operations. 1. An oligonucleotide vesicular adaptor for constructing a nucleic acid library , comprising:a 5′ paired double-stranded region at a first terminal of the adaptor, comprising a phosphorylated terminal base;a 3′ paired double-stranded region at a second terminal of the adaptor, comprising a sticky terminal; anda vesicular non-paired region between the 5′ paired double-stranded region and the 3′ paired double-stranded region,wherein the vesicular non-paired region comprises a first strand and a second strand non-complementary with each other and the first strand is of a length longer than that of the second strand.2. The oligonucleotide vesicular adaptor according to claim 1 , comprising a sense strand and an antisense strand and being of a structure of formula I from the 5′ terminal to the 3′ terminal:{'br': None, 'Y0-Y1-Y2\u2003\u2003(I)'}whereinY0 represents the 5′ paired double-stranded region, and is of a length of 10-15 nt;Y1 represents a non-paired double-stranded region, whose sense strand is of a length 5-30 nt longer than that of the antisense strand;Y2 represents the 3′ paired double-stranded region.3. A kit claim 1 , comprising:a container;an oligonucleotide vesicular adaptor for constructing a sequencing library for cyclic single-stranded nucleic acids, wherein the oligonucleotide vesicular adaptor is contained in the container;a first primer, specifically paring with the first strand of the vesicular non-paired region;a second primer, specifically paring with the second strand of the vesicular non-paired region; andan instruction.4. (canceled)5. A sequencing library for cyclic single-stranded nucleic acids constructed by the following steps of:(a) ...

AN OPTICAL STRUCTURE, LIGHTING UNIT AND A METHOD OF MANUFACTURE

An optical structure for processing the light output by a lighting unit, in which an antenna () is formed within or over an region () of the optical layer () of the structure, wherein the region () is away from the optical beam processing parts ()a of the optical layer (). 1. An optical structure for processing the light output by a lighting unit , comprising:an optical layer which is shaped to define a first beam processing structure for optically processing a light output, and said optical layer being with at least one region offset from the first beam processing structure; andan antenna formed over or within the at least one region.2. An optical structure as claimed in claim 1 , wherein the first beam processing structure comprises a lens.3. An optical structure as claimed in claim 1 , wherein the first beam processing structure comprises a reflector or diffuser.4. An optical structure as claimed in claim 1 , wherein the optical layer is formed of a plastics material.5. An optical structure as claimed in claim 4 , wherein the optical layer is formed of polycarbonate or PMMA.6. An optical structure as claimed in claim 1 , wherein the antenna is printed on the least one region of the optical layer.7. An optical structure as claimed in claim 6 , wherein the antenna is formed by 3D surface printing.8. An optical structure as claimed in claim 1 , wherein the at least one region is flat or curved.9. An optical structure as claimed in claim 1 , wherein the at least one region comprises a projection over an underlying base claim 1 , wherein the projection and base are optionally formed from a single shaped optical layer.10. A lighting unit claim 1 , comprising:a printed circuit board which carries circuit components;a lighting arrangement comprising at least one lighting unit on the printed circuit board; andan optical structure as claimed in any preceding claim provided over the lighting arrangement, wherein an electrical connection is provided between the antenna of ...

Diaminotriazoles useful as inhibitors of protein kinases

The present invention relates to inhibitors of protein kinases of formula I. The invention also provides pharmaceutical compositions comprising the compounds of the invention and methods of using the compositions in the treatment of various disorders.

OSCILLATOR AND CLOCK GENERATION CIRCUIT

Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed. 1. An oscillator , comprising:a first ring topology, comprising a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; anda second ring topology, comprising a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, whereinthe first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.2. The oscillator according to claim 1 , wherein a quantity of the first inverters is N claim 1 , and N is an integer greater than or equal to 4.3. The oscillator according to claim 2 , wherein a quantity of the second inverters is M claim 2 , and M is an integer greater than or equal to 2.4. The oscillator according to claim 3 , wherein an input terminal of each first inverter is denoted as a first node claim 3 , and the first ring topology has N first nodes; an input terminal of each second inverter is denoted as a second node claim 3 , and the second ring topology has M second nodes; and at least two second nodes are electrically connected to a corresponding quantity of the first nodes.5. The oscillator according to claim 4 , wherein the second transmission speed is greater than or equal to 0.5 times the ...

USEFUL DIAMINOTRIAZOLS AS INHIBITORS OF PROTEINQUINASES

La presente se refiere a diaminotriazoles útiles como inhibidores de proteinazas. También provee composiciones farmacéuticas que comprenden compuestos y métodos para usar dichas composiciones en el tratamiento de varios desórdenes. Reivindicación 1: Un compuesto de fórmula (1) o un sal farmacéutica aceptable de la misma, en la cual R1 es H o Y-R1, donde Y es una cadena de alquilideno opcionalmente sustituida C1-6 en la cual hasta dos unidades metileno están opcionalmente e independientemente reemplazada por -O-, -S-, -NR-, -OCO-, -COO-, o -CO-; cada ocurrencia de R es independientemente H o un grupo alifático C1-6 opcionalmente sustituido; y cada ocurrencia de R´ es independientemente H o un grupo opcionalmente sustituido seleccionado entre un grupo alifático C1-6, un anillo monocíclico de 3-8 miembros, saturado parcialmente insaturado o plenamente insaturado que tiene 0.3 heteroátomos independientemente seleccionados entre N, O, o S, o un anillo bicíclico de 8-12 miembros saturado, parcialmente insaturado plenamente insaturado que tiene 0-5 heteroátomos independientemente seleccionados entre N, O, o S; o R y R¨, son tomadas conjuntamente con el (los) átomo (s) a los cuales están ligada para formar un anillo monocíclico o bicíclico de 3-12 miembros opcionalmente sustituido, saturado, parcialmente insaturado o totalmente insaturado que tiene 0-4 heteroátomos seleccionados independientemente entre N, O, o S; R2 es -(T)nAr1, o -(T)uCy1, donde T es opcionalmente una cadena de alquilideno C14 opcionalmente sustituida donde una unidad metileno de T está opcionalmente reemplazada por -NR-, -S-, -O-, -CS-, -CO2, -OCO-, -CO-, -COCO-, -CONR-, -NRCO, -NRCO2-, SO2NR-, -NRSO2-, -CONRNR-, -NRCONR-, -OCONR-, -NRNR-, -NRSO2NR-, -SO-, -SO2-, -PO-, -PO2-, o -POR-; n es 0 o 1; Ar1 es un grupo arilo opcionalmente sustituido, seleccionado entre un anillo monocíclico de 5-6 miembros o un anillo bicíclico de 8-12 miembros que tienen 0-5 heteroátomos seleccionados independientemente ...

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR CHIP

The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

Electrostatic discharge protection network for chip

The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

DIAMINOTRIAZOLE DERIVATIVES AND THEIR USE AS PROTEIN KINASE INHIBITORS

Diaminotriazoles useful as inhibitors of protein kinases

An optical structure, lighting unit and a method of manufacture

An optical structure for processing the light output by a lighting unit, in which an antenna (30) is formed within or over an region of the optical layer (23) of the structure, wherein the region (34) is away from the optical beam processing parts (21) of the optical layer (23).

Inhibitors of tace

The present invention relates to compounds that inhibit TACE, compositions thereof, and methods of using those compounds and compositions for treating diseases.

Diaminotriazoles useful as inhibitors of protein kinases

Touch detecting structure, touch display device and touch detecting and manufacturing methods

The invention discloses a touch detecting structure, an organic light emitting touch display device, a method of detecting a touch on a device and a method of manufacturing a device. The touch detecting structure includes: a first signal transmission line arranged on a first substrate of an organic light emitting touch display device; an insulating layer arranged on the first signal transmission line and having a via hole and a protrusion; a second signal transmission line located on the insulating layer and passing the top of the protrusion; a signal transmission terminal arranged on the lateral surface of the protrusion and having one end connected with the first signal transmission line through the via hole and the other end located on the top of the protrusion, and insulated from the second signal transmission line; and a cathode film arranged on a second substrate.

System and method for power conversion

Power supply cell and power supply system using the same

It is an objective to provide a power supply cell of a power supply system and a power supply system using the same. The power supply cell includes a first power conversion circuit operative to output a first DC voltage across its first output positive terminal and first output negative terminal, a second power conversion circuit operative to output a second DC voltage across its second output positive terminal and second output negative terminal, a first controllable unidirectional semiconductor switch operative to generate a first conduction path from the first output positive terminal of the first power conversion circuit to the second output negative terminal of the second power conversion circuit, a first unidirectional semiconductor switch operative to generate a second conduction path from the first output positive terminal of the first power conversion circuit to the second output positive terminal of the second power conversion circuit, a second unidirectional semiconductor switch operative to generate a third conduction path from the first output negative terminal of the first power conversion circuit to the second output negative terminal of the second power conversion circuit, a first low-pass filter and a controlling unit operative to issue turn-on signal or turn-off signal to the first controllable unidirectional semiconductor switch so that the first power conversion circuit and the second power conversion circuit supply current to the low-pass filter via the first conduction path or both of the second conduction path and the third conduction path. The first low-pass filter can help smooth the power supply cell's output voltage and current in order to achieve a relatively wide linearly constant output power range. By controlling the ratio of series and parallel connection in a switching cycle of the switching frequency by the switching arrangement, both the output voltage and current range of the power supply cell can be enlarged smoothly and ...

Nanopore-facilitated single molecule detection of nucleic acids

Apparatus for conversion between AC power and DC power

An apparatus for conversion between AC power and DC power. The apparatus includes: a first power conversion circuit having a first AC side and a DC side, at least one second power conversion circuit each having a second AC side and sharing the DC side with the first power conversion circuit, and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein: the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit. Moreover, the choke includes: a first common-mode choke and a first differential-mode choke, wherein: the first common-mode choke and the first differential-mode choke are electrically coupled in series via a first group of coil ends of the first common-mode choke and a first group of coil ends of the first differential-mode choke, and a second group of coil ends of one of the first common-mode choke and the first differential-mode choke are electrically coupled to the first terminal of the choke, and a second group of coil ends of the other are respectively electrically coupled to the second terminal and the at least one third terminal of the choke. The first common-mode choke can help provide high inductance to the high-frequency components of the common-mode current, which flows from the AC power source, since the impedance of the common-mode choke and the differential-mode choke depends on frequency on the same scale as inductance. The advantages of using the common-mode choke is that it provides twice the inductance of separate inductor design due to the coupling effect. Therefore it filters the common-mode current more effectively on the inductance size can be reduced for a given current ripple requirement.

Diaminotriazoles useful as inhibitors of protein kinases

The present invention relates to inhibitors of protein kinases. The invention also provides pharmaceutical compositions comprising the compounds of the invention and methods of using the compositions in the treatment of various disorders.

Inhibitors of tace

The present invention relates to compounds that inhibit TACE, compositions thereof, and methods of using those compounds and compositions for treating diseases.

Nanopore-facilitated single molecule detection of nucleic acids

The present invention provides a new and improved oligonucleotide detection method based on the nanopore technology with a probe containing a complementary sequence to the target oligonucleotide and a terminal extension at the probe's 3' terminus, 5' terminus, or both termini. The improved nanopore sensor with the probe enables sensitive, selective, and direct detection, differentiation and quantification of target oligonucleotides such as miRNAs. The inventive detection method may also be employed as a non-invasive and cost-effective diagnostic method for cancer detection based on miRNA levels in the patient's blood sample.

Nanopore-facilitated single molecule detection of nucleic acids

The present invention provides a new and improved oligonucleotide detection method based on the nanopore technology with a probe containing a complementary sequence to the target oligonucleotide and a terminal extension at the probe's 3' terminus, 5' terminus, or both termini. The improved nanopore sensor with the probe enables sensitive, selective, and direct detection, differentiation and quantification of target oligonucleotides such as miRNAs. The inventive detection method may also be employed as a non-invasive and cost-effective diagnostic method for cancer detection based on miRNA levels in the patient's blood sample.

Input buffer circuit, intelligent optimization method, and semiconductor memory thereof

An input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof are provided. The input buffer circuit may include a detection circuit (110), a mode control circuit (120), a double-end differential circuit (130), and a single-end complementary metal oxide semiconductor (CMOS) unit (140). The detection circuit (110) may be configured to obtain a working frequency of a chip. The mode control circuit (120) is connected to the detection circuit (110), and configured to control, according to the working frequency obtained by the detection circuit (110), an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit (130) and the single-end CMOS circuit (140) are connected to the mode control circuit (120). The double-end differential input circuit (130) may be configured to process high-speed data transmission in the double-end differential input mode. The single-end CMOS circuit (140) may be configured to a process low-speed data transmission in the single-end CMOS input mode.

Apparatus for conversion between ac power and dc power

It is therefore an objective of the invention to provide an apparatus for conversion between AC power and DC power. The apparatus includes a first power conversion circuit having a first AC side and a first DC side, at least one second power conversion circuit each having a second AC side and a second DC side; and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit. Moreover, the choke includes a first common-mode choke and a first differential-mode choke, wherein: the first common-mode choke and the first differential-mode choke are electrically coupled in series via a first group of coil ends of the first common-mode choke and a first group of coil ends of the first differential-mode choke, and a second group of coil ends of one of the first common-mode choke and the first differential-mode choke are electrically coupled to the first terminal of the choke, and a second group of coil ends of the other are respectively electrically coupled to the second terminal and the at least one third terminal of the choke. The first common-mode choke can help provide high inductance to the high-frequency components of the common-mode current, which flows from the AC power source, since the impedance of the common-mode choke and the differential-mode choke depends on frequency on the same scale as inductance. The advantages of using the common-mode choke is that it provides twice the inductance of separate inductor design due to the coupling effect. Therefore it filters the common-mode current more effectively or the inductance size can be reduced for a given current ripple requirement.

Electrostatic discharge protection circuit for chip

The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.

Multilevel converter systems and methods with reduced common mode voltage

Diaminotriazoles useful as inhibitors of protein kinases

The present invention relates to inhibitors of protein kinases. The invention also provides pharmaceutical compositions comprising the compounds of the invention and methods of using the compositions in the treatment of various disorders.

Voltage converter

Embodiments of present disclosure relates to a converter. The converter comprises a first conversion unit, a second conversion unit, a switching circuit and a controller. The first conversion unit includes a first voltage source and a second voltage source, and is configured to generate a first voltage from an input voltage. The second conversion unit includes a third voltage source and a fourth voltage source, and is configured to generate a second voltage from the input voltage. The switching circuit is coupled to the first and second conversion units. The controller is coupled to the switching circuit, and is configured to in response to receiving an indication of voltage, cause the switching circuit to couple the first and second conversion units in parallel or in series, cause the first and second voltage sources in series or in parallel, and cause the third and fourth voltage sources in series or in parallel to generate a output voltage.

Catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones

One aspect of the present invention relates to a method for the catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones. The critical elements of the method are: a non-racemic chiral tertiary-amine-containing catalyst; a substrate selected from the group consisting of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones; and a silyl cyanide, e.g., trimethylsilyl cyanide. In preferred embodiments, the substrate is a ketone or aldehyde. A preferred embodiment of the present invention relates to practicing the method in a halocarbon solvent, e.g., chloroform. Another preferred embodiment of the present invention relates to practicing the method in an ester solvent, e.g., ethyl acetate. In certain embodiments, the methods of the present invention produce a silyl cyanohydrin with an enantiomeric excess greater than about 80%. In certain embodiments, the methods of the present invention produce a silyl cyanohydrin with an enantiomeric excess greater than about 90%.

Package structure as well as manufacturing method therefor, and semiconductor device

Embodiments of the present disclosure propose a package structure and a manufacturing method thereof, and a semiconductor device. The package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each of the vias exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each of the N first pads is formed by a respective part of the interconnection layer exposed by the corresponding via, where N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer covers and exposes part of area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad. The first pads and the second pads are used for testing when the semiconductor functional structure is at different running speeds respectively. The third pads are used for performing function interaction corresponding to the content tested by the second pad.

Package structure and method for manufacturing same, semiconductor device

A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.

Diaminotriazole derivate und deren verwendung als protein kinase inhibitoren

Oscillator and clock generation circuit

Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

Memory

Output circuit and chip

The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limit on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.

Method and apparatus for processing action of virtual object, and storage medium

A method and apparatus for processing an action of a virtual object, and a storage medium are provided. The method specifically includes: receiving an action instruction, the action instruction including: an action identifier and time-dependent information of performing an action associated with the action identifier; determining an action video frame sequence corresponding to the action identifier; determining, from the action video frame sequence, an action state image corresponding to a preset state image of the virtual object at a target time, the target time being determined according to the time-dependent information; generating a connection video frame sequence according to the action state image, the connection video frame sequence connecting the preset state image with the action video frame sequence; and splicing the connection video frame sequence with the action video frame sequence, to obtain an action video. Embodiments of this application can improve action processing efficiency of a virtual object.

Action processing method and apparatus for virtual object, and storage medium

An action processing method and apparatus for a virtual object, and a storage medium. The method specifically comprises: receiving an action instruction, wherein the action instruction may comprise: an action identifier and time-related information (101); determining an action video frame sequence corresponding to the action identifier (102); according to a preset state image of a virtual object at target time, determining, from the action video frame sequence, an action state image corresponding to the preset state image, wherein the target time can be determined according to the time-related information (103); according to the preset state image and the action state image, generating a connection video frame sequence, wherein the connection video frame sequence is used for connecting the preset state image and the action video frame sequence (104); and splicing the connection video frame sequence and the action video frame sequence to obtain an action video (105). By means of the method, the action processing efficiency for a virtual object is improved.

Clock generation circuit, memory, and clock duty cycle calibration method

Calibration circuit, memory, and calibration method

Clock generation circuit, memory and method for calibrating clock duty cycle

A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Circuit for controlling calibration, electronic device, and method for controlling calibration

A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.

Memory

Embodiments of the disclosure provide a memory, which includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. And the memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. Herein, the clock generation circuit is further configured to monitor at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range. According to the embodiments of the disclosure, the memory has a Duty Cycle Monitor (DCM) function and a Duty Cycle Adjust (DCA) function, and also can achieve detection and calibration on the differential input circuit.

Memory including clock generation circuit and duty cycle adjustment

A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Calibration circuit, memory and calibration method

A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.

變流器功率單元及其母線排

本案係關於一種變流器功率單元，包括：散熱器；n個功率開關模組，設置在該散熱器上；第一疊層母線排組，包括第一母線排和第二母線排；電容組，包括m個電容；以及第二疊層母線排組，包括第三母線排、第四母線排，第一母線排與第三母線排連接，第二母線排與第四母線排連接；n個功率開關模組構成的區域在第一平面上的垂直投影區域設為第一投影區域，電容組在第一平面上的垂直投影區域設為第二投影區域，第一投影區域與第二投影區域具有一交疊區域，其中第一平面為與電容組軸向相垂直的平面。本發明能夠減小變流器的換流回路中的雜散電感。

Catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones

One aspect of the present invention relates to a method for the catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones. The critical elements of the method are: a non-racemic chiral tertiary-amine-containing catalyst; a substrate selected from the group consisting of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones; and a silyl cyanide, e.g., trimethylsilyl cyanide. In preferred embodiments, the substrate is a ketone or aldehyde. A preferred embodiment of the present invention relates to practicing the method in a halocarbon solvent, e.g., chloroform. Another preferred embodiment of the present invention ,relates to practicing the method in an ester solvent, e.g., ethyl acetate. In certain embodiments, the methods of the present invention produce a silyl cyanohydrin with an enantiomeric excess greater than about 80%. In certain embodiments, the methods of the present invention produce a silyl cyanohydrin with an enantiomeric excess greater than about 90%.

Catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones

Catalytic asymmetric cyanosilylation of ketones, aldehydes, thioketones, thioaldehydes, imines and hydrazones

Memory

Control method and apparatus for clothing treatment device, and device and storage medium

Memory

A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

OLED display device and corresponding flexible printed circuit

An Organic Light-Emitting Diode (OLED) display device and a corresponding flexible printed circuit (FPC) are disclosed. The display device includes a first substrate and a second substrate arranged in opposition. In addition, frit is arranged on an inner side of the first substrate, and the display device also includes at least one bonding mark, where the bonding mark includes the frit, and at least one sub-bonding mark arranged on a surface of the first substrate. The at least one sub-bonding mark includes a first portion and a second portion arranged apart from each other, and the first portion and the second portion are arranged at an edge of the frit. The FPC includes at least one auxiliary bonding mark aligning the FPC to the OLED display device, where the at least one auxiliary bonding mark is aligned with the at least one sub-bonding mark of the OLED display device.

Comparator circuit, mismatch correction method, and memory

Single-loop memory device, double-loop memory device, and zq calibration method

The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver, where the first signal receiver is configured to receive a ZQ calibration command, the master chip starts calibration based on the ZQ calibration command, and the master chip sends a ZQ flag signal after completing the calibration; and the second signal receiver is configured to receive the ZQ flag signal, the slave chip starts the calibration based on the ZQ flag signal, and the slave chip sends the ZQ flag signal after completing the calibration.

Memory device and zq calibration method

The present disclosure provides a memory device and a ZQ calibration method, wherein the memory device comprises: two calibration resistor interfaces connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second master chip, and second slave chips, which are commonly connected to the ZQ calibration resistor; in a command mode, a first signal receiver is used to receive a ZQ calibration command, a second signal receiver is used to receive and delay the ZQ calibration command, the first master chip and the second master chip start to calibrate based on the ZQ calibration command, and after the calibration is completed, the first master chip and the second master chip send the ZQ flag signal through second transmission terminals; and the third signal receiver is used to receive the ZQ flag signal through a first transmission terminal, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and after the calibration is completed, the first slave chips and the second slave chips send a ZQ flag signal through second transmission terminals.

sistema de conversão de potência, e método para operar um sistema de conversão multifásico ac-ac

sistema de conversão de potência, e método para operar um sistema de conversão multifásico ac-ac. conversores de múltiplos níveis e métodos operacionais da modulação do vetor de espaço são apresentados nos quais menos do que todos os possíveis estados de comutação são empregados para a modulação do vetor de espaço dos circuitos do retificador e do inversor para promover o cancelamento ou redução da contribuição da tensão do modo comum entre eles e utilizando os subconjuntos de possível modulação do vetor de espaço estados de comutação associado com tensões do modo comum negativa ou positiva mínimas e em alguns casos utilizando vetores virtuais que têm tensões do modo comum zero para eliminar os componentes harmônicos de 3ª ordem na tensão do modo comum bem como para reduzir a tensão do modo comum afeta os associados com os estágios do inversor de múltiplos níveis.

Clock generation circuit, memory and method for calibrating clock duty cycle

A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Calibration control circuit, electronic device and calibration control method

Apparatus for conversion between ac power and dc power

It is therefore an objective of the invention to provide an apparatus for conversion between AC power and DC power. The apparatus includes a first power conversion circuit having a first AC side and a first DC side, at least one second power conversion circuit each having a second AC side and a second DC side; and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit. Moreover, the choke includes a first common-mode choke and a first differential-mode choke, wherein: the first common-mode choke and the first differential-mode choke are electrically coupled in series via a first group of coil ends of the first common-mode choke and a first group of coil ends of the first differential-mode choke, and a second group of coil ends of one of the first common-mode choke and the first differential-mode choke are electrically coupled to the first terminal of the choke, and a second group of coil ends of the other are respectively electrically coupled to the second terminal and the at least one third terminal of the choke. The first common-mode choke can help provide high inductance to the high-frequency components of the common-mode current, which flows from the AC power source, since the impedance of the common-mode choke and the differential-mode choke depends on frequency on the same scale as inductance. The advantages of using the common-mode choke is that it provides twice the inductance of separate inductor design due to the coupling effect. Therefore it filters the common-mode current more effectively or the inductance size can be reduced for a given current ripple requirement.

Fault-tolerant startup method and apparatus and computer system

Package structure, packaging method and semiconductor device

A package structure, a packaging method and a semiconductor device are provided. The method includes: providing a semiconductor functional structure, an interconnecting layer disposed on a surface of the semiconductor functional structure; forming an isolation layer exposing part of the interconnecting layer, the exposed part of the interconnecting layer acting as a first pad, and the first pad used for performing a first type test; after completing the first type test, forming a redistribution layer on the first pad and the isolation layer, the redistribution layer and the interconnecting layer electrically connected; and forming a first insulating layer exposing parts of the redistribution layer, the exposed parts of the redistribution layer acting as a second pad and a third pad, the second pad used for performing a second type test, and the third pad used for executing a functional interaction corresponding to contents of the second type test.

Packaging structure, packaging method, and semiconductor device

Electro static discharge circuit and memory

Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Memory device and zq calibration method

The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

Memory device and zq calibration method

A memory device includes: two calibration resistor interfaces connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second master chip, and second slave chips, which are commonly connected to the ZQ calibration resistor; in a command mode, a first signal receiver is used to receive a ZQ calibration command, a second signal receiver is used to receive and delay the ZQ calibration command, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and after the calibration is completed, the first slave chips and the second slave chips send a ZQ flag signal through second transmission terminals.

Memory device and zq calibration method

The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.

Interleaved converter

Power supply cell and power supply system using the same

A power supply cell of a power supply system including a first power conversion circuit to output a first DC voltage, a second power conversion circuit to output a second DC voltage, a first controllable unidirectional semiconductor switch to generate a first conduction path from the first power conversion circuit to the second power conversion circuit, a first unidirectional semiconductor switch to generate a second conduction path from the first power conversion circuit to the second power conversion circuit, a second unidirectional semiconductor switch to generate a third conduction path from the first power conversion circuit to the second power conversion circuit, a first low-pass filter, and a controlling unit operative to issue turn-on signal or turn-off signal to the first controllable unidirectional semiconductor switch to supply current to the low-pass filter via the first conduction path or both of the second conduction path and the third conduction path.

Electrostatic protection circuit and chip

An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.

Output circuit and chip

The present invention provides an output circuit and a chip. The output circuit includes a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit. The first-stage circuit is configured to read serial data in a memory and divide the serial data into first voltage signals each at a specified rate level; the second-stage circuit is configured to receive the first voltage signals, generate a plurality of second voltage signals; the third-stage circuit is configured to: allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal; and the fourth-stage circuit includes a pull-up circuit and a pull-down circuit, each including thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to generate output voltage signals of the output circuit. By eliminating the limitation on a minimum operating power supply voltage, different high-speed data output ports are compatible, thereby improving efficiency.

Output circuit and chip

Clock generation circuit, memory, and clock duty cycle calibration method

The embodiments of the application provide a clock generation circuit, a memory and a clock duty cycle calibration method; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range. The embodiments of the application may generate a first oscillation signal and a second oscillation signal with stable duty cycle that may be used for memory testing.

Clock generation circuit, memory, and clock duty cycle calibration method

Single-loop memory device, double-loop memory device, and zq calibration method

The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.

Package structure and method for manufacturing same, semiconductor device

A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.