APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value. 125-. (canceled)26. An apparatus for generating a digital value , the apparatus comprising:a generator for generating a digital value based on semiconductor process variation.27. The apparatus of claim 26 , further comprising:a freezing unit connected to the generator for freezing the digital value.28. The apparatus of claim 27 , wherein the freezing unit comprises a fuse.29. The apparatus of claim 28 , wherein the fuse is blown or un-blown to freeze the digital value.30. The apparatus of claim 29 , wherein the fuse is blown by an overcurrent.31. The apparatus of claim 29 , wherein the fuse is blown by an overvoltage.32. The apparatus of claim 29 , wherein whether the fuse is blown or un-blown is invariant over time.33. The apparatus of claim 29 , wherein a first state corresponds to the fuse being blown claim 29 , and a second state corresponds to the fuse being un-blown.34. The apparatus of claim 33 , wherein the first state corresponds to a digital value of 1 claim 33 , and the second state corresponds to a digital value of 0.35. The apparatus of claim 33 , wherein the first state corresponds to a digital value of 0 claim 33 , and the second state corresponds to a digital value of 1.36. The apparatus of claim 27 , wherein the freezing unit comprises a One-Time Programmable (OTP) device.37. The apparatus of claim 36 , wherein the OTP device is programmed to freeze the digital value.38. The apparatus of claim 37 , wherein the digital value programmed in the OTP device is invariant ...

APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers. 127-. (canceled)28. An apparatus for generating an identification key , the apparatus comprising:a key generator for generating an identification key based on whether a predetermined event occurs in a circuit.29. The apparatus of claim 28 , wherein the predetermined event comprises an open between nodes in the circuit.30. The apparatus of claim 28 , wherein the predetermined event comprises a short between nodes in the circuit.31. The apparatus of claim 28 , wherein whether a predetermined event occurs in a circuit is invariant over time.32. The apparatus of claim 28 , wherein whether a predetermined event occurs in a circuit comprises whether a short occurs between conductive layers of a semiconductor.33. The apparatus of claim 32 , wherein whether a short occurs between conductive layers of a semiconductor is invariant over time.34. The apparatus of claim 32 , wherein whether a short occurs between conductive layers of a semiconductor comprises whether a contact or a via between conductive layers of a semiconductor shorts the conductive layers.35. The apparatus of claim 34 , wherein whether a contact or a via shorts the conductive layers is invariant over time.36. The apparatus of claim 34 , wherein whether a contact or a via shorts the conductive layers is a function of a size of the contact or the via.37. The apparatus of claim 36 , wherein ...

ENCRYPTION DEVICE AND METHOD FOR DEFENDING A PHYSICAL ATTACK

Provided are a security device and a method for operating same. The security device may conceal an encryption key used for an encryption algorithm in an encryption module in correspondence to security attacks such as reading information on where the encryption key is stored in a memory by disassembling an IC chip, or extracting said information through microprobing. The encryption key may be included as a physical encryption key module in an encryption module, and a certain storage medium for storing the encryption key may be included in the encryption module. Accordingly, the encryption key is not transmitted via a bus in a security device for encryption. 1. An encryption device for executing an encryption algorithm using an encryption key as receiving an input data to be encrypted , the encryption device comprising:an encryption module, comprising an encryption key module to provide an encryption key, to execute the encryption algorithm using the encryption key provided by the encryption key module.2. The encryption device of claim 1 , wherein the encryption module comprises a plurality of encryption key modules to provide different encryption keys claim 1 ,wherein the encryption module comprises:an encryption key module selector to select one of the plurality of encryption key modules; andis an encryption unit to execute the encryption algorithm using an encryption key provided by the selected encryption key module.3. The encryption device of claim 2 , wherein the encryption key module selector selects an encryption key module corresponding to a pre-assigned identification index from among the plurality of encryption key modules.4. The encryption device of claim 2 , wherein the encryption module comprises a plurality of standard cells claim 2 , and the plurality of encryption key modules is disposed at random positions among layouts of the plurality of standard cells included in the encryption module.5. The encryption device of claim 1 , wherein:the encryption ...

Security Apparatus and Operation Method Thereof

Provided are a security apparatus and an operation method thereof. The security apparatus comprises a core circuit which performs a security function by using an authentication key such as a secret key provided by a physically unclonable function (PUF). The security apparatus may receive event information indicating that the security apparatus is in a security-vulnerable state such as a case where the security apparatus is stolen or lost. In such case, a power management circuit can apply at least one electrical shock of overvoltage and overcurrent to the security apparatus to cause physical damage to the security apparatus, so that the core circuit does not perform the security function normally.

Vehicle security network device and method for controlling same

A vehicle security network design device may comprise: a level assigning unit for assigning an automobile safety integrity level (ASIL) which provides a risk management standard for each of a plurality of functional elements in a vehicle that is at least temporarily implemented by a processor; a calculation unit for calculating device's controllability with respect to each of the plurality of functional elements on the basis of a connection structure between the plurality of functional elements and a difference value of the ASIL; and a management unit for generating a risk analysis model of a plurality of functional elements.

Apparatus and Method for Generating Identification Key

Provided is a PUF by which an identification key is generated according to a random event caused by a semiconductor process variation. The PUF can provide the identification key as a result of electrical differences among elements. According to one embodiment, the PUF can accumulate the electrical differences and/or instantaneous values without generating the identification key by using the instantaneous values caused by the electrical differences. The accumulation may be the accumulation of a discrete iteration and the result thereof. However, according to another embodiment, the accumulation may be a continuation of the accumulation result during time intervals.

APPARATUS FOR GENERATING IDENTIFICATION KEY AND MANAGEMENT METHOD THEREOF

Provided are an apparatus and a method for generating an identification key with improved reliability by: providing a plurality of resistances which are generated according to a random connection state between conductive layers of a semiconductor due to process variation of the semiconductor; discriminating a first group which has a resistance value greater than a first threshold value and less than a second threshold value among the plurality of resistances; and reading at least one resistance which does not belong to the first group out of the plurality of resistances and reading an identification key in the form of a digital value. 1. An identification key generation apparatus comprising:an identification key provider configured to provide a plurality of resistors generated based on a random connection state between conductive layers of a semiconductor due to a semiconductor process variation;a discriminator configured to discriminate a first group having a resistance value greater than a first threshold value and less than a second threshold value among the plurality of resistors; anda reader configured to read at least one resistor that does not belong to the first group among the plurality of resistors, and to provide an identification key in a form of a digital value.2. The identification key generation apparatus of claim 1 , further comprising:a controller configured to record, in a memory, information used to identify a resistor included in the first group among the plurality of resistors.3. The identification key generation apparatus of claim 2 , wherein the information used to identify the resistor included in the first group is an address of the resistor included in the first group among the plurality of resistors.4. The identification key generation apparatus of claim 1 , wherein the plurality of resistors are either vias or contacts located between the conductive layers.5. The identification key generation apparatus of claim 1 , wherein the ...

APPARATUS AND METHOD FOR GENERATING RANDOM DIGITAL VALUE

Provided is an apparatus for generating digital values to provide a random digital value. The apparatus may generate the digital value based on a semiconductor process variation. The apparatus may include a generating unit to generate a plurality of digital values, based on the semiconductor process variation, and a processing unit to process the digital values and to provide a first digital value. The generating unit may include a plurality of physically unclonable functions (PUFs). A parameter may be differently applied to the PUFs, and the PUFs may generate the digital values. 118-. (canceled)19. An apparatus for generating a digital value , the apparatus comprising:a generating unit to generate a plurality of digital values, the generating unit comprising a plurality of physically unclonable functions (PUFs), wherein a portion of the PUFs is implemented by applying at least one parameter causing a semiconductor process variation; and wherein at least one of the PUFs comprises a parameter formed between conductive layers in a semiconductor, and', 'wherein a range of the parameter selected from between a minimum value and a maximum value corresponding to whether the parameter causes a short between the conductive layers., 'a processing unit to process the digital values and to provide a first digital value,'}20. The apparatus of claim 19 , wherein at least one of the digital values is generated based on whether the parameter causes a short between the conductive layers.21. The apparatus of claim 19 , wherein the range of the parameter is determined prior to manufacturing the apparatus.22. The apparatus of claim 19 , wherein the processing unit selects claim 19 , as the first digital value among the digital values claim 19 , a digital value that satisfies a condition.23. The apparatus of claim 19 , wherein the processing unit selects claim 19 , as the first digital value among the digital values claim 19 , a value generated by a PUF in which the applied parameter ...

APPARATUS AND METHOD FOR PROCESSING AUTHENTICATION INFORMATION

Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key. 1. An information processing apparatus comprising:a physical unclonable function (PUF) to generate a first unique key as an unpredictable digital value based on electrical characteristics between nodes generated on a semiconductor element by a process variation in a semiconductor manufacturing process;a memory to store a second unique key; andan encryption processor to encrypt received data using one of the first unique key and the second unique key and store the data encrypted.2. The information processing apparatus of claim 1 , wherein the PUF generates the first unique key using whether a short or open occurs between nodes generated on a semiconductor element by a process variation in a semiconductor manufacturing process.3. The information processing apparatus of claim 2 , wherein the PUF generates the first unique key using whether an interlayer contact formed between conductive layers of a semiconductor short-circuits the conductive layers.4. The information processing apparatus of claim 3 , wherein the interlayer contact formed between the conductive layers of the semiconductor is formed to have a smaller size than that according to the design rule provided in the semiconductor manufacturing process.5. The information processing apparatus of claim 3 , wherein the PUF is configured to set the size of the interlayer contact formed between the conductive layers of the semiconductor such that a difference between a probability of the interlayer contact short-circuiting the conductive layers and a probability of the interlayer contact not short-circuiting the conductive layers is within a preset error range.6. The information processing apparatus of claim 2 , wherein the ...

Apparatus for Providing Puf-Based Hardware OTP and Method for Authenticating 2-Factor Using Same

Provided is an apparatus for generating a hardware-based OTP which is impossible to duplicate. The apparatus for generating the OTP can comprise a PUF for generating a unique PIN. In addition, provided is a method which is used for 2-Factor authentication with the apparatus for generating the OTP and existing secure elements. 1. An authentication apparatus comprising:a secure element to perform a first authentication process; anda hardware-based one-time password (OTP) generation element comprising a physically unclonable function (PUF) to generate an OTP and perform a second authentication process.2. The apparatus of claim 1 , wherein the hardware-based OTP generation element is disposed on a chip separate from the secure elements to have a die-chip wiring with the secure element claim 1 , and transmits the OTP externally through an input and output interface of the secure elements.3. The apparatus of claim 1 , wherein when a random number encrypted using a public key of the hardware-based OTP generation element is received from a certificate authority claim 1 , the hardware-based OTP generation element decrypts the random number using a private key corresponding to the public key and generated based on the PUF claim 1 , and generates the OTP using the decrypted random number.4. The apparatus of claim 3 , wherein when the public key is transmitted to the certificate authority claim 3 , the hardware-based OTP generation element encrypts the public key using a PUF-personal identification number (PIN) differing from the PUF and transmits the encrypted public key.5. The apparatus of claim 4 , wherein the hardware-based OTP generation element comprises a blocker used to extract the PUF-PIN before the authentication apparatus performs the second authentication process and is physically blocked after the extracting such that the PUF-PIN is not re-extracted.6. The apparatus of claim 1 , wherein the authentication apparatus is implemented in at least one of a subscriber ...

SEMICONDUCTOR CHIP AND METHOD FOR GENERATING DIGITAL VALUE USING PROCESS VARIATION

Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to a first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node. 1N unit cells to output a digital value of N bits, where N denotes a natural number,wherein each of the N unit cells includes a first element and a second element, andan output of the first element is connected to an input of a second element, and an output of the second element is connected to an input of the first element to constitute a feedback structure, andeach of the N unit cells generates a one-bit identification key due to an electrical characteristic value difference between the first element and the second element.. A semiconductor chip comprising: This application is a continuation of co-pending U.S. patent application Ser. No. 13/265,776, filed on Oct. 21, 2011, which claims priority from Korean Patent Application No. 10-2009-0035416, filed Apr. 23, 2009, whose contents are incorporated herein for all purposes.The following description relate to a semiconductor chip and a method of generating an identification key.Currently, with the development of technologies for electronic tags and the like, there has been an increasing need to insert a unique identification key into each of chips that are produced on a large scale. Accordingly, there is a need for a system and a method that may generate a digital value, for example, identification key, a ...

SECURE SYSTEM ON CHIP

Disclosed is a secure semiconductor chip. The semiconductor chip is, for example, a system-on-chip. The system-on-chip is operated by connecting normal IPs to a processor core included therein via a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is separately provided. Security IPs for performing a security function or handling security data are connected to the secure bus. The secure semiconductor chip can perform required authentication while shifting between a normal mode and a secure mode. 1. A semiconductor chip comprising:a processor core;a first group comprising elements connected to the processor core by a first bus; anda second group comprising elements connected to the processor core by a second bus and configured to operate in a secure mode.2. The semiconductor chip of claim 1 , wherein the second bus is physically separate from the first bus so that the second group is physically isolated from the first group.3. The semiconductor chip of claim 1 , wherein the second group processes data by using a memory address different from that of the first group.4. The semiconductor chip of claim 1 , wherein the processor core comprises a Core-A processor claim 1 , the Core-A processor being a 32-bit RISC (reduced instruction set computing) type embedded processor.5. The semiconductor chip of claim 4 , wherein the second bus comprises a hidden bus implemented by using an ASR (application specific register) of the Core-A processor as an address space for controlling elements included in the second group.6. The semiconductor chip of claim 5 , wherein the second group uses an MTA (move to ASR) command and an MFA (move from ASR) command in the secure mode for processing secure instructions claim 5 , the MTA command and the MFA command being commands for processing data in relation to the ASR.7. The semiconductor chip of claim 1 , wherein the processor core partitions a memory area into a code area and a data area and comprises ...

Vehicle security network device and method for controlling same

A vehicle security network design device may comprise: a level assigning unit for assigning an automobile safety integrity level (ASIL) which provides a risk management standard for each of a plurality of functional elements in a vehicle that is at least temporarily implemented by a processor; a calculation unit for calculating device's controllability with respect to each of the plurality of functional elements on the basis of a connection structure between the plurality of functional elements and a difference value of the ASIL; and a management unit for generating a risk analysis model of a plurality of functional elements.

IC Chip for Preventing Identification Key Leak and Authorization Method Thereof

Disclosed are an IC chip for preventing identification key leak and an authorization method thereof. An IC chip capable of performing a financial function includes: a PIN supply unit for supplying a PIN used for authorization when performing a financial function using the IC chip; and a blocking unit for physically blocking the gap between the PIN supply unit and an input-output interface when the PIN is supplied to the outside through the input-output interface at an initial access of the IC chip. 1. An integrated circuit (IC) chip to be used for performing a financial function , the IC chip comprising:a personal identification number (PIN) supply unit to supply a PIN to be used for authorization when performing the financial function using the IC chip;an input-output interface to transmit the PIN externally; anda blocking unit to physically block a connection between the PIN supply unit and the input-output interface when the PIN is transmitted externally through the input-output interface subsequent to the IC chip being initially accessed.2. The IC chip of claim 1 , wherein the blocking unit comprises at least one fuse and at least one switch to apply an overcurrent to each of the at least one fuse claim 1 , andwherein the overrcurrent is a current greater than or equal to a critical current and is able to melt the at least one fuse, andwherein, when the PIN is transmitted externally through the input-output interface subsequent to the IC chip being initially accessed, the at least one switch applies the overcurrent to the at least one fuse and physically blocks the connection between the PIN supply unit and the input-output interface.3. The IC chip of claim 1 , wherein the PIN supply unit comprises a physically unclonable function (PUF) providing the PIN using a semiconductor manufacturing process deviation.4. The IC chip of claim 1 , further comprising:an authorization unit to authorize use of the IC chip when a PIN received from a user matches the PIN supplied ...

APPARATUS AND METHOD FOR PROCESSING AUTHENTICATION INFORMATION

Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key. 1. An information processing apparatus comprising:a physical unclonable function (PUF) to generate at least one unique key as an unpredictable digital value; andan encryption processor to encrypt received data using the unique key to store the data encrypted.2. The information processing apparatus of claim 1 , wherein the PUF generates the unique key using whether a short or open occurs between nodes generated on a semiconductor element by a process variation in a semiconductor manufacturing process3. The information processing apparatus of claim 2 , wherein the PUF generates the unique key using whether an interlayer contact formed between conductive layers of a semiconductor short-circuits the conductive layers.4. The information processing apparatus of claim 3 , wherein the interlayer contact formed between the conductive layers of the semiconductor is formed to have a smaller size than that according to the design rule provided in the semiconductor manufacturing process.5. The information processing apparatus of claim 3 , wherein the PUF is configured to set the size of the interlayer contact formed between the conductive layers of the semiconductor such that a difference between a probability of the interlayer contact short-circuiting the conductive layers and a probability of the interlayer contact not short-circuiting the conductive layers is within a preset error range.6. The information processing apparatus of claim 2 , wherein the PUF comprises N unit structures to generate a 1-bit digital value using a pair of conductive layers and one interlayer contact connecting the conductive layers and generates N-bit unique keys through the N unit structures claim 2 , N ...

AUTHENTICATION APPARATUS AND METHOD

An interface element connected to a device and a security die-chip are fabricated in a single package. The security die-chip may provide a security authentication function to the interface element that does not have the security authentication function. The security die-chip may include a physically unclonable function (PUF) to provide a private key, and a hardware security module to perform encryption and decryption using the private key. 1. An authentication apparatus comprising:an interface element to interface with a device; anda security die-chip to form a package with the interface element, and to provide hardware-based authentication to the interface element in the package.2. The authentication apparatus of claim 1 , wherein the security die-chip comprises:a physically unclonable function (PUF) to provide a private key; anda hardware-wired security module to perform encryption and decryption using the private key.3. The authentication apparatus of claim 1 , further comprising a control chip to control the security die-chip to interface with the device.4. The authentication apparatus of claim 3 , wherein the control chip comprises a smart card die-chip.5. The authentication apparatus of claim 1 , wherein the interface element is a secure digital (SD).6. The authentication apparatus of claim 5 , wherein the security die-chip encrypts data stored in the SD.7. The authentication apparatus of claim 1 , wherein the interface element is a subscriber identity module (SIM).8. The authentication apparatus of claim 7 , wherein the security die-chip performs authentication of the device using a server connected via a network to the device.9. A storage device comprising:a flash memory;a controller to read data from the flash memory and to control a data program of the flash memory; anda hardware-based security die-chip to encrypt first data recorded by the controller on the flash memory, and to generate second data that is encrypted,wherein the controller stores the ...

Processor, processor operation method and electronic device comprising same

Disclosed are a processor, a processor operation method and an electronic device comprising same. The disclosed processor operation method comprises the steps of: identifying an instruction for instructing the execution of a first operation and address information of an operand corresponding to the instruction; and executing the instruction on the basis of whether or not the address information of the operand satisfies a predetermined condition. In the step of executing the instruction, a second operation configured to the instruction is executed for the operand if the address information of the operand satisfies the predetermined condition, and the first operation is executed for the operand if the address information of the operand does not satisfy the predetermined condition.

APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers. 1. An apparatus for generating an identification key , the apparatus comprising:an identification key generator to generate an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit by violating design rules provided during a semiconductor manufacturing process, andan identification key reader to read the identification key by reading whether a short occurs between the nodes constituting the circuit.2. The apparatus of claim 1 , wherein the nodes constituting the circuit correspond to conductive layers of a semiconductor claim 1 , andthe identification key generator generates the identification key based on whether a contact or a via formed between the conductive layers of the semiconductor shorts the conductive layers.3. The apparatus of claim 2 , wherein the identification key reader reads the identification key by reading whether the contact or the via shorts the conductive layers.4. The apparatus of claim 2 , wherein the contact or the via formed between the conductive layers of the semiconductor is configured to be smaller than a size determined by a design rule provided during a semiconductor manufacturing process.5. The apparatus of claim 2 , wherein the identification key generator has a size of the contact or the via to have a difference between a probability that the contact or the ...

AUTHENTICATION APPARATUS AND METHOD

An interface element connected to a device and a security die-chip are fabricated in a single package. The security die-chip may provide a security authentication function to the interface element that does not have the security authentication function. The security die-chip may include a physically unclonable function (PUF) to provide a private key, and a hardware security module to perform encryption and decryption using the private key. 18-. (canceled)9. A storage device comprising:a flash memory;a controller to read data from the flash memory and to control a data program of the flash memory; anda hardware-based security die-chip to encrypt first data recorded by the controller on the flash memory, and to generate second data that is encrypted,wherein the controller stores the second data in the flash memory.10. The storage device of claim 9 , wherein the security die-chip comprises:a physically unclonable function (PUF) to provide an authentication key; anda hardware-wired security module to encrypt the first data using the authentication key.11. The storage device of claim 10 , further comprising a smart card die-chip to control the security die-chip to interface with at least one of the controller and an external device located outside the storage device.12. The storage device of claim 10 , wherein when an authenticated access request for the first data is received claim 10 , the security die-chip decrypts the second data to the first data using the authentication key.13. The storage device of claim 9 , wherein the storage device is either a secure digital (SD) card or a micro SD card claim 9 , andwherein the storage device comprises the security die-chip in a package based on a standard of the SD card or the micro SD card.14. An operating method of the storage device claim 9 , the operating method comprising:encrypting, by a hardware-wired security module of a security die-chip packaged in the storage device, first data using a private key provided by a ...

APPARATUS AND METHOD FOR TESTING RANDOMNESS

A randomness testing apparatus is disclosed. A randomness testing apparatus according to an embodiment includes a randomness testing module to conduct a randomness test on physically unclonable function (PUF)-based hardware and a processing device to determine whether the PUF-based hardware is defective on the basis of a randomness test result. 1. An apparatus for testing randomness comprising:a randomness testing module to conduct a randomness test on physically unclonable function (PUF)-based hardware; anda processing device to determine whether the PUF-based hardware is defective on the basis of a randomness test result.2. The apparatus of claim 1 , wherein the randomness testing module conducts a mono test on the PUF-based hardware.3. The apparatus of claim 2 , wherein the randomness testing module tests equality of distributions of 1s and 0s of the PUF-based hardware.4. The apparatus of claim 3 , wherein the randomness testing module tests the equality by receiving N-bit output values from the PUF-based hardware to count a number of 0 bits or 1 bits and determining whether the counted number satisfies a first range predetermined on N claim 3 , N being a natural number.5. The apparatus of claim 1 , wherein the randomness testing module conducts a poker test on the PUF-based hardware.6. The apparatus of claim 5 , wherein the randomness testing module tests equality of patterns of values output from the PUF-based hardware.7. The apparatus of claim 6 , wherein the randomness testing module tests the equality based on whether a result of counting each of frequencies of 0 to 15 represented by 4 bits satisfies a second range predetermined on N when N-bit output values output from the PUF-based hardware are divided by 4 bits claim 6 , N being a natural number.8. The apparatus of claim 7 , wherein the processing device determines that the PUF-based hardware is acceptable when a sum of squares of the frequencies of 0 to 15 is within the second range.9. The apparatus of ...

APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers. 1. An apparatus for generating an identification key , the apparatus comprising:an identification key generator to generate an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit by violating design rules provided during a semiconductor manufacturing process, andan identification key reader to read the identification key by reading whether a short occurs between the nodes constituting the circuit.2. The apparatus of claim 1 , wherein the nodes constituting the circuit correspond to conductive layers of a semiconductor claim 1 , andthe identification key generator generates the identification key based on whether a contact or a via formed between the conductive layers of the semiconductor shorts the conductive layers.3. The apparatus of claim 2 , wherein the identification key reader reads the identification key by reading whether the contact or the via shorts the conductive layers.4. The apparatus of claim 2 , wherein the contact or the via formed between the conductive layers of the semiconductor is configured to be smaller than a size determined by a design rule provided during a semiconductor manufacturing process.5. The apparatus of claim 2 , wherein the identification key generator has a size of the contact or the via to have a difference between a probability that the contact or the ...

DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a plurality of conductive layers designed so as to be formed in a first region within a semiconductor chip, the density in which the plurality of conductive layers are disposed in the first region being at least a first threshold value and not more than a second threshold value, the first and second threshold values being less than a minimum density according to the design rules for ensuring that all of the plurality of conductive layers are formed in the first region; and a reader which provides an identification key by identifying if, among the plurality of conductive layers, a previously designated first conductive layer has been formed. 16-. (canceled)7. A method of designing a device for generating an identification key , the method comprising:disposing a plurality of conductive layers in a first region included in a semiconductor chip layout, a density of the plurality of conductive layers disposed in the first region being equal to or greater than a first threshold and equal to or less than a second threshold, and the first threshold and the second threshold being less than a minimum density according to a design rule that ensures that all the plurality of conductive layers are formed in the first region; anddisposing a reader configured to determine whether a first conductive layer designated in advance among the plurality of conductive layers is formed and to provide an identification key.8. The method of claim 7 , wherein the first threshold is a lower limit value of a density range to allow a difference between a probability that the first conductive layer is formed and a probability that the first conductive layer is not formed to be within a predetermined error range claim 7 , andwherein the second threshold is an upper limit value of the density range to ...

Device and method for generating identification key

Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be produced by designing such that the effective base width of the BJT is at least a first threshold value but not more than a second threshold value, or, such that the total of the width of a second depletion region formed by connection with a collector region and the width of a first depletion region formed by connection with an emitter region, within a base region, differs from the width of the base region by a value that is at least the first threshold value but not more than the second threshold value. Whether or not there is a short circuit between the emitter region and the collector region is stochastically generated, and if ordinary turn-on voltage is not applied, whether or not there is a short circuit is identified.

ENCRYPTION DEVICE AND METHOD FOR DEFENDING A PHYSICAL ATTACK

Provided are a security device and a method for operating same. The security device may conceal an encryption key used for an encryption algorithm in an encryption module in correspondence to security attacks such as reading information on where the encryption key is stored in a memory by disassembling an IC chip, or extracting said information through microprobing. The encryption key may be included as a physical encryption key module in an encryption module, and a certain storage medium for storing the encryption key may be included in the encryption module. Accordingly, the encryption key is not transmitted via a bus in a security device for encryption. 1. An encryption device for executing an encryption algorithm using an encryption key as receiving an input data to be encrypted , the encryption device comprising:an encryption module, comprising an encryption key module to provide an encryption key, to execute the encryption algorithm using the encryption key provided by the encryption key module.2. The encryption device of claim 1 , wherein the encryption module comprises a plurality of encryption key modules to provide different encryption keys claim 1 ,wherein the encryption module comprises:an encryption key module selector to select one of the plurality of encryption key modules; andan encryption unit to execute the encryption algorithm using an encryption key provided by the selected encryption key module.3. The encryption device of claim 2 , wherein the encryption key module selector selects an encryption key module corresponding to a pre-assigned identification index from among the plurality of encryption key modules.4. The encryption device of claim 2 , wherein the encryption module comprises a plurality of standard cells claim 2 , and the plurality of encryption key modules is disposed at random positions among layouts of the plurality of standard cells included in the encryption module.5. The encryption device of claim 1 , wherein:the encryption ...

AUTHENTICATION APPARATUS AND METHOD

Disclosed is an authentication apparatus using a public key encryption algorithm. An apparatus according to an embodiment generates a first instant public key through a random number generation process in response to an electronic signature generation request corresponding to a message. Further, the apparatus calculates and uses a first instant private key making a pair with the first instant public key, using the first instant public key. 1. An authentication apparatus comprising at least one processor , the apparatus for performing an authentication process based on an algorithm of public-key cryptosystems , and the apparatus at least temporarily implemented through the at least one processor , the apparatus comprising:a generator to generate a first instant public key in response to a request for an electronic signature corresponding to the algorithm;a calculator to calculate a first instant private key to be paired with the first instant public key in the algorithm using the first instant public key; anda processing unit to generate the electronic signature based on the algorithm using the first instant private key.2. The apparatus of claim 1 , further comprising:a communicator to transmit a message in addition to the electronic signature and the first instant public key to a counterpart apparatus.3. The apparatus of claim 2 , wherein claim 2 , in response to a request of retransmission being received from the counterpart apparatus claim 2 , the generator generates a second instant public key differing from the first instant public key based on a verification that a communication error is absent in response to a communication acknowledgement (ACK) being received.4. The apparatus of claim 1 , wherein the generator generates the first instant public key based on a random number generating process.5. The apparatus of claim 4 , further comprising:a physically unclonable function (PUF) to provide a hardware fingerprint using a randomly occurring process variation, ...

INFORMATION SECURITY SYSTEM IN SMART MOBILE ENVIRONMENT

Provided is a security communication method of a terminal device. A first authentication unit of the terminal device identifies a first subscriber to connect a first communication network. A second authentication unit of the terminal device exclusively operates with the first authentication unit, and identifies a second subscriber to connect a second communication network which is different from the first communication network. When the second subscriber is identified, at least one external communication module of the terminal device can be inactive. 1. A terminal device , comprising:an application processor configured to perform information processing for the terminal device;a first authentication unit configured to identify a subscriber when the terminal device connects to a communication network; anda second authentication unit configured to identify a subscriber to the terminal device by exclusively operating with the first authentication unit, andwherein, when the second authentication unit identifies the subscriber to the terminal device, the application processor inactivates remaining modules among modules in the terminal device for communication or data storage, from which a predetermined permanent operation group is excluded.2. The terminal device of claim 1 , wherein the permanent operation group comprises a baseband module configured to provide a cellular communication connection.3. The terminal device of claim 1 , wherein the remaining modules claim 1 , excluding the permanent operation group claim 1 , comprise at least one of a wireless local area network (WLAN) module claim 1 , a Bluetooth module claim 1 , a near field communication (NFC) module claim 1 , and data storage media.4. The terminal device of claim 1 , wherein the second authentication unit comprises an authentication circuit to block an unauthorized external access by performing secure authentication and an authentication module configured to identify the subscriber to the terminal device ...

Device and method for generating identification key

Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node.

Device and method for generating identification key

Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be produced by designing such that the effective base width of the BJT is at least a first threshold value but not more than a second threshold value, or, such that the total of the width of a second depletion region formed by connection with a collector region and the width of a first depletion region formed by connection with an emitter region, within a base region, differs from the width of the base region by a value that is at least the first threshold value but not more than the second threshold value. Whether or not there is a short circuit between the emitter region and the collector region is stochastically generated, and if ordinary turn-on voltage is not applied, whether or not there is a short circuit is identified.

Information Security System in Smart Mobile Environment

Provided is a security communication method of a terminal device. A first authentication unit of the terminal device identifies a first subscriber to connect a first communication network. A second authentication unit of the terminal device exclusively operates with the first authentication unit, and identifies a second subscriber to connect a second communication network which is different from the first communication network. When the second subscriber is identified, at least one external communication module of the terminal device can be inactive. 1. A terminal device , comprising:an application processor to perform information processing for the terminal device;a first authentication unit to identify a subscriber when the terminal device connects to a communication network; anda second authentication unit to identify a subscriber to the terminal device by exclusively operating with the first authentication unit, andwherein, when the second authentication unit identifies the subscriber to the terminal device, the application processor inactivates remaining modules among modules in the terminal device for communication or data storage, from which a predetermined permanent operation group is excluded.2. The terminal device of claim 1 , wherein the permanent operation group comprises a baseband module providing a cellular communication connection.3. The terminal device of claim 1 , wherein the remaining modules claim 1 , excluding the permanent operation group claim 1 , comprise at least one of a wireless local area network (WLAN) module claim 1 , a Bluetooth module claim 1 , a near field communication (NFC) module claim 1 , and data storage media.4. The terminal device of claim 1 , wherein the second authentication unit comprises an authentication circuit to block an unauthorized external access by performing secure authentication and an authentication module to identify the subscriber to the terminal device with respect to an access authorized by the ...

APPARATUS AND METHOD FOR GENERATING PHYSICAL UNCLONABLE FUNCTION BY MODIFYING PHOTO MASK OF SEMICONDUCTOR PROCESS

Disclosed is a method of generating a physical unclonable function (PUF) by causing unpredictable partial process failure for a semiconductor process. In a designing process, a second mask pattern may be printed by distorting a size and/or shape of at least one mask window included in a designed first mask pattern, without violating semiconductor design rules. A PUF may be generated using a photomask including the printed second mask pattern for photolithography. 1. A semiconductor manufacturing method comprising:printing a second mask pattern, obtained by modifying at least part of a first mask pattern corresponding to a semiconductor design, when the first mask pattern is input; andconducting photolithography using a photomask comprising the printed second mask pattern,wherein the second mask pattern is formed by modifying the first mask pattern such that a plurality of inter-layer contacts or vias comprised in the semiconductor design is formed stochastically and accordingly at least part of the inter-layer contacts or vias are not formed.2. The semiconductor manufacturing method of claim 1 , wherein the second mask pattern is formed by modifying or distorting at least one of a size and a shape of at least one mask window comprised in the first mask pattern.3. The semiconductor manufacturing method of claim 1 , wherein the inter-layer contacts or vias are formed at a first threshold yield or higher by photolithography using the first mask pattern and are formed at a yield ranging from a second threshold yield to a third threshold yield by photolithography using the second mask pattern claim 1 , the third threshold yield is smaller than the first threshold yield claim 1 , and the second threshold yield is smaller than the third threshold yield.4. The semiconductor manufacturing method of claim 1 , wherein the second mask pattern is formed by down-scaling a size of at least one mask window comprised in the first mask pattern by applying a scale factor smaller than ...

Apparatus and Method for Processing Authentication Information

Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key. 1. An information processing apparatus comprising:a physical unclonable function (PUF) to generate at least one unique key using a process variation in a semiconductor manufacturing process; andan encryption unit to encrypt a password received from a user using the unique key to generate an identification key.2. The information processing apparatus of claim 1 , wherein the PUF generates the unique key using whether an interlayer contact formed between conductive layers of a semiconductor short-circuits the conductive layers.3. The information processing apparatus of claim 2 , wherein the interlayer contact formed between the conductive layers of the semiconductor is formed to have a smaller size than that according to a design rule provided in the semiconductor manufacturing process.4. The information processing apparatus of claim 2 , wherein the PUF is configured to set the size of the interlayer contact formed between the conductive layers of the semiconductor such that a difference between a probability of the interlayer contact short-circuiting the conductive layers and a probability of the interlayer contact not short-circuiting the conductive layers is within a preset error range.5. The information processing apparatus of claim 1 , wherein the PUF comprises N unit structures to generate a 1-bit digital value using a pair of conductive layers and one interlayer contact connecting the conductive layers and generates N-bit unique keys through the N unit structures claim 1 , N being a natural number.6. The information processing apparatus of claim 5 , wherein the PUF generates N-bit digital values claim 5 , and the information processing apparatus groups digital values ...

DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a plurality of conductive layers designed so as to be formed in a first region within a semiconductor chip, the density in which the plurality of conductive layers are disposed in the first region being at least a first threshold value and not more than a second threshold value, the first and second threshold values being less than a minimum density according to the design rules for ensuring that all of the plurality of conductive layers are formed in the first region; and a reader which provides an identification key by identifying if, among the plurality of conductive layers, a previously designated first conductive layer has been formed. 1. A device for generating an identification key , the device comprising:a plurality of conductive layers designed to be formed in a first region in a semiconductor chip, a density of the plurality of conductive layers disposed in the first region being equal to or greater than a first threshold and equal to or less than a second threshold, and the first threshold and the second threshold being less than a minimum density according to a design rule that ensures that all the plurality of conductive layers are formed in the first region; anda reader configured to determine whether a first conductive layer designated in advance among the plurality of conductive layers is formed and to provide an identification key.2. The device of claim 1 , wherein the first threshold is a lower limit value of a density range to allow a difference between a probability that the first conductive layer is formed and a probability that the first conductive layer is not formed to be within a predetermined error range claim 1 , andwherein the second threshold is an upper limit value of the density range to allow the difference between the probability that the ...

APPARATUS AND METHOD FOR AUTHENTICATION BETWEEN DEVICES BASED ON PUF OVER MACHINE-TO-MACHINE COMMUNICATIONS

Terminal devices that perform machine-to-machine (M2M) communication may autonomously perform password authentication by autonomously generating a personal identity number (PIN) value, which is not exposed externally, using a physical unclonable function (PUF). A terminal apparatus that performs M2M communication may include a PUF embedded in the terminal apparatus to generate an authentication key for password authentication associated with the terminal apparatus, and an authentication unit to perform the password authentication associated with the terminal apparatus using the authentication key generated by the PUF. 1. A terminal device that performs machine-to-machine (M2M) communication , the terminal device comprising:a physical unclonable function (PUF) embedded in the terminal device to generate an authentication key for password authentication associated with the terminal device; andan authentication unit to perform the password authentication associated with the terminal device using the authentication key generated by the PUF.2. The terminal device of claim 1 , wherein the PUF is physically isolated from an external environment to prevent the authentication key from being exposed to the outside.3. A terminal device that performs machine-to-machine (M2M) communication claim 1 , the terminal device comprising:a secret key module to provide a secret key for transferring, using a secret key encryption scheme, a public key used for communication of the terminal device using a public key encryption scheme; anda private key module to provide a private key for generating the public key,wherein at least one of the secret key module and the private key module includes a physical unclonable function (PUF).4. The terminal device of claim 3 , further comprising:a fuse unit blocked in response to applying of overcurrent to block a path via which the secret key is extracted.5. The terminal device of claim 4 , wherein the fuse unit blocks the path after the secret key is ...

DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY

The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the device for generating an identification key may include a first node provided in a semiconductor chip, a second node which is formed in a different layer from the first node, a via which is electrically shorted to the first node, and which is formed between the first node and the second node, the overlap distance between the second node and the via, in a pattern layout of the semiconductor chip, being adjusted to a value that is less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via, and a reader which provides an identification key by identifying whether the first node and the second node are shorted due to the via. 1. A device for generating an identification key , the device comprising:a first node included in a semiconductor chip;a second node formed in a different layer from the first node;a via formed between the first node and the second node and electrically shorted to the first node, an overlap distance between the second node and the via in a pattern layout of the semiconductor chip being adjusted to be less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via; anda reader configured to determine whether the first node and the second node are shorted by the via and to provide an identification key.2. The device of claim 1 , wherein whether the first node and the second node are shorted by the via is randomly determined by a process variation in a manufacturing process of the via.3. The device of claim 1 , wherein the overlap distance between the second node and the via in the pattern layout of the semiconductor chip is adjusted to be equal to or greater than a first threshold and equal to or less than a second threshold.4. The device of claim 3 , wherein the first ...

DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY BY USING SEMICONDUCTOR PROCESS

Provided are a device and a method for generating an identification key by using a process variation in a semiconductor process. A semiconductor is manufactured by adjusting a gate side edge position of a contact such that a difference between a probability that a gate of a transistor is shorted from a drain or a source by the contact and a probability that the gate is not shorted is less than or equal to a predetermined threshold. When the manufactured semiconductor does not have a separate process, whether there is a short circuit between the gate and the drain or the source is stochastically generated by the process variation, whether there is a short circuit is detected through a reader, and an identification key is provided. 1. A device for generating an identification key , the device comprising:a transistor included in a semiconductor chip;a contact formed on the transistor, an edge of the contact in a side facing a gate of the transistor being positioned so that a difference between a probability that the gate is shorted to a drain or a source by the contact and a probability that the gate is not shorted to the drain or the source is equal to or less than a predetermined threshold; anda reader configured to determine whether the gate is shorted to the drain or the source by the contact and to generate an identification key.2. The device of claim 1 , wherein a position of the edge is different from a position of an edge in a side facing a gate based on a design rule that ensures that the gate is not shorted to the drain or the source by the contact.3. The device of claim 1 , wherein whether the gate is shorted to the drain or the source is randomly determined based on a process variation in a process of manufacturing the semiconductor chip.4. The device of claim 1 , wherein the edge is spaced apart from a boundary between the gate and the drain or a boundary between the gate and the source by a distance equal to or greater than a first threshold distance and ...

Apparatus and method for generating identification key

An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second conductive layer formed on the semiconductor chip, wherein a spacing between the first conductive layer and the second conductive layer is equal to or greater than a first threshold and equal to or less than a second threshold, and a reader configured to determine whether a first node associated with the first conductive layer and a second node associated with the second conductive layer are shorted, and to provide an identification key.

APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is an apparatus for generating an identification key by using process variation in a conductive layer manufacturing process. The apparatus may include a first contact connected to a first conductive layer included in a semiconductor chip, wherein a first node is formed by an electrical connection between the first conductive layer and the first contact, a second contact connected to a second conductive layer included in the semiconductor chip, wherein a second node is formed by an electrical connection between the second conductive layer and the second contact, and wherein a value of a spacing between the first contact and the second contact is smaller than a minimum spacing value that guarantees that the first node and the second node are not shorted on a patterning layout, and a reader configured to determine whether the first node and the second node are electrically shorted and to provide the identification key. 1. An apparatus for generating an identification key , the apparatus comprising:a first contact connected to a first conductive layer included in a semiconductor chip, a first node being formed by electrically connecting the first contact and the first conductive layer;a second contact connected to a second conductive layer included in the semiconductor chip, a second node being formed by electrically connecting the second contact and the second conductive layer, and a value of a spacing between the first contact and the second contact in a patterning layout of the semiconductor chip being less than a minimum spacing value guaranteeing that the first node and the second node are not shorted; anda reader configured to determine whether the first node and the second node are electrically shorted and to generate an identification key.2. The apparatus of claim 1 , wherein the value of the spacing between the first contact and the second contact is equal to or greater than a first threshold and equal to or less than a second threshold claim 1 , ...

VEHICLE SECURITY NETWORK DEVICE AND DESIGN METHOD THEREFOR

A security system capable of preventing a security attack/threat on a vehicle network is provided. At least one security zone is set by using a risk level which is evaluated for a plurality of vehicle functional elements. In addition, a security countermeasure corresponding to the risk level of the security zone can be provided to a conduit of the security zone so as to perform gate keeping. 1. A vehicular security network device , comprising:a conduit configured to connect, to an external network, a first security zone including a plurality of functional elements having a same risk level assessed based on a vehicular security risk assessment matrix; anda first gate keeper disposed on the conduit and configured to control an access to the plurality of functional elements.2. The device of claim 1 , wherein claim 1 , when the risk level is higher than or equal to a predetermined level claim 1 , the first gate keeper includes a plurality of independent security elements.3. The device of claim 2 , wherein at least one of the independent security elements is embodied by a hardware-based security element.4. The device of claim 3 , wherein the hardware-based security element uses an authentication key to be held by a physical unclonable function (PUF).5. The device of claim 1 , wherein the risk level is a result of lookup from the vehicular security risk assessment matrix using assessment values associated with a level of likelihood of damage (D) indicating a level of a likelihood of damage caused by a security attack claim 1 , a level of severity (S) when the damage occurs claim 1 , and a level of controllability (C) when the damage occurs.6. The device of claim 5 , wherein the level of likelihood of damage (D) is determined by a combination of a level of threat realized (T) and a level of vulnerability exploited (V).7. The device of claim 5 , wherein the level of severity (S) and the level of controllability (C) are values assessed based on an ISO 26262.8. The device of ...

Device and method for generating identification key

Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be produced by designing such that the effective base width of the BJT is at least a first threshold value but not more than a second threshold value, or, such that the total of the width of a second depletion region formed by connection with a collector region and the width of a first depletion region formed by connection with an emitter region, within a base region, differs from the width of the base region by a value that is at least the first threshold value but not more than the second threshold value. Whether or not there is a short circuit between the emitter region and the collector region is stochastically generated by means of process variation, and if ordinary turn-on voltage is not applied to the base in the produced BJT, whether or not there is a short circuit is identified by means of a reader and an identifier is provided.

HARDWARE DEVICE AND AUTHENTICATING METHOD THEREOF

A secure semiconductor chip is presented. The semiconductor chip is, for example, a system-on-chip. Processor cores included in the system-on-chip are connected to normal IPs through a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is provided separately. The secure bus is connected to security IPs which perform security functions or handle security data. The secure semiconductor chip may perform necessary authentication by switching a normal mode to a secure mode. 1. A semiconductor chip comprising:a processor core; andan authentication part configured to perform mutual authentication with an outside trusted authority to perform authentication between the semiconductor chip and the outside trusted authority.2. The semiconductor chip of claim 1 , further comprising:a first group comprising elements connected to the processor core by a first bus; anda second group comprising elements connected to the processor core by a second bus and configured to operate in a secure mode.3. The semiconductor chip of claim 2 , wherein the second group is activated to be usable only if the authentication part successfully performs the authentication.4. The semiconductor chip of claim 2 , wherein the second group includes at least one of a cryptographic IP claim 2 , a secure SRAM claim 2 , a secure DMA claim 2 , and a boot ROM.5. The semiconductor chip of claim 1 , further comprising:a PUF configured to provide a key used by the authentication part for the mutual authentication with the outside trusted authority.6. The semiconductor chip of claim 2 , wherein the second group processes data by using a memory address different from that of the first group.732. The semiconductor chip of claim 2 , wherein the processor core comprises a Core-A processor claim 2 , the Core-A processor being a -bit RISC (reduced instruction set computing) type embedded processor.8. The semiconductor chip of claim 7 , wherein the second bus comprises a hidden bus ...

Apparatus and Method for Generating Identification Key

Provided is a PUF by which an identification key is generated according to a random event caused by a semiconductor process variation. The PUF can provide the identification key as a result of electrical differences among elements. According to one embodiment, the PUF can accumulate the electrical differences and/or instantaneous values without generating the identification key by using the instantaneous values caused by the electrical differences. The accumulation may be the accumulation of a discrete iteration and the result thereof. However, according to another embodiment, the accumulation may be a continuation of the accumulation result during time intervals. 1. An apparatus for generating an identification key , the apparatus comprising:a generator configured to provide a random event based on a semiconductor process variation, the event being associated with an electrical property difference;an accumulator configured to perform an accumulation on the random event to provide a cumulative result value; anda reader configured to determine the cumulative result value to be a binary value corresponding to one of 0 and 1 based on a predetermined reference and provide an identification key corresponding to the generator,wherein the random event includes an event that, between two identically designed and manufactured elements, a first element has a greater electrical property value than that of a second element, andwherein each of the first element and the second element includes a resistor and the electrical property value includes a resistance value.2. The apparatus of claim 1 , wherein the accumulator comprises:an integrator configured to perform a current integration by accumulating, into an output, a current proportional to a difference between a first resistance value corresponding to the first element and a second resistance value corresponding to the second element until a predetermined condition is satisfied, and provide a value of the output in a case in ...

Ic chip and authentication method for user authentication

An IC chip for preventing an authentication key from leaking, and an authentication key setting and authentication key verifying method are provided. A part performing connection or disconnection between an external terminal and a smartcard chip may be configured by a separate chip or may be incorporated into the smartcard chip to configure a single chip. When the part is configured by the separate chip, the disconnection between the external terminal and the smart card chip can be performed according to whether an authentication key is verified. When the part is configured by the one chip, the disconnection between the external terminal and the smart card chip can be performed under a control of the smartcard chip according to whether the authentication key is verified.

APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value. 1. An apparatus for generating a digital value , the apparatus comprising:a digital value generator to generate a random digital value using semiconductor process variation; anda digital value freezing unit that is connected to the digital value generator, and fixed to one state of a first state and a second state based on the generated digital value, to freeze the digital value.2. The apparatus of claim 1 , wherein the digital value generator comprises a Physically Unclonable Function (PUF).3. The apparatus of claim 2 , whereinthe PUF comprises a first inverter and a second inverter that are manufactured by an equivalent process, and have different electrical characteristic values using process variation in the manufacturing process, andan output terminal of the first inverter and an input terminal of the second inverter are connected to a first node, and an input terminal of the first inverter and an output terminal of the second inverter are connected to a second node that differs from the first node, and when the first node and the second node are shorted and then opened, the digital value generator generates the digital value based on a logical level of at least one of the first node and the second node.4. The apparatus of claim 2 , whereinthe PUF comprises a differential amplifier, andthe digital value generator generates the digital value by comparing voltage values of two output nodes when two input nodes of the differential amplifier are shorted.5. The apparatus of claim 2 ...

Encryption device and method for defending a physical attack

Provided are a security device and a method for operating same. The security device may conceal an encryption key used for an encryption algorithm in an encryption module in correspondence to security attacks such as reading information on where the encryption key is stored in a memory by disassembling an IC chip, or extracting said information through microprobing. The encryption key may be included as a physical encryption key module in an encryption module, and a certain storage medium for storing the encryption key may be included in the encryption module. Accordingly, the encryption key is not transmitted via a bus in a security device for encryption.

Apparatus and Method for Processing Authentication Information

Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key. 1. An information processing apparatus comprising:a physical unclonable function (PUF) to generate at least one unique key using whether a short or open occurs between nodes generated on a semiconductor element by a process variation in a semiconductor manufacturing process; andan encryption processor to encrypt received data using the unique key to store the data encrypted.2. The information processing apparatus of claim 1 , wherein the PUF generates the unique key using whether an interlayer contact formed between conductive layers of a semiconductor short-circuits the conductive layers.3. The information processing apparatus of claim 2 , wherein the interlayer contact formed between the conductive layers of the semiconductor is formed to have a smaller size than that according to the design rule provided in the semiconductor manufacturing process.4. The information processing apparatus of claim 2 , wherein the PUF is configured to set the size of the interlayer contact formed between the conductive layers of the semiconductor such that a difference between a probability of the interlayer contact short-circuiting the conductive layers and a probability of the interlayer contact not short-circuiting the conductive layers is within a preset error range.5. The information processing apparatus of claim 1 , wherein the PUF comprises N unit structures to generate a 1-bit digital value using a pair of conductive layers and one interlayer contact connecting the conductive layers and generates N-bit unique keys through the N unit structures claim 1 , N being a natural number.6. The information processing apparatus of claim 5 , wherein the PUF generates N-bit digital values claim ...

Apparatus and method for generating digital value

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.

APPARATUS AND METHOD FOR GENERATING RANDOM DIGITAL VALUE

Provided is an apparatus for generating digital values to provide a random digital value. The apparatus may generate the digital value based on a semiconductor process variation. The apparatus may include a generating unit to generate a plurality of digital values, based on the semiconductor process variation, and a processing unit to process the digital values and to provide a first digital value. The generating unit may include a plurality of physically unclonable functions (PUFs). A parameter may be differently applied to the PUFs, and the PUFs may generate the digital values. 1. An apparatus for generating a digital value based on a semiconductor process variation , the apparatus comprising:a generating unit to generate a plurality of digital values, based on the semiconductor process variation; anda processing unit to process the digital values and to provide a first digital value,wherein the generating unit comprises a plurality of physically unclonable functions (PUFs), at least a portion of the PUFs is manufactured by differently applying at least one parameter causing the semiconductor process variation, and the PUFs generate the digital values.2. The apparatus of claim 1 , wherein at least one of the PUFs comprises at least one via formed between conductive layers in a semiconductor claim 1 , and at least one of the digital values is generated based on whether the conductive layers are shorted by the via.3. The apparatus of claim 2 , wherein the parameter comprises a size of the via.4. The apparatus of claim 3 , wherein the size of the via is selected from a range between a minimum value and a maximum value of a size of a via corresponding to whether the via causes a short between the conductive layers determined in a test process performed prior to a process of manufacturing the apparatus claim 3 , and different via sizes in the range are applied to the PUFs.5. The apparatus of claim 1 , wherein the processing unit selects claim 1 , as the first digital ...

APPARATUS AND METHOD FOR PROCESSING DIGITAL VALUE

Provided is an apparatus for testing randomness of a digital value and processing the digital value. The digital value may include first bit sequences generated by a physically unclonable function (PUF). A grouping unit may generate a plurality of groups by segmenting the first bit sequence, and a processing unit may calculate a second bit sequence from the plurality of groups by performing a logical operation. 1. A digital value processing apparatus , comprising:a grouping unit to generate a plurality of groups by segmenting a first bit sequence included in a first digital value generated by a physically unclonable function (PUF); anda processing unit to calculate a second bit sequence from the groups by performing a logical operation, and to generate a second digital value comprising the second bit sequence.2. The digital value processing apparatus of claim 1 , wherein the logical operation is an eXclusive OR (XOR) operation.3. The digital value processing apparatus of claim 1 , further comprising:a determining unit to read the first bit sequence, and to determine whether the first digital value has a predesignated level of randomness.4. The digital value processing apparatus of claim 3 , wherein the predesignated level of randomness satisfies a condition that a P-value calculated for the first bit sequence exceeds a predesignated threshold.5. The digital value processing apparatus of claim 1 , further comprising:a determining unit to determine a parameter associated with the segmenting, by reading the first bit sequence.6. The digital value processing apparatus of claim 5 , wherein the parameter is a number of the generated groups claim 5 , and a reading unit to read the first bit sequence and to calculate a ratio of bit values “1” and “0” included in the first bit sequence; and', 'a calculating unit to calculate the parameter to allow a condition that a P-value for the second bit sequence calculated based on the ratio exceeds a predesignated threshold to be ...

APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY

Provided is an apparatus for generating an identification key by a probabilistic determination of a short occurring between nodes constituting a circuit, by violating a design rule provided during a semiconductor manufacturing process. The identification key generating apparatus may include an identification key generator to generate an identification key based on whether a contact or a via used to electrically connect conductive layers in a semiconductor chip shorts the conductive layers, and an identification key reader to read the identification key by reading whether the contact or the via shorts the conductive layers. 127-. (canceled)28. A semiconductor chip for generating an identification key , the chip comprising:an identification key generator circuit, including:a plurality of two layers; and 'wherein the identification key generator circuit generates an identification key based on an electrical characteristic of a contact or via between two layers and wherein the identification key remains invariant over any period of time; and', 'a plurality of contacts or vias formed between the plurality of two layers, a hole size of at least one contact or via among the plurality of contacts or vias being greater than a hole size at which the contact or via never creates a short between the two layers, and less than a minimum hole size at which the contact or via always creates the short between the two layers,'}an identification key reader circuit that reads the identification key by reading the electrical characteristic of the contact or via between the two layers constituting the identification key generator circuit.29. The chip of claim 28 , wherein the electrical characteristic of the contact or via is determined by whether the short or open occurs between the two layers.30. The chip of claim 29 , wherein the two layers constituting the identification key generator circuit correspond to conductive layers of a semiconductor claim 29 , and the identification key ...

APPARATUS AND METHOD FOR GENERATING PHYSICAL UNCLONABLE FUNCTION BY MODIFYING PHOTO MASK OF SEMICONDUCTOR PROCESS

Disclosed is a method of generating a physical unclonable function (PUF) by causing unpredictable partial process failure for a semiconductor process. In a designing process, a second mask pattern may be printed by distorting a size and/or shape of at least one mask window included in a designed first mask pattern, without violating semiconductor design rules. A PUF may be generated using a photomask including the printed second mask pattern for photolithography. 1. A semiconductor manufacturing method comprising:printing a second mask pattern, obtained by modifying at least part of a first mask pattern corresponding to a semiconductor design, when the first mask pattern is input; andconducting photolithography using a photomask comprising the printed second mask pattern,wherein the second mask pattern is formed by modifying the first mask pattern such that a plurality of inter-layer contacts or vias comprised in the semiconductor design is formed stochastically and accordingly at least part of the inter-layer contacts or vias are not formed.2. The semiconductor manufacturing method of claim 1 , wherein the second mask pattern is formed by modifying or distorting at least one of a size and a shape of at least one mask window comprised in the first mask pattern.3. The semiconductor manufacturing method of claim 1 , wherein the inter-layer contacts or vias are formed at a first threshold yield or higher by photolithography using the first mask pattern and are formed at a yield ranging from a second threshold yield to a third threshold yield by photolithography using the second mask pattern claim 1 , the third threshold yield is smaller than the first threshold yield claim 1 , and the second threshold yield is smaller than the third threshold yield.4. The semiconductor manufacturing method of claim 1 , wherein the second mask pattern is formed by down-scaling a size of at least one mask window comprised in the first mask pattern by applying a scale factor smaller than ...

Apparatus and method for generating a digital value

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.

Apparatus and method for processing authentication information

Provided is an information processing apparatus including a physical unclonable function (PUF) to generate a unique key using a process variation in a semiconductor manufacturing process, and an encryption unit to encrypt a password and/or bio-information received from a user using the unique key.

Apparatus for providing puf-based hardware otp and method for authenticating 2-factor using same

Provided is an apparatus for generating a hardware-based OTP which is impossible to duplicate. The apparatus for generating the OTP can comprise a PUF for generating a unique PIN. In addition, provided is a method which is used for 2-Factor authentication with the apparatus for generating the OTP and existing secure elements.

Apparatus and method for generating a digital value

Device and method for generating an identification key

Apparatus and method for generating identification key

一種用於產生一識別金鑰之裝置，其係藉由意欲違背在半導體製程期間提供的設計規則，概率性判斷在構成電路的節點間是否發生短路，以產生一識別金鑰。該識別金鑰產生裝置可包括：一識別金鑰產生器，以基於用來電連接半導體晶片傳導層之一接點或一穿孔是否使傳導層短路，以產生一識別金鑰；及一識別金鑰讀取器，其藉由讀取接點或一穿孔是否使傳導層短路，以讀取該識別金鑰。

Apparatus and method for generating a digital value

Apparatus and method for processing authentication information

提供一種包含實體不可複制功能(PUF)和一加密單元的資料處理裝置，是利用一種半導體製造過程中的製程變異產生一唯一金鑰、和一種利用該唯一金鑰將密碼以及/或者從使用者得到的生物資訊加密之加密單元。

Message authentication apparatus and method based on public-key cryptosystems

Disclosed is an authentication apparatus using a public key encryption algorithm. An apparatus according to an embodiment generates a first instant public key through a random number generation process in response to an electronic signature generation request corresponding to a message. Further, the apparatus calculates and uses a first instant private key making a pair with the first instant public key, using the first instant public key.

Device and method for generating identification key

Apparatus for generating identification key and management method thereof

Apparatus and method for processing random number extracted from pufs

Provided is an apparatus for testing randomness of a digital value and processing the digital value. The digital value may include first bit sequences generated by a physically unclonable function (PUF). A grouping unit may generate a plurality of groups by segmenting the first bit sequence, and a processing unit may calculate a second bit sequence from the plurality of groups by performing a logical operation.

Method and apparatus for generating puf by transforming photo mask in semiconductor process

Ic chip for preventing identification key leak and authorization method thereof

Disclosed are an IC chip for preventing identification key leak and an authorization method thereof. An IC chip capable of performing a financial function includes: a PIN supply unit for supplying a PIN used for authorization when performing a financial function using the IC chip; and a blocking unit for physically blocking the gap between the PIN supply unit and an input-output interface when the PIN is supplied to the outside through the input-output interface at an initial access of the IC chip.

Device and method to generate an identification key

Un aparato para generar una clave de identificación, el aparato comprende: un generador (110) de claves configurado para generar un bit digital basado en si un contacto o una vía formada entre las capas (201, 202) conductoras de un circuito genera cortocircuito en las capas conductoras del circuito; y un procesador (130) configurado para: agrupar una pluralidad de bits digitales generados por el generador (110) de claves basado en a una pluralidad de contactos o vías en un primer grupo (710) con k bits digitales y un segundo grupo (720) con k bits digitales, en donde k es un número natural; y comparar el primer grupo (710) y el segundo grupo (720) para determinar un valor digital para una clave de identificación. An apparatus for generating an identification key, the apparatus comprises: a key generator (110) configured to generate a digital bit based on whether a contact or a path formed between the conductive layers (201, 202) of a circuit generates a short circuit in the conductive layers of the circuit; and a processor (130) configured to: group a plurality of digital bits generated by the key generator (110) based on a plurality of contacts or channels in a first group (710) with k digital bits and a second group (720 ) with k digital bits, where k is a natural number; and comparing the first group (710) and the second group (720) to determine a digital value for an identification key.

Apparatus for providing PUF-based hardware OTP and method for authenticating 2-factor using same

Provided is an apparatus for generating a hardware-based OTP which is impossible to duplicate. The apparatus for generating the OTP can comprise a PUF for generating a unique PIN. In addition, provided is a method which is used for 2-Factor authentication with the apparatus for generating the OTP and existing secure elements.

Apparatus for providing puf-based hardware otp and method for authenticating 2-factor using same

Provided is an apparatus for generating a hardware-based OTP which is impossible to duplicate. The apparatus for generating the OTP can comprise a PUF for generating a unique PIN. In addition, provided is a method which is used for 2-Factor authentication with the apparatus for generating the OTP and existing secure elements.

Information security system in smart mobile environment

Provided is a security communication method of a terminal device. A first authentication unit of the terminal device identifies a first subscriber to connect a first communication network. A second authentication unit of the terminal device exclusively operates with the first authentication unit, and identifies a second subscriber to connect a second communication network which is different from the first communication network. When the second subscriber is identified, at least one external communication module of the terminal device can be inactive.

Device and method for puf-based inter-device security authentication in machine-to-machine communication

Apparatus for providing puf-based hardware otp and method for authenticating 2-factor using same

Authentication apparatus and method

An interface element connected to a device and a security die-chip are fabricated in a single package. The security die-chip may provide a security authentication function to the interface element that does not have the security authentication function. The security die-chip may include a physically unclonable function (PUF) to provide a private key, and a hardware security module to perform encryption and decryption using the private key.

Processor, processor operation method and electronic device comprising same for selective instruction execution based on operand address

Disclosed are a processor, a processor operation method and an electronic device comprising same. The disclosed processor operation method comprises the steps of: identifying an instruction for instructing the execution of a first operation and address information of an operand corresponding to the instruction; and executing the instruction on the basis of whether or not the address information of the operand satisfies a predetermined condition. In the step of executing the instruction, a second operation configured to the instruction is executed for the operand if the address information of the operand satisfies the predetermined condition, and the first operation is executed for the operand if the address information of the operand does not satisfy the predetermined condition.

Apparatus and method for generating identification key

Provided is a PUF by which an identification key is generated according to a random event caused by a semiconductor process variation. The PUF can provide the identification key as a result of electrical differences among elements. According to one embodiment, the PUF can accumulate the electrical differences and/or instantaneous values without generating the identification key by using the instantaneous values caused by the electrical differences. The accumulation may be the accumulation of a discrete iteration and the result thereof. However, according to another embodiment, the accumulation may be a continuation of the accumulation result during time intervals.

測試隨機性的儀器以及方法

一種隨機性測試儀器被揭露，根據一實施例，一隨機性測試儀器包括一隨機性測試模組以在基於PUF的硬體上執行一隨機性測試，以及一處理裝置根據一隨機性測試結果判定其基於PUF的硬體是否為有缺陷的。

Vehicle security network device and method for controlling same

A vehicle security network design device may comprise: a level assigning unit for assigning an automobile safety integrity level (ASIL) which provides a risk management standard for each of a plurality of functional elements in a vehicle that is at least temporarily implemented by a processor; a calculation unit for calculating device's controllability with respect to each of the plurality of functional elements on the basis of a connection structure between the plurality of functional elements and a difference value of the ASIL; and a management unit for generating a risk analysis model of a plurality of functional elements.

Device and method for generating identification key

Semiconductor chip and method for generating digital value using process variation

Apparatus and method for generating identification key

Vehicle security network device and method for controlling same

A vehicle security network design device may comprise: a level assigning unit for assigning an automobile safety integrity level (ASIL) which provides a risk management standard for each of a plurality of functional elements in a vehicle that is at least temporarily implemented by a processor; a calculation unit for calculating device's controllability with respect to each of the plurality of functional elements on the basis of a connection structure between the plurality of functional elements and a difference value of the ASIL; and a management unit for generating a risk analysis model of a plurality of functional elements.

Semiconductor chip and method for generating digital value using process variation

Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to an first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node.

Semiconductor chip and method for generating digital value using process variation

Semiconductor chip and method for generating digital value using process variation

Provided is a semiconductor chip to generate an unique identification key. The semiconductor chip (100) includes a first inverter (110) having a first logic thresholdpa second inverter (120) having a second logic threshold, and a first switch (130). The first switch (130) includes a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to a first input voltage value. An input terminal of the first inverter (110), an output terminal, and the first terminal of the first switch (130) are connected to a first node (101 ). An output terminal of the first inverter (110), an input terminal of the second inverter (120), and the second terminal of the first switch (130) are connected to a second node (102). A second switch (150) and a third switch (140) may also be embodies using a transmission gate TG.

Device and method for generating identification key

Apparatus safe from power consumption analysis attack for encrypting and method for operating same

Device and method for generating identification key

Device and method for generating identification key

Processor, processor operation method and electronic device comprising same

Disclosed are a processor, a processor operation method and an electronic device comprising same. The disclosed processor operation method comprises the steps of: identifying an instruction for instructing the execution of a first operation and address information of an operand corresponding to the instruction; and executing the instruction on the basis of whether or not the address information of the operand satisfies a predetermined condition. In the step of executing the instruction, a second operation configured to the instruction is executed for the operand if the address information of the operand satisfies the predetermined condition, and the first operation is executed for the operand if the address information of the operand does not satisfy the predetermined condition.

IC chip for preventing identification key leak and authorization method thereof

Disclosed are an IC chip for preventing identification key leak and an authorization method thereof. An IC chip capable of performing a financial function includes: a PIN supply unit for supplying a PIN used for authorization when performing a financial function using the IC chip; and a blocking unit for physically blocking the gap between the PIN supply unit and an input-output interface when the PIN is supplied to the outside through the input-output interface at an initial access of the IC chip.

Device and method for generating identification key

The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the device for generating an identification key may include a first node provided in a semiconductor chip, a second node which is formed in a different layer from the first node, a via which is electrically shorted to the first node, and which is formed between the first node and the second node, the overlap distance between the second node and the via, in a pattern layout of the semiconductor chip, being adjusted to a value that is less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via, and a reader which provides an identification key by identifying whether the first node and the second node are shorted due to the via.

Device and method for generating identification key

Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node.

Apparatus and method for authentication between devices based on PUF over machine-to-machine communications

Terminal devices that perform machine-to-machine (M2M) communication may autonomously perform password authentication by autonomously generating a personal identity number (PIN) value, which is not exposed externally, using a physical unclonable function (PUF). A terminal apparatus that performs M2M communication may include a PUF embedded in the terminal apparatus to generate an authentication key for password authentication associated with the terminal apparatus, and an authentication unit to perform the password authentication associated with the terminal apparatus using the authentication key generated by the PUF.

Apparatus and method for generating digital value

Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.