Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 4. Отображено 4.
05-01-2006 дата публикации

Error detecting circuit

Номер: US2006005091A1
Автор: MITRA SUBHASISH, KIM KEE S, MAK TAK M, GOTETI PRASHANT M, KIM KEE S., MAK TAK M., GOTETI PRASHANT M.
Принадлежит:

In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Подробнее
Номер записи: 1
16-02-2006 дата публикации

Compacting circuit responses

Номер: US2006036985A1
Автор: MITRA SUBHASISH, KIM KEE S, KIM KEE S.
Принадлежит:

Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Подробнее
Номер записи: 2
19-01-2006 дата публикации

System and shadow bistable circuits coupled to output joining circuit

Номер: US2006015786A1
Автор: MITRA SUBHASISH, ZHANG MING, KIM KEE S, KIM KEE S.
Принадлежит:

In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

Подробнее
Номер записи: 3
06-03-2007 дата публикации

Error detecting circuit

Номер: US0007188284B2
Автор: Subhasish Mitra, Kee S. Kim, Tak M. Mak, Prashant M. Goteti, MITRA SUBHASISH, KIM KEE S, MAK TAK M, GOTETI PRASHANT M, KIM KEE S., MAK TAK M., GOTETI PRASHANT M.
Принадлежит: Intel Corporation, INTEL CORP, INTEL CORPORATION

In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Подробнее
Номер записи: 4