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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 11. Отображено 8.
20-06-2013 дата публикации

DECODING DEVICE AND CODING METHOD

Номер: US20130154857A1
Автор: KUSHIDA Sohei, TAKEMOTO Takashi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A decoding device has a buffer configured in memory to store N code streams and N decoders connected in series. Each of N decoders decodes a corresponding code steam and sequentially generates partial symbols of M bit width each unit cycle. Among the N decoders, i (i>=2) stage decoders stores multiple probabilistic models in the memory. In each unit cycle, the decoder receives an input of i−1 partial symbols which contains partial symbols generated by the i−1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i−1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with previously entered i−1 partial symbols. 1. A decoding device comprising:a buffer configured in memory to store N (N is a positive integer) code streams; andN decoders connected in series, each of the N decoders having a one-to-one correspondence with one of the N code streams, and being configured to decode the corresponding code stream and sequentially generate partial symbols of M bit width (M is a positive integer) per each unit cycle,wherein among the N decoders, i (2<=i<=N, i is a positive integer) stage decoders store multiple probabilistic models in the memory; andwherein, in each unit cycle, an i stage decoder receives an input of i−1 partial symbols which are partial symbols generated by an i−1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i−1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with the previously entered i−1 partial symbols.2. The decoding device according to claim 1 , wherein the i stage decoder connects the one partial symbol to the end of the i−1 partial symbols which ...

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Номер записи: 1
27-01-2022 дата публикации

CONTROL METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20220029612A1
Автор: IWATA Haruya, Kamiya Satoshi, KUSHIDA Sohei, Mori Takayuki, TOKUE Tatsuya
Принадлежит:

A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks. 1. A semiconductor integrated circuit comprising:a clock controller that generates a clock; anda plurality of blocks that operates by using the clock,wherein the clock controller performs a statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of which the frequency is changed from the second frequency to the first frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency, and supplies the generated clock to the plurality of blocks,and wherein the clock controller generates the clock changed to a third frequency obtained by decimating down the second frequency from the first frequency according to a time for which the first frequency is to be continued and the time for which the second ...

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Номер записи: 2
25-03-2021 дата публикации

Information processing apparatus and control method of information processing apparatus

Номер: US20210089213A1
Автор: Haruya Iwata, Satoshi Kamiya, Sohei KUSHIDA, Takayuki Mori, Tatsuya Tokue
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

An information processing apparatus comprises a central processor, a volatile memory, a non-volatile memory, a backup line, and a controller. The volatile memory is configured in such a manner that data is input and output thereto and therefrom via a bus under control of the central processor. The non-volatile memory is configured in such a manner that data is input and output thereto and therefrom via the bus under control of the central processor. The backup line is provided between the volatile memory and the non-volatile memory. The controller is configured to control data transfer performed between the volatile memory and the non-volatile memory via the backup line in a transition period between a normal mode of supplying normal power to the volatile memory and a low power consumption mode of reducing or interrupting normal power to be supplied to the volatile memory.

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Номер записи: 3
25-03-2021 дата публикации

Control method and semiconductor integrated circuit

Номер: US20210091756A1
Автор: Haruya Iwata, Satoshi Kamiya, Sohei KUSHIDA, Takayuki Mori, Tatsuya Tokue
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

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Номер записи: 4
19-09-2019 дата публикации

Semiconductor device

Номер: US20190287577A1
Автор: Haruya Iwata, Satoshi Kamiya, Sohei KUSHIDA, Takayuki Mori, Tatsuya Tokue
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

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Номер записи: 5
03-09-2013 дата публикации

Decoding device and coding method

Номер: US8525708B2
Автор: Sohei KUSHIDA, Takashi Takemoto
Принадлежит: Toshiba Corp

A decoding device has a buffer configured in memory to store N code streams and N decoders connected in series. Each of N decoders decodes a corresponding code steam and sequentially generates partial symbols of M bit width each unit cycle. Among the N decoders, i (i>=2) stage decoders stores multiple probabilistic models in the memory. In each unit cycle, the decoder receives an input of i−1 partial symbols which contains partial symbols generated by the i−1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i−1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with previously entered i−1 partial symbols.

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Номер записи: 6
16-11-2021 дата публикации

Control method and semiconductor integrated circuit

Номер: US11177798B2
Автор: Haruya Iwata, Satoshi Kamiya, Sohei KUSHIDA, Takayuki Mori, Tatsuya Tokue
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

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Номер записи: 7
25-03-2021 дата публикации

制御方法及び半導体集積回路

Номер: JP2021047707A
Автор: Haruya Iwata, Satoshi Kamiya, Sohei KUSHIDA, Takayuki Mori, Tatsuya Tokue, 宗平 串田, 智史 神谷, 治也 岩田, 貴幸 森
Принадлежит: Toshiba Corp, Toshiba Electronic Devices and Storage Corp

【課題】一つの実施形態は、クロックの周波数を適切に制御できる制御方法を提供することを目的とする。【解決手段】一つの実施形態によれば、制御方法が提供される。制御方法では、クロックの周波数を第１の周波数に制御する。制御方法では、クロックの周波数を第１の周波数から第２の周波数へ変更する。第２の周波数は、第１の周波数より低い周波数である。制御方法では、第２の周波数を継続すべき時間について統計的に予測する。制御方法では、第２の周波数への変更タイミングから第２の周波数を継続すべき時間が経過した後、クロックの周波数を第２の周波数から第１の周波数に変更する。【選択図】図３

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Номер записи: 8