System and method for managing pipelines in reconfigurable integrated circuit architectures

A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

Reconfigurable instruction cell array with conditional channel routing and in-place functionality

A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

AUTOMATIC TEST PATTERN GENERATION FOR A RECONFIGURABLE INSTRUCTION CELL ARRAY

An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals. 1. An array , comprising:a plurality of tiles, each tile including:a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels; andan instruction cell comprising a plurality of logic gates for producing an instruction cell output from selected ones of the input channels;wherein each I/O port is configured to select from the instruction cell output and from the input channels for the remaining I/O ports to form the I/O port's output channels, and wherein a subset of the I/O ports are configured in a testing mode to prevent any of their output channels from being combinatorial signals.2. The array of claim 1 , wherein each I/O port includes:a plurality of first multiplexers corresponding to the I/O port's plurality of output channels; each first multiplexer being configured in a normal mode of operation to select from the I/O port's tile's instruction cell output and from the corresponding input channel from each of the remaining I/O ports in the I/O port's tile to form an output signala plurality ...

SERIAL CONFIGURATION OF A RECONFIGURABLE INSTRUCTION CELL ARRAY

A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in each switch box. The switch boxes are arranged into serial loading sets such that the switch boxes in each serial loading set are configured to form a multi-bit shift register chain for serial shifting the corresponding configuration words. 1. A reconfigurable instruction cell array (RICA) , comprising:an array of switch boxes organized into a plurality of serial loading sets, wherein for each serial loading set, the corresponding switch boxes are arranged from a first switch box to a last switch box, each switch box including a programmable instruction cell comprising dedicated logic gates configurable to process an input word to produce an output word and a switch fabric both being configurable according to a corresponding configuration word to program a function of the programmable instruction cell and to program a routing of the input word through the switch fabric and to program a routing of the output word through the switch fabric, each switch box including an n-bit register configured to store the corresponding configuration word, wherein each configuration word comprises a plurality of n configuration bits, n being a plural integer; andwherein the n-bit registers for each serial loading set are arranged to form an n-bit shift register configured to serially shift configuration words through the serial loading set responsive to cycles of a RICA clock.2. The RICA of claim 1 , wherein the switch boxes are arranged into rows and columns claim 1 , and wherein the serial loading sets in a first plurality of the serial loading sets comprise an upper half of each column and wherein the serial loading sets in a second plurality of the serial loading sets comprise a lower half of each column.3. The RICA of claim 2 , further comprising:a first memory for storing ...

System and Method for Managing Pipelines in Reconfigurable Integrated Circuit Architectures

A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfacesand an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations isknown before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate timeswrite-enable inputs of configuration registers are disabled. 1. An integrated circuit , comprising:an active cell configured with a sensor that identifies a back pressure condition at an interface coupled to the active cell, wherein the active cell communicates a do-not-end-step signal in response to the back pressure condition;a controller arranged to receive the do-not-end step signal and suspend execution in a reconfigurable logic array.2. The integrated circuit of claim 1 , wherein the controller is further arranged to suspend execution in the reconfigurable logic array upon receipt of an interrupt request.3. The integrated circuit of claim 1 , further comprising:a set of local memory interface cells distributed throughout the reconfigurable logic array, the local memory interface cells arranged to forward a signal responsive to a condition of a volatile memory element coupled to the reconfigurable logic array.4. The integrated circuit of claim 3 , wherein the controller upon receipt of the signal responsive to the condition of the volatile ...

Switching Fabric for Embedded Reconfigurable Computing

An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses. 1. A circuit , comprising:a switch fabric configured to have a footprint on a semiconductor surface, the footprint having a plurality of sides;a plurality of input conductors configured to conduct a plurality of channels into the switch fabric with regard to each side of the footprint;a plurality of output conductors configured to conduct the plurality of channels out of the switch fabric with regard to each side of the footprint, wherein the input and output conductors for a first opposing pair of the sides are arranged in first tracks corresponding to the channels, and wherein the switch fabric includes a plurality of channel switching circuits corresponding to the channels and arranged in the footprint such that each first track spans the corresponding channel switching circuit, and wherein the input and output conductors for a second opposing pair of the sides for the footprint are arranged in second tracks such that each second track spans across all the channel switching circuits; andwherein each channel switching circuit includes a plurality of multiplexers corresponding to each side, and wherein each side's corresponding multiplexers in each channel switching circuit are configured to drive the output conductors for the channel switching circuit's corresponding channel with a selected channel from the input conductors for the remaining sides.2. The circuit of claim 1 , wherein each channel has a width equaling a plurality of bits claim 1 , and wherein the input and output conductors for the second opposing pair of sides are arranged corresponding to the plurality of bits such that each second track accommodates the input and output conductors for all the channels for ...

Parallel Configuration of a Reconfigurable Instruction Cell Array

A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

ALTERNATING LIGHT DISTRIBUTIONS FOR ACTIVE DEPTH SENSING

Aspects of the present disclosure relate to systems and methods for active depth sensing. An example apparatus configured to perform active depth sensing includes a projector. The projector is configured to emit a first distribution of light during a first time and emit a second distribution of light different from the first distribution of light during a second time. A set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light. The projector may include a laser array, and the apparatus may be configured to switch between a first plurality of lasers of the laser array to emit light during the first time and a second plurality of laser to emit light during the second time. 1. An apparatus for active depth sensing , comprising a projector configured to:emit a first distribution of light during a first time; andemit a second distribution of light different from the first distribution of light during a second time,wherein a set of final depth values of one or more objects in a scene is based on one or more reflections of the first distribution of light and one or more reflections of the second distribution of light.2. The apparatus of claim 1 , wherein the projector is further configured to emit a third distribution of light different from the first distribution of light and the second distribution of light during a third time claim 1 , wherein the set of final depth values of the one or more objects in the scene is further based on one or more reflections of the third distribution of light.3. The apparatus of claim 1 , wherein:the projector includes a laser array; andfor each laser of the laser array, the laser emits light during one or more of the first time or the second time.4. The apparatus of claim 3 , wherein claim 3 , for each laser of the laser array claim 3 , the laser emits light during one of the first time or the second ...

SORT INSTRUCTIONS FOR RECONFIGURABLE COMPUTING CORES

According to various aspects, a sorting instruction described herein may advantageously be implemented using intrinsic properties of a reconfigurable computing engine. For example, the reconfigurable computing engine may comprise an arithmetic logic unit (ALU) or other suitable operational unit(s) that can perform one or more comparisons among a given plurality of inputs and output a plurality of select signals that at least indicate maximum and minimum values among the given plurality of inputs. In addition, the reconfigurable computing engine may comprise various multiplexers that make up an interconnect fabric coupled to the ALU or other suitable operational units, wherein the multiplexers may be arranged to receive the plurality of inputs and the plurality of select signals such that the plurality of multiplexers can be dynamically configured to perform the permutations to sort the plurality of inputs. 1. A circuit , comprising:an arithmetic logic unit (ALU) configured to receive an input signal comprising N input values to be sorted and to drive N select signals that at least indicate a maximum value and a minimum value among the N input values, where N is an integer having a value greater than one; andan output switching fabric configured to receive the N input values and the N select signals driven by the ALU, wherein the output switching fabric comprises N multiplexers collectively configured to output at least the maximum value and the minimum value among the N input values based on the N select signals.2. The circuit recited in claim 1 , wherein the ALU and the output switching fabric are provided in a switch box associated with a reconfigurable instruction cell array having multiple switch boxes arranged into one or more rows and one or more columns.3. The circuit recited in claim 1 , wherein the N multiplexers are each individually configured to receive the N input values and a respective one of the N select signals.4. The circuit recited in claim 1 , ...

RECONFIGURABLE INSTRUCTION CELL ARRAY WITH CONDITIONAL CHANNEL ROUTING AND IN-PLACE FUNCTIONALITY

A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array. 1. A circuit , comprising:a plurality of switch boxes, wherein each switch box includes a set of input/output (I/O) ports, each I/O port being configured to receive a plurality of input channels and to output a plurality of output channels;wherein each I/O port includes a plurality of conditional routing circuits corresponding to the plurality of output channels, each conditional routing circuit for each switch box's I/O port including:a first multiplexer configured to select from a group of signals comprising a received input channel from each I/O port remaining in the set of I/O ports for the switch box to form a multiplexer output responsive to a first address signal; anda decoder configured to form the first address signal, the decoder being configurable to operate in a static routing mode of operation in which the first address signal does not depend upon the group of signals, the decoder being further configurable to operate in a conditional routing mode of operation in which the first address signal depends upon a decoder-selected signal from the group of input signals, wherein the conditional routing circuit is configurable to drive the multiplexer output as the conditional routing circuit's output channel.2. The circuit of claim 1 , wherein each switch box includes an instruction cell configured to perform a logical operation on at least one of the input channels received by one of the I/O ports in the set of I/O ports for the switch box to produce an instruction cell ...

System and method for managing pipelines in reconfigurable integrated circuit architectures

A reconfigurable logic array (RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a back pressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate timeswrite-enable inputs of configuration registers are disabled.

Reconfigurable instruction cell array

A reconfigurable processor architecture, compiler and method of program instruction execution provides reduced cost, short design time, low power consumption and high performance. The processor executes program instructions having datapaths of both dependent and independent program instructions. Simultaneous multithreading is also Interconnects Network supported. The processor has a reconfigurable core ( 1 ) with an interconnection network ( 4 ) and a heterogeneous array of instruction cells ( 2 ) each connected to the interconnection network ( 4 ). A decoding module ( 11 ) receives configuration instruction ( 10 ), each instruction encoding the mapping of one of the datapaths to a circuit of the instruction cells ( 2 ). The decoding module ( 11 ) decodes each configuration instruction ( 10 ) and configures the interconnection network ( 4 ) and instruction cells in order to map the datapath to the circuit of the instruction cells and execute the program instructions. A clock module ( 24 ) is reconfigurable each clock cycle by the configuration instruction ( 10 ). The compiler generates configuration instructions ( 10 ) for the processor by identifying the datapaths of both dependent and independent program instructions then mapping them as circuits of the instruction cells ( 2 ) using operation chaining.

Serial configuration of a reconfigurable instruction cell array

Parallel configuration of a reconfigurable instruction cell array

A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Umkonfigurierbares anweisungs-zellen-array

Machine learning accelerator paired with general purpose reconfigurable computing core

A method for accelerating machine learning on a computing device is described. The method includes partitioning neural network parameters and input data processed by a plurality of multiply-accumulate (MAC) units of a MAC array of the computing device. The method also includes interleaving MAC operations on the neural network parameters and the input data accessed according to a data sliding window and/or a stride N to compute an output during each cycle, in which N is greater than or equal to one.