System and method for tuning an RF circuit

A tuning system connected to a tunable RF circuit is described. The tuning system obtains an output of a sensing circuit and processes the output in the control circuit in order to tune one or more passive components in the tunable RF circuit. A related method is also described.

Scalable periphery tunable matching power amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Hot carrier injection compensation

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

Bias Control for Stacked Transistor Configuration

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed. 1. A circuital arrangement comprising: stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;', 'an input port operatively connected to an input transistor of the stacked transistors;', 'an output port operatively connected to the drain terminal of the output transistor; and', 'a reference terminal operatively coupling the input transistor to a reference potential,', 'the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and', 'wherein], 'i) an amplifier comprisingii) a gate bias circuit, a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor; and', 'b) a fixed bias ...

Scalable periphery for digital power control

A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.

Hot carrier injection compensation

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

Low dropout regulator with thin pass device

Systems, methods and apparatus for efficient control and biasing of pass devices that include at least one thin pass device and a remaining of thick pass devices. When operated at extreme high and low voltages, the at least one thin pass device maintains operation in its saturation region of operation while the remaining pass devices may be driven into their triode regions of operation. The thin and thick pass devices are arranged in a cascode configuration that includes a plurality of stacked devices. Biasing of the thin and thick cascode devices can be according to a voltage division scheme which protects the devices when the voltage across the stack is high, and provides a skewed voltage division across the stacked devices that promotes a higher gate-to-source voltage of the thick pass devices for a lower R ON . In one exemplary case, gate length of the at least one thin pass device may be reduced to provide a lower gate-to-source voltage of the thin pass device during operation in the saturation region. An exemplary implementation of an LDO controlling the pass devices for providing RF power to a power amplifier is described.

Hot Carrier Injection Compensation

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly. 1. A radio frequency (RF) amplifier arrangement configured to operate in one of at least two modes of operation , the RF amplifier arrangement comprising:a first transistor stack; anda second transistor stack, the second transistor stack being a reduced-size replica of the first transistor stack,wherein:during the first mode of operation, the first transistor stack and the second transistor stack operate in parallel as an amplifier to provide an output RF signal at an amplifier output node common to an output of the first transistor stack and to an output of the second transistor stack, the amplifier output node coupled to a supply voltage through an inductor, andduring the second mode of operation, the output of the second transistor is decoupled from the amplifier output node and coupled to the supply voltage through a resistor.2. The RF amplifier arrangement of claim 1 , wherein biasing of the first transistor stack and of the second transistor stack during the first mode of operation is based on a voltage at the output of the second transistor stack during the second mode of operation.3. The RF amplifier arrangement of claim 2 , further comprising a bias control module configured to adjust the biasing of the first transistor stack and the second transistor stack based on the voltage at the output of the second transistor stack during the second mode of operation.4. The RF amplifier arrangement of claim 3 , wherein:the voltage at the output of the second transistor stack during the second mode of operation is in correspondence of a bias current through the second transistor stack, andthe bias control module is configured to measure a drift ...

Methods and apparatuses for use in tuning reactance in a circuit device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Methods and Apparatuses for use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies. 1. A tunable inductor , comprising:a first RF terminal;a second RF terminal;one or more inductive elements connected therebetween, wherein each inductive element is an inductor or a portion thereof; anda plurality of switches connected with the one or more inductive elements, wherein each switch in the plurality of switches is configured, during operation, to receive a control signal, the control signal controlling inductance applied between the first RF terminal and the second RF terminal by turning on or off switches in the plurality of switches,wherein at least one inductive element in the one or more inductive elements is connected with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.2. The tunable inductor according to claim 1 , wherein:each inductive element in the one or more inductive elements is connected with at least one switch in the plurality of switches, andeach switch in the at least one switch is configured, during operation, to receive the same control signal.3. The tunable inductor according to claim 2 , wherein each switch in the at least one switch is serially connected therebetween.4. The tunable inductor according to claim 1 , wherein at least one inductive element in the one or more inductive elements is connected in parallel with at least one switch in the plurality of switches.5. The tunable inductor according to claim 1 , wherein the one or more inductive elements is serially connected therebetween. ...

CASCODE GAIN BOOSTING AND LINEAR GAIN CONTROL USING GATE RESISTOR

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor. 1. An amplifier circuit , comprising:an input transistor and an output transistor arranged according to single stage cascode amplifier coupled between a supply voltage and a reference ground, the input transistor and the output transistor being field-effect transistors (FETs); anda capacitor and a resistor in series connection between a gate of the output transistor and the reference ground; the amplifier circuit is configured to operate over a frequency range of operation, and', and', 'a value of the resistor is configured to provide a gain of the amplifier circuit that is higher than a gain of the amplifier circuit for a value of the resistor equal to about zero Ohms., 'over the frequency range of operation,'}], 'wherein'}2. The amplifier circuit according to claim 1 , wherein the frequency range of operation is from about 4 GHz to about 5 GHz.3. The amplifier circuit according to claim 1 , wherein the value of the resistor is in a range from about 5 Ohms to about 20 Ohms.4. The amplifier circuit according to claim 1 , wherein the value of the resistor is in a range from about 5 Ohms to about 30 Ohms.5. The amplifier circuit according to claim 1 , wherein the gain is higher by about 2 dB.6. The ...

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit. 1. An amplifier circuit including:(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;(c) a current source, coupled to the drain of the top FET stage of the cascode reference circuit; and(d) a source follower FET having a gate, a drain, and a source, the drain of the source follower FET ...

Scalable Periphery for Digital Power Control

A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase. 1. An arrangement comprising:an amplifier; and a plurality of transistors connected in parallel with one another, the plurality of transistors electrically connected between the power source and the amplifier; and', 'a logic circuit electrically connected to each of the plurality of transistors, the logic circuit configured, during operation of the arrangement, to send a different logic signal to each transistor of the plurality of transistors to individually enable or disable each transistor of the plurality of transistors., 'a power control circuit operatively coupled to the amplifier and adapted to be coupled to a power source, the power control circuit comprising2. The arrangement according to claim 1 , wherein each logic signal is a logic high signal or a logic low signal.3. The arrangement according to claim 1 , wherein an enabled transistor of the plurality of transistors operates in a triode region of operation of the transistor defined by a corresponding equivalent resistance.4. The arrangement according to claim 1 , wherein during operation claim 1 , a voltage drop through an equivalent parallel resistance of the plurality of transistors of the power control circuit varies as the number of enabled ...

Input Power Detecting Arrangement and Method

An amplifier circuit with an input power detector and a related method are described. With the input power detector and related control network, the arrangement enables and/or disables a number of unit cells in power amplifiers. 1. An arrangement comprising:one or more power amplifiers, each power amplifier comprising a plurality of unit cells, the one or more power amplifiers adapted to amplify an input signal;an input power detector separate from the signal generator, the input power detector coupled with the signal generator and adapted to determine a power level of the input signal at an input of the one or more power amplifiers; anda control network separate from the signal generator and connected with the input power detector, the control network determining, upon receipt of the power level of the input signal, a number of unit cells to disable or enable and then send control signals to the plurality of unit cells of each power amplifier to independently enable and/or disable the unit cells based on the determined number of unit cells.2. The arrangement according to claim 1 , further comprising a transceiver adapted to generate the input signal.3. The arrangement according to claim 1 , wherein the input power detector and the control network are located on a same die.4. The arrangement according to monolithically integrated.5. The arrangement according to claim 1 , wherein the control network is further configured to adjust a bias voltage of a unit cell of the plurality of unit cells of the one or more power amplifiers based on the received power level of the input signal.6. The arrangement according to claim 1 , wherein the control network is further configured to adjust a bias voltage of a unit cell of the plurality of unit cells of the one or more power amplifiers based on the unit cell being enabled or disabled.7. The arrangement according to claim 1 , wherein the control network is further configured to adjust a tunable matching circuit operatively ...

Peak-to-Average Ratio Detector

An amplifier circuit with a peak-to-average ratio detector is described. Detection of the peak-to-average ratio value can be used to tune one or more parameters that affect linearity of one or more amplifiers in the amplifier circuit to improve amplifier performance. 1. An arrangement comprising:one or more amplifiers configured, during operation of the arrangement, to provide a first signal;a detector operatively coupled to the first signal and configured, during operation of the arrangement, to detect an envelope of a coupled signal to produce an envelope signal;a filter operatively connected to the detector and configured, during operation of the arrangement, to filter the envelope signal to produce an average power signal that corresponds to an average power of the coupled signal;a subtractor operatively connected to the detector and the filter and configured, during operation of the arrangement, to produce a difference signal that corresponds to the difference between the envelope signal and the average power signal;anda circuital arrangement operatively connected to the subtractor and configured, during operation of the arrangement, to adjust one or more parameters of the one or more amplifiers based on the difference signal.2. The arrangement according to claim 1 , wherein the circuital arrangement further comprises:an analog-to-digital converter operatively connected to the subtractor and configured, during operation of the arrangement, to produce a digital signal that corresponds to a digital version of the difference signal;a logic circuit operatively connected to the analog-to-digital converter and configured, during operation of the arrangement, to produce one or more logic circuit output signals that are a function of the digital signal, anda linearity control circuit operatively connected to the logic circuit and configured, during operation of the arrangement, to adjust the one or more parameters of the one or more amplifiers based on the one or more ...

System and Method for Tuning an RF Circuit

A tuning system connected to a tunable RF circuit is described. The tuning system obtains an output of a sensing circuit and processes the output in the control circuit in order to tune one or more passive components in the tunable RF circuit. A related method is also described. 1. A system comprising:a sensor circuit configured to provide a first signal to tune one or more adjustable passive elements, the sensor circuit comprising one or more adjustable passive elements;a tunable radio frequency circuit configured to receive a second signal, the tunable RF circuit comprising one or more adjustable passive elements, anda control circuit operatively connected to the sensor circuit and the tunable RF circuit whereby the control circuit receives the first signal from the sensor circuit and provides the second signal to the tunable RF circuit to configure the one or more adjustable passive elements of the tunable RF circuit.2. The system according to claim 1 , wherein the control circuit comprises:a buffer that is operatively connected to the sensor circuit and configured, during operation of the system, to buffer the first signal to produce a buffered version of the first signal;an RF divider that is operatively connected to the buffer and configured, during operation of the system, to reduce a frequency of the buffered version of the first signal to produce a signal corresponding to a buffered, reduced frequency version of the first signal;an internal signal generator that is configured, during operation of the system, to provide a third signal to be compared with the buffered, reduced frequency version of the first signal;a counter that is operatively connected to the RF divider and the internal signal generator and configured, during operation of the system, to compare the buffered, reduced frequency version of the first signal to the third signal; anda control logic circuit that is operatively connected to the counter, the sensor circuit and the tunable RF circuit, ...

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. 1. (canceled)3. The amplification circuit of claim 2 , wherein:the one or more amplifiers comprise two or more amplifiers;inputs of the two or more amplifiers are coupled together, andoutputs of the two or more amplifiers are coupled together.4. The amplification circuit of claim 3 , wherein at least one gate capacitor of the one or more gate capacitors is a bypassing capacitor.5. The amplification circuit of claim 3 , wherein each of the one or more amplifiers comprises a switch connected in series with a gate of the input transistor claim 3 , the switch being configured to open or close the input signal path to the input transistor claim 3 , thus selectively activating or deactivating a corresponding amplifier.6. The amplification circuit of claim 5 , wherein the switch is configured to selectively connect the gate of the input transistor to either the input signal or to a fixed voltage claim 5 , so as to selectively activate or deactivate the one or more amplifiers.7. The amplification circuit of claim 3 , wherein each of the one or more amplifiers is configured to be enabled or disabled by a bias voltage applied to a gate of the input transistor.8. The amplification circuit of claim 3 , wherein each of the one or more amplifiers is configured to be enabled or disabled by one or more bias voltages applied to respective one or more gates of one or more transistors other than the ...

Retractable syringe

An automatic retractable syringe comprised of a syringe inside a compressed spring loaded locking safety sheath that moves into a protective position over the needle of the syringe that is triggered by the depression of the plunger, causing the positional locking mechanism to displace from its initial position and activate a compressed spring that expands, moving the locking safety sheath into its protective position and locks the sheath, preventing further movement of the locking safety sheath. An optional fusing system acts to permanently fix the locking mechanism in place to further secure the locking safety sheath in the protective position.

RESTRAINT SYSTEM

A restraint system for restraining a lower body portion of an individual within a seat including a rigid member configured to selectively restrain the lower body portion such that the lower body portion of the individual is movable only within a predefined area of movement. The rigid member is mounted to the seat and is capable of movement between a stowed position and a deployed position. The lower body portion is restrained by the rigid member when in the deployed position. A locking mechanism locks the rigid member in the stowed position and the deployed position. A release mechanism is associated with the locking mechanism. The release mechanism is located at a predetermined distance from the locking mechanism such that the release mechanism is located outside of the area of movement. 1. A restraint system for restraining a lower body portion of an individual within a seat comprising:a rigid member configured to selectively restrain the lower body portion such that the lower body portion of the individual is movable only within a predefined area of movement, the rigid member being mounted to the seat and being capable of movement between a stowed position and a deployed position, the lower body portion being restrained by the rigid member only in the deployed position;a locking mechanism for locking the rigid member in the stowed position and the deployed position; anda release mechanism associated with the locking mechanism, the release mechanism being located at a predetermined distance from the locking mechanism such that the release mechanism is located outside of the area of movement.2. The restraint system of claim 1 , wherein the restraint system includes a mounting bracket for attaching to a mounting surface near the area of movement of the individual.3. The restraint system of claim 2 , wherein the mounting surface is associated with a seat disposed within a vehicle.4. The restraint system of claim 3 , wherein the seat of the vehicle includes a cavity ...

SINGLE SUPPLY RF SWITCH DRIVER

A single supply RF switch driver. The single supply RF switch driver includes an inverter, where a first resistor has been integrated within the inverter, and the resistor is connected to an RF switch. In one aspect, the integration of the first resistor within the inverter allows for the elimination of a negative power supply for the inverter, while maximizing the isolation achieved in the RF switch. In another aspect, the driver is a configured to have a second resistor integrated within the inverter. A third resistor is connected between the gate of the RF switch and the inverter. In an alternate aspect, the driver operates from a positive power supply and a negative power supply, thus increasing the isolation in the RF switch even further. 120-. (canceled)21. A radio frequency (RF) circuit comprising:an RF input;an RF output;a control input;a plurality of series switch FETs coupled between the RF input and the RF output, the plurality series switch FETs comprising a first MOSFET transistor;a plurality of shunt switch FETs coupled between the RF output and a ground node, the plurality of shunt switch FETs comprising a second MOSFET transistor; a first supply voltage input,', 'a second supply voltage input,', 'a driver output,', 'a third MOSFET transistor with its source coupled to the first supply voltage input,', 'a fourth MOSFET transistor with its source coupled to the second supply voltage input and its drain directly connected to the driver output,', 'a first resistor coupled between a drain of the third MOSFET transistor and the driver output., 'a driver comprising'}22. The RF circuit of claim 21 , further comprising an inverter coupled between the control input and gates of the third MOSFET transistor and the fourth MOSFET transistor.23. The RF circuit of claim 21 , further comprising:a first isolation resistor coupled between a source of shunt switch and the ground node;a second isolation resistor coupled between a drain of the shunt switch and the ground ...

Ruggedness protection circuit

Various methods and circuital arrangements for protection of an RF amplifier are presented. According to one aspect, the RF amplifier is part of switchable RF paths that may include at least one path with one or more attenuators or switches that can be used during normal operation to define different modes of operation of the at least one path. An RF level detector monitors a level of an RF signal during operation of any one of the switchable RF paths and may control the attenuators or switches to provide an attenuation of the RF signal according to a desired level of protection at an input and/or output of the RF amplifier. According to another aspect, the RF level detector may control a switch to force the RF signal through a different switchable RF path.

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit. 1. An amplifier circuit including:(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of ...

Perforated icons with matching lighting

An illuminated switch for use in a vehicle, including: a switch frame; a skin covering the switch frame; at least one icon defined in the skin by a plurality of openings; and at least one light lens is located between the switch frame and the skin, the at least one light lens having a plurality of posts extending from a surface of the at least one light lens, the plurality of posts being arranged to match a configuration of the at least one icon and the plurality of posts extend into the skin such that they terminate at an outer show surface of the skin such that the plurality of openings will be filled with the plurality of posts.

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Methods and Apparatuses for Use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies. 1. (canceled)3. The tunable inductor according to claim 2 , wherein at least one inductive element in the plurality of inductive elements is connected in parallel with at least one switch arrangement in the plurality of switch arrangements.4. The tunable inductor according to claim 2 , wherein the plurality of inductive elements are serially connected therebetween.5. The tunable inductor according to claim 2 , wherein at least one inductive element in the plurality of inductive elements is serially connected with at least one switch arrangement in the plurality of switch arrangements.6. A system for tuning reactance to generate a target signal claim 2 , the system comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the tunable inductor according to , wherein the tunable inductor is configured, during operation, to receive a first signal and generate a second signal; and'}a controller configured, during operation, to provide a plurality of control signals to the tunable inductor, wherein the plurality of control signals is a function of the second signal and the target signal.7. A method for tuning reactance of a circuital arrangement to generate a target signal claim 2 , the method comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'providing the tunable inductor according to ;'}applying a first signal and a plurality of control signals to the tunable inductor, wherein reactance of the tunable inductor is a function of the plurality of control signals;generating a second signal ...

Methods and Apparatuses for Use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Methods and Apparatuses for Use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies. 1. canceled3. The tunable inductor of claim 2 , wherein the plurality of second RF terminals are all tied together.4. A system for tuning reactance to generate a second signal claim 2 , the system comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the tunable inductor according to , wherein the tunable inductor is configured, during operation, to receive a first signal and generate the second signal; and'}a controller configured, during operation, to provide a plurality of control signals to the tunable inductor, wherein the plurality of control signals is a function of the second signal to be generated.5. A method for tuning reactance of a circuital arrangement to generate a second signal claim 2 , the method comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'providing the tunable inductor according to ;'}applying a first signal and a plurality of control signals to the tunable inductor, wherein reactance of the tunable inductor is a function of the plurality of control signals; andgenerating the second signal based on the applying.6. The tunable inductor of claim 2 , wherein switch elements of the at least two switch elements receive the same control signal.7. The tunable inductor of claim 6 , wherein the switch elements of the at least two switch elements are serially interconnected.8. The tunable inductor of claim 7 , wherein at least one switch element of the at least two switch elements is selected from a group consisting of a field effect transistor claim 7 , an ...

High power rf switch with controlled well voltage for improved linearity

RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. 1. (canceled)2. An amplification circuit , comprising: a stack of a plurality of transistors, and', 'one or more gate capacitors connected to respective one or more transistors of the plurality of transistors;, 'one or more amplifiers, wherein each amplifier of the one or more amplifiers comprisesan output tunable matching network operatively connected to an output of the amplification circuit, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplification circuit; an input transistor of the plurality of transistors of each of the amplifiers is configured to receive an input signal;', 'the one or more gate capacitors are connected between one or more gates of the respective one or more transistors and a reference ground with the exception of the input transistor;', 'a non-bypassing gate capacitor of the one or more gate capacitors is configured to allow a gate voltage of a respective transistor of the plurality of transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor., 'wherein, in each amplifier3. The amplification circuit of claim 2 , wherein the tunable matching network comprises:one or more tunable reactive elements connected between the output of the amplification circuit and the output load; anda tunable matching control circuit configured to tune the one or more ...

3D ICON FOR USE WITH A SWITCH AND A MEHTOD OF MAKING THE 3D ICON

An assembly including a three dimensional icon defined within an interior of the assembly; the assembly including a non-moveable switch; a device for illuminating the three dimensional icon, wherein illumination of the three dimensional icon by the device causes the three dimensional icon to be visible on an exterior surface of the assembly. 1. An assembly , comprising:a three dimensional icon defined within an interior of the assembly;a non-moveable switch;a device for illuminating the three dimensional icon, wherein illumination of the three dimensional icon by the device causes the three dimensional icon to be visible on an exterior surface of the assembly.2. The assembly as in claim 1 , further comprising a polycarbonate substrate layer and the three dimensional icon is molded into the polycarbonate substrate layer.3. The assembly as in claim 2 , further comprising a layer of polyurethane applied to the polycarbonate layer.4. The assembly as in claim 1 , wherein the non-moveable switch is a capacitive sensor integrated with a printed circuit board.5. The assembly as in claim 3 , wherein the non-moveable switch is a printed touch sensor integrated into a flexible film located on a forward facing surface of the polycarbonate substrate layer that is disposed adjacent to the layer of polyurethane.6. The assembly as in claim 5 , wherein the flexible film is injection molded with the polycarbonate substrate layer.7. The assembly as in claim 1 , wherein the assembly is a portion of a vehicle interior.8. The assembly as in claim 1 , wherein the device is a light emitting diode (LED).9. The assembly as in claim 1 , further comprising a polycarbonate substrate layer and an icon sub-assembly inserted into an opening located in the polycarbonate substrate layer and a layer of polyurethane applied to the polycarbonate layer claim 1 , wherein the icon sub-assembly includes the three dimensional icon and the device for illuminating the three dimensional icon.10. The assembly ...

HIDDEN SWITCH EMBEDDED IN SOFT THERMOPLASTIC ELASTOMER OR POLYURETHANE AND METHOD OF MAKING

An assembly, the assembly including: an injection molded structural electronic component, the injection molded structural electronic component including a non-moveable switch and an illuminating device; a layer of polyurethane or thermoplastic elastomer overmolded on the injection molded structural electronic component, the layer of polyurethane or thermoplastic elastomer providing an exterior surface of the assembly; an icon located in the layer of polyurethane or thermoplastic elastomer overmolded on the injection molded structural electronic component, the icon corresponding to the non-moveable switch, wherein illumination of the icon by the illuminating device causes the icon to be visible on the exterior surface of the assembly and the exterior surface of the assembly prevents the icon from being visible when it is not illuminated by the illuminating device. 1. An assembly , comprising:an injection molded structural electronic component, the injection molded structural electronic component including a non-moveable switch and an illuminating device;a layer of polyurethane or thermoplastic elastomer overmolded on the injection molded structural electronic component, the layer of polyurethane or thermoplastic elastomer providing an exterior surface of the assembly;an icon located in the layer of polyurethane or thermoplastic elastomer overmolded on the injection molded structural electronic component, the icon corresponding to the non-moveable switch, wherein illumination of the icon by the illuminating device causes the icon to be visible on the exterior surface of the assembly and the exterior surface of the assembly prevents the icon from being visible when it is not illuminated by the illuminating device.2. The assembly as in claim 1 , the icon is a three dimensional icon.3. The assembly as in claim 1 , wherein the assembly is a portion of a vehicle interior.4. The assembly as in claim 1 , wherein the illuminating device is a light emitting diode (LED).5. The ...

VEHICLE INTERIOR TRIM PART FORMED WITH INTERGRATED ELECTRONICS AND METHOD OF MAKING

An assembly, the assembly including: a substrate; an injection molded structural electronic component; and a layer of polymer that partially encapsulates the substrate and the injection molded structural electronic component and unifies the substrate and the injection molded structural electronic component into one component. 1. An assembly , comprising:a substrate;an injection molded structural electronic component; anda layer of polymer that partially encapsulates the substrate and the injection molded structural electronic component and unifies the substrate and the injection molded structural electronic component into one component.2. The assembly as in claim 1 , further comprising another injection molded structural electronic component.3. The assembly as in claim 1 , further comprising alternative electronics.4. The assembly as in claim 3 , wherein the injection molded structural electronic component has a cut out portion that is configured to receive the alternative electronics.5. The assembly as in claim 1 , wherein the assembly is a portion of a vehicle interior.6. The assembly as in claim 1 , wherein the assembly comprises a plurality of icons.7. A method for providing an assembly claim 1 , comprising:forming an injection molded substrate;forming at least one injection molded structural electronic component;placing the injection molded substrate and the at least one injection molded structural electronic component in a tool; andpartially overmolding the injection molded substrate and the at least one injection molded structural electronic component with a polymer injected into the tool; andunifying the injection molded substrate and the at least one injection molded structural electronic component into one component with the polymer.8. The method as in claim 7 , wherein another injection molded structural electronic component is placed in the tool prior to the partially overmolding step.9. The method as in claim 7 , wherein alternative electronics are ...

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. 1. An amplifier , comprising:a scalable periphery amplifier comprising one or more unit cells connected in parallel with each other and adapted to be selectively activated or deactivated, wherein each unit cell comprises a plurality of active devices configured to operate as an amplifier;an output tunable matching network operatively connected to an output of the scalable periphery amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the scalable periphery amplifier; andan amplifier control circuitry configured to selectively activate or deactivate the one or more unit cells, thus varying a total output power from the amplifier,wherein the plurality of active devices of the one or more unit cells are a stack of a plurality of transistors, an input transistor of the plurality of transistors in the stack being configured to receive an input signal of the scalable periphery amplifier.2. The amplifier according to claim 1 , wherein the plurality of transistors of the stack are configured to substantially equalize an output voltage at an output terminal of the stack across the plurality of transistors of the stack.3. The amplifier according to claim 2 , further comprising an input tunable matching network operatively connected to an input of the scalable periphery amplifier claim 2 , wherein an impedance of the input tunable ...

Methods and Apparatuses for use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies. 1a first RF terminal;a second RF terminal;one or more inductive elements connected therebetween, wherein each inductive element is an inductor or a portion thereof; anda plurality of switches coupled with the one or more inductive elements, wherein each switch in the plurality of switches is configured to receive a control signal, and wherein the control signal controls inductance applied between the first RF terminal and the second RF terminal by turning on or off switches in the plurality of switches,and wherein at least one inductive element in the one or more inductive elements is coupled with at least two switches from among the plurality of switches, the at least two switches being serially connected therebetween.. A tunable inductor, comprising: The present application is a continuation of co-pending U.S. patent Ser. No. 13/595,893 filed on Aug. 27, 2012 and claims priority thereto; application Ser. No. 13/595,893 is a continuation-in-part of U.S. patent application Ser. No. 12/735,954 filed on Aug. 27, 2010 (now U.S. Pat. No. 9,024,700, issued May 5, 2015), and the present continuation application claims priority thereto; Both application Ser. Nos. 13/595,893 and 12/735,954 are incorporated herein by reference in their entirety; application Ser. No. 12/735,954 is a 371 National Stage Entry of PCT Patent International Application No. PCT/US09/01358 filed on Mar. 2, 2009, entitled “Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device”, and the present ...

Clocked Frequency Detector RF Auto-Tuning System

Devices and methods for auto-tuning a tunable circuit based on a frequency of operation of the tunable circuit using a clocked frequency detector circuit are described. The clocked frequency detector uses a readily available clock signal to drive a counter circuit to provide an indication of the frequency of operation of the tunable circuit. The tunable circuit, including the clocked frequency detector, can be integrated within a same chip that is autonomously configurable based on the frequency of operation and the readily available clock. 1. A radio frequency (RF) tunable integrated circuit configured to operate over a frequency range of operation of an input RF signal , comprising:one or more tunable elements; and{'sub': 'o', 'a clocked frequency detector circuit configured to detect an indication of a frequency of operation, f, of the input RF signal based on an externally supplied reference clock to the RF tunable integrated circuit,'}wherein tuning of the one or more tunable elements is based on the detected indication of the frequency of operation of the input RF signal, and is configured to provide a tuned frequency dependent performance of an output RF signal of the tunable integrated circuit.2. The radio frequency (RF) tunable integrated circuit according to claim 1 , wherein the clocked frequency detector circuit comprises:{'sub': 'o', 'a divide-by-N circuit configured to receive the input RF signal and generate therefrom a divide-by-N signal with a frequency of f/N that is higher than a frequency of the reference clock, N being a number substantially greater than one; and'}a counter circuit configured to receive the divide-by-N signal and count a number of cycles of the divide-by-N signal in a period of the reference clock.3. The radio frequency (RF) tunable integrated circuit according to claim 2 , further comprising an enabling circuit comprising a level detector claim 2 , the enabling circuit configured to provide an enabling signal to the clocked ...

Stacked Power Amplifier Power Control

Systems, methods and apparatus for efficient power control and/or compensation with respect to a varying supply voltage of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control and/or compensation is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift/variation in output power of the RF amplifier.

Stacked PA Power Control

Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.

Bias Control for Stacked Transistor Configuration

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented. 1. A circuital arrangement comprising: stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;', 'an input port operatively connected to an input transistor of the stacked transistors;', 'an output port operatively connected to the drain terminal of the output transistor; and', 'the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and', 'a reference terminal operatively coupling the input transistor to a reference potential, wherein], 'i) an amplifier comprisingii) a gate bias circuit, 'the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a desired voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the desired voltage at the source terminal of the ...

Hot Carrier Injection Compensation

Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly. 1. A radio frequency (RF) amplifier arrangement comprising:a first transistor stack configured, during operation, to amplify an RF signal at an input gate of the first transistor stack and provide an amplified version of the RF signal at an output terminal of the first transistor stack;a second transistor stack configured, during operation, to amplify the RF signal at an input gate of the second transistor stack and provide an amplified version of the RF signal at an output terminal of the second transistor stack;a first switch operatively connected between the output terminal of the first transistor stack and the output terminal of the second transistor stack, the first switch being configured, during operation, to provide a short or an open between the output terminals of the first and second transistor stacks;a second switch operatively connected between the output terminal of the second transistor stack and a first terminal of a resistor, the second switch being configured, during operation, to provide a short or an open between the output terminal of the second transistor stack and the first terminal of the resistor, anda bias control module operatively connected to the first terminal of the resistor via an input sense terminal of the bias control module and operatively connected to the input gate of the first transistor stack and the input gate of the second transistor stack via an output terminal of the bias control module.2. The RF amplifier arrangement of claim 1 , wherein during operation claim 1 , the RF amplifier arrangement is configured to operate in one of at least two selectable modes of operation claim 1 , comprising: a) a ...

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. 2. The amplification circuit of claim 1 , wherein each of the one or more amplifiers comprises a switch connected in series with a gate of the input transistor claim 1 , the switch being configured to open or close the input signal path to the input transistor claim 1 , thus selectively activating or deactivating a corresponding amplifier.3. The amplification circuit of claim 2 , wherein the switch is configured to selectively connect the gate of the input transistor to either the input signal or to a fixed voltage claim 2 , so as to selectively activate or deactivate the one or more amplifiers.4. The amplification circuit of claim 1 , wherein each amplifier of the one or more amplifiers is a biased amplifier claim 1 , a bias being applied to the biased amplifier.5. The amplification circuit of claim 2 , wherein each switch is controlled by a control circuitry of the amplification circuit.6. The amplification circuit of claim 1 , further comprising an output tunable matching network operatively connected to an output of the amplification circuit claim 1 , wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplification circuit.7. The amplification circuit of claim 6 , wherein the output tunable matching network comprises:one or more tunable reactive elements connected between the output of the amplification circuit and the ...

LNA with Controlled Phase Bypass

In electronic circuits having various gain states, small gain phase shift differences required among various gain states may pose a challenging problem. The disclosed methods and devices provide solution to such challenge. Electronic circuits are described wherein a first path including an amplifier may be bypassed by a second path including only passive elements and for gain states smaller than 0 dB. In such electronic circuits, a phase shifter included in the second path can be adjusted to address the required phase shift among various gain states. 1. An electronic circuit comprising:a first path and a second path, each connecting an input of the electronic circuit with an output of the electronic circuit; the first path comprises an amplifier;', 'at least one of the first path or the second path comprises one or more phase shifters; and', 'the second path is configurable to bypass the first path., 'wherein2. The electronic circuit of claim 1 , further comprising a plurality of gain states claim 1 , and wherein the one or more phase shifters are configured to adjust gain phase shift differences among the plurality of gain states according to a set gain phase shift difference requirement.3. The electronic circuit of claim 2 , wherein the set gain phase shift difference requirement is such that the phase shift difference lies within +/−30 degrees.4. The electronic circuit of claim 2 , wherein the set gain phase shift difference requirement is such that the phase shift difference lies within +/−10 degrees.5. The electronic circuit of claim 1 , wherein the one or more phase shifters comprises one or more variable phase shifters.6. The electronic circuit of claim 2 , wherein at least one of the first or the second path comprises one or more attenuators.7. The electronic circuit of claim 6 , further comprising one or more parallel switches each coupling across a corresponding attenuator of the one or more attenuators.8. The electronic circuit of claim 7 , wherein each ...

RF Transmit Path Calibration via On-Chip Dummy Load

Methods and devices are described for calibrating RF transmit paths of an RF front-end stage with minimum transmitted RF power at an output port of the RF front-end stage. Furthermore, an integrated RF switch with a terminating switchable load is presented which can be used to terminate a transmit path at the point of termination for measuring an RF signal at that point. 1. A radio frequency (RF) circuital arrangement configured to transmit an RF signal at an output RF transmit port via one or more RF transmit paths , wherein a transmit path of the one or more transmit RF paths comprises:one or more adjustable RF devices configured during operation to affect one or more characteristics of the RF signal; anda terminating switch positioned between an adjustable RF device of the one or more adjustable RF devices and the output RF transmit port,wherein:during a first mode of operation of the RF transmit path, the terminating switch is configured to couple the RF signal to the output RF transmit port, andduring a second mode of operation of the RF transmit path, the terminating switch is configured to isolate the RF signal from the output RF transmit port and terminate the RF signal into a terminating load connected to a terminating terminal of the terminating switch.2. The RF circuital arrangement of claim 1 , further comprising an output switch claim 1 , wherein the output switch is configured to couple a selected RF transmit path of the plurality of RF transmit paths to the output RF transmit port and isolate a remaining RF transmit paths of the plurality of RF transmit paths from the output RF transmit port.3. The RF circuital arrangement of claim 1 , wherein an isolation provided by the terminating switch with respect to the output RF transmit port during the second mode of operation is equal to or greater than about 25 dB.4. The RF circuital arrangement of claim 2 , wherein a combined isolation provided by the terminating switch and the output switch during the ...

Clockless Frequency Detector

Devices and methods for tuning a tunable circuit based on a frequency of operation of the tunable circuit using a clockless frequency detector circuit are described. The clockless frequency detector uses a filter having a slope in its frequency response curve that includes a frequency range of operation of the tunable circuit. Frequency-based attenuation through the filter of an RF signal provided to the tunable circuit is used to provide an indication of the frequency of operation. The tunable circuit, including the clockless frequency detector, can be integrated within a same chip that is autonomously configurable based on the frequency of operation.

Low Noise Amplifier with Tunable Bypass Match

A front end module (FEM) and associated method for receiving signals in a front end module are disclosed. Some embodiments of the FEM have three inputs. The FEM can process the input signals in one of three bypass modes. In bypass modes, switchable tank circuits provide a high impedance to isolate active components from the bypass path. This improves the input return loss in the passive bypass mode and thus improves the performance of the passive bypass mode by allowing the use of LNAs without an input switch. In the active gain mode, one of a plurality of signals are amplified by one of an equal number of amplifiers coupled to the FEM output. Accordingly, the FEM can output signals applied to any one of the FEM inputs in bypass mode, or an amplified version of one of the input signals. In some embodiments, the FEM has only one input and one LNA. In such embodiments, an output selector switch selects between a bypass path and a gain path. 1. A gain/bypass circuit comprising:(a) a low noise amplifier (LNA) directly coupled to a gain/bypass circuit input and selectively coupled to a gain/bypass circuit output; and wherein in bypass mode the matching network is coupled to the gain/bypass circuit input and to the gain/bypass circuit output and the LNA output is disconnected from the gain/bypass circuit output; and', 'wherein in gain mode, the matching network is disconnected from the gain/bypass circuit input and the gain/bypass circuit output and the LNA output is connected to the gain/bypass circuit output., '(b) a matching network selectively coupled to the gain/bypass circuit input and selectively coupled to a gain/bypass circuit output, wherein the input impedance of the matching network is such that the impedance at the gain/bypass circuit input in bypass mode is within a desired tolerance of the impedance at the gain/bypass circuit input in gain mode;'}2. The gain/bypass circuit of claim 1 , wherein the impedance of the matching network is selectable.3. The gain/ ...

CASCODE AMPLIFIER BIAS CIRCUITS

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit. 1. A method for biasing the final stages of a cascode amplifier , including:(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;(c) automatically adjusting a gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the ...

Bias control for stacked transistor configuration

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

Higher linearity passive mixer

Transmission of a high frequency signal is provided by a passive mixer. The passive mixer receives a low frequency signal as an input. The passive mixer includes a plurality of transistors each with a gate, a source, and a drain. The passive mixer also includes a local oscillator connected to the gates of the transistors. The gates of the transistors are also connected to a DC bias proportional to the threshold voltage of the transistors. In addition, an output of the passive mixer may be attenuated by a passive attenuator wherein both the passive attenuator and passive mixer are substantially free of quiescent current.

Cascode amplifier bias circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

New compounds derived from schweinfurthins G, E, F

Nouveaux composés dérivés des schweinfurthine s G , E, F La présente invention concerne des nouveaux composés dérivés des schweinfurthines de formule (I) : Elle concerne également les compositions pharmaceutiques les contenant ainsi que leur utilisation pour la prévention, l’inhibition et/ou le traitement de cancers, de maladies neurodégénératives, de la dyslipidémie, de l’hypercholestérolémie, et/ou de maladies virales et leurs procédés de préparation. Figure : Néant. New compounds derived from schweinfurthins G, E, F The present invention relates to new compounds derived from schweinfurthins of formula (I): It also relates to the pharmaceutical compositions containing them as well as their use for the prevention, inhibition and / or treatment of cancers, neurodegenerative diseases, dyslipidemia, hypercholesterolemia, and/or viral diseases and processes for their preparation. Figure: None.

Scalable periphery tunable matching power amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Clocked frequency detector RF auto-tuning system

Devices and methods for auto-tuning a tunable circuit based on a frequency of operation of the tunable circuit using a clocked frequency detector circuit are described. The clocked frequency detector uses a readily available clock signal to drive a counter circuit to provide an indication of the frequency of operation of the tunable circuit. The tunable circuit, including the clocked frequency detector, can be integrated within a same chip that is autonomously configurable based on the frequency of operation and the readily available clock.

Methods and apparatuses for use in tuning reactance in a circuit device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Incandescent lamp with filament mounting means and socket adaptor

INCANDESCENT LAMP WITH FILAMENT MOUNTING MEANS AND SOCKET ADAPTOR Abstract of the Disclosure An incandescent electric lamp having an envelope with a portion through which a pair of lead-in studs are brought out, the filament leads being connected to the studs. The lamp is sealed off in the area where the studs are located and an adaptor is provided to make contact with the portions of the studs extending through the envelope so that the lamp can be mounted in a socket. * * * * * * * * *

BULB WITH BULB HOLDER AND INTERMEDIATE PLUG

Restraint system for vehicle

An apparatus and for restraining occupants of a vehicle is disclosed, the apparatus having a rigid member configured to restrain an upper or lower body portion of an individual located in the vehicle. The individual moves within a range of motion that is represented by an area of movement. The rigid member is capable of movement between a stowed position and a deployed position. The upper body portion or the lower body portion is restrained by the rigid member only in the deployed position. A locking mechanism for locking the rigid member in the stowed position and the deployed position is provided. A release mechanism activates the locking mechanism. The release mechanism is located at a predetermined distance from the locking mechanism such that the release mechanism is located outside of the area of movement.

Tunable wilkinson splitter

Methods and apparatuses for providing a tunable Wilkinson power splitter are presented. According to one aspect, the tunable splitter includes tunable branches realized via lumped elements that provide controlled impedance and phase at different selectable center frequencies of operation. For each of the center frequencies, the tunable Wilkinson splitter has a performance according to a corresponding fixed center frequency Wilkinson power splitter provided by a relatively narrow instantaneous bandwidth. Over a number of the center frequencies supported, performances of the tunable Wilkinson splitter overlap to provide a combined performance having a desired wider bandwidth. According to another aspect, each of the tunable branches includes an LC network that includes tunable capacitors and inductors. One or more of the tunable Wilkinson power splitters can be cascaded to provide a performance according to a wider instantaneous bandwidth.

Input power detecting arrangement and method

An amplifier circuit with an input power detector and a related method are described. With the input power detector and related control network, the arrangement enables and/or disables a number of unit cells in power amplifiers.

HIDDEN SWITCH EMBEDDED IN SOFT THERMOPLASTIC ELASTOMER OR POLYURETHANE AND METHOD OF MANUFACTURING

Eine Anordnung (10), wobei die Anordnung (10) enthält: eine spritzgegossene strukturelle elektronische Komponente (14), wobei die spritzgegossene strukturelle elektronische Komponente (14) einen nicht beweglichen Schalter (20) und eine Beleuchtungsvorrichtung (22) enthält; eine Schicht aus Polyurethan oder thermoplastischem Elastomer (16), die auf der spritzgegossenen strukturellen elektronischen Komponente (14) übergeformt ist, wobei die Schicht aus Polyurethan oder thermoplastischem Elastomer (16) eine Außenfläche der Anordnung (10) bereitstellt; ein Symbol (12), das sich in der Schicht aus Polyurethan oder thermoplastischem Elastomer (16), die auf der spritzgegossenen strukturellen elektronischen Komponente (14) übergeformt ist, befindet, wobei das Symbol (12) dem nicht beweglichen Schalter (20) entspricht, wobei eine Beleuchtung des Symbols (12) durch die Beleuchtungsvorrichtung (22) bewirkt, dass das Symbol (12) auf der Außenfläche der Anordnung (10) sichtbar ist, und die Außenfläche der Anordnung (10) verhindert, dass das Symbol (12) sichtbar ist, wenn es nicht durch die Beleuchtungsvorrichtung (22) beleuchtet wird. An assembly (10), the assembly (10) including: an injection molded structural electronic component (14), the injection molded structural electronic component (14) including a fixed switch (20) and a lighting device (22); a layer of polyurethane or thermoplastic elastomer (16) overmolded on the injection molded structural electronic component (14), the layer of polyurethane or thermoplastic elastomer (16) providing an exterior surface of the assembly (10); a symbol (12) residing in the layer of polyurethane or thermoplastic elastomer (16) overmolded on the injection molded structural electronic component (14), the symbol (12) corresponding to the immovable switch (20); wherein illumination of the symbol (12) by the lighting device (22) causes the symbol (12) to be visible on the outer surface of the arrangement (10), and the outer surface of the ...

Cascode gain boosting and linear gain control using gate resistor

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Schaltkapazitätsaufhebungsschaltung

Es werden Verfahren und Vorrichtungen zur Beseitigung nichtlinearer Kapazitäten in Hochleistungs-Hochfrequenz-(HF-)Schaltern, die in Bulk-Complementary-Metal-Oxide-Semiconductor-(CMOS-)Verfahren hergestellt werden, offenbart. Die Verfahren und Vorrichtungen sind auch auf gestapelte Schalter und HF-Schalter anwendbar, die in Silizium-auf-Isolator-(SOI-)Technologie hergestellt werden.

Loro produzione e la realizzazione procedimento per la preparazione di del procedimento pastiglie nonche macchina per la

Methods and Apparatus for Selection of a Virtualisation Engine

Embodiments described herein relate to methods and apparatuses for selecting a first virtualisation engine to execute an application deployment request. A method in a selection engine ( 104, 700 ) comprises receiving ( 300 ) an application deployment request ( 101 ) comprising an identification of an application image ( 102 ); selecting ( 306 ) the first virtualisation engine from a plurality of virtualisation engines based on a plurality of respective values of at least one characteristic associated with execution of the application image by each of the plurality of virtualisation engines; and initiating ( 308 ) execution of the application image by the first virtualisation engine.

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Scalable periphery tunable matching power amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

High power RF switch with controlled well voltage for improved linearity

RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.

Lampada ad incandescenza e relativo attacco

Methods and apparatus for selection of a virtualisation engine

Embodiments described herein relate to methods and apparatuses for selecting a first virtualisation engine to execute an application deployment request. A method in a selection engine (104, 700) comprises receiving (300) an application deployment request (101) comprising an identification of an application image (102); selecting (306) the first virtualisation engine from a plurality of virtualisation engines based on a plurality of respective values of at least one characteristic associated with execution of the application image by each of the plurality of virtualisation engines; and initiating (308) execution of the application image by the first virtualisation engine.

3D-Bildzeichen zur Verwendung mit einem Schalter und ein Verfahren zum Herstellen des 3D-Bildzeichens

Anordnung aufweisend ein dreidimensionales Bildzeichen, das in einem Inneren der Anordnung gebildet ist; wobei die Anordnung aufweist: einen nicht bewegbaren Schalter; eine Einrichtung zur Beleuchtung des dreidimensionalen Bildzeichens, wobei das Beleuchten des dreidimensionalen Bildzeichens durch die Einrichtung bewirkt, dass das dreidimensionale Bildzeichens auf einer Außenfläche der Anordnung sichtbar ist.

Cascode amplifier bias circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Cascode gain boosting and linear gain control using gate resistor

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Switch capacitance cancellation circuit

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal–oxide–semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Cascode gain boosting and linear gain control using gate resistor

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Lna with tx harmonic filter

Methods and devices for reducing coupling of RF frequency components between different bands of an RF system are presented. In one aspect, a notch filter having a notch centered at a harmonic of a fundamental frequency of a first band transmit side is coupled to an output of an LNA of the first band. In another aspect, the harmonic is a second harmonic, a third harmonic or higher order harmonics. In another aspect, the notch filter includes a plurality of notches at respective plurality of harmonics. In a further aspect, the notch has an attenuation of 30 dB or greater at the second harmonic and 10 dB or greater at the third harmonic. Further included is a method for reducing coupling of harmonics of signals transmitted in the first band into a receive path of the second band, thereby increasing noise figure/sensitivity performances of the receive path.

Perforated icons with matching lighting

An illuminated switch for use in a vehicle, including: a switch frame; a skin covering the switch frame; at least one icon defined in the skin by a plurality of openings; and at least one light lens is located between the switch frame and the skin, the at least one light lens having a plurality of posts extending from a surface of the at least one light lens, the plurality of posts being arranged to match a configuration of the at least one icon and the plurality of posts extend into the skin such that they terminate at an outer show surface of the skin such that the plurality of openings will be filled with the plurality of posts.

Source Switch Split LNA Design with Thin Cascodes and High Supply Voltage

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Low noise architecture for a direct conversion transmitter

Switch capacitance cancellation circuit

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Tunable Wilkinson splitter

Methods and apparatuses for providing a tunable Wilkinson power splitter are presented. According to one aspect, the tunable splitter includes tunable branches realized via lumped elements that provide controlled impedance and phase at different selectable center frequencies of operation. For each of the center frequencies, the tunable Wilkinson splitter has a performance according to a corresponding fixed center frequency Wilkinson power splitter provided by a relatively narrow instantaneous bandwidth. Over a number of the center frequencies supported, performances of the tunable Wilkinson splitter overlap to provide a combined performance having a desired wider bandwidth. According to another aspect, each of the tunable branches includes an LC network that includes tunable capacitors and inductors. One or more of the tunable Wilkinson power splitters can be cascaded to provide a performance according to a wider instantaneous bandwidth.

Novel compounds derived from schweinfurthins g, e and f

Novel compounds derived from schweinfurthins G, E and F The present invention relates to novel compounds derived from schweinfurthins of formula (I): (I). The invention also relates to pharmaceutical compositions containing them and also to the use thereof for the prevention, inhibition and/or treatment of cancers, neurodegenerative diseases, dyslipidaemia, hypercholesterolaemia, parasitic diseases and/or viral diseases and to processes for preparing them.

Saugdämpfvorrichtung mit interner Dämpfung für einen Kompressor der Klimaanlage eines Fahrzeugs

Eine Saugdämpfvorrichtung umfasst ein Gehäuse mit einer Einlassöffnung, die darin gebildet ist, und ein Ventilgehäuse, das angrenzend an die Einlassöffnung angeordnet ist. Das Ventilgehäuse umfasst mindestens eine Öffnung, die darin gebildet ist. Ein Ventilkern ist gleitfähig innerhalb des Ventilgehäuses angeordnet. Ein Hebel, der eine Rotationsachse aufweist, der an einem Teil des Ventilgehäuses angebracht ist, umfasst einen ersten Hebelarm, der an einer ersten Seite der Rotationsachse angeordnet ist, und einen zweiten Hebelarm, der an einer zweiten Seite der Rotationsachse angeordnet ist. Der zweite Hebelarm stößt an eine umlaufende Außenfläche des Ventilkerns. Ein Federelement ist zwischen dem ersten Hebelarm und dem Ventilkern angeordnet. Das Federelement ist konfiguriert, um eine Kraft auf den ersten Hebelarm auszuüben, um zu verursachen, dass der zweite Hebelarm eine laterale Kraft auf den Ventilkern ausübt, um Vibrationen des Federelements zu dämpfen.

Scalable Periphery Tunable Matching Power Amplifier

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Mit integrierter elektronik ausgebildetes fahrzeuginnenverkleidungsteil und verfahren zur herstellung

Eine Anordnung, wobei die Anordnung enthält: ein Substrat; eine spritzgegossene strukturelle elektronische Komponente; und eine Polymerschicht, die das Substrat und die spritzgegossene strukturelle elektronische Komponente teilweise einkapselt und das Substrat und die spritzgegossene strukturelle elektronische Komponente zu einer einzigen Komponente vereinigt.

Source switch split LNA design with thin cascodes and high supply voltage

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Novel compounds derived from schweinfurthins g, e and f

Novel compounds derived from schweinfurthins G, E and F The present invention relates to novel compounds derived from schweinfurthins of formula (I): (I). The invention also relates to pharmaceutical compositions containing them and also to the use thereof for the prevention, inhibition and/or treatment of cancers, neurodegenerative diseases, dyslipidaemia, hypercholesterolaemia, parasitic diseases and/or viral diseases and to processes for preparing them.

Lna with tx harmonic filter

Methods and devices for reducing coupling of RF frequency components between different bands of an RF system are presented. According to one aspect, a notch filter having a notch centered at a harmonic of a fundamental frequency of a first band transmit side is coupled to an output of an LNA of the first band. According to another aspect, the harmonic is a second harmonic, a third harmonic or higher order harmonics. According to another aspect, the notch filter includes a plurality of notches at respective plurality of harmonics. According to a further aspect, the notch has an attenuation of 30 dB or greater at the second harmonic and 10 dB or greater at the third harmonic. Further included is a method for reducing coupling of harmonics of signals transmitted in the first band into a receive path of the second band, thereby increasing noise figure/sensitivity performances of the receive path.

Methods and Apparatuses for Use in Tuning Reactance in a Circuit Device

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

On-premises positioning determination and analytics system

The present disclosure provides methods and systems for tracking a shipping vessel travel route through a retail enterprise during a stock cycle. Location information associated with assets can be collected at a retail location, from which a detailed route through the retail location may be recreated and overlaid on map data reflecting a retail location layout. Further analysis may be performed on the route. Additionally, the route may be overlaid on a map, including product information and packaging information, allowing for various metrics and metric visualizations to be generated that can be further analyzed to achieve various objectives.

Switch capacitance cancellation circuit

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Stacked PA power control

Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.

Bias control for stacked transistor configuration

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.