CACHE MEMORY CAPABLE OF ADJUSTING BURST LENGTH OF WRITE-BACK DATA IN WRITE-BACK OPERATION

A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block. 111-. (canceled)12. A cache memory comprising:a write-back determination unit determining whether a block is a write-back block based on replacement information on the block;a burst length determination unit determining a burst length of write-back data included in the write-back block based on a number of effective bits of a n-bit dirty value and a minimum burst length, when the block is the write-back block; anda processor outputting a first output signal for controlling a data storing unit to output the write-back data in response to the determined burst length and outputting a second output signal for performing a read operation to a system bus.13. The cache memory of claim 12 , wherein the replacement information comprises at least one of information on the block claim 12 , frequency of accesses of the block claim 12 , and data update time of the block.14. The cache memory of claim 12 , wherein the first output signal is a write-back operation signal and is output to the data storing unit.15. The cache memory of claim 12 , wherein the second output signal is a data request signal including a read address.16. The cache memory of claim 12 , wherein the burst length is an integer multiple of the minimum burst length.17. The cache memory of claim 12 , further comprising a dirty value storing unit storing the n-bit dirty value.18. The cache memory of claim 12 , further comprising a write-back buffer storing the write-back data output from the data storing unit to the system bus.19. The cache memory of claim 12 , wherein the burst length ...

TESSELLATION METHOD FOR ASSIGNING A TESSELLATION FACTOR PER POINT AND DEVICE PERFORMING THE METHOD

A tessellation method includes assigning a tessellation factor to each of a plurality of points in a patch and generating, in the vicinity of a first point of the plurality of points, at least one new point based on a first tessellation factor assigned to the first point. The at least one first new point corresponds to the first point. 1. A method of tessellating surfaces in a graphics pipeline by a graphic processor , the method comprising:assigning a tessellation factor to each of a plurality of points in a patch; andgenerating, in the vicinity of a first point of the plurality of points, at least one first new point based on a first tessellation factor assigned to the first point,wherein the at least one first new point corresponds to the first point.2. The method of claim 1 , wherein the tessellation factor assigned to each of the points is an integer equal to or larger than zero claim 1 , or a decimal.3. The method of claim 1 , wherein the vicinity of the first point is the first point claim 1 , an edge including the first point claim 1 , or a face including the first point.4. The method of claim 1 , wherein the first tessellation factor is an integer larger than zero or a decimal.5. The method of claim 1 , wherein the at least one first new point is not generated when the first tessellation factor is a predetermined value.6. The method of claim 1 , wherein the at least one first new point is generated at a portion of an edge and a second new point corresponding to a second tessellation factor assigned to the second point is not generated at the edge when the first point and a second point share the edge.7. The method of claim 1 , wherein each of the plurality of points represents geometric data including at least one of a position and a normal vector.8. The method of claim 1 , wherein each of plurality of the points represents a vertex having attributes including a position claim 1 , a normal vector claim 1 , and a texture coordinate.9. The method of claim 1 , ...

IMAGE PROCESSING DEVICE AND METHOD FOR OPERATING IMAGE PROCESSING DEVICE

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data. 1. An image processing device comprising:a multimedia intellectual property (IP) block configured to process image data including a first component comprising a luma component and a second component comprising a chroma component;a memory; anda frame buffer compressor (FBC) configured to compress the image data to generate compressed data and store the compressed data in the memory,wherein the frame buffer compressor includes an encoder and a decoder,wherein the encoder includes a first mode selector configured to determine whether to perform a first mode or a second mode,wherein the encoder includes a compress manager configured to control a compression sequence of the first component and the second component of the image data.2. The image processing device of claim 1 , wherein the encoder further includes a plurality of compress modules configured to compress the image data to generate the compressed data claim 1 ,wherein a number of compress modules used for generating the compressed data in the first mode is different from a number of compress modules used for generating the compressed data in the second mode.3. The image processing device of claim 2 , wherein the plurality of compress modules include:a first compress module configured to compress the image data to generate a first compressed data;a second compress module configured to compress the first compressed data to generate a second compressed data; anda third compress module configured to compress the second compressed data to generate a ...

METHOD OF GENERATING TESSELLATION DATA AND APPARATUS FOR PERFORMING THE SAME

A method of generating tessellation data include analyzing patch data of each of a plurality of patches; generating shared data that is shared by the patches, non-shared data that are not shared by the patches, and attribute data on an attribute of control points of each of the patches from the patch data according to a result of the analyzing; and compressing the non-shared data and the attribute data. 1. A method of generating tessellation data , the method comprising:analyzing patch data of each of a plurality of patches;generating shared data that is shared by the patches, non-shared data that are not shared by the patches, and attribute data on an attribute of control points of each of the patches from the patch data according to a result of the analyzing; andcompressing the non-shared data and the attribute data.2. The method of claim 1 , further comprising maintaining a group data structure relating to the shared data claim 1 , a patch data structure relating to each of the non-shared data claim 1 , and a control point data structure relating to each of the attribute data based on the shared data claim 1 , the non-shared data claim 1 , and the attribute data.3. The method of claim 1 , wherein the shared data comprises a number of control points claim 1 , a partitioning type claim 1 , a domain face type claim 1 , output data topology claim 1 , and a tessellation factor of the patches.4. The method of claim 1 , wherein the non-shared data comprises an index of each of the control points included in each of the patches and a tessellation factor of each patch.5. The method of claim 2 , wherein the compressing comprises compressing each patch data structure and compressing each control point data structure.6. The method of claim 2 , wherein the group data structure comprises a pointer indicating each of patch data structures respectively matching the patches related with the group data structure.7. The method of claim 2 , wherein the group data structure comprises ...

GRAPHICS PROCESSING UNIT, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME

A method of operating a graphics processing unit includes determining, based on input data, whether to perform a tiling operation before or after a tessellation operation and performing the tiling operation according to the determination result. Performing the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the out-side of a convex hull defined by control points of the patch. Performing the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation. 13-. (canceled)4. A graphics processing unit (GPU) configured to perform a tiling operation and a tessellation operation , comprising:a pre-tiler configured to perform the tiling operation before the tessellation operation;a post-tiler configured to perform the tiling operation after the tessellation operation; anda control logic configured to control, based on input data, whether the pre-tiler or the post tiler performs the tiling operation,wherein the control logic controls the post-tiler to perform the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the outside of a convex hull defined by control points of the patch, and the control logic controls the post-tiler to perform the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation.5. The graphics processing unit (GPU) of claim 4 , wherein the control logic controls the pre-tiler to perform the tiling operation before the tessellation operation if the input data is the patch claim 4 , and if the geometry of the patch is at the in-side of the convex hull claim 4 , and if the geometry of the patch is not changed by the shading operation.6. The graphics processing unit (GPU) of claim 4 , further comprising a hull shader claim 4 ...

METHOD AND DEVICE FOR PROVIDING A COMPOSITION OF MULTI IMAGE LAYERS

A method for multi image layer composition includes dividing a frame buffer into tile areas, for each the area, determining image layers to be composited, for each tile area, generating a composite image layer by compositing its determined image layers, and merging the composite image layers into an overall composite image layer, wherein generating the composite image layers for at least one of the tiles comprises reading image layer information of the image layers from a top image layer to a bottom image layer, determining whether to read a lower image layer using the information of the image layers thereabove, if the lower image layer is determined not to be read, defining the image layer above the lower image layer as an effective bottom image layer, and compositing the effective bottom image layer with upper image layers, and not compositing the effective bottom image layer with an image layer thereunder. 1. A method for providing a composition of multi image layers , the method comprising:dividing a storage area of a frame buffer into tile areas;for each tile area, determining image layers to he composited;for each tile area, generating a composite image layer by compositing its determined image layers; andmerging the composite image layers of the respective tile areas into an overall composite image layer; reading image layer information of the image layers in an order from a top image layer to a bottom image layer;', 'determining whether to read a lower image layer using the information of the image layer above the lower image layer;', 'if the lower image layer is determined not to be read, defining the image layer above the lower image layer as an effective bottom image layer; and', 'compositing the effective bottom image layer with upper image layers thereabove, and not compositing the effective bottom image layer with an image layer thereunder., 'wherein generating the composite image layer for at least one of the tile areas comprises2. The method of claim ...

COMPOSITOR, SYSTEM-ON-CHIP HAVING THE SAME, AND METHOD OF DRIVING SYSTEM-ON-CHIP

A compositor selects a subset of image layers from a plurality of image layers with which to form an intermediate image. The compositor forms a resultant image from an intermediate image and one or more remaining image layers. 1. A compositor comprising:a sorter configured to sort a plurality of image layers based on update information thereof and select first and second image layers according to a result of sorting the first to third image layers; andan intermediate image generator configured to generate an intermediate image by performing composition on the selected first and second image layers.2. The compositor of claim 1 , further comprising a resultant image generator configured to generate a resultant image by performing composition on the intermediate image and the third image layer.3. The compositor of claim 1 , wherein the intermediate image generator generates the intermediate image according to an alpha blending rule.4. The compositor of claim 3 , wherein the intermediate image generator does not generate an intermediate image when the first and second image layers satisfy the alpha blending rule.5. The compositor of claim 1 , wherein the update informationinformation indicating whether any image layers are updated;update rates of the image layers; anda composition rule.6. The compositor of claim 5 , wherein the update rates comprise information regarding frame per second (FPS).7. The compositor of claim 6 , wherein FPS of each of the selected image layers is less than an FPS of the remaining image layer.8. The compositor of claim 5 , wherein the composition rule comprises a blend function.9. The compositor of claim 1 , wherein the composition comprises blending.10. A system-on-chip (SoC) comprising:a compositor configured to sort a plurality of image layers based on update information thereof, select a subset of the layers according to a result of sorting the image layers, generate an intermediate image by performing composition on the selected image ...

GRAPHIC PROCESSING UNIT, GRAPHIC PROCESSING SYSTEM INCLUDING THE SAME AND RENDERING METHOD USING THE SAME

A graphic processing unit, a graphic processing system comprising the same, and a rendering method using the same. The graphic processing unit includes a geometry processing unit configured to receive a vertex and to output a primitive and information about texture patches corresponding to the primitive using the vertex, and a rendering processing unit configured to convert the output primitive into a fragment and to perform fragment shading on the converted fragment, wherein the texture patch indexed by the texture patch information is pre-loaded to the rendering processing unit before the fragment shading is performed. 2. The graphic processing unit of claim 1 , wherein the geometry processing unit includes a vertex processing unit configured to receive the first vertex and to convert and output the received first vertex claim 1 , anda primitive assembly unit configured to assemble the first primitive from the converted and to output vertex and the texture patch information defined to correspond to the first primitive.3. The graphic processing unit of claim 2 , wherein the first primitive is a triangular primitive.4. The graphic processing unit of claim 2 , wherein the texture patch information includes texture patch descriptors indexing defined texture patch regions in a texture.5. The graphic processing unit of claim 4 , wherein the texture includes a plurality of textures claim 4 , and the texture patches are defined in the plurality of textures claim 4 , respectively.6. The graphic processing unit of claim 4 , wherein the geometry processing unit further includes a tiling unit configured to divide an image frame into a plurality of tiles and to generate a list of primitives belonging to the divided tiles claim 4 , wherein the first primitive is among the list of primitives.7. The graphic processing unit of claim 6 , wherein the list of primitives includes position information for the primitives belonging to the divided tiles claim 6 , attribute information and ...

IMAGE PROCESSING DEVICE AND METHOD FOR OPERATING IMAGE PROCESSING DEVICE

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data. 1. An image processing device comprising:a multimedia intellectual property (IP) block configured to process image data including a first component and a second component;a memory; anda frame buffer compressor (FBC) configured to compress the image data to generate compressed data and store the compressed data in the memory,wherein the frame buffer compressor includes a logic circuit configured to control a compression sequence of the first component and the second component of the image data.2. The image processing device of claim 1 , wherein after compressing the first component and the second component in accordance with the compression sequence determined by the logic circuit claim 1 , the frame buffer compressor merges the compressed data of the first component and the compressed data of the second compressed data to generate a single bit stream.3. The image processing device of claim 2 , wherein the frame buffer compressor merges the compressed data of the first component and the compressed data of the second component in an arbitrary sequence different from the compression sequence of the first component and the second component to generate the single bit stream.4. The image processing device of claim 2 , wherein the frame buffer compressor interleaves and merges the compressed data of the first component and the compressed data of the second component to generate the single bit stream.57-. (canceled)8. The image processing device of claim 1 , wherein the image data is image data conforming to a ...

Image processing device

Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

IMAGE PROCESSING DEVICE

Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data. 1. An image processing device comprising:a multimedia intellectual property (IP) configured to receive and process first image data and generate and use second image data;a frame buffer compressor configured to compress the second image data into third image data and decompress the third image data into the second image data;a memory configured to store the third image data and accessed by the multimedia IP,wherein the frame buffer compressor performs compression or decompression when the multimedia IP accesses the memory,the frame buffer compressor operates in a lossy compression mode or a lossless compression mode,the lossless compressed third image data includes a first payload and a first header, the first header indicates a compression ratio of the first payload, andthe lossy compressed third image data includes second payload only, and the second payload is compressed by a preset compression ratio.2. The image processing device of claim 1 , wherein a size of the first payload is an integer multiple of a size of a data access unit of the memory.3. The image processing device of claim 1 , wherein the first payload includes a first binary code and a first k value code claim 1 , the first binary code is the second image data entropy encoded and the first k value code represents a k value of the entropy encoded first binary code claim 1 , andwherein the second payload includes a second binary code and a second k value code, the second ...

Semiconductor device

A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Cache memory capable of adjusting burst length of write-back data in write-back operation

A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Image processing device

Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second 5 image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data. FIG. 1 10

Image processing device

Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

System on chip and mobile device including the same

A system on chip and a mobile device are provided. The mobile device comprises a processor configured to receive raw image data, process the raw image data into floating-point format image data, and output the floating-point format image data, a memory configured to store therein the floating-point format image data, and a display processing unit configured to receive the floating-point format image data stored in the memory therefrom, and perform high dynamic range (HDR) processing on the floating-point format image data.

Halbleiterbauelement

Ein Halbleiterbauelement umfasst einen Prozessor, der dazu eingerichtet ist, einen Rendervorgang eines Einzelbildes auszuführen, um Renderdaten zu erfassen, und die erfassten Renderdaten auf ein Speicherbauelement zu schreiben, und einen Anzeigecontroller, der dazu eingerichtet ist, einen Lesevorgang des Speicherbauelements, auf das die Renderdaten geschrieben sind, auszuführen, um Bilddaten zu erfassen. Das Halbleiterbauelement umfasst ferner eine Mikrosequenzierschaltung, die dazu eingerichtet ist, auf Grundlage eines Grades der Ausführung des Rendervorgangs ein Startsignal an den Anzeigecontroller zu senden. Der Anzeigecontroller ist ferner dazu eingerichtet, auf Grundlage des gesendeten Startsignals den Lesevorgang zu starten.

Image processing device and method for operating image processing device

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate 5 compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data. 10 FIG. 1

Display controller and display device including the same

A display controller includes a resource controller configured to receive layer information about each of a first layer and a second layer that are output at different times through a display panel during a unit frame. The display controller includes a data input direct memory access (DMA) configured to receive first image data corresponding to the first layer and second image data corresponding to the second layer, and a hardware resource configured to receive the first and second image data from the data input DMA, process the received first and second image data according to the layer information, and generate first layer data of the first layer and second layer data of the second layer. The resource controller is configured to control the data input DMA according to the layer information to determine an order in which the first and second image data are provided to the hardware resource.

Apparatuses and methods for processing graphics and computer readable mediums storing the methods

An apparatus according to an example embodiment of the present invention, may process data of a present span. During processing, data corresponding to an address of the start data of the next span may be prefetched from the external memory device based on information related to the presently processed data. The prefetched data may store in the cache memory.

Tessellation method for assigning a tessellation factor per point and device performing the method

点別にテッセレーションファクタを割り当てる方法と、該方法を行う装置

【課題】点別にテッセレーションファクタを割り当てる方法と、該方法を行う装置とを提供する。 【解決手段】グラフィックスプロセッサによってグラフィックスパイプラインでの複数の表面のテッセレーティング方法は、パッチで含まれた複数の点のそれぞれにテッセレーションファクタを割り当てる段階と、複数の点うちから第１点の周囲に、第１点に割り当てられた第１テッセレーションファクタに基づいて少なくとも１つの新たな第１点を生成する段階と、を含み、少なくとも１つの新たな第１点は、第１点に該当する。 【選択図】 図３

Method and apparatus for processing pixel rasterization in three-dimensional rendering processor

A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Graphic processing unit for image rendering, graphic processing system including the same and image rendering method using the same

A graphic processing unit, a graphic processing system comprising the same, and a rendering method using the same. The graphic processing unit includes a geometry processing unit configured to receive a vertex and to output a primitive and information about texture patches corresponding to the primitive using the vertex, and a rendering processing unit configured to convert the output primitive into a fragment and to perform fragment shading on the converted fragment, wherein the texture patch indexed by the texture patch information is pre-loaded to the rendering processing unit before the fragment shading is performed.

Tessellation method for assigning a tessellation factor per point and device performing the method

A tessellation method includes assigning a tessellation factor to each of a plurality of points in a patch and generating, in the vicinity of a first point of the plurality of points, at least one new point based on a first tessellation factor assigned to the first point. The at least one first new point corresponds to the first point.

Graphics processing unit, method of operating the same, and devices including the same

A method of operating a graphics processing unit includes determining, based on input data, whether to perform a tiling operation before or after a tessellation operation and performing the tiling operation according to the determination result. Performing the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the out-side of a convex hull defined by control points of the patch. Performing the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation.

Method of generating tessellation data and apparatus for performing the same

A method of generating tessellation data include analyzing patch data of each of a plurality of patches; generating shared data that is shared by the patches, non-shared data that are not shared by the patches, and attribute data on an attribute of control points of each of the patches from the patch data according to a result of the analyzing; and compressing the non-shared data and the attribute data.