METHOD FOR GENERATING ELECTRICALLY CONDUCTING AND/OR SEMICONDUCTING STRUCTURES IN TWO OR THREE DIMENSIONS, A METHOD FOR ERASING THE SAME STRUCTURES AND AN ELECTRIC FIELD GENERATOR/MODULATOR FOR USE WITH THE METHOD FOR GENERATING

A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

A METHOD FOR FORMING FERROELECTRIC THIN FILMS, THE USE OF THE METHOD AND A MEMORY WITH A FERROELECTRIC OLIGOMER MEMORY MATERIAL

In a method for forming ferroelectric thin films of vinylidene fluoride oligomer or vinylidene fluoride co-oligomer, oligomer material is evaporated in vacuum chamber and deposited as a thin film on a substrate which is cooled to a temperature in a range determined by process parameters and physical properties of the deposited VDF oligomer or co-oligomer thin film. In an application of the method of the invention for fabricating ferroelectric memory cells or ferroelectric memory devices, a ferroelectric memory material is provided in the form of a thin film of VDF oligomer or VDF co-oligomer located between electrode structures. A ferroelectric memory cell or ferroelectric memory device fabricated in this manner has the memory material in the form of a thin film of VDF oligomer or VDF co-oligomer provided on at least one of first and second electrode structures, such that the thin film is provided on at least one of the electrode structures or between first and second electrode structures ...

Digital processing system

A digital processing system P, configured as a regular tree with n+1 levels S0, S1, S2 . . . Sn and degree k, provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn-q, q=1,2, . . . n-1, in the circuit P provided nested in the Kcircuits Pn-q+1 on the overlying level Sn-q+1, each circuit Pn-q+1 on this level including k circuits Pn-q. A q=n defined zeroth level in the circuit Pn includes from K+1 to Kcircuits P0 which form kernel processors in the processing device P and on the level S0 and constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in each of the circuits p1 on the level S1. Each of the circuits P1, P2, . . . Pn, includes a logic unit E which generally is connected with circuits P0, P1, . . . Pn-1. Each of the circuits P0, P1, . . . Pn has additionally identical interfaces I, such that IP0-IP1- . . . IPn.

OPTICAL LOGIC ELEMENT AND METHODS FOR RESPECTIVELY ITS PREPARATION AND OPTICAL ADDRESSING, AS WELL AS THE USE THEREOF IN AN OPTICAL LOGIC DEVICE

In a multistable optical logic element with a light-sensitive organic material (1) which undergoes a photocycle with several physical states by irradiation with light, and wherein a physical state is assigned a logical value which can be changed by addressing the element optically, the element initially before the addressing is in a metastable state generated in advance. A multistable optical logic element has been made proximity-addressable by providing at least a colour light source (1) for optical addressing and at least one colour-sensitive optical detector (5) adjacent to the light-sensitive material. In a method for preparing of the light-sensitive material (1) a desired initial metastable state is generated in the photocycle and assigned a determined logical value for the element. In a method for optical addressing of the optical logic element steps for respectively writing and storing, reading, erasing and switching comprises generating transitions between states in the photocycle ...

A METHOD FOR GENERATING ELECTRICAL CONDUCTING OR SEMICONDUCTING STRUCTURES IN TWO OR THREE DIMENSIONS, A METHOD FOR ERASING THE SAME STRUCTURES AND AN ELECTRIC FIELD GENERATOR/MODULATOR FOR USE WITH THE METHOD FOR GENERATING

In a method for generating electrical conducting or semiconducting structures in three dimensions in a matrix which comprises two or more materials in spatially separated material structures, an electric field is applied to the separate material structure or the field-modulated spatially according to a protocol which represents a predetermined pattern of electrical conducting or semiconducting structures which are generated in the material structure in response to the field. The matrix composed by the material structures will hence comprise structures of this kind in three dimensions. In a method for global erasing an electric field is applied to the matrix until the materials in the matrix in response to the field in their entirety arrive in a non-conducting state. In an electric field generator/modulator (EFGM) which can be used for patterning and generating electrical conducting or semiconducting structures, two electrode means (E1;E2) comprise parallel strip electrodes (21;22) provided ...

ELECTRODE MEANS, COMPRISING POLYMER MATERIALS, WITH OR WITHOUT FUNCTIONAL ELEMENTS AND AN ELECTRODE DEVICE FORMED OF SAID MEANS

In an electrode means for addressing of a functional element (7) there is between a first (1) and a second (2) electrode provided a layer (4) of electrical isolating material such that the electrodes (1, 2) intersect each other without direct physical or electrical contact and form a bridge structure. Over both electrodes (1, 2) a contact layer (10) of an electrical conducting or semiconducting material is provided and contacts both electrodes (1, 2) electrically. In an electrode means with detecting, information storing and/or information indicating function a functional element (7) with passive electrical addressing of the functional element is provided. The functional element (7) is provided adjacent to or in the intersection between the electrodes (1, 2) and may constitute a sensor element or an information storing and/or an information indicating element. The contact layer (3) forms a patterned or integrated a global contact layer and contacts both electrode layers electrically, and ...

Non-destructive readout

In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits ( 3; 4 ). An active word line (AWL) is selected by a multiplexer ( 7 ), while inactive word lines (IWL) are clamped to ground during readout. A second apparatus for performing the ...

Methods in transmission of files in a data communication network

In methods in the transmission in a data communications network of arbitrarily formatted files between a sender ( 1 ) which represents an information provider and one/or more receivers ( 8 ) which represent users, a network server ( 5 ) is used in the transmission, the transmission itself taking place substantially transparent to both sender ( 1 ) and receiver ( 8 ). Before the transmission, a file which shall be transmitted is compression-coded, whereafter it is transmitted packet-divided via the server ( 5 ) to the receiver ( 8 ). In the transmission an already compression-coded file is subjected to a processing specific for one or more users and/or one or more specific application either in the server ( 5 ) or in the receiver ( 8 ) or both, without any effects on the transmission as such. Software used for the processing can be stored either at the sender ( 1 ), server ( 5 ) or receiver ( 8 ) and possibly downloaded automatically to the processing location. The particular operational ...

A matrix-addressable optoelectronic apparatus and electrode means in the same

METHOD FOR IMPROVING SECURITY IN LOGIN AND SINGLE SIGN-ON PROCEDURES

In a method for improving client's login and sign-on security in accessing services offered by service providers over shared network resources such as Internet and particularly working within the framework of the www, a password is created for the client at a first attempt to access the service provider. The client's password is generated either at an authentication authority in trust relationship with the service provider and transmitted to the client, or the client is allowed to create his or her password on the basis of random character sequences transmitted from the authentication authority. For subsequent access to the service provider the authentication authority presents a client for characters in ordered sequences or in a diagram containing in an appropriate order a single occurrence of each password character. The client performs a selection of the password for validation and transmits the validation back to the authentication authority, which verifies the password and informs ...

DATA STORAGE AND PROCESSING APPARATUS, AND METHOD FOR FABRICATING THE SAME

A data storage and processing apparatus comprising ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules on a substrate. The memory and/or processing modules are provided as a single main layer or multiple main layers on the top of the substrate. The apparatus comprises active components in the form of transistors and/or diodes for operating the apparatus. In one set of embodiments at least some and at most all the transistors and/or diodes for operating the apparatus are provided on or in the substrate. In another set of embodiments at least some and at most all of the layers on the top of the substrate comprise low-temperature compatible organic materials and/or low temperature compatible processed inorganic films, even without requiring transistors and/or diodes to be provided on or in the substrate. In a method for fabricating a data storage and processing apparatus of this kind, the memory and/or processing modules are provided on the substrate by depositing the ...

Data storage and processing apparatus, and method for fabricating the same

A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.

Method for operating a ferroelectric of electret memory device, and a device of this kind

A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

Volumetric data storage apparatus

In a volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices electrode means are provided so as to form alternating word and bit line means for the memory devices, whereby the number of the electrode means is only one more than the number of memory devices. Moreover adjoining electrode means are arranged in such a manner as to furnish a high proportion of memory cells which can be switched in two or more directions, thus yielding a much higher output when addressed and having an improved signal-to-noise ratio. Each memory device can, due to having a dense electrode arrangement, be provided with an attainable memory cell fill factor approaching unity and half the memory cells can in case be provided switchable in two or more directions, such that the fill factor of these in any case shall approach 0.5. A volumetric data storage apparatus with a very high storage density can hence be obtained, while several of the problems encountered with stacked ...

A METHOD IN THE FABRICATION OF A FERROELECTRIC MEMORY DEVICE

In a method in the fabrication of a ferroelectric memory device comprising a memory layer sandwiched between first and second electrode sets, the memory layer as well as both electrode sets are each realized in the memory device by a suitable printing process. © KIPO & WIPO 2008 ...

A METHOD FOR OPERATING A FERROELECTRIC OR ELECTRET MEMORY DEVICE, AND A DEVICE OF THIS KIND

In a method for operating a matrix- addressable ferroelectric or electret memory device a first plurality of voltage differences is applied across first and second sets of electrodes when data are read from the memory cells thereof and a second plurality of voltage differences is applied across the first and, second sets of electrodes in the case where data are refreshed or rewritten to the memory cells. In each case the first and second plurality of voltage differences correspond to sets of potential levels as predefined by a voltage pulse protocol comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is determined and used for determining at least one correction factor for the voltage pulses, whereby at least one pulse parameter thereof is adjusted in accordance with the at least one correction factor. The invention also relates to a ferroelectric or electret memory device for implementing the above method. © KIPO & WIPO 2007 ...

Read-only memory and read-only memory devices

A read-only memory is made electrically addressable over a passive conductor matrix, wherein at least a portion of the volume between intersection of two conductors (2;4) in the matrix defines a memory cell (5) in the read-only memory. Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2;4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. The read-only memory device may be realized either as planar or also volumetrically by stacking several read-only memories (ROM ...

BIMODAL OPERATION OF FERRROELECTRIC AND ELECTRET MEMORY CELLS AND DEVICES

In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states. Imprinted memory cells can be overwritten to effect a temporary and volatile storage of data in a memory device in a ferroelectric or electret memory device by assigning a first logical value to imprinted memory cells and a second logical value by transferring selected to memory cells transferred into a relaxed volatile state, whereby the stored logical values can be discriminated ...

A VOLUMETRIC DATA STORAGE APPARATUS COMPRISING A PLURALITY OF STACKED MATRIX-ADDRESSABLE MEMORY DEVICES

In a volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices (M) electrode means (E) are provided so as to form alternating word and bit line means (WL; BL) for the memory devices, whereby the number of the electrode means is only one more than the number of memory devices. Moreover adjoining electrode means (Ek, Ek+1) are arranged in such a manner as to furnish a high proportion of memory cells (6) which can be switched in two or more directions, thus yielding a much higher output when addressed and having an improved signal-to-noise ratio. Each memory device (M) can, due to having a dense electrode arrangement, be provided with an attainable memory cell fill factor approaching unity and half the memory cells can in case be provided switchable in two or more directions, such that the fill factor of these in any case shall approach 0.5. A volumetric data storage apparatus with a very high storage density can hence be obtained, while several ...

ELECTRICALLY ADDRESSABLE PASSIVE DEVICE, METHOD FOR ELECTRICAL ADDRESSING OF THE SAME AND USES OF THE DEVICE AND THE METHOD

An electrically addressable passive device for registration, storage and/or processing of data comprises a functional medium (1) in the form of a continuous or patterned structure (S) which may undergo a physical or chemical change of state. The functional medium (1) comprises individually addressable cells (2) which represent a registered or detected value or are assigned a predetermined logical value for the cell. The cell (2) is provided between the anode (3) and cathode (4) in an electrode means (E) which contacts the function medium in the cell and causes an electrical coupling therethrough, the functional medium having a non-linear impedance characteristic, whereby the cell (2) directly can be supplied with energy which effects a change in the state of the cell. In a method for electrical addressing of the passive device wherein the addressing comprises operations for i.a. detection and registration as well as further operations for writing, reading and switching of a logical value ...

MULTIDIMENSIONAL ADDRESSING ARCHITECTURE FOR ELECTRONIC DEVICES

In a means for providing addressability in an apparatus comprising one or more volume elements which together with said means form part of a matrix in the apparatus and wherein a volume element comprises one or more cells with a data storage or processing functionality, said means establishes an electrical connection to specific cells by means of electrodes in the matrix and thereby defining a cell in the volume element. Said means comprises at least three sets of plural strip-like electrodes, the strip-like electrodes of each set being provided in substantially parallel relationship to each other in a two-dimensional and planar layer forming an additional part of the matrix. A set of strip-like electrodes in one layer is oriented at an angle to the projected angle of orientation of the electrodes sets in proximal neighbouring layers onto this one layer, such that the sets of strip-like electrodes in proximal neighbouring layers exhibit a mutual non-orthogonal relationship. A selective ...

DIGITAL PROCESSING DEVICE

A digital processing device P, generally configured as a regular tree with n+1 levels S 0, S 1, S 2...S n and degree k, is provided in the form of a circuit P n on the level S n and forms the root node of the tree, an underlying level S n-q, q=1,2,...n-1, in the circuit P comprising generally k q circuits P n-q provided nested in the k q-1 circuits P n-q+1 on the overlying level S n-q+1, each circuit P n-q+1 on this level comprising k circuits P n-q. A for q=n defined zeroth level in the circuit P n comprises from k n-1 +1 to k n circuits P 0 which form kernel processors in the processing device P and on the level S 0 constitute the leaf nodes of the tree, the kernel processor P 0 being provided nested in a number from 1 to k in each of the circuits P 1 on the level S 1. Each of the circuits P 1, P 2,...P n, comprises a logic unit E which generally is connected with circuits P 0, P1,...P n-1 provided nested in the former circuits on the nearest underlying level and is additionally adapted ...

VERTICAL ELECTRICAL INTERCONNECTIONS IN A STACK

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwich self-supporting structure, wherein the layers comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind comprises steps for adding said layers successively, one layer at a time such that the layers form a staggered structure and for providing one or more layers with at least one electrical contacting pad for linking to one or more interlayer edge connectors. © KIPO & WIPO 2007 ...

A READ-ONLY MEMORY AND READ-ONLY MEMORY DEVICES

A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory ...

Matrix-addressable optoelectronic apparatus and electrode means in the same

In a matrix-addressable optoelectronic apparatus which includes a functional medium in the form of an optoelectronically active material provided in a global layer in sandwich between a first and second electrode with parallel strip-like electrodes wherein the electrodes of the second electrode are oriented at an angle to the electrodes of the first electrode, functional elements are formed in the active material where respective electrodes overlap and correspond to optically active pixels in a display device or pixels in an optical detector, depending upon the active material used. In each of the first and second electrode, the electrodes are provided in a dense parallel configuration and mutually insulated by a thin film with a thickness that is only a fraction of the width of the electrodes.

SCALABLE DATA PROCESSING APPARATUS

In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin- film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device. © KIPO & WIPO 2007 ...

METHOD FOR GENERATING ELECTRICAL CONDUCTING OR SEMICONDUCTING STRUCTURES IN TWO OR THREE DIMENSIONS, A METHOD FOR ERASING THE SAME STRUCTURES AND AN ELECTRIC FIELD GENERATOR/MODULATOR FOR USE WITH THE METHOD FOR GENERATING

A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions. A method for global erasing is also disclosed, wherein an electric field is applied to the matrix until the materials in the matrix, in their entirety, arrive in a non-conducting state in response to the field.

Method for operating a ferroelectric of electret memory device, and a device of this kind

In a method for operating a matrix-addressable ferroelectric or electret memory device a first plurality of voltage differences is applied across first and second sets of electrodes when data are read from the memory cells thereof and a second plurality of voltage differences is applied across the first and, second sets of electrodes in the case where data are refreshed or rewritten to the memory cells. In each case the first and second plurality of voltage differences correspond to sets of potential levels as predefined by a voltage pulse protocol comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is determined and used for determining at least one correction factor for the voltage pulses, whereby at least one pulse parameter thereof is adjusted in accordance with the at least one correction factor. The invention also relates to a ferroelectric or electret memory device for implementing the above method.

SCALEABLE INTEGRATED DATA PROCESSING DEVICE

A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory ...

A METHOD FOR GENERATION OF ELECTRICAL CONDUCTING OR SEMICONDUCTING STRUCTURES IN THREE DIMENSIONS AND METHODS FOR ERASURE OF THE SAME STRUCTURES

In a method for generating electrical conducting or semiconducting structures in three dimensions in a matrix which comprises two or more materials in spatially separate material structures, each material structure is irradiated with a radiation of a given intensity and/or frequency characteristic adapted to the material's response thereto, the radiation being modulated spatially according to a determined protocol which represents a predetermined pattern of electrical conducting or semiconducting structures in the relevant material structure and in response to the irradiation two-dimensional electrical conducting or semiconducting structures with a predetermined pattern are generated in the material structure such that the matrix comprised by the material structures is provided with electrical conducting or semiconducting structures in three dimensions. In a method for erasing electrical conducting or semiconducting structures of this kind each material structure is irradiated in a corresponding ...

SENSE AMPLIFIER SYSTEMS AND A MATRIX-ADDRESSABLE MEMORY DEVICE PROVIDED THEREWITH

A sense amplifier system for sensing the charge of a charge-storing means (601) comprises a first and second charge reference means (600a, 600b) connected in parallel and similar to the charge-storing means (601) and having respectively opposite polarization. The charge reference means (600a, 600b) and the charge- storing means (601) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA1, RSA2) are connected with output nodes (RBL1, RBL2) of the charge reference means (600a, 600b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo- differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means (601) and generates an output signal indicative of a polarization state of the charge-storing means. Another embodiment adapted for sensing the charges of a plurality of charge-storing means (701) and comprising ...

A READ-ONLY MEMORY AND READ-ONLY MEMORY DEVICE

A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory ...

NON-DESTRUCTIVE READOUT

In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits (3; 4). An active word line (AWL) is selected by a multiplexer (7), while inactive word lines (IWL) are clamped to ground during readout. A second apparatus for performing the method ...

A MATRIX-ADDRESSABLE OPTOELECTRONIC APPARATUS AND ELECTRODE MEANS IN THE SAME

In a matrix-addressable optoelectronic apparatus comprising a functional medium in the form of an optoelectronically active material (3) provided in a global layer in sandwich between a first and second electrode means (EMl,EM2) with parallel strip-like electrodes (1; 2) wherein the electrodes (2) of the second electrode means (EM2) are oriented at an angle to the electrodes (1) of the first electrode means (EM2), functional elements (5) are formed in the active material where respective electrodes (1, 2) overlap and correspond to optically active pixels (5) in a display device or pixels (5) in an optical detector, depending upon the active material (3) used. In each of the electrode means (EM1; EM2) the electrodes (1; 2) are provided in a dense parallel configuration and mutually insulated by a thin film (6) with a thickness that is only a fraction of the width of the electrodes. This allows for a fill factor of pixels (5) in the active material (3) approaching unity and a corresponding ...

ELECTRODES, METHOD AND APPARATUS FOR MEMORY STRUCTURE

In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (ε) in the form of parallel strip-like electrical conductors in each layer, the electrodes (ε) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g. a matrix-addressable data processing device or matrix-addressable data storage ...

A METHOD FOR TRANSMISSION OF CLASSIFIED AND PRIORITISED INFORMATION

In a method for making more effective the end user's (5) access to and exploitation of information which is offered by a global information provider 5 (4), wherein the information consists of dynamic data, quasi-static data, static data or a mixture thereof,including static databases, films, music, text etc. which for theend user's utilization in principle only needs to be transmitted once from information provider (4) to end user (5), the information which is offered on data files is classified with a unique classification key for each data file and priority protocols generated for transmission of data files on basis of a priority matrix which comprises elements formed by criteria for a transmission, said elements stating combinations of these criteria. Each classified data file is assigned to at least one priority protocol which is selected among generated priority protocols on the basis of the classification key of the data file, the assigned priority protocol stating the conditions ...

A FERROELECTRIC DATA PROCESSING DEVICE

In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent to electrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be possible to switch between the polarization states of the logic element, which hence may be used for implementing ...

Read-only memory and read-only memory device

A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory ...

Scalable data processing apparatus

In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device.

A volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices

Bimodal operation of ferroelectric and electret memory cells and devices

In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states. Imprinted memory cells can be overwritten to effect a temporary and volatile storage of data in a memory device in a ferroelectric or electret memory device by assigning a first logical value to imprinted memory cells and a second logical value by transferring selected to memory cells transferred into a relaxed volatile state, whereby the stored logical values can be discriminated ...

Data Storage Device

In a non-volatile electric memory system a card-like memory unit ( 10 ) and a read/write unit ( 11 ) are provided as physically separate units. The memory unit ( 10 ) is based on a memory material ( 4 ) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit ( 10 ) comprises contact means ( 9 ) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit ( 10 ) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means ( 9 ). Establishing a physical contact between the memory unit ( 10 ) and the read/write unit ( 11 ) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected. The memory material ( 4 ) of the memory unit ( 10 ) can be a ferroelectric or electret material that can be polarized into two discernible polarization states, or it can be ...

Card-like memory unit with separate read/write unit

In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Operating temperature optimization in a ferroelectric or electret memory

In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Method in the fabrication of a ferroelectric memory device

In a method in the fabrication of a ferroelectric memory device comprising a memory layer sandwiched between first and second electrode sets, the memory layer as well as both electrode sets are each realized in the memory device by a suitable printing process.

Data storage device

In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit (10) comprises contact means (9) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit (10) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (9). Establishing a physical contact between the memory unit (10) and the read/write unit (11) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected. The memory material (4) of the memory unit (10) can be a ferroelectric or electret material that can be polarized into two discernible polarization states, or it can be a material with a resistive ...

Method for generation of electrical conducting or semiconducting structures in three dimensions and methods for erasure of the structures

Electrically conducting and/or semiconducting structures are generated in three dimensions in a composite matrix including two or more materials provided in spatially separate and homogenous material structures. Materials undergo specific physical and/or chemical changes causing transition from electrically non-conducing to electrically conducting and semiconducting state. The material structures are radiated with a given intensity or frequency characteristic adapted to the specific response of the material. Spatially modulating the radiation according to a protocol representing a pattern of electrically conducing and semiconducting structures in the relevant material structures generates the two dimensional electrically conducting and semiconducting structures in the material structure. The composite matrix is provided with electrically conducting and semiconducting structures in three dimensions. Spectral ranges of the radiation include gamma, x-ray, ultraviolet, visible light, inferred ...

Method for improving security in login and single sign-on procedures

In a method for improving client's login and sign-on security in accessing services offered by service providers over shared network resources such as Internet and particularly working within the framework of the www, a password is created for the client at a first attempt to access the service provider. The client's password is generated either at an authentication authority in trust relationship with the service provider and transmitted to the client, or the client is allowed to create his or her password on the basis of random character sequences transmitted from the authentication authority. For subsequent access to the service provider the authentication authority presents a client for characters in ordered sequences or in a diagram containing in an appropriate order a single occurrence of each password character. The client performs a selection of the password for validation and transmits the validation back to the authentication authority, which verifies the password and informs ...

Electrode means, a method for its manufacture, an apparatus comprising the electrode means as well as use of the latter

In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (epsilon) in the form of parallel strip-like electrical conductors in each layer, the electrodes (epsilon) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g. a matrix-addressable data processing device or matrix-addressable data ...

Scaleable integrated data processing device

A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scaleable parallel architectures integrated with optimal interconnectivity in three dimensions.

Data Storage Device

In a non-volatile electric memory system a memory unit ( 4 ) and a read/write unit ( 11 ) are provided as physically separate units. The memory unit ( 10 ) is based on a memory material ( 4 ) that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrode means and/or contact means are either provided in the memory unit or in the read/write unit and contact means are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Contact means in the read/write unit are provided connectable to driving, sensing and control means located in the read/write unit or in an external device connected with the latter. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected ...

Operating temperature optimization in a ferroelectric or electret memory

In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Electrodes, method and apparatus for memory structure

Method for operating a ferroelectric of electret memory device, and a device of this kind

Sense amplifier systems and a matrix-addressable memory device provided therewith

A sense amplifier system for sensing the charge of a charge-storing means ( 601 ) comprises first and second charge reference means ( 600 a ,600 b) connected in parallel and similar to the charge-storing means itself and having respectively opposite polarizations. The charge reference means ( 600 a ,600 b) and the charge storing means ( 600 ) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA₁, RSA₂) are connected with output nodes (RBL₁, RBL₂) of the charge reference means ( 600 a ,600 b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means ( 601 ) and generates an output signal indicative of a polarization state of the charge-storing means. Another sense amplifier system is generically similar, ...

A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating

In a method for generating electrical conducting or semiconducting structures in three dimensions in a matrix which comprises two or more materials in spatially separated material structures, an electric field is applied to the separate material structure or the field-modulated spatially according to a protocol which represents a predetermined pattern of electrical conducting or semiconducting structures which are generated in the material structure in response to the field. The matrix composed by the material structures will hence comprise structures of this kind in three dimensions. In a method for global erasing an electric field is applied to the matrix until the materials in the matrix in response to the field in their entirety arrive in a non-conducting state. In an electric field generator/modulator (EFGM) which can be used for patterning and generating electrical conducting or semiconducting structures, two electrode means (E1;E2) comprise parallel strip electrodes (21;22) provided mutually spaced apart in parallel planes such that the electrodes (21, 22) form a matrix-like arrangement. The electrode means (E1;E2) are over cross-connection devices (24, 25) connected with a power supply (23). EFGM (20) is adapted for receiving a thin-film material between the electrode devices (E1, E2) in order to generate said structures.

METHOD FOR PRODUCING TWO OR THREE-DIMENSIONAL ELECTRICALLY CONDUCTIVE OR SEMICONDUCTIVE STRUCTURES, A CLEARING METHOD THEREOF, AND A GENERATOR / MODULATOR OF AN ELECTRICAL FIELD FOR USE IN THE MANUFACTURE METHOD

Electrically addressable passive device, method for electrical addressing of the same and uses of the device and the method

An electrically addressable passive device for recording, storage and/or processing of data comprises a functional medium in the form of a continuous or patterned structure which may undergo a physical or chemical change of state. The functional medium is realized as a homogenous or stratified structure comprising a least one substantially organic material. The functional medium comprises individually addressable cells which represent a registered or detected value or are assigned a predetermined logical value for the cell. The cell is provided between the anode and cathode in an electrode means which contacts the function medium in the cell and causes an electrical coupling therethrough, whereby the cell directly can be supplied with energy which effects a change in the state of the cell, the functional medium having an overall non-linear impedance characteristic, and said at least one substantially organic material of the functional medium being a polymer material. In the method the addressing comprises operations for i.a. detection and recording as well as further operations for writing, reading and switching of a logical value assigned to the cell, electric energy is applied directly to the functional medium of the cell in order to change its state and hence effect an addressing operation. It can be used in optical detector means, volumetric data storage devices or data processing devices.

A non-volatile electrical memory system

Data storage and processing apparatus, and method for fabricating the same

Scalable data processing apparatus

In a scalable data processing appa-ratus, particularly a data storage appara-tus, one or more thin-film devices which form a substantially planar layer com-prise a plurality of sublayers of thin film. Two or more thin-film devices are pro-vided as an integrated stack of the sub-stantially planar layers which form the thin-film devices, such that the appara-tus thereby forms a stacked configura-tion. Each thin-film device comprises one or more memory areas which form matrix addressable memories and addi-tionally circuit areas which form elec-tronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said in-terfaces being realized with communica-tion and signal lines as well as supporting circuitry for processing extending verti-cally through dedicated interface areas in the thin-film device.

Electrically addressable device, method for electrical addressing of the same and uses of the device and the method

A method for forming ferroelectric thin films, the use of the method and a memory with a ferroelectric oligomer memory material

In a method for forming ferroelectric thin films of vinylidene fluoride oligomer or vinylidene fluoride co-oligomer, oligomer material is evaporated in vacuum chamber and deposited as a thin film on a substrate which is cooled to a temperature in a range determined by process parameters and physical properties of the deposited VDF oligomer or co-oligomer thin film. In an application of the method of the invention for fabricating ferroelectric memory cells or ferroelectric memory devices, a ferroelectric memory material is provided in the form of a thin film of VDF oligomer or VDF co-oligomer located between electrode structures. A ferroelectric memory cell or ferroelectric memory device fabricated in this manner has the memory material in the form of a thin film of VDF oligomer or VDF co-oligomer provided on at least one of first and second electrode structures, such that the thin film is provided on at least one of the electrode structures or between first and second electrode structures.

Electrodes, method and apparatus for memory structure

In an electrode means comprising a first and a second thin-film electrode layers L1, L2 with electrodes ɛ in the form of parallel strip-like electrical conductors in each layer, the electrodes ɛ are provided only separated by a thin film 6 of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall 6a therebetween. The electrode layers L1, L2 are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means EM, the electrode layers L1, L2 of each are mutually oriented with their respective electrodes 12 crossing at an angle, preferably orthogonally and with a functional medium 3 provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g. a matrix-addressable data processing device or matrix-addressable data storage device comprising individually addressable functional elements 5 in the form of e.g. respectively logic cells or memory cells, the fill factor thereof in the global functional medium 3 approaching unity and a maximum number of the cells in the apparatus of approximately A/f?2¿, wherein A is the area of the global functional medium 3 sandwiched between the electrode layers L1, L2, and f is a process-constrained minimum feature.

Multidimensional addressing architecture for electronic devices

In a means for providing addressability in an apparatus comprising one or more volume elements which together with said means form part of a matrix in the apparatus and wherein a volume element comprises one or more cells with a data storage or processing functionality, said means establishes an electrical connection to specific cells by means of electrodes in the matrix and thereby defining a cell in the volume element. Said means comprises at least three sets of plural strip-like electrodes, the strip-like electrodes of each set being provided in substantially parallel relationship to each other in a two-dimensional and planar layer forming an additional part of the matrix. A set of strip-like electrodes in one layer is oriented at an angle to the projected angle of orientation of the electrodes sets in proximal neighbouring layers onto this one layer, such that the sets of strip-like electrodes in proximal neighbouring layers exhibit a mutual non-orthogonal relationship. A selective addressing of a cell takes place applying current or voltage to selected electrodes in each electrode set. An apparatus comprising a means of this kind is realized by a stack of two or more matrices located on a substrate, thus implementing a volumetric device for data storage or data processing.

A method for transmission of classified and prioritised information

A data storage device

In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Optical logic element and methods for its preparation and optical addressing, respectively, and use thereof in an optical logic device

A method for generation of electrial conducting orsemiconducting structures in three dimensions and methods for erasure of the same structures.

A matrix-addressable optoelectronic apparatus and electrode means in the same

In a matrix-addressable optoelectronic apparatus comprising a functional medium in the form of an optoelectronically active material (3) provided in a global layer in sandwich between a first and second electrode means (EMl,EM2) with parallel strip-like electrodes (1; 2) wherein the electrodes (2) of the second electrode means (EM2) are oriented at an angle to the electrodes (1) of the first electrode means (EM2), functional elements (5) are formed in the active material where respective electrodes (1, 2) overlap and correspond to optically active pixels (5) in a display device or pixels (5) in an optical detector, depending upon the active material (3) used. In each of the electrode means (EM1; EM2) the electrodes (1; 2) are provided in a dense parallel configuration and mutually insulated by a thin film (6) with a thickness that is only a fraction of the width of the electrodes. This allows for a fill factor of pixels (5) in the active material (3) approaching unity and a corresponding high degree of pixellation, thus providing either a display with a high surface brightness and high resolution or an optical detector with high sensitivity and high resolution.

Electrode means, with or without functional elements and an electrode device formed of said means

In an electrode means for addressing of a functional element (7) a layer (4) of electrical isolating material is provided between first and second electrodes (1;2) intersecting without direct physical or electrical contact and forming a bridge structure. Over both electrodes (1,2) an electrical conducting or semiconducting contact layer (10) of organic material is provided and contacts both electrodes (1,2) electrically. In an electrode means with detecting, information storing and/or information indicating function an electrically addressable functional element (7) is provided adjacent to or in the intersection between the electrodes (1,2). In an electrode device (13) comprising two or more electrode means (26) of this kind, the electrodes (1, 2) form patterned layers of row and column electrodes in a 2-dimensional matrix, wherein the contact layer (3) forms a patterned or integrated global layer and functional elements (7) which each registers with an electrode intersection in the matrix, are provided in one or more patterned or non-patterned layers. Use in an optical or electronic camera, in a chemical camera, in an electrically addressable memory device or electrically addressable data processing device, and in an electrically addressable display device.

A matrix-addressable optoelectronic apparatus and electrode means in the same

In a matrix-addressable optoelectronic apparatus comprising a functional medium in the form of an optoelectronically active material (3) provided in a global layer in sandwich between a first and second electrode means (EMl,EM2) with parallel strip-like electrodes (1; 2) wherein the electrodes (2) of the second electrode means (EM2) are oriented at an angle to the electrodes (1) of the first electrode means (EM2), functional elements (5) are formed in the active material where respective electrodes (1, 2) overlap and correspond to optically active pixels (5) in a display device or pixels (5) in an optical detector, depending upon the active material (3) used. In each of the electrode means (EM1; EM2) the electrodes (1; 2) are provided in a dense parallel configuration and mutually insulated by a thin film (6) with a thickness that is only a fraction of the width of the electrodes. This allows for a fill factor of pixels (5) in the active material (3) approaching unity and a corresponding high degree of pixellation, thus providing either a display with a high surface brightness and high resolution or an optical detector with high sensitivity and high resolution.

Electrodes, method and apparatus for memory structure

In an electrode means comprising a first and a second thin-film electrode layers (L1,L2) with electrodes (.epsilon.) in the form of parallel stripe-like electrical conductors in each layer, the electrodes (.epsilon.) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1,L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1,L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g. a matrix-addressable data processing device or matrix-addressable data storage device comprising individually addressable functional elements (5) in the form of e.g. respectively logic cells or memory cells, the fill factor thereof in the global functional medium (3) approaching unity and a maximum number of the cells in the apparatus of approximately A/f2, wherein A is the area of the global functional medium (3) sandwiched between the electrode layers (L1,L2), and f is a process-constrained minimum feature.

Scalable data processing apparatus

In a scalable data processing appa-ratus, particularly a data storage appara-tus, one or more thin-film devices which form a substantially planar layer com-prise a plurality of sublayers of thin film. Two or more thin-film devices are pro-vided as an integrated stack of the sub-stantially planar layers which form the thin-film devices, such that the appara-tus thereby forms a stacked configura-tion. Each thin-film device comprises one or more memory areas which form matrix addressable memories and addi-tionally circuit areas which form elec-tronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said in-terfaces being realized with communica-tion and signal lines as well as supporting circuitry for processing extending verti-cally through dedicated interface areas in the thin-film device.

A ferroelectric data processing device

In a ferroelectric data-processing device for processing and/or storage of data with active or passive electrical addressing a data-carrying medium are used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched therebetween and is provided as a continuous or patterned layer above and adjacent to electrode structures in the form of a matrix, the electrode structures being mutually isolated by an electrical isolating material (6). A logic element (4) is formed in the thin film (1) along the side edges of an y electrode (3) and down to the x electrode (2) at the overlap. The logic element (4) is addressed by applying to the electrodes (2,3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be; possible to switch between the polarization states of the logic element, which hence may be used for implementing a bistable switch or a memory cell. The data-processing device according to the invention may be stacked layerwise if the separate layers are separated by an electrical insulating layer and hence be used for implementing volumetric data-processing devices.

Optical logic element and methods for its preparation and optical addressing, respectively, and its use in an optical logic device

Methods in transmission and searching of video information

Multidimensional addressing architecture for electronic devices

In a means for providing addressability in an apparatus comprising one or more volume elements which together with said means form part of a matrix in the apparatus and wherein a volume element comprises one or more cells with a data storage or processing functionality, said means establishes an electrical connection to specific cells by means of electrodes in the matrix and thereby defining a cell in the volume element. Said means comprises at least three sets of plural strip-like electrodes, the strip-like electrodes of each set being provided in substantially parallel relationship to each other in a two-dimensional planar layer forming an additional part of the matrix. A set of strip-like electrodes in a layer is oriented at an angle to the projected angle of orientation of the electrode sets in proximal neighbouring layers onto this layer, such that the sets of strip-like electrodes in proximal neighbouring layers exhibit a mutual non-orthogonal relationship. A selective addressing of a cell takes place applying current or voltage to selected electrodes in each electrode set. An apparatus comprising a means of this kind is realized by a stack of two or more matrices located on a substrate, thus implementing a volumetric device for data storage or data processing.

FIXED MEMORY AND FIXED MEMORY ARRANGEMENTS

Non-destructive reading

A ferroelectric data processing device

In a ferroelectric data-processing device for processing and/or storage of data with active or passive electrical addressing a data-carrying medium are used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched therebetween and is provided as a continuous or patterned layer above and adjacent to electrode structures in the form of a matrix, the electrode structures being mutually isolated by an electrical isolating material (6). A logic element (4) is formed in the thin film (1) along the side edges of an y electrode (3) and down to the x electrode (2) at the overlap. The logic element (4) is addressed by applying to the electrodes (2,3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be; possible to switch between the polarization states of the logic element, which hence may be used for implementing a bistable switch or a memory cell. The data-processing device according to the invention may be stacked layerwise if the separate layers are separated by an electrical insulating layer and hence be used for implementing volumetric data-processing devices.

A method for generation of electrical conducting or semiconducting structures in three dimensions and methods for erasure of the same structures

Optoelectronic camera and method for image formatting in the same

An optoelectronic camera comprises an objective system formed by a number of optical active structures (L), particularly refractive structures in the form of microlenses or lenslets provided in an array. A detector device (D) is assigned to the lens array and comprises detectors (Dn) formed by sensor elements (E) which define pixels in the optical image. Each detector (Dn) defines a sample of the optical image and optimally all samples are used to generate a digital image. The optoelectronic camera may be realized as a colour image camera, particularly for recording images in an RGB system. In a method for digital electronic formatting of an image recorded with the optoelectronic camera, zoom and pan functions are implemented in the camera.

Reading memory and reading memory devices

Optical logical element and method for its preparation and optical addressing respectively

Matrix addressable optoelectronic apparatus and electrode assembly in the same

Optical logic element and optical logic device

An optical logic element (OLE), particularly a multistate, multistable optical logic element, and even more particularly a proximity-addressable optical logic element, comprises an optical memory substance (1), which can transfer from one physical or chemical state to a second physical or chemical state. The memory substance (1) is provided in or on a layer-like structure, and an activator (2) which generates a magnetic, electromagnetic or electrical field or supplies energy to the memory substance (1) and an optical detector for detection of the memory substance's optical response conditional on the memory substance's physical or chemical state, is provided in or adjacent to the layer-like structure, the optical logic element (OLE) thus forming an integrated component. An optical logic device (OLD) comprises at least one structure (S) composed of the optical logic elements, where the optical memory substance (1), the activator (2) and the detector (3) in each optical logic element (OLE) in the structure (S) merges into and is connected to the memory substance, the activator and the detector in the surrounding logic elements (OLEs) in the structure (S). Each logic element (OLE) in the structure (S) has an unambiguous assignment between the memory substance (1) and the activator (2) and an assignment between the memory substance (1) and the optical detector (3) for unambiguous detection and can be accessed and addressed individually. The structures (S) in the optical logic device (OLD) may be entirely or partly configured as optical memories, logic and arithmetic circuits and registers respectively or in a combination of these, as an optical data processor.

A ferroelectric data processing device

In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent to electrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be possible to switch between the polarization states of the logic element, which hence may be used for implementing a bistable switch or a memory cell. The data processing device according to the invention may be stacked layerwise if the separate layers are separated by an electrical isolating layer and hence be used for implementing volumetric data processing devices.

Reading memory and reading memory devices

Procedure for transferring information

In a method for making more effective the end user's (5) access to and exploitation of information which is offered by a global information provider 5(4), wherein the information consists of dynamic data, quasi-static data, static data or a mixture thereof, including static databases, films, music, text etc. which for the end user's utilization in principle only needs to be transmitted once from information provider (4) to end user (5), the information which is offered on data files is classified with a unique classification key for each data file and priority protocols generated for transmission of data files on basis of a priority matrix which comprises elements formed by criteria for a transmission, said elements stating combinations of these criteria. Each classified data file is assigned to at least one priority protocol which is selected among generated priority protocols on the basis of the classification key of the data file, the assigned priority protocol stating the conditions for the transmission of the data file. The communication channels for a transmission is selected on the basis of the assigned priority protocol. Information is accessed in one of the following modes: (I) information is transmitted directly to the end user according to a predetermined or modified priority protocol or according to a priority protocol assigned for the occasion; (II) information is transmitted default and automatically directly to one of more end users according to a predetermined priority protocol; (III) information is transmitted according to an assigned priority protocol and stored in physical proximity to the end user.

Data storage and processing apparatus, and method for fabricating the same

A data storage and processing apparatus comprising ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules on a substrate. The memory and/or processing modules are provided as a single main layer or multiple main layers on the top of the substrate. The apparatus comprises active components in the form of transistors and/or diodes for operating the apparatus. In one set of embodiments at least some and at most all the transistors and/or diodes for operating the apparatus are provided on or in the substrate. In another set of embodiments at least some and at most all of the layers on the top of the substrate comprise low-temperature compatible organic materials and/or low temperature compatible processed inorganic films, even without requiring transistors and/or diodes to be provided on or in the substrate. In a method for fabricating a data storage and processing apparatus of this kind, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps. The deposition and processing of the layers take place under thermal conditions that avoid subjecting an already deposited and processed underlying layer or layers to static or dynamic temperatures exceeding given stability limits, particularly in regard of organic materials.

A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating

In a method for generating electrical conducting or semiconducting structures in three dimensions in a matrix which comprises two or more materials in spatially separated material structures, an electric field is applied to the separate material structure or the field-modulated spatially according to a protocol which represents a predetermined pattern of electrical conducting or semiconducting structures which are generated in the material structure in response to the field. The matrix composed by the material structures will hence comprise structures of this kind in three dimensions. In a method for global erasing an electric field is applied to the matrix until the materials in the matrix in response to the field in their entirety arrive in a non-conducting state. In an electric field generator/modulator (EFGM) which can be used for patterning and generating electrical conducting or semiconducting structures, two electrode means (E1;E2) comprise parallel strip electrodes (21;22) provided mutually spaced apart in parallel planes such that the electrodes (21, 22) form a matrix-like arrangement. The electrode means (E1;E2) are over cross-connection devices (24, 25) connected with a power supply (23). EFGM (20) is adapted for receiving a thin-film material between the electrode devices (E1, E2) in order to generate said structures.

ELECTRODES, METHOD AND APPARATUS FOR MEMORY STRUCTURE

In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (ϵ) in the form of parallel strip-like electrical conductors in each layer, the electrodes (ϵ) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g. a matrix-addressable data processing device or matrix-addressable data storage device comprising individually addressable functional elements (5) in the form of e.g. respectively logic cells or memory cells, the fill factor thereof in the global functional medium (3) approaching unity and a maximum number of the cells in the apparatus of approximately A/f2, wherein A is the area of the global functional medium (3) sandwiched between the electrode layers (L1, L2), and f is a process-constrained minimum feature.

Vertical electrical interconnections in a stack

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwich self-supporting structure, wherein the layers comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind comprises steps for adding said layers successively, one layer at a time such that the layers form a staggered structure and for providing one or more layers with at least one electrical contacting pad for linking to one or more interlayer edge connectors.

A read-only memory and read-only memory devices

A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory device. The device may be realized either planar or also volumetrically by stacking several read-only memories (ROM) in horizontal layers (15) and connecting them with the substrate (1) via addressing buses.

Sense amplifier systems and a matrix-addressable memory device provided therewith

A sense amplifier system for sensing the charge of a charge-~storing means (601) comprises a first and second charge reference means (600a, 600b) connected in parallel and similar to the charge-storing means (601) and having respectively opposite polarization. The charge reference means (600a, 600b) and the charge-storing means (601) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA1, RSA2) are connected with output nodes (RBL1, RBL2) of the charge reference means (600a, 600b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means (601) and generates an output signal indicative of a polarization state of the charge-storing means. Another embodiment adapted for sensing the charges of a plurality of charge-storing means (701) and comprising at least two pairs of charge reference means is also described. A non-volatile matrix-addressable memory system comprising an electrical polarizable dielectric memory material exhibiting hysterisis and a sense amplifier system as described is also claimed.

Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device

In a multistable optical logic element with a light-sensitive organic material (1) which undergoes a photocycle with several physical states by irradiation with light, and wherein a physical state is assigned a logical value which can be changed by addressing the element optically, the element initially before the addressing is in a metastable state generated in advance. A multistable optical logic element has been made proximity-addressable by providing at least a colour light source (1) for optical addressing and at least one colour-sensitive optical detector (5) adjacent to the light-sensitive material. In a method for preparing of the light-sensitive material (1) a desired initial metastable state is generated in the photocycle and assigned a determined logical value for the element. In a method for optical addressing of the optical logic element steps for respectively writing and storing, reading, erasing and switching comprises generating transitions between states in the photocycle and detection of the states. Use in an optical logical device for storing and processing of data.

A method for improving security in login and single sign-on procedures

In a method for improving client's login and sign-on security in accessing services offered by service providers over shared network resources such as Internet and particularly working within the framework of the www, a password is created for the client at a first attempt to access the service provider. The client's password is generated either at an authentication authority in trust relationship with the service provider and transmitted to the client, or the client is allowed to create his or her password on the basis of random character sequences transmitted from the authentication authority. For subsequent access to the service provider the authentication authority presents a client for characters in ordered sequences or in a diagram containing in an appropriate order a single occurrence of each password character. The client performs a selection of the password for validation and transmits the validation back to the authentication authority, which verifies the password and informs the service provider of the verification. In a most preferred embodiment the password characters are never transmitted between the authentication authority and the client in a validation and verification procedure, and the former is wholly disconnected from either the client's credentials or any transactions subsequently to be undertaken between the service provider and the client.

Scaleable integrated data processing device

Fremgangsmate i fabrikasjonen av en ferroelektrisk minneinnretning

Elektrisk adresserbar, passiv innretning, fremgangsmåte til elektrisk adressering av samme og anvendelse av innretning ogfremgangsmåte

Skalerbart databehandlingsapparat

Digitale verarbeitungsvorrichtung

Matrixadressierbare optoelektronische vorrichtung und elektrodenmittel darin

Ferroelektrische datenverarbeitungsanordnung

Zerstörungsfreies auslesen

Optisches logikelement und verfahren zu dessen anfertigung beziehungsweise zur optischen adressierung sowie dessen verwendung in einer optischen logikvorrichtung

Datalagrings og prosesseringsapparat og fremgangsmÕte til fremstilling av samme

Elektroden, verfahren und vorrichtung für eine speicherstruktur

Optoelektronische kamera und verfahren zur bildformatierung

Festwertspeicher und festwertspeicheranordnungen

Festwertspeicher und festwertspeicheranordnung

Elektrisch addressierbare passive anordnung, dazugehöriges elektrisches adressierungsverfahren sowie verwendung der anordnung und des verfahrens

Datalagring og behandling av data, samt fremgangsmate til fremstilling av samme

強誘電体メモリ・デバイスの作製方法

【課題】タグ、ラベル又はパッケージの印刷プロセス、あるいは、パッケージング・プロセス自体に容易に採用できる再書き込み可能な不揮発性メモリ・デバイスを作製する簡易で安価な方法を提供する。 【解決手段】ａ）第１の印刷手段を用いて絶縁性基板上に第１の印刷インクで第１の電極層を印刷し、それによって第１の組の電極を形成するためと、ｂ）第２の印刷手段を用いて第１の電極層上に第２の印刷インクでメモリ材料のパターニングされた、あるいは、パターニングされていない層を印刷し、ｃ）第３の印刷手段を用いてメモリ層上に第３の印刷インクで第２の電極層を印刷し、それによって第２の組の電極を形成するための連続した工程を含み、それら単独又は組合せのいずれかで実行される作製方法を提供する。 【選択図】図１ａ

Datalagring og behandling av data, samt fremgangsmåte til fremstilling av samme

Volumetrische datenspeichervorrichtung mit mehreren gestapelten matrixadressierbaren speichereinrichtungen

Fremgangsmåter og innretning til validering av en håndskrevet personlig signatur

Skalerbart databehandlingsapparat

Skalerbar datalagringsinnretning

Elektrisk adresserbar, passiv innretning, fremgangsmÕte til elektrisk adressering av samme og anvendelse av innretning og fremgangsmÕte

Elektrisk adresserbar, passiv innretning, fremgangsmÕte til elektrisk adressering av samme og anvendelse av innretning og fremgangsmÕte

Methods in transmission of files in a data communication network

In a method in the transmission in a data communications network of arbitrarily formatted files between a sender which represents an information provider and one or more receivers which represent users, a network server is used in the transmission, the transmission itself taking place substantially transparent to both sender and receiver. Before the transmission a file which shall be transmitted is compression-coded, whereafter it is transmitted packet-divided via the server to the receiver. In the transmission an already compression-coded file is subjected to a processing specific for one or more users and/or one or more specific applications, either in the server or in the receiver or both, without any effects on the transmission as such. Software used for the processing can be stored either at the sender, server or receiver and possibly downloaded automatically to the processing location. The particular operational and decision steps in the method are preferably realized in consecutive and approximately simultaneous and/or interfoliated steps. Use for transmission and specific processing of large files comprising one or more different data types, including image information on the Internet, particularly for use in the media industry.

Sense amplifier systems and a matrix-addressable memory device provided therewith

A sense amplifier system for sensing the charge of a charge-­storing means (601) comprises a first and second charge reference means (600a, 600b) connected in parallel and similar to the charge-storing means (601) and having respectively opposite polarization. The charge reference means (600a, 600b) and the charge-storing means (601) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA1, RSA2) are connected with output nodes (RBL1, RBL2) of the charge reference means (600a, 600b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means (601) and generates an output signal indicative of a polarization state of the charge-storing means. Another embodiment adapted for sensing the charges of a plurality of charge-storing means (701) and comprising at least two pairs of charge reference means is also described. A non-volatile matrix-addressable memory system comprising an electrical polarizable dielectric memory material exhibiting hysterisis and a sense amplifier system as described is also claimed.

Sense amplifier systems and a matrix-addressable memory device provided therewith

A charge sensing device with a sense amplifier system implemented in a non-volatile matrix-addressable memory device comprising an electrical polarizable dielectric memory material exhibiting hysteresis, particularly a ferroelectric or electret material. The memory cells of the memory device can be selectively addressed for a write/read operation and the sense amplifier system is used for readout of polarization states of the memory cells.

Leseverstärkersysteme und damit ausgestattete matrixadressierbare speichereinrichtung

Sense amplifier systems and a matrix-addressable memory device provided therewith

A charge sensing device with a sense amplifier system implemented in a non-volatile matrix-addressable memory device comprising an electrical polarizable dielectric memory material exhibiting hysteresis, particularly a ferroelectric or electret material. The memory cells of the memory device can be selectively addressed for a write/read operation and the sense amplifier system is used for readout of polarization states of the memory cells.

Procedimientos y dispositivos para validar una firma personal.

PARA EL REGISTRO, ANALISIS Y VALIDACION DE UNA FIRMA MANUSCRITA PERSONAL, LA FIRMA ES REGISTRADA MEDIANTE UN DISPOSITIVO ESCRITOR DOTADO DE UN DETECTOR DE MOVIMIENTO DE EJE MULTIPLE Y SE GENERA UN FLUJO DE DATOS PARA EL MOVIMIENTO DEL DISPOSITIVO ESCRITOR CON DOS O SEIS GRADOS DE LIBERTAD, ASI COMO UN FONDO RELOJ. EL FLUJO DE DATOS ES TRANSMITIDO A UN DISPOSITIVO PROCESADOR DE DATOS PARA SU ANALISIS Y TRANSFORMACION EN FORMATO COMPILADO PREDETERMINADO QUE SON ALMACENADOS EN FICHEROS EN UNA BASE DE DATOS. UNA FIRMA PERSONAL RECIEN REGISTRADA SE VALIDA COMPARANDOLA CON UNA FIRMA PERSONAL CORRESPONDIENTE Y AUTENTICADA QUE ESTA ALMACENADA EN LA BASE DE DATOS. EN UN PROCEDIMIENTO PARA LA VALIDACION DE UNA FIRMA PERSONAL RECIEN REGISTRADA EL FLUJO DE DATOS SE TRANSFORMA EN LA MISMA FORMA EN LOS CORRESPONDIENTES FORMATOS DE DATOS COMPILADOS QUE ESTAN ALMACENADOS EN LOS FICHEROS DE DATOS. SU CONTENIDO ES COMPARADO CON EL CONTENIDO DE LOS FICHEROS DE LA BASE DE DATOS Y LA FIRMA ES VALIDADA COMO AUTENTICA SI EL RESULTADO DE LA COMPARACION CUMPLE CRITERIOS PREDETERMINADOS. SE DESCRIBE UN DISPOSITIVO DE ESCRITURA ELECTRONICA (1) PARA UTILIZARLO EN EL REGISTRO DE FIRMAS COMO UNA PLUMILLA ELECTRONICA CON UNA PUNTA DE ESCRIBIR (2) Y UN DETECTOR (3) PARA LA DETECCION DEL MOVIMIENTO DE ESCRITURA CON SEIS GRADOS DE LIBERTAD.

Verfahren und vorrichtung zum bestätigen einer persönlichen unterschrift

FremgangsmÕter og innretning til validering av en hÕndskrevet personlig signatur

FremgangsmÕter og innretning til validering av en hÕndskrevet personlig signatur

Fremgangsmåter ved overföring av filer i et datakommunikasjonsnett

Fremgangsmåter ved overføring av filer i et datakommunikasjonsnett

FremgangsmÕter ved overføring av filer i et datakommunikasjonsnett