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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 536. Отображено 101.
22-12-2016 дата публикации

PHOTO PATTERN METHOD TO INCREASE VIA ETCHING RATE

Номер: US20160372401A1
Автор: Zheng-Chang MU, Cheng-Wei LIN, Kuang-Wen LIU, MU ZHENG-CHANG, LIN CHENG-WEI, LIU KUANG-WEN, MU Zheng-Chang, LIN Cheng-Wei, LIU Kuang-Wen
Принадлежит:

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

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Номер записи: 1
02-03-2017 дата публикации

PHOTO PATTERN METHOD TO INCREASE VIA ETCHING RATE

Номер: US20170062270A1
Автор: Zheng-Chang MU, Cheng-Wei LIN, Kuang-Wen LIU, MU ZHENG-CHANG, LIN CHENG-WEI, LIU KUANG-WEN, MU Zheng-Chang, LIN Cheng-Wei, LIU Kuang-Wen
Принадлежит:

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided. 1. A method of fabricating a semiconductor device having a via , the method comprising:forming an inter-metal dielectric layer on a first portion of a conductive bottom substrate layer, wherein the first portion of the conductive bottom substrate layer is isolated from surrounding portions of the conductive bottom substrate layer;photo patterning a via mask onto the inter-metal dielectric layer;etching the inter-metal dielectric layer to define an open via area to the first portion of the conductive bottom substrate layer, wherein a portion of the inter-metal dielectric layer remains around the open via area with the first portion of the conductive bottom there below;depositing a conductive via material in the open via area adjacent the first portion of the conductive bottom substrate layer;removing conductive via material remaining above the inter-metal dielectric layer; andforming a conductive top layer on the inter-metal dielectric layer and the conductive via material,wherein photo patterning the via mask onto the inter-metal dielectric layer comprises photo patterning the via mask with a via area mask open ratio of at least 90%.2. The method of claim 1 , wherein photo patterning the via mask onto the inter-metal dielectric layer comprises photo patterning the via mask with a via area mask open ratio of 98%.3. The method of claim 1 , wherein photo patterning the via mask onto the inter-metal dielectric layer comprises photo patterning the via mask with a via area mask open ratio of 100%.4. The method ...

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Номер записи: 2
12-04-2012 дата публикации

WALLMOUNT REMOTE CONTROL INTEGRATING REMOTE CONTROL FUNCTION OF AN INTELLIGENT CELLULAR PHONE

Номер: US20120088493A1
Автор: CHEN Wan-Tien, LIN WEI-CHENG
Принадлежит:

A wallmount remote control integrating remote control function of an intelligent cellular phone has a body, a phone holder and a transmission connector. The body has a circuit unit and an input unit and a power supply unit electrically connected with the circuit unit. The phone holder serves to accommodate a cellular phone therein. The transmission connector is mounted on the phone holder, is electrically connected with the power supply unit and the circuit unit, and can be connected with a transmission port of a cellular phone to transmit data and power from the cellular phone. When an intelligent cellular phone is inserted in the wallmount remote control, the input function of the wallmount remote control is disabled and the cellular phone replaces the wallmount remote control to remotely control the household appliance. When the cellular phone is removed, the wallmount remote control is enabled to perform its original input function. 1. A wallmount remote control integrating remote control function of an intelligent cellular phone , comprising: a front surface;', 'a circuit unit mounted inside the body and having a microprocessor, and a transmission module and a wireless communication module electrically connected with the microprocessor;', 'an input unit electrically connected with the microprocessor, mounted on the front surface of the body;', 'a switching unit mounted on outside the body and electrically connected with the microprocessor to generate and transmit a switching signal to the microprocessor if the switching unit is triggered, so the microprocessor enables or disables the input unit according to the switching signal; and', 'a power supply unit mounted inside the body for supplying an operating power to the circuit unit, the input unit and the switching unit;, 'a body havinga phone holder having a stopper and two arms formed on and protruding forwardly from the front surface; anda transmission connector mounted on the stopper, and electrically ...

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Номер записи: 3
20-09-2012 дата публикации

Controlling device and method for abnormality prediction of semiconductor processing equipment

Номер: US20120239317A1
Автор: Cheng-Wei Lin
Принадлежит: Powertech Technology Inc

Disclosed in this invention is a controlling device for abnormality prediction of semiconductor processing equipment. The controlling device includes a multiplexer connecting a plurality of vibration sensors to a spectrum analyzer. Therein, the vibration sensors are non-destructively installed to a variable-frequency rotating mechanism inside the semiconductor processing equipment. The multiplexer includes an adapter and at least a modularized multi-channel connecting assembly plugged into the adapter where the number of the connected vibration sensors is less than the number of the signal connecting terminals of the multiplexer so that at least one terminal is unconnected with the vibration sensors. Additionally, a control signal wire connects the unconnected terminal to a corresponding controller of the variable-frequency rotating element. The vibration spectrum analyzer is configured to record and collect both vibration signals and control signals where these signals are transformed into time-domain waveforms to track the lifetime of the equipment, to predict the failure of the equipment, and to reduce equipment down time, parts waiting time, and equipment repair time of the semiconductor processing equipment.

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Номер записи: 4
28-03-2013 дата публикации

SEPARATION TYPE PNEUMATIC DUAL PARTITION MEMBRANE PUMP AND EXTERNAL PNEUMATIC CONTROL VALVE THEREOF

Номер: US20130078121A1
Автор: LIN Cheng-Wei
Принадлежит:

The present invention relates to a separation type pneumatic dual partition membrane pump, which comprises a pump body and an external pneumatic control valve which is separately installed. Through the operation of the external pneumatic control valve, the main shaft of the pump body and the valve rod of the external pneumatic control valve are reciprocally moved, and the two partition membranes respectively generate stretch and compress motions for changing the volume of each liquid room in the pump body so as to perform the pump stroke and the liquid suction stroke to the liquid. 1. A separation type pneumatic dual partition membrane pump , comprising:a pump body, pump chambers formed at two sides being respectively installed with a shaft hole for the installation of a main shaft, a liquid outlet channel having an outlet port, a liquid inlet channel having an inlet port, two sides of said liquid outlet and said liquid inlet channels adjacent to said pump chambers being respectively installed with a pair of check valves, and two ends of said main shaft being respectively fastened with a partition membrane for dividing each pump chamber into an air room and a liquid room; and two end covers respectively combined at one side of said pump body, said above-mentioned partition membranes being fastened between each end cover and said pump body, said two end covers being respectively formed with a first and a second air inlet apertures, and a first and a second main air passage apertures communicated with said air room, the interiors of said first and said second air inlet apertures being respectively installed with a switch valve; andan external pneumatic control valve, a valve member thereof being formed with a main air inlet port and at least an air guide branch pipe communicated with said main air inlet port; a fixing sleeve pipe installed in said valve member, the surface thereof being radially installed with first, second, third, fourth, fifth air apertures spaced ...

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Номер записи: 5
24-10-2013 дата публикации

Information exchange method and information exchange system

Номер: US20130282306A1
Автор: Cheng-Wei Lin, Chien-Yeh Hsu, Ching-Nan Lin, Hui-Chen Lin, Meng-Chao Kao, Po-Hsu Chen
Принадлежит: Wistron Corp

An information exchange method includes steps of shaking a first electronic device and a second electronic device simultaneously; recording a first vibration waveform of the first electronic device and recording a second vibration waveform of the second electronic device; determining whether the first vibration waveform and the second vibration waveform match each other; and transmitting a first information related to the first electronic device to the second electronic device when the first vibration waveform and the second vibration waveform match each other.

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Номер записи: 6
21-11-2013 дата публикации

ELECTRONIC DEVICE AND CONNECTING COMPONENT

Номер: US20130309882A1
Автор: LIN WEI-CHENG
Принадлежит: WISTRON CORP.

An electronic device includes a first housing, a second housing disposed on the first housing, and a connecting component. The connecting component includes a connecting body and an elastic conductive element. The connecting component is located between the first housing and the second housing. The elastic conductive element with an elastic restoring force is movably disposed in the connecting component. When a part of the elastic conductive element protrudes beyond the connecting body, the elastic conductive element is connected to the second housing and the connecting body. 1. An electronic device , comprising:a first housing;a second housing disposed on the first housing; and a connecting body located between the first housing and the second housing, wherein the connecting body is a hollow structure having a first opening and a second opening opposite to the first opening, and the first opening faces the first housing, and the second opening faces the second housing;', 'an elastic conductive element movably disposed in the connecting body,, 'a connecting component, comprising'}wherein when a part of the elastic conductive element protrudes beyond the second opening, the elastic conductive element is connected to the second housing and the connecting body.2. The electronic device as claimed in claim 1 , further comprising an electrical connector located between the first housing and the second housing claim 1 , and the connecting body disposed on the electrical connector.3. The electronic device as claimed in claim 2 , wherein the electrical connector comprises a metal housing having a hole claim 2 , wherein the connecting body is disposed on the metal housing claim 2 , and the hole corresponds to the first opening.4. The electronic device as claimed in claim 1 , further comprising a circuit board located between the first housing and the second housing claim 1 , and the connecting body disposed on the circuit board.5. The electronic device as claimed in claim 4 , ...

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Номер записи: 7
07-01-2016 дата публикации

MEASURING TEHNOLOGY FOR OPTICAL ELEMENT FOR OBTAINING MEASUREMENT ERROR OPTICAL ELEMENT

Номер: US20160003706A1
Автор: CHANG Shenq-Tsong, HUANG Ting-Ming, LIN WEI-CHENG
Принадлежит: NATIONAL APPLIED RESEARCH LABORATORIES

A measuring method for an optical element for obtaining a plurality of measurement errors of the optical element is disclosed, which comprises steps of irradiating a laser ray to an overall portion of the optical element, wherein the optical element is supported as one of a horizontal state and a vertical state; rotating continuously the optical element with 360 degrees to reflect the laser ray to obtain a reflected light wavefront picture from the reflected laser ray; analyzing the reflected light wavefront picture to obtain a plurality of aberration characteristics information, respectively, each being one of a sine and a cosine wave functions of a wavefront error for each of the plurality of specified rotation angles; analyzing a plurality of interference factors each for the plurality of measurement errors on each of the plurality of aberration characteristics information, respectively; calculating and extracting a plurality of classified aberration characteristics information for each of the plurality of specified rotation angles of the optical element from each of the plurality of aberration characteristics information according to the plurality of measurement errors, respectively; and analyzing each of the plurality of classified aberration characteristics information to obtain an error amount corresponding to each of the plurality of measurement errors, respectively. 1. A measuring method for an optical element for obtaining a plurality of measurement errors of the optical element , comprising steps of:(a) irradiating a laser ray to an entirety of the optical element, wherein the optical element is supported as one of a horizontal state and a vertical state;(b) rotating continuously the optical element with 360 degrees to reflect the laser ray to obtain a reflected light wavefront picture from the reflected laser ray for each of a plurality of specified rotation angles of the optical element;(c) analyzing the reflected light wavefront picture for each of a ...

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Номер записи: 8
02-01-2020 дата публикации

INTEGRATED CIRCUIT STRUCTURE, LAYOUT DIAGRAM METHOD, AND SYSTEM

Номер: US20200004914A1
Автор: Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments. 1. An integrated circuit (IC) structure comprising:a first plurality of metal segments positioned in a first metal layer, each metal segment of the first plurality of metal segments extending in a first direction;a second plurality of metal segments positioned in a second metal layer overlying the first metal layer, each metal segment of the second plurality of metal segments extending in a second direction perpendicular to the first direction; anda third plurality of metal segments positioned in a third metal layer overlying the second metal layer, each metal segment of the third plurality of metal segments extending in the first direction,wherein a pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.2. The IC structure of claim 1 , wherein each of the pitch of the second plurality of metal segments and the pitch of the third plurality of metal segments is larger than the pitch of the first plurality of metal segments.3. The IC structure of claim 1 , further comprising a fourth plurality of metal segments positioned in a fourth metal layer overlying the third metal layer claim 1 , each metal segment of the fourth plurality of metal segments extending in the second direction claim 1 , wherein a pitch of the fourth plurality of metal segments is larger than the pitch of the second plurality of ...

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Номер записи: 9
07-01-2021 дата публикации

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

Номер: US20210005633A1
Автор: Chen Yan-Hao, LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG, YUAN Lipen, Zhuang Hui-Zhong
Принадлежит:

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. An circuit cell , comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion of the circuit including a plurality of first fin structures arranged in a plurality of first rows; anda second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell.2. The circuit cell of claim 1 , wherein the circuit cell is optimized for speed based on inclusion of the first circuit component in the first fin portion claim 1 , wherein the first fin portion is a high fin portion.3. The circuit cell of claim 1 , wherein the circuit cell is optimized for power consumption based on inclusion of the second circuit component in the second fin portion claim 1 , wherein the second fin portion is a less fin portion.4. The circuit cell of claim 1 , wherein the circuit cell is arranged in a double height cell layout with the first fin portion and the second fin portion being arranged in adjacent rows.5. The circuit cell of claim 1 , wherein the first ...

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Номер записи: 10
07-01-2021 дата публикации

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

Номер: US20210005634A1
Автор: Chen Yan-Hao, LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG, YUAN Lipen, Zhuang Hui-Zhong
Принадлежит:

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. A method of fabricating an circuit cell , comprising:accessing a logic design for implementing a function of the circuit cell, the logic design including a plurality of logic components; a first circuit structure comprising a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion including a plurality of first fin structures arranged in first rows, and', 'a second circuit structure comprising a second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;, 'accessing a plurality of circuit structures for implementing one or more of the logic components, the plurality of circuit structures including,'}generating a plurality of circuit designs that use different combinations of the plurality of circuit structures that implement the function;filtering the generated circuit designs that do not meet a first circuit criterion; andselecting a remaining circuit design that has an optimum value for a second circuit criterion.2. The method of ...

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Номер записи: 11
02-01-2020 дата публикации

Multiple fin height integrated circuit

Номер: US20200006318A1
Автор: Hui-Tang YANG, Jiann-Tyng Tzeng, Lipen YUAN, Wei-An Lai, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.

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Номер записи: 12
02-01-2020 дата публикации

DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE

Номер: US20200006338A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, SUE Pin-Dai, TIEN Li-Chun, TZENG JIANN-TYNG, Zhuang Hui-Zhong
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate. 1. A dual transmission gate , comprising:a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor, situated within a first row from among a plurality of rows of an electronic device design real estate, configured to receive a first clocking signal;a first n-type metal-oxide- ...

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Номер записи: 13
07-01-2021 дата публикации

POWER SUPPLY DEVICE AND OPERATION METHOD THEREOF

Номер: US20210006150A1
Автор: Chiu Po-cheng, LAI WEI-HSUN, LIN WEI-CHENG, WANG Chien-Yu
Принадлежит:

A power supply device includes an inductor, a switch, a power supply, and a snubber circuit. A first terminal of the switch is coupled to a first terminal of the inductor. A first terminal of the power supply is coupled to a second terminal of the witch. A first terminal of the snubber circuit is coupled to the first terminal of the switch at a first voltage output terminal. A second terminal of the snubber circuit is electrically coupled to a second terminal of the power supply at a second voltage output terminal, in which the inductor, the switch, the power supply, and the snubber circuit are configured to cooperate to generate an output voltage at the first voltage output terminal and the second voltage output terminal. 1. A power supply device , comprising:an inductor;a switch, a first terminal of the switch being coupled to a first terminal of the inductor;a power supply, a first terminal of the power supply being coupled to a second terminal of the switch; anda snubber circuit, a first terminal of the snubber circuit being coupled to the first terminal of the switch at a first voltage output terminal, and a second terminal of the snubber circuit being coupled to a second terminal of the power supply at a second voltage output terminal;wherein the inductor, the switch, the power supply, and the snubber circuit are configured to cooperate to generate an output voltage between the first voltage output terminal and the second voltage output terminal.2. The power supply device of claim 1 , further comprising:a voltage signal converter, comprising a first converter output terminal and a second converter output terminal, wherein a second terminal of the inductor is coupled to the first converter output terminal, and the second terminal of the power supply is coupled to the second converter output terminal.3. The power supply device of claim 1 , wherein the snubber circuit comprises:an energy storage element;an energy release element, wherein a first terminal of the ...

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Номер записи: 14
08-01-2015 дата публикации

ELECTRONIC SIGNAL TRANSMITTING DEVICE AND INTEGRATED CIRCUIT THEREOF

Номер: US20150009630A1
Автор: Chang Wei-Shuen, Chu Wei-Shen, Lee Hong-Kuei, LIN WEI-CHENG, TUEN LUNG-FAI, Weng Chi-Fang
Принадлежит: WISTRON CORPORATION

An electronic signal transmitting device is disposed in a housing of an integrated circuit. The integrated circuit includes at least one first signal end and at least one second signal end. The electronic signal transmitting device includes at least one electromagnetic transmitting unit, coupled between the first signal end and the second signal end for transmitting an electronic signal between the first signal end and the second signal end; and an electromagnetic insulating layer covering the electromagnetic transmitting unit for protecting the integrated circuit from electromagnetic interference.

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Номер записи: 15
10-01-2019 дата публикации

MULTI-BAND ANTENNA STRUCTURE

Номер: US20190013564A1
Автор: Chiu Po-Wei, Hsiao Chien-Jen, Hsu Sheng-Ruei, Liang Yang-Te, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

A multi-band antenna structure includes a substrate having a first wiring area located on one side surface thereof. The first wiring area has a first metal trace, a second metal trace and a connecting portion formed therein. The first and the second metal trace are respectively in an elongated spiral pattern; and the connecting portion is electrically connected at two opposite ends to the first and the second metal trace. The multi-band antenna structure can be directly integrated into electrical circuits on a circuit board to provide the advantages of reduced manufacturing cost and capable of transmitting or receiving multiple bands of signals. 1. A multi-band antenna structure , comprising:a substrate having a first wiring area located on one side surface thereof; in the first wiring area, there being provided a first metal trace, a second metal trace and a connecting portion; the first and the second metal trace being respectively in an elongated spiral pattern; and the connecting portion being electrically connected at two opposite ends to the first and the second metal trace.2. The multi-band antenna structure as claimed in claim 1 , wherein the first metal trace has a first end claim 1 , a second end located at a distance away from the second end claim 1 , and a first intermediate portion located and extended between the first and the second end and being in an elongated spiral pattern with the first end located at an outer side thereof and the second end located at an inner side thereof; and wherein the second metal trace has a third end claim 1 , a fourth end located at a distance away from the third end claim 1 , and a second intermediate portion located and extended between the third and the fourth end and being in an elongated spiral pattern with the third end located at an outer side thereof and the fourth end located at an inner side thereof.3. The multi-band antenna structure as claimed in claim 2 , wherein the first end of the first metal trace is ...

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Номер записи: 16
14-01-2021 дата публикации

Semiconductor device and method of forming the semiconductor device

Номер: US20210013086A1
Автор: Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.

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Номер записи: 17
15-01-2015 дата публикации

ANTI-EPITHELIAL CELL ADHESION MOLECULE (EpCAM) ANTIBODIES AND METHODS OF USE THEREOF

Номер: US20150017230A1
Автор: Cheng-Wei Lin, Han-Chung Wu, Mei-ying LIAO
Принадлежит: Academia Sinica

An isolated monoclonal antibody or an antigen-binding fragment thereof is disclosed. The antibody or the antigen-binding fragment is characterized by: (a) having a specific binding affinity to epithelial cell adhesion molecule (EpCAM) comprising the amino acid sequence of SEQ ID NO: 1; (b) having a specific binding affinity to cancer cells expressing EpCAM said cancer cells being selected from the group consisting of oral cancer cells, nasopharyngeal cancer cells (NPC), colorectal cancer cells, and ovarian cancer cells; and (c) having no binding affinity to human umbilical vein endothelial cell (HUVEC) and normal nasal mucosal epithelia (NNM). Also disclosed is an isolated monoclonal antibody or an antigen-binding fragment thereof that has a specific binding affinity to an epitope within the sequence of KPEGALQNNDGLYDPDCDE (SEQ ID NO: 63) located within the EGF-like domain II of epithelial cell adhesion molecule (EpCAM). Methods of using the same are also disclosed.

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Номер записи: 18
19-01-2017 дата публикации

MTJ-BASED CONTENT ADDRESSABLE MEMORY

Номер: US20170018308A1
Автор: Ghosh Swaroop, Lin Cheng Wei
Принадлежит: UNIVERSITY OF SOUTH FLORIDA

Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words. 1. A content addressable memory cell apparatus , comprising:a plurality of domain-wall-based magnetic tunnel junctions (DW-MTJs) interconnected to write complementary bits, wherein a write polarity on each of the plurality of DW-MTJs is controlled by modulating a direction of current;a plurality of transistors;a plurality of searchlines;a wordline;a bitline (BL);a sourceline (SrL); anda plurality of matchlines.2. The content addressable memory cell apparatus of claim 1 , wherein a write operation is performed by turning on a first transistor of the plurality of transistors claim 1 , turning off at least one of the other transistors of the plurality of transistors claim 1 , and shifting the domain walls of the DW-MTJs through operations of the sourceline and the bitline.3. The content addressable memory cell apparatus of claim 2 , wherein a ‘0’ bit-state is written by making (SrL claim 2 , BL)=(1 claim 2 ,0) claim 2 , and wherein an ‘1’ bit-state is written by making (SrL claim 2 , BL)=(0 claim 2 ,1).4. The content addressable memory cell apparatus of claim 2 , wherein a search operation is performed by turning off the first transistor and placing a search value on at least two of the plurality of the search lines.5. The content addressable memory cell apparatus of claim 4 , wherein a match between the search value and a stored value is determined by a high resistance between at least two of the plurality of matchlines.6. The content addressable memory cell apparatus of claim 4 , ...

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Номер записи: 19
17-01-2019 дата публикации

Aging-sensitive recycling sensors for chip authentication

Номер: US20190018058A1
Автор: Cheng-Wei Lin, Swaroop Ghosh
Принадлежит: UNIVERSITY OF SOUTH FLORIDA

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

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Номер записи: 20
18-01-2018 дата публикации

FINGERPRINT IDENTIFICATION DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180018493A1
Автор: Hsiao Chien-Jen, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

A fingerprint identification device and a manufacturing method of the fingerprint identification device. The fingerprint identification device includes a substrate, a sensation electrode layer and a fingerprint identification sensation chip. The substrate has a first face, a second face and multiple perforations in connection with the first and second faces. The sensation electrode layer is disposed on the first face of the substrate and has multiple first electrodes, multiple second electrodes and an insulation layer. The first and second electrodes and the insulation layer are laminated with each other. A part of the insulation layer is disposed between the first and second electrodes and another part of the insulation layer encloses the first and second electrodes. The fingerprint identification sensation chip is disposed on the second face of the substrate. 1. A fingerprint identification device comprising:a substrate having a first face, a second face and multiple perforations in connection with the first and second faces, the substrate being made of glass material, the multiple perforations being formed by means of laser perforation;a sensation electrode layer disposed on the first face of the substrate, the sensation electrode layer having multiple first electrodes, multiple second electrodes and an insulation layer, the first and second electrodes and the insulation layer being laminated with each other, a part of the insulation layer being disposed between the first and second electrodes and another part of the insulation layer enclosing the first and second electrodes;a fingerprint identification sensation chip disposed on the second face of the substrate; anda conductive layer having multiple conductors, the conductors being partially positioned in the perforations of the substrate to extend through the perforations and partially disposed on the second face of the substrate, the first and second electrodes being electrically connected to the fingerprint ...

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Номер записи: 21
21-01-2016 дата публикации

Semiconductor Devices and Fabrication Methods With Improved Word Line Resistance And Reduced Salicide Bridge Formation

Номер: US20160020295A1
Автор: CHEN Kuan-Chih, LIN Cheng-Wei, Liu Kuang-Wen
Принадлежит:

Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

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Номер записи: 22
16-01-2020 дата публикации

SEMICONDUCTOR DEVICE INCLUDING CELL REGION HAVING MOR SIMILAR CELL DENSITIES IN DIFFERENT HEIGHT ROWS, AND METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM OF SAME

Номер: US20200019667A1
Автор: LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG, YANG Hui-Ting, YUAN Lipen
Принадлежит:

A method of generating a layout diagram includes: identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities; relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights; for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities. 1. A method of manufacturing a semiconductor device , the method comprising: [ 'relative to a second direction, substantially perpendicular to the first direction, the first and second rows having corresponding first (H1) and second (H2) heights;', 'identifying a first area in the layout diagram which is populated with cells, the first area including first and second rows extending substantially parallel to a first direction, the first and second rows having substantially different cell densities;'}, 'for a first one of the cells having H1 height (a first H1 cell) in a first location in the first row, substituting a multi-row-height cell for the first H1 cell, the multi-row-height cell being narrower than the first H1 cell relative to the first direction; and', 'placing a first part of the multi-row-height cell into a portion of the first location resulting in the first and second rows having more similar cell densities., 'for a layout diagram stored on a non-transitory computer-readable medium, generating a layout diagram including2. The method of claim 1 , wherein the identifying ...

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Номер записи: 23
16-01-2020 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20200020588A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch. 1. A method of forming an integrated chip , comprising:forming a plurality of gate structures over a substrate;forming a plurality of source and drain regions along opposing sides of the plurality of gate structures;defining a plurality of middle-of-the-line (MOL) structures at locations laterally interleaved between the plurality of gate structures; andredefining the plurality of MOL structures by getting rid of a part but not all of one or more of the plurality of MOL structures, wherein redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.2. The method of claim 1 ,wherein the plurality of MOL structures are defined according to a first photomask; andwherein the plurality of MOL structures are redefined according to a cut mask.3. The method of claim 1 , wherein redefining the plurality of MOL structures forms two separate MOL active structures from a single one of the plurality of MOL structures.4. The method of claim 1 , wherein the plurality of MOL structures are defined to be at a substantially regular pitch that is smaller than the irregular pitch.5. The method of claim 1 , further comprising:forming an inter-level ...

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Номер записи: 24
21-01-2021 дата публикации

Random Cut Patterning

Номер: US20210020570A1
Автор: Chih-Ming Lai, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

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Номер записи: 25
16-01-2020 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20200021292A1
Автор: Chuang Cheng-Chi, Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit includes a first gate, a second gate, a first contact and a first insulating layer. The first gate extends in the first direction and is located on a first level. The second gate extends in the first direction, is located on the first level, and is separated from the first gate in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first gate and the second gate, is located on a second level different from the first level, and is coupled to at least the first gate. The first insulating layer extends in the second direction, overlaps the first gate and the second gate, and is between the second gate and the first contact. 1. An integrated circuit comprising:a first active region in a substrate, extending in a first direction, and being located on a first level;a second active region in the substrate, extending in the first direction, being located on the first level, and being separated from the first active region in a second direction different from the first direction;a first contact coupled to the first active region, extending in the second direction, being located on a second level different from the first level, and overlapping the first active region;a second contact coupled to the second active region, extending in the second direction, being located on the second level, overlapping the second active region, and being separated from the first contact in at least the second direction; anda third contact extending in the second direction, overlapping the first contact and the second contact, being located on a third level different from the first level and the second level, and being coupled to the first active region and the first contact.2. The integrated circuit of claim 1 , wherein the third contact is further coupled to the second contact and the second active region.3. The integrated circuit of claim 2 , wherein the integrated circuit is part of an inverter circuit.4 ...

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Номер записи: 26
24-04-2014 дата публикации

DATA WRITING METHOD AND DATA STORAGE DEVICE

Номер: US20140112069A1
Автор: LIN Cheng-Wei
Принадлежит: SILICON MOTION, INC.

The invention provides a data writing method and device for a flash memory. According to the method, the flash memory obtains write data to be written to the flash memory, directs the flash memory to write a data page of the write data to a strong page of a target pair page of a target block, and directs the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page. 1. A data writing method for a flash memory , comprising:obtaining write data to be written to the flash memory;directing the flash memory to write a data page of the write data to a strong page of a target pair page of a target block; anddirecting the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page.2. The data writing method as claimed in claim 1 , further comprising:selecting the target block for storing the write data from a plurality of blocks of the flash memory;selecting the target pair page from a plurality of pair pages of the target block according to a pair page record table; andrepeating selection of the target pair page, writing of the data page, and writing of the first predetermined data until all of the write data are written to the target block.3. The data writing method as claimed in claim 1 , further comprising:selecting the target block for storing write data from a plurality of blocks of the flash memory;selecting the target page from a plurality of pages of the target block;determining whether the target page is a strong page according to a pair page record table;when the target page is the strong page, performing step of directing the flash memory to write the data page of the write data to the target page; andwhen the target page is not the strong page, performing step of directing the flash memory to write the predetermined data to the target page.41. The data writing ...

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Номер записи: 27
10-02-2022 дата публикации

SEMICONDUCTOR DEVICES WITH BACKSIDE POWER DISTRIBUTION NETWORK AND FRONTSIDE THROUGH SILICON VIA

Номер: US20220045011A1
Автор: Chuang Cheng-Chi, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer. 1. A semiconductor structure , comprising: a first conductive line in the backside dielectric layer; and', 'a second conductive line in the backside dielectric layer, wherein the backside dielectric layer is in contact with a first surface of a substrate;, 'a power distribution network in a backside dielectric layer, comprisinga plurality of backside vias through the substrate and in contact with the first conductive line;a via rail in contact with a second surface of the substrate, wherein the second surface is on an opposite side of the first surface;a first interlayer dielectric in contact with the via rail and the substrate;a second interlayer dielectric in contact with the first interlayer dielectric;a first interconnect layer in the second interlayer dielectric;a third interlayer dielectric in contact with the second interlayer dielectric;a plurality of vias in the third interlayer dielectric, wherein the plurality of vias is electrically coupled to the via rail;a top ...

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Номер записи: 28
23-01-2020 дата публикации

LUMINOUS ELECTRONIC CLOCK

Номер: US20200026241A1
Автор: LIN Cheng-Wei
Принадлежит:

A luminous electronic clock includes a multi-diameter forward tapered case frame; a transparent plate installed in a front circumferential edge of the case frame with a sealing ring mounted between them; a dial spaced behind the transparent plate and having time markers, temperature numbers and humidity numbers provided thereon; clock, thermometer and hygrometer movements mounted on a back side of the dial; hands of the clock and pointers of the thermometer and the hygrometer mounted on movement shafts and located on a front side of the dial; a set of LED lights installed around the clock movement shaft and located behind the dial; battery holders mounted behind the dial; and a case back fixedly held to a rear circumferential edge of the case frame by retaining springs and having windows corresponding to the movements and the battery holders. 1. A luminous electronic clock , comprising a case frame , a transparent plate , a dial , a cover plate , a movement , a set of LED lights , battery holders and a case back , characterized in that the transparent plate is installed on the case frame in a front circumferential edge thereof; the dial has a reflecting sheet on a back side thereof and has time markers provided along a radially outer peripheral area on a front side thereof; the dial is located behind the transparent plate; a movement shaft hole is provided at a center of the dial; the cover plate is installed on the front side of the dial and covers the movement shaft hole; the dial is made of a translucent acrylic or PS material; the movement includes a clock movement , and the movement is mounted corresponding to the movement shaft hole , so that a movement shaft of the clock movement is extended through the movement shaft hole and the cover plate; hands for the clock are mounted on sections of the movement shaft that is exposed from the front side of the cover plate; the LED lights are installed in the movement shaft hole and around the movement shaft of the ...

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Номер записи: 29
28-01-2021 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20210028311A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices. 1. A method , comprising:forming a plurality of fins protruding from a first dielectric layer;depositing a spacer on a sidewall of the fin and in contact with the first dielectric layer;depositing a second dielectric layer on the first dielectric layer;depositing a conductive material between the second dielectric layer and the spacer to form a conductive rail, wherein a top surface of the conductive rail is below a top surface of the plurality of fins; andforming a source/drain terminal in contact with the conductive rail.2. The method of claim 1 , further comprising forming a seed layer on the first dielectric layer.3. The method of claim 2 , wherein depositing the conductive material comprises epitaxially growing the conductive material from a top surface of the seed layer.4. The method of claim 2 , wherein forming the seed layer comprises:depositing a seed ...

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Номер записи: 30
30-01-2020 дата публикации

LIGHT-EMITTING CLOCK

Номер: US20200033809A1
Автор: LIN Cheng-Wei
Принадлежит:

A light-emitting clock has a case, a dial, a light-emitting mechanism, a movement and a plurality of hands. The case has a front cover, a back cover and a washer. The front cover is coupled to the back cover. The washer is disposed between the front cover and the back cover. The dial is disposed between the washer and the back cover. The light-emitting mechanism has a switch, a power unit electrically connected to the switch, and at least one lamp strip electrically connected to the switch. The switch and the power unit are disposed on the back cover. The lamp strip is annularly disposed at the washer. A light-emitting surface of the lamp strip at least faces the rim of the dial. The movement is disposed on the back cover. The hands are coupled to the movement and correspond in position to one side of the dial. 1. A light-emitting clock , comprising:a case having a front cover, a back cover and a washer, the front cover being coupled to the back cover, with the washer disposed between the front cover and the back cover;a dial disposed between the washer and the back cover;a light-emitting mechanism comprising a switch, a power unit electrically connected to the switch, and at least one lamp strip electrically connected to the switch, wherein the switch and the power unit are disposed on the back cover, with the lamp strip annularly disposed at the washer, and a light-emitting surface of the lamp strip at least faces a rim of the dial;a movement disposed on the back cover; anda plurality of hands coupled to the movement and corresponding in position to a side of the dial.2. The light-emitting clock of claim 1 , wherein a receiving groove is annularly disposed at an inner edge of a bottom of the washer claim 1 , and the lamp strip is disposed in the receiving groove.3. The light-emitting clock of claim 1 , wherein another receiving groove is annularly disposed at an outer edge of a top of the washer and has another lamp strip electrically connected to the switch.4. ...

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Номер записи: 31
09-02-2017 дата публикации

Method of Manufacturing Nitrone Compound

Номер: US20170036989A1
Автор: Hong Bor-Cherng, LIN Cheng-Wei
Принадлежит:

A method of manufacturing nitrone compounds is provided. The method includes: providing a nitro compound; and performing a photoreaction of the nitro compound, a catalyst and an additive under visible light to obtain the nitrone compound. 1. A method of manufacturing nitrone compound , comprising:providing a nitro compound; andperforming a photoreaction of the nitro compound, a catalyst and an additive under visible light to obtain the nitrone compound.2. The method of claim 1 , wherein the catalyst is Ru(bpy)Cl.6HO claim 1 , Ru(bpy)Cl claim 1 , Ru(bpy)(BF) claim 1 , Ru(bpy)(PF) claim 1 , Ir[dF(CF)ppy](dtbbpy)(PF) or Ir(ppy)(dtbbpy)(PF).3. The method of claim 1 , wherein a wavelength of the visible light is within the range of 350 to 700 nm.4. The method of claim 3 , wherein a wavelength of the visible light is within the range of 450 to 460 nm.5. The method of claim 1 , wherein the nitro compound is a second order or third order nitro compound.6. The method of claim 1 , wherein the additive is diisopropylethylamine (DIPEA) claim 1 , diisopropylisobutylamine (DIPIBA) or a derivative of 1 claim 1 ,4-Dihydropyridine (DHP).7. The method of claim 6 , wherein when the additive is diisopropylisobutylamine (DIPIBA) claim 6 , an aldehyde compound is further added in the photoreaction.8. The method of claim 6 , wherein the derivative of 1 claim 6 ,4-Dihydropyridine (DHP) is Hantzsch ester.9. The method of claim 1 , wherein the catalyst is performed a photoredox catalyst reaction in the photoreaction. This application claims priority from Taiwan Patent Application No. 104125714, filed on Aug. 6, 2015, in the Taiwan Intellectual Property Office, the content of which are hereby incorporated by reference in their entirety for all purposes.1. Field of the InventionThe present invention relates to a manufacturing method, in particular with respect to a manufacturing method of manufacturing nitrone compound.2. Description of the Related ArtNitrone compound is a key intermediate for ...

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Номер записи: 32
08-02-2018 дата публикации

METHOD OF ADJUSTING METAL LINE PITCH

Номер: US20180039723A1
Автор: CHEN Chih-Liang, Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P. 1. A method , performed by at least one processor , comprising:obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form;determining a unit pattern having a width of n times of the gate pitch;assigning m consecutive metal lines to the unit pattern;dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R);determining an integer P so that a value of the remainder R divided by P satisfies a layout precision; anddetermining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.2. The method according to further comprising generating a netlist data including information on the inter-pattern metal line pitch and the intra-pattern metal line pitch.3. The method according to claim 1 , wherein the ratio between gate pitch and metal line pitch is 3:2 or 4:3.4. The method according to claim 1 , wherein the metal line belongs to metal-1 (M1) layer.5. The method according to further comprising claim 1 , after the assigning claim 1 , determining whether the gate pitch is divisible by m.6. The method according to further comprising determining the metal pitch to be 2n/m times of the gate pitch if the gate pitch is divisible by m.7. The method ...

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Номер записи: 33
09-02-2017 дата публикации

INTEGRATED CIRCUIT HAVING SLOT VIA AND METHOD OF FORMING THE SAME

Номер: US20170040260A1
Автор: LIN WEI-CHENG, NARAYANASETTI Praneeth, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line. 1. An integrated circuit comprising:a first doped region in a substrate;a first conductive line over a top surface of the substrate, and wherein the first conductive line has a first length extending in a first direction and a first width extending in a second direction, the first length being greater than the first width and each of the first length and first width are parallel with the top surface of the substrate;a second conductive line parallel the first conductive line, wherein the second conductive line has a second length and a second width, the second width being less than the second length and each of the second width and second length being parallel with a top surface of the substrate, wherein the first doped region is disposed below and interposing the first and second conductive lines; anda slot via interfacing the first and second conductive lines wherein the slot via has a third length and a third width each parallel the top surface of the substrate, and wherein the third length is greater than the third width, wherein a first portion of the slot via is in direct contact with the first conductive line, a second portion of the slot via is in direct contact with the second conductive line, and the slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line such that a sum of a length of the first portion and a length of the second portion is less than the ...

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Номер записи: 34
06-02-2020 дата публикации

POWER STRUCTURE WITH POWER PICK-UP CELL CONNECTING TO BURIED POWER RAIL

Номер: US20200042668A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit includes two buried power rails located beneath a first metal layer overlying the substrate, and two upper power rails in a second metal layer overlying the first metal layer. The two upper power rails are perpendicular to the two buried power rails. The integrated circuit includes a power pick-up cell having a functional circuit. The functional circuit includes a conductive segment beneath the first metal layer and a power pad in the first metal layer. The power pad is conductively connected to one of the upper power rails through a first via. The first power pad is conductively connected to the first conductive segment through a second via. The first conductive segment is conductively connected to one of the buried power rails through a third via. 1. An integrated circuit comprising:a substrate;a first metal layer overlying the substrate;a first buried power rail and a second buried power rail both extending in a first direction and located beneath the first metal layer;a second metal layer overlying the first metal layer;a first upper power rail and a second upper power rail each in the second metal layer and extending in a direction that is perpendicular to the first direction;a power pick-up cell having a functional circuit, the functional circuit comprising a first conductive segment located beneath the first metal layer, and a first power pad in the first metal layer;wherein the first power pad is conductively connected to the first upper power rail through at least one first via between the second metal layer and the first metal layer and the first power pad is conductively connected to the first conductive segment through at least one second via between the first metal layer and the first conductive segment; andwherein the first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.2. The integrated circuit of claim ...

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Номер записи: 35
07-02-2019 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20190043759A1
Автор: CHEN Chih-Liang, CHEN Chun-Kuang, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch. 1. An integrated chip , comprising:a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction;a plurality of gate structures arranged over the substrate at a substantially regular pitch;a plurality of middle-of-the-line (MOL) structures respectively interleaved between adjacent ones of the plurality of gate structures;wherein the plurality of MOL structures comprise MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect; andwherein the plurality of MOL active structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.2. The integrated chip of claim 1 , further comprising:a plurality of vias disposed within an inter-level dielectric (ILD) layer and contacting the MOL active structures, wherein the plurality of vias have sidewalls continuously extending between a bottom of the ILD layer and a top of the ILD layer.3. The ...

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Номер записи: 36
06-02-2020 дата публикации

High-Density Semiconductor Device

Номер: US20200043741A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a first material on a substrate;depositing on the substrate a second material;depositing a spacer material on the first and second materials;forming a third material on a top surface and a sidewall of the spacer; andetching the third material on the sidewall of the spacer to expose a portion of the first material.2. The method of claim 1 , wherein the second material has an etch selectivity different from an etch selectivity of the first material3. The method of claim 1 , further comprising converting the third material on the top surface and the sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.4. The method of claim 3 , wherein converting the third material on the top surface and the sidewall of the spacer into the fourth material includes implanting ions in the third material on the top surface and the sidewall of the spacer.5. The method of claim 3 , wherein converting the third material on the top surface and the sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.6. The method of claim 5 , wherein the tilt angle is between about 30 degrees and about 60 degrees relative to a horizontal axis.7. The method of claim 1 , further comprising removing the exposed portion of the first material to expose a portion of the substrate.8. The method of claim 1 , further comprising etching back the second material to a ...

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Номер записи: 37
15-02-2018 дата публикации

Source Driving Device with 3 Types of Gate Oxide Layer

Номер: US20180047355A1
Автор: Jui-Chang Lin, Ming-Han Lee, Wei-Cheng Lin, Yu-Hao Hsu
Принадлежит: NOVATEK MICROELECTRONICS CORP

A source driving device for a display system includes a receiving module, for receiving display data; a register module, for sorting pixel data included in the display data to generate sorted pixel data; a latch module, for outputting sequenced display data to the level shifting module; a level shifting module, for adjusting the sequenced display data from a low voltage range to a medium voltage range; a converting module; for converting the sequenced display data to analog display voltages; a buffer module, for generating a plurality source driving signals according to the analog display voltages; and an output switching module, for outputting the plurality source driving signals to a display device of the display system operating in a high voltage range; wherein circuit components in the source driving device operating in different voltage ranges have different gate oxide thicknesses.

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Номер записи: 38
16-02-2017 дата публикации

ELECTRO-STATIC DISCHARGE PROTECTION STRUCTURE AND ELECTRONIC DEVICE

Номер: US20170048954A1
Автор: Cheng Tzu-En, Hung Wen-Shan, Lee Hong-Kuei, Li Hui-Yu, LIN WEI-CHENG, Peng Ping-Cheng, Weng Chi-Fang
Принадлежит:

An electro-static discharge protection structure adapted to be utilized in an electronic device is provided. The electronic device includes a housing, a printed circuit board, and a connector. The electro-static discharge protection structure includes a first discharge circuit and a discharge device. The first discharge circuit is electrically connected to the housing. The discharge device is connected to the first discharge circuit. The discharge device includes a discharge plate which includes a plurality of charge entry points and a plurality of charge exit points. The connector is disposed between the discharge device and the printed circuit board. An electronic device including the electro-static discharge protection structure is also provided. 1. An electro-static discharge protection structure for an electronic device that comprises a housing , a printed circuit board , and a connector , the electro-static discharge protection structure comprising:a first discharge circuit electrically connected to the housing; anda discharge device connected to the first discharge circuit and comprising at least one discharge plate that comprises a plurality of charge entry points and a plurality of charge exit points thereon, wherein the connector is disposed between the discharge device and the printed circuit board.2. The electro-static discharge protection structure according to claim 1 , wherein the at least one discharge plate further comprises a first ground region and a second ground region claim 1 , wherein the charge exit points are disposed in the first ground region and the charge entry points are disposed in the second ground region.3. The electro-static discharge protection structure according to claim 2 , wherein the at least one discharge plate further comprises a plurality of discharge lines disposed between the charge entry points and the charge exit points.4. The electro-static discharge protection structure according to claim 3 , wherein the second ground ...

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Номер записи: 39
03-03-2022 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20220068791A1
Автор: Jiann-Tyng Tzeng, Kam-Tou SIO, Meng-Hung Shen, Te-Hsin Chiu, Wei-An Lai, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.

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Номер записи: 40
23-02-2017 дата публикации

CARRIER FOR HARD DISK DRIVE

Номер: US20170052572A1
Автор: Chen Kuo-Feng, LIN Cheng-Wei, WANG Hung-Yuan
Принадлежит:

A carrier includes a frame defining a first space configured to accommodate a first type of hard disk drive, and an adjusting mechanism slidably coupled to the frame. The adjusting mechanism is transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second type of hard disk drive different from the first type of hard disk drive. 1. A carrier for a hard disk drive comprising:a frame defining a first space configured to accommodate a first hard disk drive, and an adjusting mechanism slidably coupled to the frame, the adjusting mechanism transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second hard disk drive different from the first hard disk drive;wherein the adjusting mechanism comprises an installing portion configured for installation of the first hard disk drive or the second hard disk drive, and two coupling portions extending from two opposite ends of the installing portion, the two coupling portions being slidably coupled to the frame; the frame comprises a first connecting wall and a second connecting wall opposite to the first connecting wall, and the first connecting wall defines a receiving room; when the adjusting mechanism is in the first configuration, the installation portion is received in the receiving room and under the first connecting wall, and when the adjusting mechanism is in the second configuration, the installation portion is located between the first connecting wall and the ...

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Номер записи: 41
15-05-2014 дата публикации

SHIFT REGISTER CIRCUIT

Номер: US20140132582A1
Автор: Chen Kuan-Yu, LIN WEI-CHENG
Принадлежит: AU OPTRONICS CORP.

A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a first driving circuit and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The first driving circuit is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the first driving circuit. The voltage-stabilizing circuit is electrically connected with the output terminal of the first driving circuit for stabilizing the control signal from the first driving circuit. Some circuits of some other shift registers are controlled according to the control signal. 1. A shift register circuit comprising plural stages of shift registers , each stage of shift register comprising:a pull-up circuit for charging a first node;a first driving circuit electrically connected with the first node, wherein according to the voltage level of the first node, an output signal is outputted from an output terminal of the first driving circuit, wherein the output signal is provided to a next-stage shift register as a start pulse signal, and provided to specific shift registers previous to the current-stage shift register as a control signal; anda voltage-stabilizing circuit electrically connected with the output terminal of the first driving circuit for stabilizing the output signal of the first driving circuit;wherein the voltage-stabilizing circuit comprises:a voltage-stabilizing control unit for generating a voltage-stabilizing control signal corresponding to the current-stage shift register;a first voltage-stabilizing unit electrically connected with the voltage-stabilizing control unit for receiving the voltage-stabilizing control signal, wherein according to the voltage-stabilizing control signal, the first voltage-stabilizing unit determines whether the output terminal of the first driving circuit is discharged; anda second ...

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Номер записи: 42
04-03-2021 дата публикации

WATER COOLING SYSTEM FOR PROVIDING WATER WITH CONSTANT TEMPERATURE

Номер: US20210063102A1
Автор: CHUANG YUNG-CHENG, CHUANG Yung-Yu, LIN Cheng-Wei
Принадлежит:

A water cooling system includes a temperature control device which is connected with a first heat exchanger. A second heat exchanger includes a water temperature control path and a constant temperature water path. The water of the first heat exchanger is controlled by the temperature control device and flows to the water temperature control path. The water in the constant temperature water path tows through the second heat exchanger to proceed heat exchange with the water in the water temperature control path, and then flows to the target equipment. The temperature difference of the water flowing to the target equipment is smaller than that of conventional water cooling system. 1. A water cooling system comprising:a temperature controller;a first heat exchanger having a hot water path, a refrigerant path and an even temperature water path, two ends of the hot water path respectively connected to the temperature controller, two ends of the refrigerant path respectively connected to the temperature controller, the even temperature water path including an even temperature water outlet and an even temperature water inlet;a first tank;a first pump connected between the first tank and the even temperature water inlet;a second heat exchanger including a water temperature control path and a constant temperature water path, the water temperature control path including a first inlet and a first outlet, the first inlet connected to the even temperature water outlet, the first outlet connected to the first tank, the constant temperature water path including a constant temperature water outlet and a constant temperature water inlet;a second tank;a target equipment connected between the constant temperature water outlet and the second tank;a second pump connected between the second tank and the constant temperature water inlet;wherein the temperature controller controls temperature of the refrigerant path and the even temperature water path, water in the even temperature water ...

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Номер записи: 43
20-02-2020 дата публикации

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

Номер: US20200058681A1
Автор: Chen Yan-Hao, LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG, YUAN Lipen, Zhuang Hui-Zhong
Принадлежит:

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. A integrated circuit cell , comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows; anda second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.2. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is optimized for speed based on inclusion of the first circuit component in the high fin portion.3. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is optimized for power consumption based on inclusion of the second circuit component in the less fin portion.4. The integrated circuit cell of claim 1 , wherein the integrated circuit cell is arranged in a double height cell layout with the high fin portion and the less fin portion being arranged in adjacent rows.5. The integrated circuit cell of claim 1 , wherein the first circuit component is electrically coupled to the second circuit component to form a standard cell for a logic circuit.6. The integrated circuit cell of claim 5 , wherein the logic circuit is a multi- ...

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Номер записи: 44
28-02-2019 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20190065658A1
Автор: CHEN Chih-Liang, CHEN Shun Li, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Zhuang Hui-Zhong
Принадлежит:

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule. 1. A method of forming an integrated circuit , the method comprising: generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction and being located on a first layout level;', 'generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns; and', 'generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature ...

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Номер записи: 45
08-03-2018 дата публикации

System for and method of manufacturing a layout design of an integrated circuit

Номер: US20180068050A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou SIO, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

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Номер записи: 46
09-03-2017 дата публикации

PLASMA-BASED PROCESSING SYSTEM AND OPERATION METHOD THEREOF

Номер: US20170069467A1
Автор: Kawai Parker Yoko, LIN WEI-CHENG, SHENG Tienyu
Принадлежит:

A plasma-based processing system and a corresponding operation method are proposed. One or more absorbers are positioned between a plasma generation volume inside the plasma chamber and a support structure configured to support the workpiece, and then a portion of plasma delivered from the plasma generation volume to the support structure (or the workpiece) is absorbed by the absorber(s). Further, the absorber(s) are made of electrical conductive material(s), and the structure of at least one absorber and/or the relative geometric relation between at least two absorbers is adjustable. Hence, the position(s) of the electric conductor(s) overlap(s) with the delivered plasma may be adjusted, and then the ion current distribution on the cross section of the delivered plasma may be modified correspondingly. 1. A plasma-based processing system , comprising:a plasma chamber, configured to generate plasma in a plasma generation volume inside the plasma chamber;a support structure, configured to support a workpiece; andan absorber, positioned between the plasma generation volume and the support structure, and configured to absorb a portion of the plasma delivered from the plasma generation volume to the support structure; andwherein, on a cross section of the plasma delivered from the plasma generation volume to the support structure, the absorber has at least one radial element being able to move in a radial direction along the cross section; andwherein the absorber is made of electrical conductive material.2. The system of claim 1 , wherein the support structure is positioned outside the plasma chamber.3. The system of claim 1 , wherein a contour of the absorber has at least one hole-pattern structure.4. The system of claim 1 , on the cross section of the plasma delivered from the plasma generation volume to the support structure claim 1 , the absorber has N radial elements claim 1 , which move in the radial direction along the cross section claim 1 , and each angle ...

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Номер записи: 47
05-06-2014 дата публикации

GAS MIXTURE METHOD AND APPARATUS FOR GENERATING ION BEAM

Номер: US20140151572A1
Автор: HU Koulin, LIN WEI-CHENG, WAN ZHIMIN
Принадлежит: ADVANCED ION BEAM TECHNOLOGY, INC.

A gas mixture method and apparatus of prolonging lifetime of an ion source for generating an ion beam particularly an ion beam containing carbon is proposed here. By mixing the dopant gas and the minor gas together to generate an ion beam, undesired reaction between the gas species and the ion source can be mitigated and thus lifetime of the ion source can be prolonged. Accordingly, quality of ion beam can be maintained. 1. A gas mixture method of prolonging lifetime of an ion source for generating an ion beam comprising:supplying a dopant gas into a container, wherein the dopant gas is a carbon-containing gas used for generating carbon-containing ions; and{'sub': 2', '4', '3', '3', '4, 'supplying a minor gas into the container to dilute the dopant gas for prolonging lifetime of the ion source, wherein the minor gas can be H, CF, Xe, Kr, Ar, PH, AsH, CHor any combination thereof; and'}providing a gas mixture in the ion source chamber to generate the ion beam after mixing the dopant gas and the minor gas at a mixture ratio in the container, wherein the mixture ratio is volume ratio.2. The gas mixture method according to claim 1 , wherein the container is a gas bottle and the dopant gas and minor gas are already pre-mixed at the fixed mixture ratio in the gas bottle.3. (canceled)4. The gas mixture method according to claim 1 , wherein the dopant gas can be CO claim 1 , CO2 claim 1 , CH4 claim 1 , CF4 claim 1 , C2H2O4 or any combination thereof.5. The gas mixture method according to claim 1 , wherein the gas mixture comprises CO2 claim 1 , CO and H2.6. The gas mixture method according to claim 5 , wherein the mixture ratio of CO2 claim 5 , CO and H2 is 10:A:X claim 5 , wherein A ranges from 0.1 to 2 and X ranges from 1 to 6.7. The gas mixture method according to claim 5 , wherein the mixture ratio of CO2 claim 5 , CO and H2 is 10:0.5:3.8. The gas mixture method according to claim 1 , wherein the gas mixture comprises CO2 claim 1 , CO claim 1 , H2 and Xe.9. The gas ...

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Номер записи: 48
07-03-2019 дата публикации

MIXED METAL DODECABORIDES AND USES THEREOF

Номер: US20190071318A1
Автор: Akopov Georgiy, Kaner Richard Barry, LIN Cheng-Wei, Sobell Zachary C., Turner Christopher Lawrence, Yeung Michael Tyrone
Принадлежит: The Regents of the University of California

Disclosed herein, in certain embodiments, are compounds, methods, tools, and abrasive materials comprising mixed transition metal dodecaborides. 2. The composite matrix of claim 1 , wherein the composite matrix is resistant to oxidation.3. The composite matrix of claim 1 , wherein the composite matrix possesses a density of 4.0 g/cmor less.4. The composite matrix of claim 1 , wherein the composite matrix possesses a hardness between 38.0 and 52.0 GPa.5. The composite matrix of claim 1 , wherein the composite matrix is crystalline and comprises a unit cell that is cubic or tetragonal as determined by X-ray powder diffraction.6. The composite matrix of claim 5 , wherein the unit cell is cubic and the length between two adjacent vertices in the unit cell is a claim 5 , wherein a is from 7.350 to 7.550 Å.7. The composite matrix of claim 5 , wherein the unit cell is tetragonal and comprises two distinct lengths between one vertex and at least two adjacent vertices claim 5 , wherein the two distinct lengths comprise a first length c and a second length a claim 5 , wherein c is from 7.350 to 7.550 Å and a is from 5.150 to 5.450 Å.8. The composite matrix of claim 1 , wherein the composite matrix is ZrYB.9. The composite matrix of claim 1 , wherein the composite matrix is ZrScB.10. The composite matrix of claim 1 , wherein the composite matrix is YScB.11. The composite matrix of claim 1 , wherein the composite matrix is ZrGdB.12. The composite matrix of claim 1 , wherein the composite matrix is ZrSmB.13. The composite matrix of claim 1 , wherein the composite matrix is ZrNdB.14. The composite matrix of claim 1 , wherein the composite matrix is ZrPrB.16. The composite matrix of claim 15 , wherein the composite matrix is YGdB claim 15 , ScGdB claim 15 , YSmB claim 15 , ScSmB claim 15 , YNdB claim 15 , ScNdB claim 15 , YPrB claim 15 , ScPrB claim 15 , ZrTbB claim 15 , YTbB claim 15 , ScTbB claim 15 , ZrDyB claim 15 , YDyB claim 15 , ScDyB claim 15 , ZrHoB claim 15 , YHoB claim ...

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Номер записи: 49
07-03-2019 дата публикации

Flow Guiding Device for a Fan

Номер: US20190072107A1
Автор: Horng Alex, LIN Cheng-Wei, Yin Tso-Kuo
Принадлежит:

A flow guiding device includes a flow-guiding member and a blade. The flow-guiding member includes a flow-guiding portion, a neck portion and a first coupling portion. The flow-guiding portion is connected to a first end of the neck portion. The first coupling portion is located at a second end of the neck portion. The flow-guiding portion, the neck portion and the first coupling portion are connected in series in a radial direction. The blade includes a second coupling portion at a free end of the blade. The second coupling portion is coupled with the first coupling portion. The flow-guiding portion has a cross-sectional area smaller than or equal to a cross-sectional area of the blade. A cross-sectional area of the neck portion viewed from the radial direction at the first end is smaller than a cross-sectional area of the neck portion viewed from the radial direction at the second end. 1. A flow guiding device comprising:a flow-guiding member including a flow-guiding portion, a neck portion and a first coupling portion, wherein the flow-guiding portion is connected to a first end of the neck portion, wherein the first coupling portion is located at a second end of the neck portion, and wherein the flow-guiding portion, the neck portion and the first coupling portion are connected in series in a radial direction; anda blade including a second coupling portion at a free end of the blade, wherein the second coupling portion is coupled with the first coupling portion, wherein the flow-guiding portion has a cross-sectional area perpendicular to the radial direction smaller than or equal to a cross-sectional area of the blade perpendicular to the radial direction, and wherein a cross-sectional area of the neck portion perpendicular to the radial direction at the first end is smaller than a cross-sectional area of the neck portion perpendicular to the radial direction at the second end.2. The flow guiding device as claimed in claim 1 , wherein the cross-sectional area of ...

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Номер записи: 50
05-03-2020 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

Номер: US20200074044A1
Автор: CHEN Chih-Liang, CHEN Shun Li, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, Young Charles Chew-Yuen, Zhuang Hui-Zhong
Принадлежит:

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules. 1. A system for designing an integrated circuit , the system comprises:a non-transitory computer readable medium configured to store executable instructions; anda processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction;', 'placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns;', 'placing a first conductive feature layout pattern on a second layout level different from the first layout ...

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Номер записи: 51
18-03-2021 дата публикации

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20210083668A1
Автор: Chuang Cheng-Chi, Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit includes a first and a second active region, a first contact, a second contact and a first insulating layer. The first active region is in a substrate, extends in a first direction, and is located on a first level. The second active region is in the substrate, extends in the first direction, is located on the first level, and is separated from the first active region in a second direction. The first contact is coupled to the first and the second active region, extends in the second direction, is located on a second level, and overlaps the first and the second active region. The second contact extends in the second direction, overlaps the first contact, and is located on a third level. The first insulating layer extends in the second direction, and is between the second contact and the first contact. 1. An integrated circuit comprising:a first active region in a substrate, extending in a first direction, and being located on a first level;a second active region in the substrate, extending in the first direction, being located on the first level, and being separated from the first active region in a second direction different from the first direction;a first contact coupled to the first active region and the second active region, extending in the second direction, being located on a second level different from the first level, and overlapping the first active region and the second active region;a second contact extending in the second direction, overlapping the first contact, being located on a third level different from the first level and the second level; anda first insulating layer extending in the second direction, and being between the second contact and the first contact.2. The integrated circuit of claim 1 , wherein the first contact overlaps the first active region.3. The integrated circuit of claim 1 , further comprising:a third active region in the substrate, extending in the first direction, being located on the first level, and being ...

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Номер записи: 52
12-03-2020 дата публикации

STRUCTURE AND APPARATUS FOR TIRE PRESSURE MONITORING

Номер: US20200079160A1
Автор: Chiu Po-Wei, Hsiao Chien-Jen, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

An apparatus for tire pressure monitoring comprises a case, a gas nozzle unit movably connected to the outside of the case, and a structure for tire pressure monitoring which is received in a receiving space in the case. The structure for tire pressure monitoring comprises a main body, a signal processing unit, a sensing unit connected to the signal processing unit, and a power unit to provide power. The main body has a first part and a second part. The first part is disposed on a top side of the second part; the first and the second parts are not on the same plane. The signal processing unit and the sensing unit are disposed on one side of the first part and on the top side of the second part, respectively. The power unit is disposed on a bottom side of the second part. 1. A structure for tire pressure monitoring , comprising:a main body having a first part and a second part, wherein the first part is disposed on a top side of the second part, wherein the first part and the second part are not on the same plane;a signal processing unit disposed at one side of the first part of the main body, wherein the signal processing unit is provided with a wireless emitter, a processing unit connected to the wireless emitter, and a first circuit board, wherein the wireless emitter and the processing unit are disposed on one side of the first circuit board;a sensing unit disposed on the top side of the second part of the main body, wherein the sensing unit is provided with at least one sensor and a second circuit board, wherein the at least one sensor is disposed on one side of the second circuit board and connected to the processing unit disposed on the first circuit board; anda power unit disposed on a bottom side of the second part corresponding to the sensing unit, wherein the power unit is connected to the signal processing unit and the sensing unit to provide power.2. The structure for tire pressure monitoring according to claim 1 , further comprising a first encapsulant ...

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Номер записи: 53
31-03-2022 дата публикации

TRAFFIC STATUS DISPLAY SYSTEM AND RELATED DISPLAY METHOD

Номер: US20220101720A1
Автор: Huang Chia-Hsien, LIN Cheng-Wei
Принадлежит:

A traffic status display system for displaying a traffic status display picture is disclosed. The traffic status display picture includes a map information including a plurality of intersection traffic statuses, wherein each intersection traffic status of the plurality of intersection traffic statuses includes a traffic light status display picture configured to display a traffic light status of each sub-intersection of an intersection; and a traffic turning vector display picture, configured to display a flow-out table and a flow-in table of the intersection according to a vehicle traffic data. 1. A traffic status display system , for displaying a traffic status display picture , wherein the traffic status display picture comprises:{'claim-text': ['a traffic light status display picture, configured to display a traffic light status of each sub-intersection of an intersection; and', 'a traffic turning vector display picture, configured to display a flow-out table and a flow-in table of the intersection according to a vehicle traffic data.'], '#text': 'a map information, including a plurality of intersection traffic statuses, wherein each intersection traffic status of the plurality of intersection traffic statuses comprises:'}2. The traffic status display system of claim 1 , wherein the traffic light status display picture of each intersection traffic status of the plurality of intersection traffic statuses is determined according to a corresponding real-time traffic phase and a corresponding default traffic phase claim 1 , and the default traffic phase is obtained from a database claim 1 , wherein the traffic light status display picture includes different combinations of traffic phases of each sub-intersection.3. The traffic status display system of claim 1 , wherein each sub-intersection has an increasing number claim 1 , when a cardinal direction of four cardinal directions has a plurality of sub-intersections claim 1 , remainders of the increasing numbers ...

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Номер записи: 54
25-03-2021 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20210091000A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Hui-Ting
Принадлежит:

A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor;forming a plurality of first contact vias connected to a part of the gate strips;forming a plurality of first metal strips above the plurality of gate strips, wherein the plurality of first metal strips are co-planar, and each first metal strip and one of the gate strips are crisscrossed from top view;connecting one of the first metal strips to one of the first contact vias;forming a plurality of second contact vias above a part of the first metal strips excluding said one of the first metal strips; andforming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view;wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half ...

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Номер записи: 55
05-04-2018 дата публикации

MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL

Номер: US20180096930A1
Автор: CHEN Chih-Liang, LIN WEI-CHENG, SHEN Meng-Hung, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method is disclosed that includes disposing a first conductive metal segment; disposing a second conductive metal segment over an active area; disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment; disposing a first conductive via on the first conductive metal segment; and disposing a first conductive line coupled to the first conductive metal segment through the first conductive via. 1. A method comprising:disposing a first conductive metal segment;disposing a second conductive metal segment over an active area;disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment;disposing a first conductive via on the first conductive metal segment; anddisposing a first conductive line coupled to the first conductive metal segment through the first conductive via.2. The method of claim 1 , further comprising:disposing a second conductive via on the second conductive metal segment, wherein the conductive line is coupled to the second conductive via.3. The method of claim 1 , further comprising:disposing a gate over the active area, under the local conductive segment, and between the first conductive metal segment and the second conductive metal segment.4. The method of claim 3 , wherein a height of the local conductive segment plus a height of the gate is substantially equal to a height of the second conductive metal segment.5. The method of claim 1 , wherein a height of the first conductive metal segment is greater than a height of the second conductive metal segment.6. The method of claim 1 , further comprising:disposing an isolation segment over the second conductive metal segment for isolating the conductive line from a second conductive line.7. The method of claim 1 , wherein a length of the second conductive metal segment is shorter than a length of the first conductive metal segment.8. A method comprising:disposing a first conductive ...

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Номер записи: 56
01-04-2021 дата публикации

Double rule integrated circuit layouts for a dual transmission gate

Номер: US20210098453A1
Автор: Hui-Zhong ZHUANG, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

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Номер записи: 57
01-04-2021 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20210098482A1
Автор: LIN Cheng-Wei, LIU Kuan-Cheng, Liu Kuang-Wen
Принадлежит:

A semiconductor structure includes a substrate, at least one first conductive structure, at least one second conductive structure, at least one first memory structure, and at least one second memory structure. The substrate has an array region and a dummy region. The first conductive structure is disposed on the array region. The second conductive structure is disposed on the dummy region. The first memory structure is disposed on the first conductive structure. The first memory structure includes a first channel layer, and the first channel layer is in contact with the first conductive structure. The second memory structure is disposed on the second conductive structure. The second memory structure includes a second channel layer, and the second channel layer is isolated from the second conductive structure. 1. A semiconductor structure , comprising:a substrate having an array region and a dummy region;at least one first conductive structure disposed on the array region;at least one second conductive structure disposed on the dummy region;at least one first memory structure disposed on the first conductive structure, wherein the first memory structure comprises a first channel layer, and the first channel layer is in contact with the first conductive structure; andat least one second memory structure disposed on the second conductive structure, wherein the second memory structure comprises a second channel layer, and the second channel layer is isolated from the second conductive structure.2. The semiconductor structure of claim 1 , wherein a number of the first memory structure is plural claim 1 , and a number of the second memory structure is plural claim 1 , and a distribution density of the first memory structures is higher than a distribution density of the second memory structures.3. The semiconductor structure of claim 1 , further comprising:a dielectric layer disposed on the substrate; anda plurality of conductive layers embedded in the dielectric layer, ...

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Номер записи: 58
12-05-2022 дата публикации

ROUTING-RESOURCE-IMPROVING METHOD OF GENERATING LAYOUT DIAGRAM, SYSTEM FOR SAME AND SEMICONDUCTOR DEVICE

Номер: US20220147688A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Jay
Принадлежит:

A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram. 1. A method of manufacturing a semiconductor device , the method comprising: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern);', 'determining that the candidate pattern satisfies one or more criteria; and', 'increasing a size of the candidate pattern thereby revising the layout diagram., 'generating the layout diagram including, 'for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device,'}2. The method of claim 1 , wherein:the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device;a cell of the layout diagram is organized into MD-columns, the MD-columns extending in a first direction; determining that a first metal-to-drain/source (MD) pattern in the transistor level is located in the first MD ...

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Номер записи: 59
14-04-2016 дата публикации

Gap Compensation Mechanism for Self Adaptive Posture Adjustment

Номер: US20160103293A1
Автор: CHANG Shenq-Tsong, HUANG Ting-Ming, LIN WEI-CHENG, Pan Hsu-Pin, Tseng Shih-Feng
Принадлежит:

A gap compensation mechanism capable of self adaptive posture adjustment is disclosed, which comprises a base seat, having at least a fixation portion disposed thereon, the fixation portion having a flow path area disposed peripheral thereto; at least an adjustment unit, sleeved onto an outer rim of the fixation portion; and a filler, being filled within the flow path area. As such, a workpiece to be fixed may be disposed on a face of an adjustment unit. Further, the adjustment unit provides at least three freedoms for the altitude and two axial inclinations for self adaptively compensating a gap with any geometrical shapes and thus further adjusting the posture of the combined workpiece. After all the adjustments, a filler is filled to reinforce the structure and finally a fixation unit is employed for locking and fixing. 1. A gap compensation mechanism capable of self adaptive posture adjustment , comprising:a base seat, having at least a fixation portion disposed thereon, the fixation portion having a flow path area disposed peripheral thereto;at least an adjustment unit, sleeved onto an outer rim of the fixation portion; anda filler, being filled within the flow path area.2. The gap compensation mechanism capable of self adaptive posture adjustment as claimed in claim 1 , wherein the fixation portion is a threaded sleeve.3. The gap compensation mechanism capable of self adaptive posture adjustment as claimed in claim 1 , wherein the adjustment unit comprises a resilient element claim 1 , a stacker disposed on the resilient element claim 1 , and an adjustment element disposed on the stacker.4. The gap compensation mechanism capable of self adaptive posture adjustment as claimed in claim 3 , wherein the resilient element includes a compression spring claim 3 , a disk-like spring claim 3 , and a wave-like spring.5. The gap compensation mechanism capable of self adaptive posture adjustment as claimed in claim 3 , wherein each of the stacker and the adjustment ...

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Номер записи: 60
28-03-2019 дата публикации

STANDARD CELLS HAVING VIA RAIL AND DEEP VIA STRUCTURES

Номер: US20190096809A1
Автор: CHEN Chih-Liang, Chuang Cheng-Chi, Lai Wayne, LIN WEI-CHENG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines. 1. A semiconductor structure comprising:a plurality of gate structures;a plurality of vias formed in a first dielectric layer, wherein each via of the plurality of vias is formed on each gate structure of the plurality of gate structures;a conductive rail structure formed in the first dielectric layer and over at least one via of the plurality of vias, wherein the conductive rail structure is electrically connected to the at least one via of the plurality of vias;a second dielectric layer formed over the first dielectric layer and the conductive rail structure;a deep via formed at least in the second dielectric layer and over the conductive rail structure, wherein the deep via is electrically connected to the conductive rail structure; anda first plurality of metal lines formed over and electrically connected to the deep via.2. The semiconductor structure of claim 1 , wherein the plurality of gate structures are formed perpendicular to the conductive rail structure.3. The semiconductor structure of claim 1 , wherein the plurality of gate structures are gate structures of transistor devices.4. The semiconductor structure of claim 3 , wherein the transistor devices comprise a fin field-effect transistor.5. The semiconductor structure of further comprising a second plurality of metal lines formed above the conductive rail structure and in parallel with the conductive rail structure.6. The semiconductor structure of claim 5 , wherein the second plurality of metal ...

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Номер записи: 61
28-03-2019 дата публикации

LOCAL INTERCONNECT STRUCTURE

Номер: US20190096909A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, Chuang Cheng-Chi, Lai Chih-Ming, LAI Wei-An, LIN WEI-CHENG, Liu Ru-Gun, TZENG JIANN-TYNG, WU Chia-Tien, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures. 1. An apparatus comprising:a transistor with a gate terminal, a first source/drain terminal coupled to a reference metal line, and a second source/drain terminal;a local interconnect structure coupled to the gate terminal and routed at a same interconnect level as the reference metal line;a first interconnect structure coupled to the first source/drain terminal and routed above the local interconnect structure; anda second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure.2. The apparatus of claim 1 , further comprising:an other transistor with an other gate terminal, a third source/drain terminal coupled to an other reference metal line, and a fourth source/drain terminal, wherein the local interconnect structure is coupled to the gate terminal and the other gate terminal;a third interconnect structure coupled to the third source/drain terminal and routed above the local interconnect structure and at the same interconnect level as the first and second ...

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Номер записи: 62
12-04-2018 дата публикации

LIQUID CRYSTAL MODULE WITH FINGERPRINT IDENTIFICATION FUNCTION

Номер: US20180101039A1
Автор: Hsiao Chien-Jen, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

A liquid crystal module with fingerprint identification function includes an array glass substrate, a colored light filtering glass substrate, a liquid crystal material layer, a pixel display layer and a detection wire and sensation electrode layer. The liquid crystal material layer, the pixel display layer and the detection wire and sensation electrode layer are disposed between the array glass substrate and the colored light filtering glass substrate. The pixel display layer cooperates with the internal wiring and electrode structures of the detection wire and sensation electrode layer to achieve complex functions of displaying, fingerprint detection/identification and touch control. 1. A liquid crystal module with fingerprint identification function , comprising:an array glass substrate having a first face and a second face, the first and second faces being oppositely positioned on upper and lower faces of the array glass substrate;a colored light filtering glass substrate having a third face and a fourth face, the third face corresponding to the second face;a liquid crystal material layer disposed between the array glass substrate and the colored light filtering glass substrate;a pixel display layer disposed on the second face of the array glass substrate, the pixel display layer having multiple scanning wires, multiple common signal wires and multiple thin-film transistors, the scanning wires and the common signal wires together defining multiple display blocks, the thin-film transistors being respectively disposed in the display blocks, the thin-film transistors being selectively electrically connected to the scanning wires and the common signal wires;a detection wire and sensation electrode layer having multiple detection wires and multiple sensation electrodes, the detection wire and sensation electrode layer being overlaid on the pixel display layer in parallel to the scanning wires, the sensation electrodes being electrically connected to the detection ...

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Номер записи: 63
12-04-2018 дата публикации

Liquid crystal device with fingerprint identification function

Номер: US20180101714A1
Автор: Chien-Jen Hsiao, Shih-Hsiu Tseng, Wei-Cheng Lin
Принадлежит: Keycore Technology Corp

A liquid crystal device with fingerprint identification function includes an array glass substrate, a colored light filtering glass substrate, an organic light-emitting layer, a pixel display layer and a detection wire and sensation electrode layer. The organic light-emitting layer, the pixel display layer and the detection wire and sensation electrode layer are disposed between the array glass substrate and the colored light filtering glass substrate. The pixel display layer cooperates with the internal wiring and electrode structures of the detection wire and sensation electrode layer to achieve complex functions of displaying, fingerprint detection/identification and touch control.

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Номер записи: 64
03-07-2014 дата публикации

FALL DETECTION AND PROTECTION SYSTEM AND METHOD

Номер: US20140184382A1
Автор: LIN Cheng-Wei, Yang Bing-Shiang
Принадлежит: NATIONAL CHIAO TUNG UNIVERSITY

The invention provides a fall detection and protection system and method. The fall detection and protection system includes a guarding device to be worn on a user, and a portable device having a pre-determined threshold value stored therein for detecting an activity of a user to acquire an activity status value, which is to be compared with the threshold value so as to detect and determine whether the user falls. When a fall is detected, the portable device transmits a triggering signal to the guarding device to activate the guarding function of the guarding device, thereby preventing the user from injury caused by the impact and collision of a fall. 1. A fall detection and protection system , comprising:a guarding device capable of being worn on a user and having a guarding function for reducing impact upon falling; and a detecting unit for detecting an activity of the user to obtain an activity status value;', 'a comparison unit for comparing the activity status value with a pre-determined threshold value to detect and determine a status of the user; and', 'a triggering unit for transmitting a triggering signal to the guarding device to activate the guarding function when the status of the user indicates a fall., 'a portable device, comprising2. The fall detection and protection system of claim 1 , wherein the detecting unit includes an accelerometer or a gyro.3. The fall detection and protection system of claim 1 , wherein the activity status value includes an acceleration value claim 1 , an angular velocity value claim 1 , or a calculation value resulting from one of the acceleration value and the angular velocity value.4. The fall detection and protection system of claim 1 , wherein the guarding device further comprises a plurality of guarding units claim 1 , and the triggering unit transmits a respective triggering signal to each of the guarding units to activate the guarding function.5. The fall detection and protection system of claim 1 , wherein the pre- ...

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Номер записи: 65
30-04-2015 дата публикации

ILLUMINATING VENTILATOR

Номер: US20150117034A1
Автор: Chen Chien-Chih, Horng Alex, LIN Cheng-Wei, Wu Shih-Ting
Принадлежит:

An illuminating ventilator including a fan, a connecting frame, a lamp seat and a cover is provided. The fan has a housing and a fan wheel, wherein the housing has a first coupling portion, an inlet, an outlet and an inner space communicating with said inlet and outlet, and the fan wheel is received in the inner space. The connecting frame couples with the housing and has an opening in alignment with the inlet of the housing, wherein the connecting frame has a second coupling portion coupling with the first coupling portion of the housing. The lamp seat is mounted on one of the connecting frame and housing and has a receiving portion for receiving a lamp. The cover is coupled with the connecting frame and has a plurality of apertures communicating with the opening. 1. An illuminating ventilator , comprising:a fan having a housing and a fan wheel, wherein the housing has a first coupling portion, an inlet, an outlet and an inner space communicating with said inlet and outlet, and the fan wheel is received in the inner space;a connecting frame coupling with the housing and having an opening in alignment with the inlet of the housing, wherein the connecting frame has a second coupling portion coupling with the first coupling portion of the housing;a lamp seat mounted on one of the connecting frame and the housing and having a receiving portion for receiving a lamp; anda cover coupled with the connecting frame and having a plurality of apertures communicating with the opening.2. The illuminating ventilator as claimed in claim 1 , wherein the lamp seat is mounted on a surface of the connecting frame claim 1 , said surface faces away from the housing and is close to the opening claim 1 , the receiving portion is formed on a side of the connecting frame claim 1 , and said side is away from the housing.3. The illuminating ventilator as claimed in claim 1 , wherein the lamp seat is mounted on a surface of the housing and extends through the opening of the connecting frame ...

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Номер записи: 66
02-04-2020 дата публикации

Method and structure to reduce cell width in integrated circuits

Номер: US20200104445A1
Автор: Chih-Ming Lai, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit includes an active zone extending in a first direction, and a spacer extending in a second direction perpendicular to the first direction. The spacer protrudes into a substrate and divides the active zone into a first part and a second part. The integrated circuit includes a first conductive segment and a second conductive segment each extending in the second direction and in a middle layer between the substrate and a metal layer. The first conductive segment forms conductive contact with an active region of a first transistor in the first part of the active zone, and the second conductive segment forms conductive contact with an active region of the second transistor in the second part of the active zone. The spacer joins the first conductive segment and the second conductive segment while electrically isolating the first conductive segment from the second conductive segment.

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Номер записи: 67
02-04-2020 дата публикации

ROUTING-RESOURCE-IMPROVING METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME

Номер: US20200104447A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Jay
Принадлежит:

A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram. 1. A method of manufacturing a semiconductor device , the method comprising: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern);', 'determining that the candidate pattern satisfies one or more criteria; and', 'at least reducing a size of the candidate pattern thereby revising the layout diagram., 'generating the layout diagram including, 'for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including first and overlying second levels (corresponding M_1st and M_2nd levels) of metallization and a first level (VIA_1st level) of interconnection therebetween corresponding to first and overlying second layers of metallization and a first layer of interconnection therebetween in the semiconductor device,'}2. The method of claim 1 , wherein:the layout diagram includes first and overlying second levels (corresponding M_1st and M_2nd levels) of metallization and a first level (VIA_1st level) of interconnection therebetween corresponding to first and overlying second layers of metallization and a first layer of interconnection therebetween in the semiconductor device; andthe candidate pattern is the first M_2nd pattern; determining that the first M_2nd pattern is designated ...

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Номер записи: 68
02-04-2020 дата публикации

SEMICONDUCTOR STRUCTURE, DEVICE, AND METHOD

Номер: US20200104460A1
Автор: LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG
Принадлежит:

A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction. 1. A structure comprising:a first conductive segment and a second conductive segment, in a first conductive layer, configured as a first terminal and a second terminal of a first transistor of a first type;a third conductive segment and a fourth conductive segment, in a second conductive layer stacked over the first conductive layer, configured as a first terminal and a second terminal of a second transistor of a second type; anda first gate arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments, the first gate configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and', 'the second conductive segment is offset from the fourth conductive segment along the first direction., 'wherein'}2. The structure of claim 1 , wherein the third conductive segment partially overlies the first conductive segment claim 1 , and the fourth conductive segment partially ...

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Номер записи: 69
02-04-2020 дата публикации

CONTACT STRUCTURE, METHOD, LAYOUT, AND SYSTEM

Номер: US20200105660A1
Автор: Chuang Cheng-Chi, Lai Chih-Ming, LIN WEI-CHENG, Sio Kam-Tou, TZENG JIANN-TYNG, YUAN Lipen
Принадлежит:

An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction. 1. An integrated circuit (IC) structure comprising:a fin structure;a contact overlying the fin structure along a first direction; andan isolation layer between the contact and the fin structure,wherein the isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.2. The IC structure of claim 1 , whereinthe fin structure is a first fin structure,the IC structure further comprises a second fin structure, andthe contact overlies and is electrically connected to the second fin structure.3. The IC structure of claim 2 , whereinthe first fin structure comprises a first type of semiconductor material, andthe second fin structure comprises a second type of semiconductor material different from the first type.4. The IC structure of claim 1 , further comprising a via overlying the contact and the isolation layer claim 1 , wherein the via is electrically connected to the contact.5. The IC structure of claim 4 , further comprising:a first metal segment overlying and electrically connected to the via;a second metal segment overlying the contact and another fin structure underlying the contact; andan inter-level dielectric (ILD) layer between the second metal segment and the contact,wherein the first metal segment and the second metal segment are part of a same metal layer.6. The IC structure of claim 5 , whereinthe first metal segment and the second metal segment are positioned between a first power rail and a second power rail in the same metal layer,the first metal segment and the second metal segment have approximately a same width w,a separation between the first metal segment and the first power rail and a separation between ...

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Номер записи: 70
02-04-2020 дата публикации

HYBRID POWER RAIL STRUCTURE

Номер: US20200105671A1
Автор: LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail. 1. An integrated circuit structure comprising:a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side;a first power rail extending in a first direction, being embedded in the front side of the substrate and configured to provide a first supply voltage;a second power rail configured to provide a second supply voltage different from the first supply voltage, the second power rail extending in the first direction, being embedded in the front side of the substrate and being separated from the first power rail in a second direction different from the first direction;a first device positioned between the first power rail and the second power rail, and located on the front side of the substrate; anda first via structure extending to the back side of the substrate and being electrically coupled to the second power rail.2. The integrated circuit of claim 1 , wherein the first power rail comprises a metal layer positioned on the first device.3. The integrated circuit of claim 1 , wherein the second power rail is a buried power rail.4. The integrated circuit of claim 1 , wherein the first power rail is ...

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Номер записи: 71
03-06-2021 дата публикации

High-Density Semiconductor Device

Номер: US20210166947A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method comprising:depositing a first material on a substrate;depositing on the substrate a second material;depositing a spacer material on the first and second materials;forming a third material on a sidewall of the spacer; andetching the third material on the sidewall of the spacer to expose a portion of the first material.2. The method of claim 1 , wherein the second material has an etch selectivity different from an etch selectivity of the first material3. The method of claim 1 , further comprising converting the third material on the sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.4. The method of claim 3 , wherein converting the third material on the sidewall of the spacer into the fourth material includes implanting ions in the third material on the sidewall of the spacer.5. The method of claim 3 , wherein converting the third material on the sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.6. The method of claim 5 , wherein the tilt angle is between about 30 degrees and about 60 degrees relative to a horizontal axis.7. The method of claim 1 , further comprising removing the exposed portion of the first material to expose a portion of the substrate.8. The method of claim 1 , further comprising etching back the second material to a height of the first material.9. The method of claim 1 , further comprising etching the substrate using a second spacer material as an etch mask to form a ...

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Номер записи: 72
18-05-2017 дата публикации

PROJECTOR AND IMAGE MODULE THEREFOR

Номер: US20170139314A1
Автор: Chen Lu-Hua, Huang Jiun-Woei, LIN WEI-CHENG, Tseng Shih-Feng
Принадлежит: NATIONAL APPLIED RESEARCH LABORATORIES

A projector having a first end and a second end opposite to the first end includes an image source, a mirror and a first lens set. The image source is disposed at the first end, and projects lights of an image along a first direction. The mirror is disposed at the second end along the first direction. The first lens set is disposed between the image source and the mirror, and forms for the lights a common aperture located between the first lens set and the mirror. 1. A projector having a first end and a second end opposite to the first end , comprising:an image source disposed at the first end, and projecting lights of an image along a first direction;a mirror disposed at the second end along the first direction; anda first lens set disposed between the image source and the mirror, and forming for the lights a common aperture located between the first lens set and the mirror.2. The projector as claimed in claim 1 , wherein an intermediate image is formed between the common aperture and the mirror.3. The projector as claimed in claim 2 , wherein the intermediate image has a size larger than that of the image.4. The projector as claimed in claim 1 , wherein the mirror is a concave sinusoidal reflex mirror.5. The projector as claimed in claim 1 , wherein the image source is a telecentric light-emitting element.6. The projector as claimed in claim 1 , further comprising a second lens set disposed between the common aperture and the intermediated image.7. The projector as claimed in claim 7 , wherein the second lens set includes a plurality of spherical lenses.8. The projector as claimed in claim 8 , wherein the first lens set includes a plurality of spherical lenses.9. An imaging module used in a projector for projecting lights of an image from an image source claim 8 , comprising:a first lens set having an incident side and an exit side, and forming for the lights at the incident side a common aperture at the exit side; anda concave mirror configured to face the exit ...

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Номер записи: 73
30-04-2020 дата публикации

METAL WITH BURIED POWER FOR INCREASED IC DEVICE DENSITY

Номер: US20200134128A1
Автор: Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Hui-Ting
Принадлежит:

A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track. 120-. (canceled)21. A device comprising:a double-height cell having routing tracks in a first layer of metallization on an insulating layer, the double-height cell having two sides extending in a first direction and separated by the double-height cell in a second direction perpendicular to the first direction, wherein a first routing track has a first run-side extending in the first direction along the first side of the double-height cell, and a second routing track has a second run-side extending in the first direction along the second side of the double-height cell;a via connection in the insulating layer that connects a terminal of a transistor to one of the routing tracks on the insulating layer, wherein the terminal of the transistor includes one of a gate, a source, or drain of the transistor;a first buried power line, extending in the first direction, underneath the insulating layer, and aligned with the first run-side of the first routing track in the double-height cell;a second buried power line, extending in the first direction, underneath the insulating ...

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Номер записи: 74
30-04-2020 дата публикации

Line space, routing and patterning methodology

Номер: US20200135637A1
Автор: Chih-Ming Lai, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX- 1 ) having a first metal pattern pitch (MX- 1 P ); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreX P ) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.

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Номер записи: 75
30-04-2020 дата публикации

INTEGRATED CIRCUIT INCLUDING SUPERVIA AND METHOD OF MAKING

Номер: US20200135640A1
Автор: LIN WEI-CHENG, Sio Kam-Tou, TZENG JIANN-TYNG
Принадлежит:

An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line. 1. An integrated circuit comprising:a substrate;a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate;a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance;a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance; anda supervia directly connected to the first conductive line and the third conductive line.2. The integrated circuit of claim 1 , wherein the supervia has a uniform tapered profile.3. The integrated circuit of claim 1 , wherein the supervia has a varied tapered profile.4. The integrated circuit of claim 1 , further comprising a fourth conductive line extending in the ...

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Номер записи: 76
30-04-2020 дата публикации

Double rule integrated circuit layouts for a dual transmission gate

Номер: US20200135732A1
Автор: Hui-Zhong ZHUANG, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Shih-Wei Peng, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

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Номер записи: 77
24-05-2018 дата публикации

Fingerprint identification module

Номер: US20180144180A1
Автор: Chien-Jen Hsiao, Shih-Hsiu Tseng, Wei-Cheng Lin
Принадлежит: Keycore Technology Corp

A fingerprint identification module includes a substrate and multiple fingerprint sensation units. The substrate has a first face and a second face. The fingerprint sensation units are disposed on the second face of the substrate. Each fingerprint sensation unit has a substrate layer. The substrate layer has a first surface, a second surface, a sensation layer and a control IC. The sensation layer is disposed on the first surface. The control IC is selectively disposed on the first surface or the second surface. The fingerprint identification module improves the shortcomings that it is uneasy to manufacture large-scale palm print identification module and the manufacturing cost of the large-scale palm print identification module is too high.

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Номер записи: 78
25-05-2017 дата публикации

FINGERPRINT IDENTIFICATION UNIT

Номер: US20170147848A1
Автор: Hsiao Chien-Jen, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

A fingerprint identification unit is directly integrated into a touch panel, a Color Filter (CF), a Thin-Film Transistor (TFT), or a Liquid Crystal Module (LCM) to largely increase the identified sensitivity to solve the problem of the conventional fingerprint identification unit that is required to form on a silicon wafer first. 1. A fingerprint identification unit formed on a base , which having a top and a bottom side , comprising:a first coating layer disposed either on the top side or on the bottom side of the base;a first fingerprint identification electrode layer disposed on one side of the first coating layer opposite to the base and having a plurality of first fingerprint identification electrodes;a second coating layer covering the first fingerprint identification electrode layer;a second fingerprint identification electrode layer disposed on one side of the second coating layer opposite to the first fingerprint identification electrode layer having a plurality of second fingerprint identification electrodes;a conductor layer having a plurality of metal conductors, which are selectively electrically connected to the first and the second fingerprint identification electrode layer; anda third coating layer covering the second fingerprint identification electrode layer and part of the conductor layer.2. The fingerprint identification unit as claimed in being a touch panel claim 1 , comprising:{'b': '2311', 'a glass substrate having a first and a second surface; and the first surface defining a touch zone and a non-touch zone, which is located adjacent to the touch zone to surround a periphery of the touch zone;'}a shielding being disposed either on the first or the second surface and located corresponding to the non-touch zonea touch electrode layer being disposed on the second surface of the glass substrate and having a plurality of first and second touch electrodes, which being electrically connected to the first and second touch electrodes;a first ...

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Номер записи: 79
15-09-2022 дата публикации

Variable width nano-sheet field-effect transistor cell structure

Номер: US20220292244A1
Автор: Hui-Zhong ZHUANG, Jiann-Tyng Tzeng, Lipen YUAN, Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Yu-Xuan Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.

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Номер записи: 80
31-05-2018 дата публикации

High-Density Semiconductor Device

Номер: US20180151381A1
Автор: CHEN Chih-Liang, Chen Hsin-Chih, Chou Lei-Chun, Ju Shi Ning, Lai Chih-Ming, LIN WEI-CHENG, LIN Wei-Liang, Liu Ru-Gun, Sio Kam-Tou, Tseng Chin-Yuan, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material. 1. A method of manufacturing a semiconductor device , the method comprising:depositing a first material on a substrate;depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material;depositing a spacer material on the first and second materials; andetching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.2. The method of claim 1 , further comprising:forming a mandrel above the substrate;depositing a second spacer material on a sidewall of the mandrel; andremoving the mandrel, thereby leaving a spacer.3. The method of claim 2 , further comprising forming a third material on a top surface and opposite first and second sidewalls of the spacer.4. The method of claim 3 , further comprising converting the third material on the top surface and the second sidewall of the spacer into a fourth material that has an etch selectivity different from an etch selectivity of the third material.5. The method of claim 4 , wherein converting the third material on the top surface and the second sidewall of the spacer into the fourth material includes implanting ions in the third material on the top surface and the second sidewall of the spacer.6. The method of claim 4 , wherein converting the third material on the top surface and the second sidewall of the spacer into the fourth material includes tilting the semiconductor device at a tilt angle.7. The method of claim 3 , further comprising etching the ...

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Номер записи: 81
31-05-2018 дата публикации

Self Aligned Via and Method for Fabricating the Same

Номер: US20180151432A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, Chuang Cheng-Chi, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, Sio Kam-Tou, TZENG JIANN-TYNG, WU Chia-Tien, Young Charles Chew-Yuen
Принадлежит:

A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal. 1. A method for fabricating a semiconductor device , comprising:depositing a first metal into a first trench of a first dielectric layer such that a top surface of the first metal is below a top surface of the first dielectric layer;depositing a second dielectric layer over the first metal;depositing a third dielectric layer over the first dielectric layer and the second dielectric layer;etching the third dielectric layer to create a second trench that exposes a portion of the first dielectric layer and a portion of the second dielectric layer; andetching the exposed portion of the second dielectric layer to expose a portion of the first metal to create a via to the first metal.2. The method of claim 1 , further comprising depositing a second metal into the second trench such that the second metal is electrically coupled to the first metal.3. The method of claim 1 , wherein a top surface of the second dielectric layer is at substantially the same level as the top surface of the first dielectric layer4. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer have different etching sensitivities.5. The method of claim 1 , wherein the third dielectric ...

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Номер записи: 82
31-05-2018 дата публикации

INTERCONNECT METAL LAYOUT FOR INTEGRATED CIRCUIT

Номер: US20180151567A1
Автор: LIN WEI-CHENG, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes an active region comprising a source/drain region and a plurality of poly strips spaced apart and arranged along a first direction crossing over the active region. The first direction is substantially perpendicular to a lengthwise direction of the active region. A first metal pattern is disposed on the poly strips and arranged along the first direction. A plurality of first interconnect plugs is interposed in between the poly strips and the first metal pattern and in between the active region and the first metal pattern. A position of the first interconnect plugs being variable along the first direction. 1. A semiconductor device , comprising:an active region comprising a source/drain region;a plurality of gates spaced apart and arranged along a first direction which is substantially perpendicular to a lengthwise direction of the active region;a first metal pattern disposed on the gates and comprising a plurality of first metal leads arranged along the first direction, wherein a pitch of two immediately adjacent gates is substantially double a first metal pitch of two immediately adjacent first metal leads; anda plurality of first interconnect plugs interposed in between the gates and the first metal pattern and in between the active region and the first metal pattern.2. The semiconductor device of claim 1 , wherein the plurality of gates comprise a pair of dummy gates that are arranged along the first direction and that define a device cell boundary.3. The semiconductor device of claim 2 , further comprising:a second metal pattern disposed on the first metal pattern along a second direction that is substantially perpendicular to the first direction; anda plurality of second interconnect plugs interposed in between the first metal pattern and the second metal pattern.4. The semiconductor device of claim 3 , wherein the second metal pattern comprises a pair of power straps and a plurality of second metal leads claim 3 , and the second ...

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Номер записи: 83
17-06-2021 дата публикации

STANDARD CELLS HAVING VIA RAIL AND DEEP VIA STRUCTURES

Номер: US20210183772A1
Автор: CHEN Chih-Liang, Chuang Cheng-Chi, Lai Wayne, LIN WEI-CHENG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines. 1. A method for forming a semiconductor structure , comprising:forming a plurality of source/drain (S/D) contact structures;depositing a first conductive material to form first and second via rail structures, wherein at least one of the first and second via rail structures is in physical contact with two or more S/D contact structures of the plurality of S/D contact structures;depositing a second conductive material to form a deep via in physical contact with the second via rail structure;forming a first interconnect line above the first and second via rail structures and in physical contact with the first via rail structure, wherein the first interconnect line is formed in a lowest wiring level; andforming a second interconnect line over and physically connected to the deep via, wherein the second interconnect line is in a second lowest wiring level.2. The method of claim 1 , further comprising depositing a first dielectric layer and etching a plurality of first trenches in the first dielectric layer.3. The method of claim 2 , wherein depositing the first conductive material comprises depositing copper into the plurality of first trenches.4. The method of claim 2 , further comprising depositing a second dielectric layer on the first dielectric layer and etching a second trench in the second dielectric layer.5. The method of claim 4 , wherein depositing the second conductive material comprises depositing copper into the second trench.6. The method of claim 1 ...

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Номер записи: 84
18-06-2015 дата публикации

FLUID MIXING DEVICE

Номер: US20150165404A1
Автор: Ho Mu-Chuan, Li Chien-Hsien, LIN Cheng-Wei, Wu Han-Yu
Принадлежит:

A fluid mixing device includes a double pipe, a feed hopper, and a mixing chamber having a concave disc and a plurality of guide plateguide plates, wherein the double pipe has an inner pipe body, an outer pipe body, and a plurality of stoppers for forming a plurality of channel openings between the inner pipe body and the outer pipe body. The fluid flows through the double pipe and the feed hopper, and then lashes the concave disc in the mixing chamber to achieve a fast and uniform mixing effect. 1. A fluid mixing device , comprising: an inner pipe body having a first inlet and an opposing first outlet;', 'an outer pipe body surrounding the inner pipe body, and having a second inlet and an opposing second outlet; and', 'a plurality of stoppers disposed between the inner pipe body and the outer pipe body to form a plurality of channels between the inner pipe body and the outer pipe body;, 'a double pipe comprising a funnel-shaped channel; and', 'a third inlet and an opposing third outlet, wherein the third outlet is positioned at a bottom of the funnel-shaped channel, and corresponding in position to the first outlet and the second outlet of the double pipe; and, 'a feed hopper for housing the double pipe, having a concave disc positioned below the third outlet,', 'a plurality of guide plates surrounding the concave disc, wherein an included angle formed between a surface of each of the guide plates and the radial direction of the concave disc ranges from 0° to 75°., 'a mixing chamber disposed below the funnel-shaped channel and having2. The fluid mixing device of claim i the outer pipe body is a half-fusiform pipe body.3. The fluid mixing device of claim 1 , wherein a cross-sectional area of the second outlet of the outer pipe body is smaller than that of the second inlet.4. The fluid mixing device of claim 1 , wherein the included angle formed between the surface of each of the guide plates and the radial direction of the concave disc ranges from 30° to 60°.5. The ...

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Номер записи: 85
08-06-2017 дата публикации

TOUCH DEVICE WITH FINGERPRINT IDENTIFICATION FUNCTION

Номер: US20170161535A1
Автор: Hsiao Chien-Jen, LIN WEI-CHENG, Tseng Shih-Hsiu
Принадлежит:

A touch device with fingerprint identification function includes a touch unit and a fingerprint identification unit. The touch unit has a touch section and a non-touch section. The non-touch section is disposed around the touch section in adjacency to the touch section. The fingerprint identification unit is disposed on the non-touch section of the touch unit. The fingerprint identification unit is integrated with the touch unit. Therefore, it is unnecessary to additionally form a perforation or a channel on the touch device for arranging the fingerprint identification unit as in the conventional touch device. In this case, the structural strength of the touch device will not be deteriorated. Also, the manufacturing cost can be lowered. 1. A touch device with fingerprint identification function , comprising:a touch unit defined with a touch section and a non-touch section, the non-touch section being disposed around the touch section in adjacency to the touch section, the touch unit having:a first substrate having a first surface and a second surface, the first surface being a plane face or a curved face;a shield layer selectively disposed on the non-touch section of the first surface or the second surface;a second substrate having a third surface and a fourth surface;a touch electrode layer disposed on the touch section of the third surface of the second substrate, the touch electrode layer having multiple first touch electrodes and multiple second touch electrodes and multiple metal wires, the first and second touch electrodes being electrically connected with the metal wires;an optical adhesive layer disposed between the first and second substrates; anda flexible circuit board having multiple circuit wires and a touch chip, the circuit wires being electrically connected with the touch chip and the metal wires, the flexible circuit board being selectively disposed on the third surface or the fourth surface of the second substrate; anda fingerprint identification ...

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Номер записи: 86
15-06-2017 дата публикации

WHEEL RIM AND METHOD OF MANUFACTURING THE SAME

Номер: US20170166005A1
Автор: HSU CHE-WEI, LIN WEI-CHENG
Принадлежит:

A wheel rim includes a rim body, two firm tracks, and a plurality of hollow anti-thermal unit. The two firm tracks were mounted on two sides of the rim body, and these hollow anti-thermal units are spread in two firm tracks. The hollow anti-thermal unit can reduce transfer rate of the thermal when braking a car. 1. A wheel disposed between two corresponding braking elements , comprising:a rim body adopting a carbon fiber composite material;two firm tracks opposite to each other and exposedly mounted on two sides of the rim body, wherein the two firm tracks respectively correspond to the two braking elements; anda plurality of hollow anti-thermal units spread in the two firm tracks.2. The wheel rim of claim 1 , wherein the hollow anti-thermal units are hollow glass balls or hollow ceramic balls.3. The wheel rim of claim 2 , wherein an average particle diameter of the hollow anti-thermal units ranges from 20 μm to 50 μm.4. The wheel rim of claim 1 , wherein the hollow anti-thermal units are hollow soda lime borosilicate glass balls.5. A wheel rim disposed between two corresponding braking elements claim 1 , comprising:a rim body adopting a carbon fiber composite material formed integrally; anda plurality of hollow anti-thermal units spread in two surfaces of the rim body corresponding to the two braking elements.6. The wheel rim of claim 5 , wherein the hollow anti-thermal units are hollow glass balls or hollow ceramic balls.7. The wheel rim of claim 5 , wherein the hollow anti-thermal units are hollow soda lime borosilicate glass balls.8. The wheel rim of claim 7 , wherein an average particle diameter of the hollow anti-thermal units ranges from 20 μm to 50 μm.9. A method of manufacturing the wheel rim as in any one of claim 1 , comprising:adding the plurality of hollow anti-thermal units to a macromolecule material and sufficiently mixing to spread the hollow anti-thermal units in the macromolecule material;mixing with a carbon fiber material to become a carbon ...

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Номер записи: 87
14-06-2018 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SAME

Номер: US20180166431A1
Автор: Lai Chih-Ming, LIN WEI-CHENG, PENG SHIH-WEI, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip. 1. A semiconductor device , comprising:at least one first gate strip;at least one second gate strip, wherein an end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other;at least one first conductive line over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip; andat least one first conductive via connecting the at least one first conductive line and the at least one first gate strip.2. The semiconductor device of claim 1 , further comprising:at least one second conductive via connecting the at least one first conductive line and the at least one second gate strip.3. The semiconductor device of claim 1 , wherein a lengthwise direction of the at least one first conductive line is substantially parallel with a lengthwise direction of the at least one first gate strip.4. The semiconductor device of claim 3 , wherein a lengthwise direction of the at least one first conductive line is substantially parallel with a lengthwise direction of the at least one second gate strip.5. The semiconductor device of claim 1 , further comprising:at least one second conductive line over the at least one first ...

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Номер записи: 88
30-05-2019 дата публикации

SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD

Номер: US20190164882A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, LIOU CHUN-HUNG, Liu Jack, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, YOUNG CHEW-YUEN
Принадлежит:

A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail. 1. A semiconductor device , comprising:a substrate;a dielectric region situated on the substrate;a plurality of conductive regions situated on the dielectric region;a first conductive rail situated within the dielectric region, the first conductive rail being electrically connected to a first conductive region of the plurality of conductive regions; anda conductive structure penetrating through the substrate and formed under the first conductive rail, the conductive structure being electrically connected to the first conductive rail.2. The semiconductor device of claim 1 , the conductive structure comprises a conductive through-substrate via.3. The semiconductor device of claim 1 , further comprising:a power grid conductor situated under the substrate, the power grid conductor being electrically connected to the conductive structure.4. The semiconductor device of claim 3 , further comprising:a metal pad situated between the substrate and the power grid conductor, the metal pad configured to electrically connect the power grid conductor to the substrate.5. The semiconductor device of claim 1 , further comprising:a fin structure protruding from the substrate and the dielectric region and contacting the conductive structure.6. The semiconductor device of claim 5 , further comprising:a second conductive rail situated within the dielectric ...

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Номер записи: 89
30-05-2019 дата публикации

Middle-end-of-line strap for standard cell

Номер: US20190164883A1
Автор: Charles Chew-Yuen Young, Chih-Liang Chen, Jiann-Tyng Tzeng, Kam-Tou SIO, Meng-Hung Shen, Wei-Cheng Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively.

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Номер записи: 90
30-05-2019 дата публикации

METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICES

Номер: US20190165178A1
Автор: CHEN Chih-Liang, Chou Lei-Chun, LIN WEI-CHENG, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, YANG Hui-Ting, Young Charles Chew-Yuen
Принадлежит:

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices. 1. A semiconductor structure comprising:a substrate and an interlayer dielectric layer formed on the substrate;a fin protruding from the substrate and the interlayer dielectric layer;a rail structure formed in the interlayer dielectric layer, wherein the rail structure is opposing a first sidewall of the fin and in parallel with the fin; andfirst and second conductive structures formed around the fin and directly contacting the rail structure.2. The semiconductor structure of claim 1 , further comprises another rail structure formed in the interlayer dielectric layer claim 1 , wherein the another rail structure is opposing a second sidewall of the fin and in parallel with the fin.3. The semiconductor structure of claim 2 , wherein at least one of the first and second conductive structures directly contacts the another rail structure.4. The semiconductor ...

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Номер записи: 91
01-07-2021 дата публикации

METHOD AND DEVICE FOR DETERMINING WHETHER OBJECT INCLUDES DEFECT

Номер: US20210201089A1
Автор: LIN Cheng-Wei
Принадлежит: WISTRON CORPORATION

A method and device for determining whether an object includes a defect are provided. The method includes the following steps. A tested image of a tested object is obtained. Selected good product sample data corresponding to the tested object is obtained. A dissimilarity value between the tested image and the selected good product sample data is calculated by using a dissimilarity model, and whether the tested object is a good product or a defective product is determined according to the dissimilarity value. 1. A method for determining whether an object comprises a defect , comprising:obtaining a tested image of a tested object;obtaining selected good product sample data corresponding to the tested object; andcalculating a dissimilarity value between the tested image and the selected good product sample data by using a dissimilarity model, and determining whether the tested object is a good product or a defective product according to the dissimilarity value.2. The method for determining whether the object comprises a defect according to claim 1 , further comprising:obtaining multiple training datasets corresponding to multiple objects, each training dataset comprising at least one piece of defective product data, at least one piece of good product data and at least one piece of good product sample data of the corresponding objects; andtraining the dissimilarity model based on the at least one piece of defective product data, the at least one piece of good product data and the good product sample data of each object in the training dataset.3. The method for determining whether the object comprises a defect according to claim 2 , wherein the dissimilarity model is trained by a triplet loss supervised learning algorithm claim 2 , andthe training the dissimilarity model comprises:putting the training dataset corresponding to the object and a weight into a first feature model to obtain an eigenvector;calculating a triplet loss value of the object by using a triplet loss ...

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Номер записи: 92
01-07-2021 дата публикации

LAYOUT ARCHITECTURE FOR A CELL

Номер: US20210202466A1
Автор: LIN WEI-CHENG, Peng Shi-Wei, TZENG JIANN-TYNG, Wu Guo-Huei, Zhuang Hui-Zhong
Принадлежит:

A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other. 1. A circuit comprising:a first metal layer comprising a plurality of first metal layer strips, wherein the plurality of first metal layer strips comprises a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary, wherein the second boundary is opposite to the first boundary, and wherein each of the plurality of first metal layer strips, the first boundary, and the second boundary are substantially parallel to each other; anda second metal layer comprising a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip, wherein the first second metal layer strip is connected to the first metal layer at the first first metal layer strip, wherein the second second metal layer strip is connected to the first metal layer at the second first metal layer strip, and wherein each of the first second metal layer strip and the second second metal layer strip are substantially parallel to each other.2. The device of claim 1 , wherein the first second metal layer strip is an odd numbered second metal layer strip claim 1 , and wherein the second ...

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Номер записи: 93
18-09-2014 дата публикации

BACKSIDE SENSING BIOFET WITH ENHANCED PERFORMANCE

Номер: US20140264467A1
Автор: Cheng Chun-Wen, Lai Fei-Lung, Liao Ta-Chuan, LIN WEI-CHENG, Liu Yi-Shao, Yang Chien-Kuo
Принадлежит:

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer. 1. A biological field-effect transistors (BioFET) device , comprising:a substrate;a transistor structure in the substrate having a gate structure over a source region, a drain region, and an active region, the active region including a channel region and a treated layer;an isolation layer on a side of the substrate opposite from the gate structure, said isolation layer having an opening at the active region of the transistor structure; anda dielectric layer in the opening.2. The BioFET device of claim 1 , wherein the treated layer is a lightly doped layer.3. The BioFET device of claim 1 , wherein the treated layer comprise a dopant having a conductivity type opposite from a dopant in the channel region.4. The BioFET device of claim 1 , wherein the treated layer comprises hydrogen.5. The BioFET device of claim 1 , further comprising a metal crown structure over the isolation layer and at least partially covering sidewalls of the opening.6. The BioFET device of claim 1 , wherein the dielectric layer comprises aluminum oxide claim 1 , titanium oxide claim 1 , hafnium oxide claim 1 , tantalum oxide claim 1 , tin oxide claim 1 , or a combination of these.7. The BioFET device of claim 1 , further comprising:a fluidic channel disposed on the isolation layer.8. The BioFET device of claim 1 , further ...

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Номер записи: 94
02-07-2015 дата публикации

Air-Guiding Casing of a Ventilation Fan

Номер: US20150184878A1
Автор: Huang Ho-Min, Kuo Chi-Hung, LIN Cheng-Wei, SU Chia-Hung
Принадлежит:

An air-guiding casing of a ventilation fan includes a main body and an air-guiding tube. The main body forms a compartment and includes an inlet and an outlet. The inlet and the outlet are in communication with the compartment. A first engaging portion is arranged on a part of an edge of the outlet and on one side of the main body. The air-guiding tube has an engaging end and an outlet end opposite to the engaging end. A second engaging portion is arranged on the engaging end. The first and second engaging portions are engaged with each other. 1. An air-guiding casing of a ventilation fan , comprising:a main body forming a compartment and comprising an inlet and an outlet, wherein the inlet and the outlet are in communication with the compartment, and wherein a first engaging portion is arranged on a part of an edge of the outlet and on one side of the main body; andan air-guiding tube having an engaging end and an outlet end opposite to the engaging end, wherein a second engaging portion is arranged on the engaging end, and wherein first and second engaging portions are engaged with each other.2. The air-guiding casing of the ventilation fan as claimed in claim 1 , wherein the main body further comprises a base plate and a plurality of side plates arranged at an outer periphery of the base plate claim 1 , wherein the base plate and the plurality of side plates together define the compartment claim 1 , and wherein the outlet is arranged on one of the plurality of side plates.3. The air-guiding casing of the ventilation fan as claimed in claim 2 , wherein two opposing wings are arranged on the one of the plurality of side plates claim 2 , wherein the two opposing wings are located at the part of the edge of the outlet claim 2 , wherein each of the two opposing wings comprises at least one engaging hole claim 2 , wherein two opposing guiding plates are arranged at the engaging end of the air-guiding tube claim 2 , wherein each of the two opposing guiding plates ...

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Номер записи: 95
02-07-2015 дата публикации

METHOD OF ENCRYPTION AND DECRYPTION FOR SHARED LIBRARY IN OPEN OPERATING SYSTEM

Номер: US20150186681A1
Автор: LIN WEI-CHENG
Принадлежит: GIGA-BYTE TECHNOLOGY CO., LTD.

A method of encryption and decryption for shared libraries in an open operating system is provided. By encrypting a partial portion of an executable and linkable format (ELF) file, where the ELF file is dependent on the shared libraries, an operating system lacking a secret key is not able to use the encrypted ELF file and thus not able to load the shared libraries into the memory for execution, thereby ensuring the protection of the shared libraries. 1. A method of encryption for shared libraries in an open operating system , wherein said shared libraries are dependent libraries that an executable and linkable format (ELF) file is dependent on , and said ELF includes an ELF header , at least one program header table , and at least one segment , said method of encryption comprising:encrypting partial portions of said ELF header and said at least one program header table.2. The method of encryption as of claim 1 , wherein said ELF header includes an identification segment.3. The method of encryption as of claim 2 , further comprising:encrypting the portion of said ELF header excluding said identification segment.4. The method of encryption as of claim 3 , further comprising:modifying said identification segment so as to generate an updated identification segment.5. The method of encryption as of claim 1 , wherein said at least one segment includes a dynamic segment (PT_DYNAMIC).6. The method of encryption as of claim 5 , further comprising:encrypting said dynamic segment (PT_DYNAMIC).7. The method of encryption as of claim 1 , further comprising the steps of:generating a random number; andencrypting partial portions of said ELF header and said at least one program header table through said random number.87. The method of encryption as of claim 1 , further comprising the steps of:providing a string password;performing a hash operation on said string password so as to generate a hash number; andencrypting said random number through said hash number so as to generate an ...

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Номер записи: 96
08-07-2021 дата публикации

MULTI-CHIP PACKING STRUCTURE EMPLOYING MILLIMETER WAVE

Номер: US20210210443A1
Автор: Hsiao Chien-Jen, LIN WEI-CHENG, Liu Chung-Hsin, Tseng Shih-Hsin
Принадлежит:

A multi-chip packaging structure employing millimeter wave includes a substrate material, a first and a second substrate board and an adhesive layer. The substrate material has a first metal pad. The first substrate board has a first and a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are layer-by-layer stacked and electrically connected. The first and second metal pads are electrically connected via at least one metal lead. The adhesive layer is disposed between the substrate material and the first substrate board. The second substrate board has a third and a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are layer-by-layer stacked and electrically connected. The electro-conductive boss blocks are respectively electrically connected with the second and third metal pads. Chips and antennas are integrated to integrate signal height and avoid interference and minify the volume. 1. A multi-chip packaging structure employing millimeter wave , comprising:a substrate material having a first face and a second face, the first face having a first metal pad;a first substrate board having a first integrated circuit, a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are respectively layer-by-layer stacked and electrically connected with each other, the first and second metal pads being electrically connected via at least one metal lead;an adhesive layer disposed between the substrate material and the first substrate board;a second substrate board having a third integrated circuit, a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are respectively layer-by-layer stacked and electrically connected with each other; andmultiple electro-conductive boss blocks respectively electrically connected with the second and third metal pads.2. The multi-chip packaging structure employing millimeter wave as ...

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Номер записи: 97
15-07-2021 дата публикации

MULTIPLE FIN HEIGHT INTEGRATED CIRCUIT

Номер: US20210217744A1
Автор: LAI Wei-An, LIN WEI-CHENG, TZENG JIANN-TYNG, YANG Hui-Ting, YUAN Lipen
Принадлежит:

A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height. 1. A semiconductor device , comprising:a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from a top surface of the first dielectric material to a top surface of the first fin; anda second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.2. The semiconductor device of claim 1 , whereinthe first dielectric material has a first dielectric material thickness,the second dielectric material has a second dielectric material thickness, and the second dielectric material thickness is greater than the first dielectric material thickness.3. The semiconductor device of claim 1 , wherein the first dielectric material has a first dielectric material thickness claim 1 , the second dielectric material has a second dielectric material thickness claim 1 , and the first dielectric material thickness and the second dielectric material thickness are a same thickness.4. The semiconductor device of claim 1 , wherein the first fin has a first fin width and the second fin has a second fin width claim ...

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Номер записи: 98
06-07-2017 дата публикации

Electronic paper display apparatus and driving method thereof

Номер: US20170193894A1
Автор: Chi-Wei Lin, Kuo-Han Hsu, Mon-Wei Wu, Wei-Cheng Lin, Yi-Te Lee
Принадлежит: SiPix Technology Inc

An electronic paper display apparatus including an electronic paper display panel to display an image page, a display driver coupled to the electronic paper display panel, and a data processor coupled to the display driver. The display driver drives the electronic paper display panel to display a plurality of image frames according to image data, so as to display the image page. The data processor converts a first look-up table into a second look-up table and merges a current frame and a previous frame into a combined frame. The data processor generates the image data according to the combined frame and the second look-up table and outputs the image data. The image frames include the current frame and the previous frame. A driving method of the electronic paper display apparatus is also provided.

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Номер записи: 99
11-06-2020 дата публикации

SYSTEM FOR AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

Номер: US20200184139A1
Автор: CHEN Chih-Liang, Chien Wei-Chen, Lai Chih-Ming, LIN WEI-CHENG, Liu Ru-Gun, PENG SHIH-WEI, Sio Kam-Tou, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias. 1. A method of manufacturing an integrated circuit , the method comprising:defining a via grid having a first minimum pitch in a first direction and a second minimum pitch in a second direction different from the first direction;defining design criteria of the integrated circuit, the design criteria including at least via spacing rules of the integrated circuit;generating a first layout design of the integrated circuit based on the via grid and the design criteria, the first layout design having a first set of vias arranged in first rows and first columns based on the via grid, the first rows of the first set of vias being arranged in the first direction, the first columns of the first set of vias being arranged in the second direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set;generating a via color layout design of the integrated circuit based on the first layout design ...

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Номер записи: 100
21-07-2016 дата публикации

INTEGRATED CIRCUIT HAVING SLOT VIA AND METHOD OF FORMING THE SAME

Номер: US20160211213A1
Автор: LIN WEI-CHENG, NARAYANASETTI Praneeth, TZENG JIANN-TYNG, Young Charles Chew-Yuen
Принадлежит:

An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line. 1. An integrated circuit on a substrate comprising:a first conductive line on a first metal level of the integrated circuit, wherein the first conductive line extends in a first direction parallel a top surface of the substrate;a second conductive line on a second metal level of the integrated circuit above the first metal level, wherein the second conductive line extends in a second direction parallel the top surface of the substrate, the second direction perpendicular to the first direction; anda slot via having a length in the first direction and a width in the second direction, the length being greater than the width and electrically connecting the first conductive line with the second conductive line, wherein the slot via overlaps with the first conductive line and with the second conductive line, and the slot via extends beyond a periphery of the second conductive line, and wherein an entirety of the length of the slot via in the first direction interfaces with the first conductive line.2. The integrated circuit of claim 1 , wherein an entire length width of the slot via overlaps with the second conductive line.3. The integrated circuit of claim 1 , wherein a sidewall of the first conductive line is aligned with a sidewall of disposed between the second conductive line and the top surface of the substrate.45.-. (canceled)6. The integrated circuit of claim 1 , further comprising a third conductive line on the second ...

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Номер записи: 101