TRANSPARENT OPTICAL COUPLER ACTIVE MATRIX ARRAY

A backplane has an array of output terminals arranged on an output surface of the backplane, and an array of solid state optical switches, each optical switch corresponding to one of the output terminals, wherein the solid state optical switches are responsive to light of a control wavelength and are transparent to light of a sensing wavelength, wherein the backplane is of a material transparent to light of a sensing wavelength different from the control wavelength. An optical system includes a backplane having an array of optocouplers, a projector to generate light of a control wavelength to which the optocouplers are responsive, optics to direct the control light onto the array of optocouplers on a backplane, an imaging system responsive to light of a sensing wavelength, wherein the backplane is at least partially transparent to the sensing wavelength.

Gated co-planar poly-silicon thin film diode

A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel ...

Systems and Methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Active matrix backplane formed using thin film optocouplers

A device includes a backplane having multiple output terminals arranged in an array on an output surface of the backplane. The device further includes an active matrix array comprising thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals. Storage capacitors may be coupled respectively to the output terminals. A pixelated light source provides pixelated light that controls the optical switches.

ACTIVE MATRIX BACKPLANE FORMED USING THIN FILM OPTOCOUPLERS

A device includes a backplane having multiple output terminals arranged in an array on an output surface of the backplane. The device further includes an active matrix array comprising thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals. Storage capacitors may be coupled respectively to the output terminals. A pixelated light source provides pixelated light that controls the optical switches. 1. A device comprising: multiple output terminals arranged on an output surface of the backplane;', thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals, the optical switches and the output terminals arranged in an array; and', 'storage capacitors coupled respectively to the output terminals; and, 'an optocoupler active matrix array, comprising], 'a backplane, comprisinga pixelated light source configured to provide pixelated light that controls the optical switches.2. The device of claim 1 , wherein the pixelated light source comprises:at least one light generating device configured to provide a light beam; andat least one mirror; anda movement mechanism configured to provide movement of the mirror along at least two dimensions.3. The device of claim 1 , wherein the pixelated light source comprises multiple light generating devices claim 1 , each of the multiple light generating devices arranged to control at least one of the optical switches.4. The device of claim 1 , wherein the pixelated light source comprises:at least one light generating device; anda micro mirror array comprising multiple rotatable micro mirrors.5. The device of claim 1 , wherein the pixelated light source comprises a flat panel display claim 1 , wherein each pixel of the flat panel display corresponds to a pixel of the active matrix array.6. The device of claim 5 , wherein an array of optical devices is disposed between the flat panel display and the ...

MICRO-ASSEMBLER SYSTEM FOR CONTROLLING PLACEMENT OF MICRO-OBJECTS

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler.

ACTIVE MATRIX BACKPLANE FORMED BY USING THIN FILM OPTOCOUPLERS

An apparatus includes a backplane which includes multiple output terminals which are arranged on the output surface of the backplane as an array. The apparatus further includes an active matrix array which includes thin film solid state optical switches which are combined between the output terminals and an input terminal of the backplane. Storage capacitors are combined with the output terminals, respectively. A pixelated light source provides pixelated light to control the optical switches. The optical switches described in the present invention can protect a semiconductor bonding part from a high electric field by using one or more field plates. COPYRIGHT KIPO 2016 (CC) Ground connection (BB) Upper electrodes (AA) One pixel ...

Integrateable capacitors and microcoils and methods of making thereof

Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom electrode structure to removing a suspension portion of a moveable top electrode from an RF part of a circuit.

Method for reduction of stiction while manipulating micro objects on a surface

A system and method reduce stiction while manipulating micro objects on a surface. The system and method employed a field generator configured to generate a driving force at a frequency and amplitude to at least partially overcome stiction between the micro objects and the surface. The field generator is further configured to generate a manipulation force to manipulate the micro objects on the surface in two dimensions. The manipulation force is spatially programmable.

Capacitive imaging device with active pixels

An apparatus includes a sensor array with a plurality of active pixels. Each active pixel in the sensor array includes: a three transistor (3T) sensor with a source follower transistor, and a detection diode coupled in series to a parasitic capacitor at a sensing junction. A gate of the source follower transistor amplifier is coupled to the sensing junction. The apparatus includes an insulator layer over the sensor array. The insulator layer provides a variable capacitance to the sensing junctions of underlying active pixels in response to portions of an object being proximate to the insulator layer. The variable capacitance is used to detect an image of the object.

Tag system implementing a normal-on antenna and methods of use

Systems and methods for operating a tag system. The methods comprising: wirelessly communicating, from a tag, a first signal at a first frequency spectrum that allows a tag reader to detect the first signal, when the tag is not proximate to an antenna modulation marker or when the antenna modulation marker has a first orientation relative to the tag; and performing operations by the tag to wirelessly communicate a second signal at a second frequency spectrum that does not allow the tag reader to detect the first signal, when the tag is proximate to the antenna modulation marker or when the antenna modulation marker has a second different orientation relative to the tag.

METHOD AND SYSTEM FOR MASS ASSEMBLY OF THIN-FILM MATERIALS

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers to a target substrate. 1. A system comprising:a plurality of chiplet carriers each comprising a portion of thin film material attached to a portion of a carrier wafer, a sheet of the thin film material being attached to the carrier wafer before the carrier wafer and the thin film material are separated into the chiplets;a micro assembler that arranges the chiplet carriers on an assembly surface from a disordered pattern to a predetermined pattern; anda carrier that transfers the portions of the thin film material from the chiplet carriers to a target substrate.2. The system of claim 1 , wherein the thin film material comprises a van der Waals material.3. The system of claim 1 , further comprising a singulation tool that separates the carrier wafer and the sheet of the thin film material after attachment thereto.4. The system of claim 1 , wherein the carrier comprises a stamp having an array of mildly adhesive protrusions in the predetermined pattern so that each of the protrusion aligns with one of the chiplet carriers claim 1 , the stamp being configured to:press the protrusions against the chiplet carriers on the assembly surface;rapidly cool the protrusions to a first temperature;pull away from the chiplet carriers to remove the portions of the thin film material from the portions of the carrier wafers via the protrusions;press the portions of the thin film material onto a target substrate; andchange the protrusions to a second ...

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Transparent optical coupler active matrix array

A backplane has an array of output terminals arranged on an output surface of the backplane, and an array of solid state optical switches, each optical switch corresponding to one of the output terminals, wherein the solid state optical switches are responsive to light of a control wavelength and are transparent to light of a sensing wavelength, wherein the backplane is of a material transparent to light of a sensing wavelength different from the control wavelength. An optical system includes a backplane having an array of optocouplers, a projector to generate light of a control wavelength to which the optocouplers are responsive, optics to direct the control light onto the array of optocouplers on a backplane, an imaging system responsive to light of a sensing wavelength, wherein the backplane is at least partially transparent to the sensing wavelength.

Transfer Elements that Selectably Hold and Release Objects Based on Changes in Stiffness

Transfer elements include an adhesion element having a higher Young's modulus at a lower temperature and a lower Young's modulus at a higher temperature. Heating elements are operable to change an operating temperature of each adhesion element in response to an input. A controller is coupled to provide the inputs to the heating elements to cause a change in temperature at least between the higher and lower temperature. The change in temperature causes the transfer elements to selectably hold objects to and release the objects in response to changes between the higher and lower Young's moduli of transfer elements

MICRO-ASSEMBLER SYSTEM FOR MANIPULATING MICRO-OBJECTS

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

Digital 3D fabrication using multi-layered mold

A replica 3D structure is fabricated inside a multi-layered mold by patterning each mold layer to define a void/opening that matches a corresponding cross section of the structure's peripheral surface, and filling the patterned opening of each layer with a structural material (i.e., before depositing a subsequent layer of mold material). The mold material (e.g., photoresist or another dissolvable sacrificial material) is blanket deposited (e.g., by slot-die, spray coating) and then patterned using a laser or a printed mask. Each layer of modeling material (e.g., polymer, ceramic or metal, or a combination thereof) is electro-plated or otherwise deposited on the previously formed modeling material layer. High vertical resolution is achieved by utilizing relatively thin mold layers. The mold layer deposition, patterning and modeling material deposition is repeated until the replica 3D structure is entirely formed inside the multi-layered mold, and then the mold is dissolved or otherwise removed ...

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Rectifying devices and fabrication methods

A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.

Digital printing plate and system with electrostatically latched deformable membranes

A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Integration of semiconductor epilayers on non-native substrates

An article includes a support substrate bonded to heterostructure epitaxial layers that include one or more electronic devices. The support substrate has a bonding surface and the heterostructure epitaxial layers have a surface with the epitaxial growth direction of the heterostructure epitaxial layers towards the surface. The surface of the heterostructure epitaxial layers is bonded at the bonding surface of the support substrate by ion exchange between the surface of the heterostructure epitaxial layers and the bonding surface of the support substrate.

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Gated co-planar poly-silicon thin film diode

A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel ...

TRANSFER SUBSTRATE UTILIZING SELECTABLE SURFACE ADHESION TRANSFER ELEMENTS

An apparatus includes a transfer substrate with two or more transfer elements. Each of the transfer elements includes an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature. The second surface adhesion less than the first surface adhesion. Each transfer element has a thermal element operable to change a temperature of the adhesion element in response to an input. A controller is coupled to provide the inputs to the thermal elements of the two or more transfer elements to cause a subset of the transfer elements to selectably hold objects to and release the objects from the transfer substrate in response to changes between the first and second surface adhesion of the subset of the transfer elements 1. An apparatus , comprising: an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature, the second surface adhesion less than the first surface adhesion; and', 'a thermal element operable to change a temperature of the adhesion element in response to an input; and, 'a transfer substrate, comprising two or more transfer elements, each of the transfer elements comprisinga controller coupled to provide the inputs to the thermal elements of the two or more transfer elements to cause a subset of the transfer elements to selectably hold objects to and release the objects from the transfer substrate in response to changes between the first and second surface adhesion of the subset of the transfer elements.2. The apparatus of claim 1 , wherein the objects comprise sub-millimeter electronic devices.3. The apparatus of claim 1 , wherein the two or more transfer elements comprise an array of transfer elements spaced at a pitch between 1 μm and 1 mm.4. The apparatus of claim 1 , wherein the adhesion element is formed of a multi-polymer that contains stearyl acrylate (SA) polymer.5. The apparatus of claim 1 , wherein a difference between the ...

Polysensing bioelectronic test plate

An electronic test plate includes a test plate comprising plurality of wells, each well configured to contain a substance to be analyzed. Sensors are arranged to sense characteristics of the substance and to generate sensor signals based on the sensed characteristics over time. The sensors are arranged so that multiple sensors are associated with each well. At least one sensor of the multiple sensors senses a characteristic of the substance that is different from a characteristic sensed by another sensor of the multiple sensors. Sensor select circuitry is arranged on a backplane disposed along the test plate. The sensor select circuitry is coupled to the sensors and enable the sensor signals of selected sensors to be accessed at a data output of the backplane.

Integrated driver electronics for MEMS device using high voltage thin film transistors

An apparatus integrating electrostatically actuated MEMS devices and high voltage driver (actuator) electronics on a single substrate, where the driver electronics utilize offset-gate high voltage thin-film transistors (HVTFTs) that facilitate the transmission of high actuating voltages using relatively low control voltages, thereby facilitating the formation of large arrays of electrostatically-actuated MEMS devices. The driver circuit is arranged such that the high actuating voltage is applied to an actuating electrode of the actuated MEMS device and drain electrode of the HVTFT when the HVTFT is turned off, thereby minimizing dielectric breakdown. When the HVTFT is turned on in response to the relatively low control voltage, the high actuating voltage is discharged to ground from the drain (offset) electrode to the source (not offset) electrode.

Direct electrostatic assembly with capacitively coupled electrodes

A system and method manipulate micro objects. A field generator is configured to generate a force field varying in both space and time to manipulate the micro objects on a substrate. The substrate is not permanently affixed to the field generator and allows the force field to pass through the substrate.

Method for fabricating a spring structure on a substrate

Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

HIGH REGISTRATION PARTICLES-TRANSFERRING SYSTEM

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

CONTINUOUS HIGH-SPEED 3D PRINTING

A method for providing high-speed three dimensional (3D) printing is provided. The method includes producing at least one three dimensional (3D) printed part. Producing the 3D part includes continuously constructing to extend outwardly a diameter of a rotating cylindrical core via continuous deposition of a layer, and defining a first pattern in the continuously deposited layer corresponding to a cross-section of the at least one 3D printed part.

Amorphous silicon sensor with micro-spring interconnects for achieving high uniformity in integrated light-emitting sources

A hybrid structure or device is provided wherein carried on a single substrate is at least one micro-spring interconnect having an elastic material that is initially fixed to a surface of the substrate, an anchor portion which is fixed to the substrate surface and a free portion. The spring contact is self-assembling in that as the free portion is released it moves out of the plane of the substrate. Also integrated on the substrate is a sensor having an active layer and contacts. The substrate and sensor may be formed of materials which are somewhat partially transparent to light at certain infrared wavelengths. The integrated sensor/spring contact configuration may be used in an imaging system to sense output from a light source which is used for image formation. The light source may be a laser array, LED array or other appropriate light source. The sensor is appropriately sized to sense all or some part of light from the light source. The sensor may also be sufficiently transparent so ...

CAPACITIVE IMAGING DEVICE WITH ACTIVE PIXELS

An apparatus includes a sensor array with a plurality of active pixels. Each active pixel in the sensor array includes: a three transistor (3T) sensor with a source follower transistor, and a detection diode coupled in series to a parasitic capacitor at a sensing junction. A gate of the source follower transistor amplifier is coupled to the sensing junction. The apparatus includes an insulator layer over the sensor array. The insulator layer provides a variable capacitance to the sensing junctions of underlying active pixels in response to portions of an object being proximate to the insulator layer. The variable capacitance is used to detect an image of the object. 120-. (canceled)21. A capacitive image pixel , comprising:a three-transistor (3T) sensor comprising a source follower transistor having a gate, wherein the 3T sensor has a charge cycle and a readout cycle, wherein during the charge cycle a first capacitance builds at the gate of the source follower transistor to establish a first gate voltage and wherein during the readout cycle a second capacitance builds at the gate of the source follower transistor to establish a second gate voltage, wherein the difference between the first and second gate voltage is correlative to the nearness of an object.22. The capacitive image pixel of claim 21 , further comprising an enabling transistor to enable the source follower transistor and a reset transistor to reset the source follower transistor.23. The capacitive image pixel of claim 22 , wherein the enabling transistor enables the charge cycle.24. The capacitive image pixel of claim 21 , further comprising a biasing diode tied to the gate of the source follower transistor.25. The capacitive image pixel of claim 21 , wherein the object is capable of altering the second capacitance when the object is near the 3T sensor.26. A capacitive image sensor comprising: a three-transistor (3T) sensor comprising a source follower transistor having a gate,', 'wherein the 3T sensor ...

GATED CO-PLANAR POLY-SILICON THIN FILM DIODE

A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel ...

PRINTED CIRCUIT BOARDS BY MASSIVE PARALLEL ASSEMBLY

A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.

Integrateable capacitors and microcoils and methods of making thereof

Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor ...

DIGITAL PRINTING PLATE AND SYSTEM WITH ELECTROSTATICALLY LATCHED DEFORMABLE MEMBRANES

A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Digital 3D Fabrication Using Multi-Layered Mold

A replica 3D structure is fabricated inside a multi-layered mold by patterning each mold layer to define a void/opening that matches a corresponding cross section of the structure's peripheral surface, and filling the patterned opening of each layer with a structural material (i.e., before depositing a subsequent layer of mold material). The mold material (e.g., photoresist or another dissolvable sacrificial material) is blanket deposited (e.g., by slot-die, spray coating) and then patterned using a laser or a printed mask. Each layer of modeling material (e.g., polymer, ceramic or metal, or a combination thereof) is electro-plated or otherwise deposited on the previously formed modeling material layer. High vertical resolution is achieved by utilizing relatively thin mold layers. The mold layer deposition, patterning and modeling material deposition is repeated until the replica 3D structure is entirely formed inside the multi-layered mold, and then the mold is dissolved or otherwise removed ...

Method of forming a photodiode

A self-destructing device includes a stressed substrate with a heater thermally coupled to the stressed substrate. The device includes a power source and trigger circuitry comprising a sensor and a switch. The sensor generates a trigger signal when exposed to a trigger stimulus. The switch couples the power source to the heater in response to the trigger signal When energized by the power source, the heater generates heat sufficient to initiate self-destruction of the stressed substrate.

Externally induced charge patterning using rectifying devices

A system and method form charge patterns on micro objects. The system and method employ a micro object including a rectifying device. The rectifying device exhibits an asymmetric current-voltage (I-V) response curve. Further, the system and method employ a device external to the micro object to induce the flow of charge through the rectifying device.

Method and system for mass assembly of thin film materials

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers in parallel to a target substrate.

Sub-resolution gaps generated by controlled over-etching

Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.

POLYSENSING BIOELECTRONIC TEST PLATE

An electronic test plate includes a test plate comprising plurality of wells, each well configured to contain a substance to be analyzed. Sensors are arranged to sense characteristics of the substance and to generate sensor signals based on the sensed characteristics over time. The sensors are arranged so that multiple sensors are associated with each well. At least one sensor of the multiple sensors senses a characteristic of the substance that is different from a characteristic sensed by another sensor of the multiple sensors. Sensor select circuitry is arranged on a backplane disposed along the test plate. The sensor select circuitry is coupled to the sensors and enable the sensor signals of selected sensors to be accessed at a data output of the backplane. 1. A device comprising:a test plate comprising plurality of wells, each well configured to contain a substance to be analyzed; andsensors configured to sense characteristics of the substance and to generate sensor signals based on the sensed characteristics, the sensors arranged so that multiple sensors are associated with each well, at least one sensor of the multiple sensors configured to sense a characteristic of the substance that is different from a characteristic sensed by another sensor of the multiple sensors; andsensor select circuitry coupled to the sensors, the sensor select circuitry arranged on a backplane disposed along the test plate, the sensor select circuitry configured to enable the sensor signals of selected sensors to be accessed at a data output.2. The device of claim 1 , wherein the device includes one or more optically transparent regions that allow each well to be optically interrogated.3. The device of claim 1 , wherein at least one of the sensor select circuitry and the sensors comprise thin film transistors (TFT).4. The device of claim 1 , wherein the multiple sensors comprise two or more of electrical claim 1 , chemical claim 1 , optical claim 1 , acoustic and oxygen sensors.5. The ...

Capacitive imaging device with active pixels and method

A capacitive image sensor includes a sensor array having capacitive image pixels. Each pixel has a two-transistor configuration including a pixel selection transistor and a source follower transistor. The pixel selection transistor activates the source follower transistor. The source follower is coupled to a variable capacitance that affects an input impedance of the source follower. An AC current is source is used to interrogate the activated source follower to determine an output impedance of the source follower. The output impedance is a function of the input impedance and the output impedance is representative of the nearness of an object.

SENSOR AND HEATER FOR STIMULUS-INITIATED FRACTURE OF A SUBSTRATE

A self-destructing device includes a stressed substrate with a heater thermally coupled to the stressed substrate. The device includes a power source and trigger circuitry comprising a sensor and a switch. The sensor generates a trigger signal when exposed to a trigger stimulus. The switch couples the power source to the heater in response to the trigger signal When energized by the power source, the heater generates heat sufficient to initiate self-destruction of the stressed substrate. 1. A method of forming a photodiode comprising:depositing a first electrode layer over a substrate;depositing a first doped layer of an active region over the first electrode layer;depositing an intrinsic layer over the first doped layer;depositing a second doped layer of the active region over the intrinsic layer;depositing a second electrode layer over the second doped layer; andpatterning the first electrode layer, the first doped layer, the intrinsic layer, the second doped layer, and the second electrode layer to form the photodiode in not more than two mask steps.2. The method of claim 1 , wherein the patterning comprises:patterning the first electrode layer and the first doped layer in a first patterning step using a first mask;patterning the second electrode layer, the second doped layer, and the intrinsic layer in a second patterning step using a second mask; andduring the second patterning step removing the first doped layer in unprotected regions in a self-aligned manner.3. The method of claim 1 , further comprising forming an adhesion promoting surface on the substrate claim 1 , wherein depositing the first electrode layer comprises depositing the first electrode layer on the adhesion promoting surface.4. The method of claim 3 , wherein forming the adhesion promoting surface comprises depositing a layer of silicon oxide claim 3 , silicon nitride claim 3 , or silicon oxynitride by plasma-enhanced chemical vapor deposition.5. The method of claim 1 , wherein the second ...

Printed circuit boards by massive parallel assembly

A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern.

Passive detector with nonvolatile memory storage

A passive detector includes a sensor configured to sense an environmental parameter and to generate an output signal at an output of the sensor in response to the sensed environmental parameter. An energy scavenging circuit is coupled to the sensor, the energy scavenging circuit configured to convert a first voltage, V1, across the sensor to a second voltage, V2, where V2>V1. A discriminator is powered by the second voltage and is coupled to the output of the sensor. A nonvolatile memory is coupled to an output of the discriminator. The discriminator is configured to compare the sensor output signal to a threshold and, in response to the sensor output signal being above the threshold, to provide a programming signal at the output of the discriminator. The programming signal is configured to cause data to be stored or erased in the nonvolatile memory.

Microchip charge patterning

A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and using an external device to develop charge in the material.

METHOD AND SYSTEM FOR MASS ASSEMBLY OF THIN FILM MATERIALS

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers in parallel to a target substrate. 1. A method , comprising:attaching sheets of thin film material to a carrier wafer;separating the carrier wafer and the attached sheets of thin film material to form chiplet carriers, each chiplet carrier comprising a portion of the sheets of thin film material attached to a portion of the carrier wafer;placing the chiplet carriers on an assembly surface in a disordered pattern;arranging the chiplet carriers from the disordered pattern to a predetermined pattern; andtransferring the portions of the thin film material from the chiplet carriers in parallel to a target substrate.2. The method of claim 1 , wherein the thin film material comprises a van der Waals material.3. The method of claim 1 , wherein transferring the portions of the thin film material from the chiplet carriers in parallel to a target substrate comprises:pressing a stamp against the chiplet carriers on the assembly surface, the stamp comprising an array of mildly adhesive protrusions in the predetermined pattern so that each of the protrusion contacts the portion of thin film material;separating the stamp from the chiplet carriers so that the portions of the thin film material are removed from the portions of the carrier wafer by the protrusions; andpressing the stamp onto the target substrate such that the thin film material is deposited on the target substrate.4. The method of claim 3 , wherein the stamp is pressed against the chiplet ...

Capacitive imaging device with active pixels

An apparatus includes a sensor array with a plurality of active pixels. Each active pixel in the sensor array includes: a three transistor (3T) sensor with a source follower transistor, and a detection diode coupled in series to a parasitic capacitor at a sensing junction. A gate of the source follower transistor amplifier is coupled to the sensing junction. The apparatus includes an insulator layer over the sensor array. The insulator layer provides a variable capacitance to the sensing junctions of underlying active pixels in response to portions of an object being proximate to the insulator layer. The variable capacitance is used to detect an image of the object.

EXTERNALLY INDUCED CHARGE PATTERNING USING RECTIFYING DEVICES

A system and method form charge patterns on micro objects. The system and method employ a micro object including a rectifying device. The rectifying device exhibits an asymmetric current-voltage (I-V) response curve. Further, the system and method employ a device external to the micro object to induce the flow of charge through the rectifying device. 1. A system for forming charge patterns on micro objects , said system comprising:a micro object including a rectifying device, the rectifying device exhibiting an asymmetric current-voltage (I-V) response curve; anda device external to the micro object configured to induce the flow of charge through the rectifying device.2. The system of claim 1 , wherein the device induces the flow of charge through the rectifying device using capacitive or magnetic coupling.3. The system of claim 1 , wherein the rectifying diode includes at least one diode.4. The system of claim 1 , wherein the rectifying diode includes a thin film diode.5. The system of claim 4 , wherein the thin film diode includes at least one of an s-Si:H PIN diode and an organic thin film diode.6. The system of claim 1 , wherein the rectifying device includes a thin film Schottky diode.7. The system of claim 6 , wherein the thin film Schottky diode includes a thin film material being one of cadmium selenide (CdSe) and gallium indium zinc oxide (GIZO).8. The system of claim 1 , wherein the micro object includes a substrate claim 1 , and wherein the rectifying device is formed on or in the substrate.9. The system of claim 1 , wherein a terminal of the rectifying device is connected to the external environment of the micro object.10. The system of claim 1 , wherein the device is configured to generate an electric or magnetic field to induce the flow of charge through the rectifying device.11. The system of claim 10 , wherein the device is further configured to move the micro object using the same electric or magnetic field inducing the flow of charge through the ...

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

PASSIVE DETECTOR WITH NONVOLATILE MEMORY STORAGE

A passive detector includes a sensor configured to sense an environmental parameter and to generate an output signal at an output of the sensor in response to the sensed environmental parameter. An energy scavenging circuit is coupled to the sensor, the energy scavenging circuit configured to convert a first voltage, V, across the sensor to a second voltage, V, where V>V. A discriminator is powered by the second voltage and is coupled to the output of the sensor. A nonvolatile memory is coupled to an output of the discriminator. The discriminator is configured to compare the sensor output signal to a threshold and, in response to the sensor output signal being above the threshold, to provide a programming signal at the output of the discriminator. The programming signal is configured to cause data to be stored or erased in the nonvolatile memory. 1. A passive detector comprising:a sensor configured to sense an environmental parameter and to generate an output signal at an output of the sensor in response to the sensed environmental parameter;{'sub': 1', '2', '2', '1, 'an energy scavenging circuit coupled to the sensor, the energy scavenging circuit configured to convert a first voltage, V, across the sensor to a second voltage, V, where V>V;'}a discriminator powered by the second voltage and coupled to the output of the sensor; anda nonvolatile memory coupled to an output of the discriminator, wherein the discriminator is configured to compare the sensor output signal to a threshold and, in response to the sensor output signal being above the threshold, to provide a programming signal at the output of the discriminator, the programming signal configured to cause data to be stored or erased in the nonvolatile memory.2. The passive detector of wherein the nonvolatile memory comprises at least one flash memory cell.3. The passive detector of wherein the programming signal is capable of changing a state of a nonvolatile memory cell of the nonvolatile memory from a first ...

Method of controlling placement of micro-objects

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler.

Integrateable capacitors and microcoils and methods of making thereof

Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor ...

Stressed substrates for transient electronic systems

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during ...

INTEGRATION OF SEMICONDUCTOR EPILAYERS ON NON-NATIVE SUBSTRATES

An article includes a support substrate bonded to heterostructure epitaxial layers that include one or more electronic devices. The support substrate has a bonding surface and the heterostructure epitaxial layers have a surface with the epitaxial growth direction of the heterostructure epitaxial layers towards the surface. The surface of the heterostructure epitaxial layers is bonded at the bonding surface of the support substrate by ion exchange between the surface of the heterostructure epitaxial layers and the bonding surface of the support substrate. 1. An article , comprising:a support substrate having bonding surface; andheterostructure epitaxial layers that include one or more electronic devices, the heterostructure epitaxial layers having a surface and an epitaxial growth direction towards the surface, the heterostructure epitaxial layers bonded to the support substrate at the surface of the heterostructure epitaxial layers by ion exchange between the surface of the heterostructure epitaxial layers and the bonding surface of the support substrate, wherein the support substrate and the heterostructure epitaxial layers are configured to powderize together in response to a trigger.2. The article of claim 1 , wherein the heterostructure epitaxial layers are less than 10 μm thick.3. The article of claim 1 , wherein the electronic devices comprise one or more of a laser diode claim 1 , a light-emitting diode claim 1 , a diode claim 1 , a transistor claim 1 , a photodetector claim 1 , a light guide claim 1 , a semiconductor optical amplifier claim 1 , an electronic switch claim 1 , a field-effect device claim 1 , and a modulator.4. The article of claim 1 , wherein the electronic devices comprise one or more of GaAs claim 1 , InP claim 1 , Si claim 1 , and GaN-based electronic devices.5. The article of claim 1 , wherein the support substrate is chemically tempered glass.6. The article of claim 1 , wherein a growth substrate used to grow the heterostructure epitaxial ...

Digital printing plate and system with electrostatically latched deformable membranes

A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Impedance readout circuit and method having filter for determining an AC current component inversely proportional to the output impedance of a pixel

An impedance readout circuit receives an input signal from a pixel, or an array of pixels. The circuit includes an amplifier to amplify the input signal and detects a DC component of the input signal. The circuit establishes an AC sampling voltage at the output of the amplifier enabling a filter of the circuit to determine an AC current component of the amplifier output. The AC current component is inversely proportional to the output impedance of the pixel.

Printed circuit boards by massive parallel assembly

A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.

Microchip charge patterning

A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

High voltage thin film optical switch

A thin film optical switch includes a layer of photosensitive material that extends laterally with first and second electrodes are spaced apart laterally from one another along the layer of photo sensitive material. The first and second electrodes contact the photo sensitive material at first and second junctions, respectively. At least one field plate is electrically insulated from the photo sensitive material and extends laterally along the layer of photo sensitive material over the first or the second junction. The field plate is electrically connected to the first electrode or the second electrode.

METHOD FOR REDUCTION OF STICTION WHILE MANIPULATING MICRO OBJECTS ON A SURFACE

A system and method reduce stiction while manipulating micro objects on a surface. The system and method employed a field generator configured to generate a driving force at a frequency and amplitude to at least partially overcome stiction between the micro objects and the surface. The field generator is further configured to generate a manipulation force to manipulate the micro objects on the surface in two dimensions. The manipulation force is spatially programmable. 1. A system for manipulating micro objects , the system comprising:a surface upon which the micro objects are manipulated; and generate a driving force at a frequency and amplitude to at least partially overcome stiction between the micro objects and the surface; and', 'generate a manipulation force to manipulate the micro objects on the surface in two dimensions, the manipulation force being spatially programmable., 'a field generator configured to2. The system of claim 1 , wherein the micro objects are a few microns to 100s of microns in size.3. The system of claim 1 , wherein the field generator is further configured to:superimpose the driving force on the manipulation force to achieve motion of the micro objects.4. The system of claim 3 , wherein the driving force is superimposed on the manipulation force during only part of the manipulation force.5. The system of claim 3 , wherein the frequency and the amplitude of the driving force only partially overcomes stiction between the micro objects and the surface.6. The system of claim 5 , wherein the frequency and amplitude of the driving force control the amount of damping when the driving force is superimposed on the manipulation force.7. The system of claim 1 , wherein the frequency of the driving force is at least an order of magnitude greater than the frequency of the manipulation force.8. The system of claim 1 , wherein the driving force is a repeating step change in force or a repeating step pulse.9. The system of claim 1 , wherein the field ...

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Fabrication method for microelectronic components and microchip inks used in electrostatic assembly

Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material having a positive charge polarity is formed on a silicon wafer over previously-fabricated integrated circuits, then a sacrificial metal mask is patterned only over a portion of the charge-inducing material structure, and a second charge-inducing material structure (e.g., a self-assembling octadecyltrichlorosilane monolayer) is deposited having a negative charge polarity. The sacrificial metal mask is then removed to expose the masked portion of the first charge-inducing material structure, thereby providing the chiplet with both a positive charge polarity region and a negative charge polarity region.

Stressed Substrates For Transient Electronic Systems

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event. 1. A transient electronic device comprising:a stressed substrate including at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress and being operably integrally connected to the at least one tensile stress layer such that residual tensile and compressive stresses are self-equilibrating; anda trigger mechanism attached to the stressed substrate and including means for generating an initial fracture in said stressed substrate,wherein said residual tensile and compressive stresses are sufficient to generate secondary fractures in response to said initial fracture that propagate throughout said stressed substrate, whereby said stressed substrate is powderized.2. The transient electronic device of claim 1 , further comprising a functional layer including one or more electronic elements claim 1 , wherein the functional layer is bonded to the stressed substrate such that the ...

HIGH REGISTRATION PARTICLES-TRANSFERRING SYSTEM

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface. 1. A particles-transferring system comprising:a first substrate comprising a first surface to support a plurality of particles in a pattern;a particle transferring unit comprising an outer surface to be offset from the first surface by a first gap, wherein the particle transferring unit is to remove the plurality of particles from the first surface in response to the plurality of particles being within the first gap, wherein the particle transferring unit is to secure the plurality of particles in the pattern to the outer surface and is to transport the plurality of particles in the pattern; anda second substrate comprising a second surface to be offset from the outer surface by a second gap, wherein the second substrate is to remove the plurality of particles in the pattern from the particle transferring unit in response to the plurality of particles being within the second gap, wherein the plurality of particles is to be secured in the pattern to the second surface.2. The particles-transferring system of claim 1 , wherein ...

Spring structure with self-aligned release material

Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.

MICRO ASSEMBLER WITH FINE ANGLE CONTROL

An assembly surface has an array of electrodes arranged such that each of a plurality of chiplets can be positioned to cover at least one of the electrodes. A field generator applies a rotation field that is orthogonal to the clamping force field applied by the electrodes. A processor is operable to determine a desired orientation angle of a first subset of the chiplets and activate one or more of the electrodes so that a second subset of the chiplets different than the first subset is kept from rotating by a clamping force field applied by the one or more of the electrodes. While the clamping force field is being applied, the processor applies the rotation field at the selected angle to cause the first subset of the chiplets to be oriented at the desired orientation angle.

HIGH VOLTAGE THIN FILM OPTICAL SWITCH

A thin film optical switch includes a layer of photosensitive material that extends laterally with first and second electrodes are spaced apart laterally from one another along the layer of photo sensitive material. The first and second electrodes contact the photo sensitive material at first and second junctions, respectively. At least one field plate is electrically insulated from the photo sensitive material and extends laterally along the layer of photo sensitive material over the first or the second junction. The field plate is electrically connected to the first electrode or the second electrode.

RECTIFYING DEVICES AND FABRICATION METHODS

A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix. 1. An electronic field emission rectifier comprising:a substrate;a first metal layer disposed on the substrate and having a peripheral edge;a dielectric layer having a pattern and disposed on the first metal layer; anda second metal layer disposed on and having the pattern of the dielectric layer, wherein the pattern produces one or more edges of the dielectric and second metal layers, and wherein a total length of the one or more edges of the dielectric and second metal layers is at least about 50% greater than a length of the peripheral edge of the first metal layer.2. The device of claim 1 , wherein the one or more edges of the dielectric and second metal layers comprises a meandering peripheral edge that extends substantially across a rectifier area of the device.3. The device of claim 1 , wherein the length of the edges of the dielectric and second metal layers is at least about 100% greater than the length of the peripheral edge of the first metal layer.4. The device of claim 1 , wherein the one or more edges of the dielectric and second metal layers comprises multiple discrete edges within an outer peripheral edge of the dielectric and second metal layers.5. The device of claim 1 , wherein the one or more edges of the dielectric and second metal layers include an outer peripheral edge that extends substantially across a rectifier area of the rectifier.6. The device of claim 1 , wherein the one or more edges of the dielectric and second metal layers ...

PRINTED CIRCUIT BOARDS BY MASSIVE PARALLEL ASSEMBLY

A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. 1. A method of forming an interconnect substrate , comprising:providing at least two unit cells;arranging the unit cells to form a desired circuit pattern; andjoining the unit cells to form the interconnect substrate having the desired circuit pattern.2. The method of claim 1 , wherein at least one of the unit cells is only an insulator.3. The method of claim 1 , wherein at least one of the unit cells is an insulator with a conductive line on one side of the insulator.4. The method of claim 1 , wherein at least one of the unit cells is an insulator with a conductive line on both sides of the insulator.5. The method of claim 1 , wherein at least one of the unit cells is an insulator with conductive lines on both sides of the insulator claim 1 , and at least one via to electrically connect the lines together.6. The method of claim 1 , wherein arranging the unit cells comprises one of manipulating electrical fields claim 1 , manipulating magnetic fields claim 1 , manipulating surface energies claim 1 , using digitally addressed heaters claim 1 , digitally addressed solder melting claim 1 , laser addressed pick and place claim 1 , and micro-pick-and-place with adhesive.7. The method of claim 1 , wherein joining the two until cells comprises one of fusing claim 1 , sintering claim 1 , plating claim 1 , self-assembly of conductive lines claim 1 , shrinking a substrate upon which the unit cells reside claim 1 , expanding the unit cells and printing conductive lines to connect the unit cells.8. The method of claim 1 , wherein the unit cells are at least partially made up of a plastic and joining the two unit cells comprises cross-linking the plastic.9. The method of claim 1 , further comprising orienting the unit cells in ...

Rectifying devices and fabrication methods

A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.

High registration particles-transferring system

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

Stressed substrates for transient electronic systems

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during ...

MICROCHIP CHARGE PATTERNING

A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid. 1. A method of forming a charge pattern on a microchip , comprising:depositing a material on the surface of the microchip; andimmersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.2. The method of claim 1 , wherein depositing a material on the surface comprises depositing a thin film of the material.3. The method of claim 2 , wherein depositing the thin film comprises one of spin-coating claim 2 , printing claim 2 , dip-coating claim 2 , self-assembly claim 2 , or vapor deposition.4. The method of claim 1 , wherein immersing the microchip in a fluid to develop charge comprises immersing the microchip in a fluid and developing free charges through interaction with the fluid.5. The method of claim 1 , wherein depositing the material comprises surface deposition of a material having at least one of sulfonic acid claim 1 , phosphonic acid claim 1 , and carboxyllic acid functionality.6. The method of claim 1 , wherein depositing the material comprises depositing a material having at least one of amine and imidizole functionality.7. The method of claim 4 , wherein the fluid is a polar solution such as water.8. The method of claim 4 , wherein the fluid is a non-polar solution.9. The method of claim 8 , wherein the non-polar solution is one of an isopar series of liquids claim 8 , a hydrocarbon liquids claim 8 , or dodecane.10. The method of claim 8 , where the non-polar solution contains a charge-director added to the fluid claim 8 , wherein the charge-director comprises one of an amphiphilic material claim 8 , lecithin claim 8 , span-80 claim 8 , alohas claim 8 , OLOA claim 8 , or AOT.11. The method of claim 2 , wherein the material is one of either an anionic or ...

Transfer substrate utilizing selectable surface adhesion transfer elements

An apparatus includes a transfer substrate with two or more transfer elements. Each of the transfer elements includes an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature. The second surface adhesion less than the first surface adhesion. Each transfer element has a thermal element operable to change a temperature of the adhesion element in response to an input. A controller is coupled to provide the inputs to the thermal elements of the two or more transfer elements to cause a subset of the transfer elements to selectably hold objects to and release the objects from the transfer substrate in response to changes between the first and second surface adhesion of the subset of the transfer elements.

SEMICONDUCTOR-FREE VACUUM FIELD EFFECT TRANSISTOR FABRICATION AND 3D VACUUM FIELD EFFECT TRANSISTOR ARRAYS

A vacuum field-emission-transistor device, a drain comprised of either a metal or a semimetal material, a gate arranged adjacent to, but separated from, the drain, a source comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate, and a void through the metal drain and the metal gate to expose the drain, wherein the distance between the drain and the source is shorter than a mean free path distance of electrons in air. 1. A vacuum field-emission-transistor device , comprising:a drain electrode comprised of either a metal or a semimetal material;a metal gate arranged adjacent to, but separated from, the drain;a source electrode comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate; anda void through just the source and the metal gate to expose the drain, wherein the void is open to ambient atmosphere,wherein a distance between the drain and the source is shorter than a mean free path distance of electrons in ambient air and the distance between the metal gate and the source is less than half the distance between the metal gate and the drain.2. The device of claim 1 , further comprising an array of devices arranged adjacent to each other in a planar array.3. The device of claim 2 , wherein the drain of each device in the array of devices is held at a common voltage.4. The device of claim 1 , wherein the source and the drain are one of the group consisting of: graphene claim 1 , copper claim 1 , or gold.5. The device of claim 1 , wherein the gate is a self-limited oxidizing metal or semimetal.6. The device of claim 1 , wherein the gate is one of either aluminum or silicon.7. The device of claim 1 , wherein the source and drain have a coating to enhance their work function.8. A device claim 1 , comprising: a drain electrode formed from regions of metal or semimetal on a first dielectric film;', 'a gate formed on a second dielectric film arranged on the first dielectric film;', 'a ...

CONSTRUCTING 3-DIMENSIONAL PARTS USING ELECTROPHOTOGRAPHY

Systems and methods for constructing 3-dimensional (3D) parts are disclosed. A printing system may include a deposition system configured to print a plurality of 2-dimensional (2D) layers onto a plurality of carrier sheets. The printing system also includes a transferring system configured to transfer a 2D layer from a carrier sheet of the plurality of carrier sheets, onto the 3D part. The 3D part may be located on a base substrate. The printing system further includes a feed system configured to provide the plurality of carrier sheets from the deposition system to the transfer system in a successive fashion while maintaining the directionality of printing in the deposition and transferring systems.

TAG SYSTEM IMPLEMENTING A NORMAL-ON ANTENNA AND METHODS OF USE

Systems and methods for operating a tag system. The methods comprising: wirelessly communicating, from a tag, a first signal at a first frequency spectrum that allows a tag reader to detect the first signal, when the tag is not proximate to an antenna modulation marker or when the antenna modulation marker has a first orientation relative to the tag; and performing operations by the tag to wirelessly communicate a second signal at a second frequency spectrum that does not allow the tag reader to detect the first signal, when the tag is proximate to the antenna modulation marker or when the antenna modulation marker has a second different orientation relative to the tag.

MICROCHIP CHARGE PATTERNING

A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and using an external device to develop charge in the material.

GATED CO-PLANAR POLY-SILICON THIN FILM DIODE

A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. 1. A thin-film diode , comprising:a first contact of a material having a first conductivity type;a second contact of a material having a second conductivity type arranged co-planarly with the first contact;a channel arranged between the first and second contacts;a gate arranged adjacent the channel; anda voltage source electrically connected to the gate.2. The diode of claim 1 , wherein the material having a first conductivity type comprises one of either n-doped poly-silicon claim 1 , p-doped polysilicon or amorphous silicon.3. The diode of claim 1 , wherein the channel comprises poly-silicon.4. The diode of claim 1 , wherein the first and second contacts and the channel comprise one layer of either poly-silicon or amorphous silicon having selectively doped regions.5. ...

POLARIZATION CONTROLLED TRANSISTOR

A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction. 1. A transistor comprising:a first layer comprising a group III-nitride semiconductor;a second layer comprising a group III-nitride semiconductor disposed over the first layer;a third layer comprising a group III-nitride semiconductor disposed over the second layer, an interface between the second layer and the third layer forming a polarization heterojunction;a fourth layer comprising a group III-nitride semiconductor disposed over the third layer, an interface between the third layer and the fourth layer forming a pn junction;a first electrical contact pad disposed on the fourth layer;a second electrical contact pad disposed on the third layer;a third electrical contact pad electronically coupled to bias the polarization heterojunction.2. The transistor of claim 1 , wherein the second layer is n-doped claim 1 , the third layer is n-doped and the fourth layer is p-doped.3. The transistor of claim 2 , wherein a doping concentration of n-doped layers on the order of 10to 10cmand a doping concentration of p-doped layers on the order of 10to 10cm.4. The transistor of claim 1 , wherein a distance between the pn junction and the polarization heterojunction is between 25 nm and 500 nm.5. The transistor of claim 1 , wherein ...

CONSTRUCTING 3-DIMENSIONAL PARTS USING ELECTROPHOTOGRAPHY

Systems and methods for constructing 3-dimensional (3D) parts are disclosed. A printing system may include a deposition system configured to print a plurality of 2-dimensional (2D) layers onto a plurality of carrier sheets. The printing system also includes a transferring system configured to transfer a 2D layer from a carrier sheet of the plurality of carrier sheets, onto the 3D part. The 3D part may be located on a base substrate. The printing system further includes a feed system configured to provide the plurality of carrier sheets from the deposition system to the transfer system in a successive fashion while maintaining the directionality of printing in the deposition and transferring systems. 1. A system for producing a 3-dimensional (3D) part , the system comprising:a deposition system configured to print a plurality of 2-dimensional (2D) layers onto a plurality of carrier sheets, wherein the plurality of carrier sheets move through the deposition in a direction;a transferring system configured to transfer at least one 2D layer from at least one carrier sheet of the plurality of carrier sheets, onto the 3D part, wherein the 3D part is located on a base substrate; anda feed system configured to provide the plurality of carrier sheets from the deposition system to the transfer system.2. The system of claim 1 , wherein:the deposition system is further configured to successively print the plurality of 2D layers onto the plurality of carrier sheets without changing the direction of the plurality of carrier sheets during a deposition process; andthe transfer system is configured to successively print the plurality of 2D layers onto the 3D part without changing the direction of the plurality of carrier sheets during a transfer process; andthe feed system is configured to maintain the directionality of motion of the carrier sheets in the deposition and transfer systems and produce the 3D part without reversing the print and transfer processing directions for the ...

PATTERN-WISE DEPOSITION OF ANTI-SINTERING AGENTS VIA SURFACE ENERGY MODULATION FOR 3D PRINTING

A system has a surface, a feedstock deposition head arranged to deposit a sinterable feedstock having a binder on the surface, a patterning system arranged adjacent the surface to change the feedstock surface energy according to a pattern to form selective surface energy patterns on the feedstock, a sintering-selectivity material deposition head arranged adjacent the feedstock deposition head to deposit sintering-selectivity fluid, the sintering-selectivity fluid selected to conform to the selective surface energy patterns, and a sintering chamber to sinter the feedstock after deposition of the anti-sintering agent. A method of forming three-dimensional objects includes depositing a, sinterable feedstock onto a surface, forming a surface energy pattern in the sinterable feedstock by pattern-wise debinding of the binder from the sinterable feedstock, depositing a sintering-selectivity fluid mixed with a solvent selected to cause the sintering-selectivity material to conform to the surface energy pattern, and sintering the feedstock. 1. A system , comprising:a surface;a feedstock deposition head arranged to deposit a sinterable feedstock having a binder on the surface;a patterning system arranged adjacent the surface to change the feedstock surface energy according to a pattern to form selective surface energy patterns on the feedstock;a sintering-selectivity material deposition head arranged adjacent the feedstock deposition head to deposit sintering-selectivity fluid, the sintering-selectivity fluid selected to conform to the selective surface energy patterns; anda sintering chamber to sinter the feedstock after deposition of the anti-sintering agent.2. The system as claimed in claim 1 , wherein the patterning system comprises one of a patterning laser claim 1 , grating light valve claim 1 , digital micromirror device claim 1 , ion claim 1 , electron or particle bombardment system claim 1 , a plasma treatment system claim 1 , oxygen plasma treatment system claim 1 , ...

SCALABLE HIGH-VOLTAGE CONTROL CIRCUITS USING THIN FILM ELECTRONICS

A device includes a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor. 1. A device , comprising: a first optical switch;', 'a first transistor connected to the first optical switch; and', 'a second transistor connected to the first optical switch and the first transistor; and, 'a first stage comprising a second optical switch;', 'a third transistor connected to the second transistor and the second optical switch; and', 'a fourth transistor connected to the second transistor, the second optical switch, and the third transistor., 'a second stage comprising2. The device of claim 1 , wherein the first optical switch comprises a semiconductor with two terminal contacts claim 1 , wherein the semiconductor comprises hydrogenated amorphous silicon (a-Si:H) claim 1 , and wherein the terminal contacts form a Schottky barrier to the semiconductor.3. The device of claim 1 , wherein the first optical switch comprises a semiconductor with two terminal contacts claim 1 , wherein the semiconductor comprises an organic material claim 1 , a metal oxide claim 1 , or a combination thereof.4. The device of claim 1 , wherein the second transistor comprises a source claim 1 , a gate claim 1 , and a drain claim 1 , and wherein the gate of the second transistor is controlled by the first optical switch.5. The device of claim 4 , wherein the second transistor comprises:a thin-film transistor (TFT) with an ungated channel region between the gate and the drain; andone or more field plates between the gate and the drain.6. The device of claim 1 , wherein the first and second optical switches ...

Scalable high-voltage control circuits using thin film electronics

A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor serves as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor serves as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor.

Digital 3D Fabrication Using Multi-Layered Mold

A replica 3D structure is fabricated inside a multi-layered mold by patterning each mold layer to define a void/opening that matches a corresponding cross section of the structure's peripheral surface, and filling the patterned opening of each layer with a structural material (i.e., before depositing a subsequent layer of mold material). The mold material (e.g., photoresist or another dissolvable sacrificial material) is blanket deposited (e.g., by slot-die, spray coating) and then patterned using a laser or a printed mask. Each layer of modeling material (e.g., polymer, ceramic or metal, or a combination thereof) is electro-plated or otherwise deposited on the previously formed modeling material layer. High vertical resolution is achieved by utilizing relatively thin mold layers. The mold layer deposition, patterning and modeling material deposition is repeated until the replica 3D structure is entirely formed inside the multi-layered mold, and then the mold is dissolved or otherwise removed. 1. A method for fabricating a three dimensional (3D) structure , the method comprising:sequentially depositing a plurality of mold material layers such that the plurality of mold material layers collectively form a multi-layer mold;individually patterning each of the plurality of mold material layers in accordance with a digital description such that each said mold material layer defines a void portion; anddepositing a modeling material portion into each said void portion such that each said modeling material portion fills an associated void portion before depositing a subsequent mold material layer of said plurality of mold material layers, and such that said modeling material portions disposed in said plurality of mold material layers collectively form said 3D structure.2. The method of claim 1 , wherein sequentially depositing said plurality of mold material layers comprises depositing photoresist.3. The method of claim 1 , wherein sequentially depositing said plurality of ...

Fabrication Method For Microelectronic Components And Microchip Inks Used In Electrostatic Assembly

Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material (e.g., SiO 2 ) having a first (e.g., positive) charge polarity is formed on a silicon wafer over previously-fabricated integrated circuits (ICs), then a sacrificial metal mask (e.g., MoCr) is patterned only over a portion of the charge-inducing material structure, and a second charge-inducing material structure (e.g., a self-assembling octadecyltrichlorosilane (OTS) monolayer) is deposited having a second (e.g., negative) charge polarity. The sacrificial metal mask is then removed to expose the masked portion of the first charge-inducing material structure, thereby providing the chiplet with both a positive charge polarity region and a negative charge polarity region.

DIRECT ELECTROSTATIC ASSEMBLY WITH CAPACITIVELY COUPLED ELECTRODES

A system and method manipulate micro objects. A field generator is configured to generate a force field varying in both space and time to manipulate the micro objects on a substrate. The substrate is not permanently affixed to the field generator and allows the force field to pass through the substrate. 1. A system for manipulating micro objects , said system comprising:a field generator configured to generate a force field varying in both space and time to manipulate the micro objects; anda substrate upon which the micro objects are manipulated by the field generator, wherein the substrate is not permanently affixed to the field generator and wherein the substrate allows the force field to pass through the substrate.2. The system of claim 1 , wherein the force field is an electric field.3. The system of claim 2 , wherein the field generator includes a plurality of electrodes for generating the electric field.4. The system of claim 2 , wherein the field generator includes a photosensitive material for generating the electric field.5. The system of claim 2 , wherein the substrate is an electrically insulating material.6. The system of claim 5 , wherein the substrate is a polymer or a ceramic.7. The system of claim 1 , wherein the force field is a magnetic field.8. The system of claim 7 , wherein the field generator includes a plurality of coils for generating the magnetic field.9. The system of claim 7 , wherein the substrate is a non-ferromagnetic or paramagnetic material.10. The system of claim 1 , further including:a second substrate; anda device transferring the micro objects from the substrate to the second substrate in a manner that preserves the relative positions and orientations of the micro objects.11. The system of claim 1 , further including:a fixation device configured to fix the micro objects to the substrate.12. The system of claim 11 , wherein the micro objects are fixed to the substrate by at least one of:localized heating of the substrate;localized ...

CAPACITIVE IMAGING DEVICE WITH ACTIVE PIXELS AND METHOD

A capacitive image sensor includes a sensor array having capacitive image pixels. Each pixel has a two-transistor configuration including a pixel selection transistor and a source follower transistor. The pixel selection transistor activates the source follower transistor. The source follower is coupled to a variable capacitance that affects an input impedance of the source follower. An AC current is source is used to interrogate the activated source follower to determine an output impedance of the source follower. The output impedance is a function of the input impedance and the output impedance is representative of the nearness of an object. 1. A capacitive image pixel , comprising:a two-transistor configuration having a pixel selection transistor that activates a source follower transistor, wherein the source follower transistor is coupled to a variable capacitance affecting an input impedance of the source follower transistor and wherein an AC current source is used to interrogate the activated source follower transistor to determine an output impedance of the source follower transistor, wherein the output impedance is a function of the input impedance, and wherein the output impedance is representative of the nearness of an object.2. The capacitive image pixel of claim 1 , wherein the variable capacitance varies in accordance with the nearness of the object claim 1 , wherein the object is affective in altering capacitance.3. The capacitive image pixel of claim 1 , further comprising a DC current source.4. The capacitive image pixel of claim 3 , wherein the DC current source sets a working bias point.5. The capacitive image pixel of claim 1 , wherein the AC current source provides a known amplitude and frequency.6. The capacitive image pixel of claim 1 , wherein the capacitive image pixel is implemented with thin film technology.7. The capacitive image pixel of claim 1 , wherein the AC current source provides a sinusoidal signal or a square-wave signal.8. A ...

Impedance readout circuit and method

An impedance readout circuit receives an input signal from a pixel, or an array of pixels. The circuit includes an amplifier to amplify the input signal and detects a DC component of the input signal. The circuit establishes an AC sampling voltage at the output of the amplifier enabling a filter of the circuit to determine an AC current component of the amplifier output. The AC current component is inversely proportional to the output impedance of the pixel.

Integrateable capacitors and microcoils and methods of making thereof

Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom electrode structure to removing a suspension portion of a moveable top electrode from an RF part of a circuit.

Method and system for assembly of micro-leds onto a substrate

MicroLED chips are transferred from an epitaxy wafer to a first coupon substrate. The first coupon substrate has a first, soft adhesive layer that temporarily holds the microLED chips. Using a first transfer substrate, a subset of the microLED chips are transferred from the first coupon substrate to a second coupon substrate having a second, soft adhesive layer. A pattern of microLED chips are transferred from another substrate to the second coupon substrate via a second transfer substrate to fill vacancies in the subset of microLED chips. The transfer substrates are operable to hold and release pluralities of micro objects.

Direct electrostatic assembly with capacitively coupled electrodes

A system and method manipulate micro objects. A field generator is configured to generate a force field varying in both space and time to manipulate the micro objects on a substrate. The substrate is not permanently affixed to the field generator and allows the force field to pass through the substrate.

Transfer substrate utilizing selectable surface adhesion transfer elements

An apparatus includes a transfer substrate with two or more transfer elements. Each of the transfer elements includes an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature. The second surface adhesion less than the first surface adhesion. Each transfer element has a thermal element operable to change a temperature of the adhesion element in response to an input. A controller is coupled to provide the inputs to the thermal elements of the two or more transfer elements to cause a subset of the transfer elements to selectably hold objects to and release the objects from the transfer substrate in response to changes between the first and second surface adhesion of the subset of the transfer elements

Scalable high-voltage control circuits using thin film electronics

A device includes a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.

Fountain jet image formation on charged image surface

A system and method for creating a fountain solution pattern for digital imaging, can include a charge image bearing surface bearing a charge image, an array of insulated channels, wherein a fountain solution can enter and fills the array of insulated channels by capillary action to a ledge region of the insulated channels in the array of insulated channels, and a scorotron that charges a surface of the fountain solution in the array of insulated channels. The array of insulated channels can be moved into proximity with the charge image on the charge image bearing surface of a digital printer, such that a fountain solution pattern can be developed on the charge image bearing surface with a measured amount of the fountain solution.

High registration particles-transferring system

Disclosed herein are techniques for transferring particles in a pattern. In one implementation, a particle-transferring system includes a first substrate comprising a first surface configured to support a plurality of particles in a non-uniform pattern, and a particle transfer unit configured to remove the plurality of particles from the first surface in response to the plurality of particles being within a first gap. The system also includes a second substrate configured to remove the plurality of particles from the particle transfer unit and secure the plurality of particles to the second surface in response to the plurality of particles being within a second gap. The particle transfer unit is configured to transfer the plurality of particles and maintain the non-uniform pattern regardless of the positions of the plurality of particles, which are not predefined to fit features of the particle transfer unit.

透過性を有するオプティカル・カプラのアクティブ・マトリクス・アレイ

【課題】アドレス指定する面から作動および検知を行うバックプレーンを提供する。 【解決手段】バックプレーンは、バックプレーンの出力面上に配列される出力端子のアレイと、それぞれが出力端子のうちの１つに対応する、ソリッドステートの光スイッチのアレイであって、ソリッドステートの光スイッチが制御波長の光に反応し、検知波長の光に対して透過性を有する、ソリッドステートの光スイッチのアレイとを含み、制御波長とは異なる検知波長の光に対して透過性を有する材料から成る。光学システムは、オプティカル・カプラのアレイを有するバックプレーンと、オプティカル・カプラが反応する制御波長の光を生成するプロジェクタと、制御光をバックプレーン上の前記オプティカル・カプラのアレイに誘導するための光学系と、検知波長の光に反応する画像形成システムと、を含み、このバックプレーンは、少なくとも部分的に前記検知波長に対して透過性を有する。 【選択図】図７

マイクロチップの電荷パターン形成

【課題】マイクロチップ上に形成したデバイスの貯蔵寿命が長くなるように、良好な安定性を有している電荷パターン形成することができるシステムを提供する。 【解決手段】マイクロチップ１２表面に物質を堆積させることと；該マイクロチップを流体に浸漬して、周囲の流体との相互作用によって前記物質中または前記物質上に電荷を発生させることとを含む。チップ加工に適合する製造技術を用い、製造したマイクロチップ１２は、チップ上の回路を保護するためにシールド１４を有している。シールドは、絶縁体１６を有する。絶縁体によって、表面に堆積した電荷または物質パターンが、マイクロチップ上の回路と相互作用を起こすのを防ぐことができる。ＡＢＢＡＢというパターンは、例えば、＋−−＋−といった異なる電荷を表していてもよく、または電荷が発生するような物質パターンを表していてもよい。 【選択図】図２

Pattern-wise deposition of anti-sintering agents via surface energy modulation for 3d printing

A system has a surface, a feedstock deposition head arranged to deposit a sinterable feedstock having a binder on the surface, a patterning system arranged adjacent the surface to change the feedstock surface energy according to a pattern to form selective surface energy patterns on the feedstock, a sintering-selectivity material deposition head arranged adjacent the feedstock deposition head to deposit sintering-selectivity fluid, the sintering-selectivity fluid selected to conform to the selective surface energy patterns, and a sintering chamber to sinter the feedstock after deposition of the anti-sintering agent. A method of forming three-dimensional objects includes depositing a, sinterable feedstock onto a surface, forming a surface energy pattern in the sinterable feedstock by pattern-wise debinding of the binder from the sinterable feedstock, depositing a fluid comprising a sintering-selectivity material mixed with a solvent selected to cause the sintering-selectivity material to conform to the surface energy pattern, and sintering the feedstock.

Apparatus for continuous high-speed 3D printing

A printing system for producing at least one three dimensional (3D) printed part is described. The printing system includes a deposition system configured to continuously deposit a layer onto a cylinder to outwardly extend a diameter of the cylinder, wherein the layer comprises a first pattern. The printing system also includes a rotating system configured to rotate the cylinder, and a control system configured to synchronize the deposition system with the cylinder.

Methods and systems for producing a three-dimensional part

Micro assembler with fine angle control

An assembly surface has an array of electrodes arranged such that each of a plurality of chiplets can be positioned to cover at least one of the electrodes. A field generator applies a rotation field that is orthogonal to the clamping force field applied by the electrodes. A processor is operable to determine a desired orientation angle of a first subset of the chiplets and activate one or more of the electrodes so that a second subset of the chiplets different than the first subset is kept from rotating by a clamping force field applied by the one or more of the electrodes. While the clamping force field is being applied, the processor applies the rotation field at the selected angle to cause the first subset of the chiplets to be oriented at the desired orientation angle.

Micro assembler with fine angle control

First and second chiplets are positioned along a surface to respectively cover first and second electrodes. The first electrode is activated to cause an attraction force between the first electrode and the first chiplet. The second electrode is deactivated allowing the second chiplet to rotate on the surface. While the first electrode is activated and the second electrode is deactivated, a rotation field is applied to cause the second chiplet to be oriented at a desired orientation angle, the first chiplet being prevented from rotating by the attraction force.

Micro assembler with fine angle control

First and second chiplets are positioned along a surface to respectively cover first and second electrodes. The first electrode is activated to cause an attraction force between the first electrode and the first chiplet. The second electrode is deactivated allowing the second chiplet to rotate on the surface. While the first electrode is activated and the second electrode is deactivated, a rotation field is applied to cause the second chiplet to be oriented at a desired orientation angle, the first chiplet being prevented from rotating by the attraction force.

Micro assembler with fine angle control

First and second chiplets are positioned along a surface to respectively cover first and second electrodes. The first electrode is activated to cause an attraction force between the first electrode and the first chiplet. The second electrode is deactivated allowing the second chiplet to rotate on the surface. While the first electrode is activated and the second electrode is deactivated, a rotation field is applied to cause the second chiplet to be oriented at a desired orientation angle, the first chiplet being prevented from rotating by the attraction force.

Micro assembler with fine angle control

薄膜電子部品を使用するスケーラブルな高電圧制御回路

【課題】スケーラブルな高電圧制御回路を提供する。 【解決手段】ＥＭＳアクチュエータを駆動するための高電圧スイッチングデバイスは、第１のソースと、第１のゲートと、第１のドレインと、１つ以上の電極と、を有する第１のトランジスタ１２０Ａ～１２０Ｊを含む。第１のトランジスタは、インバータとしての役割を果たす。デバイスはまた、第２のソースと、第２のゲートと、第２のドレインと、を有する第２のトランジスタ１４０Ａ～１４０Ｊも含む。第１のソース及び第２のソースは、一緒に接続される。第１のドレイン及び第２のドレインは、一緒に接続される。第２のトランジスタは、出力、ドライバ又はその両方としての役割を果たす。１つ以上の電極、第２のゲート又はこれらの組み合わせは、第２のトランジスタのステップ電圧をサンプリングするタップ付きドレインとしての役割を果たす。 【選択図】図１

Heat image forming device and method

A heating circuit having an array of switching heating elements (e.g., field effect transistors, thin film transistors) provides a transient heat pattern over a surface (e.g., substrate, imaging member surface, transfer roll surface) moving relative to the heating circuit, to produce a pixelated heat image and heat a target pattern on the surface. Heat is generated by current flow in the heating elements, and the power developed by the heating circuit is the product of source-drain voltage and current in the channel. Digital addressing may accomplished by matrix addressing the array. Current may be supplied along data address lines by an external voltage controlled by digital electronics understood by a skilled artisan to provide the desired heat at a respective heating element pixels addressed by a specific gate line. The circuit may include a current return line that may be low resistance, for example, by using a 2-dimensional mesh.

Constructing 3-dimensional parts using electrophotography

Systems and methods for constructing 3-dimensional (3D) parts are disclosed. A printing system may include a deposition system configured to print a plurality of 2-dimensional (2D) layers onto a plurality of carrier sheets. The printing system also includes a transferring system configured to transfer a 2D layer from a carrier sheet of the plurality of carrier sheets, onto the 3D part. The 3D part may be located on a base substrate. The printing system further includes a feed system configured to provide the plurality of carrier sheets from the deposition system to the transfer system in a successive fashion while maintaining the directionality of printing in the deposition and transferring systems.

Polarization controlled transistor

A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.

High registration particles-transferring system

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

Secondary roller for fountain solution contact angle pinning

Ink-based digital printing systems useful for ink printing include a secondary roller having a rotatable reimageable surface layer configured to receive fountain solution. The fountain solution layer is patterned on the secondary roller and then partially transferred to an imaging blanket, where the fountain solution image is inked. The resulting ink image may be transferred to a print substrate. To achieve a very high-resolution (e.g., 1200-dpi, over 900-dpi) print with these secondary roller configurations, an equivalent very high-resolution fountain solution image needs to be transferred from the secondary roller onto the imaging blanket. To increase the resolution of the image on the secondary roller, examples include a textured surface layer added to the secondary roller for contact angle pinning the fountain solution on the roll. Approaches to introduce a micro-structure onto the surface layer of the secondary roller, and also superoleophobic surface coatings are described.

Matrix-addressed heat image forming device

Based on evaporation of fountain solution from a rotating blanket cylinder to create an image that may be inked and printed, a digitally addressable heater array at or just below the blanket surface evaporates deposited fountain solution and forms a fountain solution latent image on the surface. The heater array has controllable heating elements (e.g., field effect transistors, thin film transistors) that provide a transient heat pattern on the surface to evaporate the fountain solution. Heat is generated by current flow in the heating elements, and power developed by the heating circuit is the product of source-drain voltage and current in the channel. Current may be supplied along data lines by an external voltage controlled by digital electronics to provide the desired heat at heating elements addressed by a specific gate line. The heater array may include a current return line that may be a 2-dimensional mesh.

３ｄプリントのための表面エネルギー変調を介した抗焼結剤のパターン式堆積

【課題】焼結可能な凝集性の高密度供給原料の３Ｄプリントシステム、および焼結可能な凝集性の高密度供給原料による三次元オブジェクトを形成する方法を提供する。 【解決手段】システムは、表面と、バインダを有する焼結可能な供給原料を表面上に堆積させるように配置された供給原料堆積ヘッドと、表面に隣接して配置されて、パターンに従って供給原料表面エネルギーを変化させて、供給原料上に選択的表面エネルギーパターンを形成するパターン化システムと、供給原料堆積ヘッドに隣接して配置されて、焼結選択性流体を堆積させる焼結選択性材料堆積ヘッドと、選択的表面エネルギーパターンに適合するように選択される焼結選択性流体と、抗焼結剤の堆積後に供給原料を焼結するための焼結チャンバと、を有する。 【選択図】図１

Transfer substrate utilizing selectable surface adhesion transfer elements

デジタルコンピュータのａｉｄを用いた機械学習対応マイクロアセンブリ制御のためのシステム及び方法

【課題】リアルタイムで実装することができる様々な形状の微小物体のアセンブリを制御する拡張可能な方法及びシステムを提供する。【解決手段】システムにおいて、物体を操作するための動的ポテンシャルエネルギー地形は、電極１２のアレイ３５内の電極の各々を制御することによって生成される。１つ以上のコンピューティングデバイス１６は、高速カメラ１５又は容量検知などの物体の位置を追跡するセンサを使用して、微小物体の初期位置を推定することと、電極の少なくともいくつかによって生成された電極電位による微小物体の動きのための動的モデルの連続表現を生成し、動的モデル上の自動分化及びガウス求積法を使用して、微少物体を所望の位置に移動させるために電極によって生成される最適な電位を導出することと、計算された最適化された電極電位をアレイにマッピングして、電極を作動させることと、を行うために使用される。【選択図】図１

薄膜オプトカプラを使用して形成されるアクティブマトリクスバックプレーン

【課題】薄膜オプトカプラを使用して形成されるアクティブマトリックスバックプレーンを提供する。【解決手段】デバイスは、バックプレーンであって、バックプレーンの出力面上にアレイ状に配置されている複数の出力端子２３０を有する、バックプレーンを含む。デバイスは、それぞれバックプレーンの入力端子と出力端子との間に結合されている、薄膜ソリッドステート光スイッチ２２０を備えるアクティブマトリクスアレイをさらに含む。蓄積容量がそれぞれ出力端子に結合され得る。ピクセル化光源が、光スイッチを制御するピクセル化光である。【選択図】図２

Method of continuous high-speed 3d printing

A method of providing high-speed three dimensional (3D) printing is described. The method includes producing at least one three dimensional (3D) printed part. Producing the 3D part includes continuously constructing to extend outwardly a diameter of a rotating cylindrical core via continuous deposition of a layer, and defining a first pattern in the continuously deposited layer corresponding to a cross-section of the at least one 3D printed part.

Method of continuous high-speed 3D printing

A method of providing high-speed three dimensional (3D) printing is described. The method includes producing at least one three dimensional (3D) printed part. Producing the 3D part includes continuously constructing to extend outwardly a diameter of a rotating cylindrical core via continuous deposition of a layer, and defining a first pattern in the continuously deposited layer corresponding to a cross-section of the at least one 3D printed part.

Switching device for driving an actuator

A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor serves as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor serves as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor.

Micro-assembler system for manipulating micro-objects

Method of controlling the placement of micro-objects on a micro-assembler

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

微小物体を操作するためのマイクロアセンブラシステム

【課題】様々なデバイスの製造において、使用され得る微粒子等の微小物体の配列方法を提供する。【解決手段】マイクロアセンブラ１１０の表面上の微小物体１２０の配置を制御する方法及びシステム１００が開示される。制御パターンを使用して、マイクロアセンブラ１１０の電極に、マイクロアセンブラ１１０の表面上の１つ以上の微小物体１２０を操作、移動、位置付け、又は配向させるために使用され得る、誘電泳動（ｄｉｅｌｅｃｔｒｏｐｈｏｒｅｔｉｃ、ＤＥＰ）力及び電気泳動（ｅｌｅｃｔｒｏｐｈｏｒｅｔｉｃ、ＥＰ）力を発生させることができる。制御パターンは、制御パターンのライブラリの一部であり得る。【選択図】図１

微小物体の配置を制御するためのマイクロアセンブラシステム

【課題】様々なデバイスの製造において、様々な目的で使用される微粒子等の微小物体の配列方法を提供する。【解決手段】マイクロアセンブラ１１０の表面上の微小物体１２０の配置を制御する方法及びシステム１００。制御パターンを使用して、マイクロアセンブラ１１０のフォトトランジスタ又は電極に、マイクロアセンブラ１１０の表面上の１つ以上の微小物体１２０を操作、移動、位置付け、又は配向させるために使用され得る、誘電泳動（ＤＥＰ）力及び電気泳動（ＥＰ）力を発生させる。【選択図】図１

Method of controlling the placement of micro-objects on a micro-assembler

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

デジタルコンピュータを用いたマイクロアセンブリ制御で使用する機械学習ベースの位置推定のためのシステム及び方法

【課題】デジタルコンピュータを用いたマイクロアセンブリ制御で使用するための機械学習ベースの位置推定のためのシステム及び方法を提供する。【解決手段】物理学ベースのモデル及び機械学習モデルの両方を含むハイブリッドモデルを使用する、微小物体が移動する位置の予測において、制御ループ待ち時間が考慮に入れられる。モデルは、勾配ブースティングを使用し、訓練データとの比較に基づいて、以前の段階の間に計算された残差に基づいて適合される。各段階の損失関数は、作成されているモデルに基づいて選択される。ハイブリッドモデルは、過剰適合を防止し、十分な予測能力を有するために、訓練データから外挿及び内挿されたデータで評価される。物理学ベースのモデル及び機械学習モデルの両方を含めることにより、ハイブリッドモデルは、微小物体の動きに関与する決定論的構成要素及び確率論的構成要素の両方を考慮に入れることができる。【選択図】図１

Micro-assembler system for controlling placement of micro-objects

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler.

Digital printing plate and system with electrostatically latched deformable membranes

A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

薄膜電子部品を使用するスケーラブルな高電圧制御回路

【課題】スケーラブルな高電圧制御回路を提供する。【解決手段】高電圧スイッチングデバイス１００は、光スイッチ１１０Ａ～１１０Ｊと、各光スイッチに接続された第１のトランジスタ１２０Ａ～１２０Ｊと、各光スイッチ及び各トランジスタに接続された第２のトランジスタ１４０Ａ～１４０Ｊと、を有する第１の段を含む。本デバイスはまた、第２の光スイッチを有する第２の段と、第２のトランジスタ及び第２の光スイッチに接続された第３のトランジスタと、第２のトランジスタ、第２の光スイッチ、及び第３のトランジスタに接続された第４のトランジスタと、を含む。【選択図】図１

Digital printing plate and system with electrostatically latched deformable membranes

A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.

Transfer elements that selectably hold and release objects based on changes in stiffness

Secondary roller for fountain solution contact angle pinning

Ink-based digital printing systems useful for ink printing include a secondary roller having a rotatable reimageable surface layer configured to receive fountain solution. The fountain solution layer is patterned on the secondary roller and then partially transferred to an imaging blanket, where the fountain solution image is inked. The resulting ink image may be transferred to a print substrate. To achieve a very high-resolution (e.g., 1200-dpi, over 900-dpi) print with these secondary roller configurations, an equivalent very high-resolution fountain solution image needs to be transferred from the secondary roller onto the imaging blanket. To increase the resolution of the image on the secondary roller, examples include a textured surface layer added to the secondary roller for contact angle pinning the fountain solution on the roll. Approaches to introduce a micro-structure onto the surface layer of the secondary roller, and also superoleophobic surface coatings are described.

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Systems and methods for biasing high fill-factor sensor arrays and the like

A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in the invention allows to achieve mass production of photosensors without the use of wire bonding.