POWER SUPPLY MANAGEMENT CIRCUIT UTILIZING MULTISTAGE ACTIVATION AND RELATED MANAGEMENT METHOD

A management circuit for a power supply is provided. The power supply includes a power factor correction circuit and a power conversion circuit. An output of the power factor correction circuit is coupled to an input of the power conversion circuit. The management circuit includes a power factor correction controller, a pulse width modulation controller and a control circuit. The power factor correction controller controls power factor correction of the power factor correction circuit. The pulse width modulation controller controls power conversion of the power conversion circuit. The control circuit selectively activates the pulse width modulation controller according to a first activated signal generated by an input power of the power supply. After the pulse width modulation controller is activated, the control circuit generates a second activated signal based on the first activated signal. The control circuit activates the power factor conversion controller according to the second activated signal.

Snubber circuit and buffering method for snubber circuit

A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.

Snubber circuit and method of using bipolar junction transistor in snubber circuit

A snubber circuit includes: a capacitor including a first terminal and a second terminal, where the first terminal of the capacitor is electrically connected to a first terminal of the snubber circuit; and a Bipolar Junction Transistor (BJT), where one of the emitter and the collector of the BJT is electrically connected to the second terminal of the capacitor, and the other one of the emitter and the collector of the BJT is electrically connected to a second terminal of the snubber circuit. The snubber circuit can be electrically connected in parallel to an active component or a load to protect the circuitry connected to the load, and more particularly to absorb spike or noise generated during high-frequency switching of the active component to recycle energy, in order to achieve the goal of reducing spike voltages and enhancing efficiency.

POWER ADAPTER

A power adapter including a main circuit board and an auxiliary circuit board is provided. The main circuit board has a first surface and a second surface opposite to each other, and the first surface of the main circuit board is configured with a transformer and a first capacitor. The auxiliary circuit board has a first surface and a second surface opposite to each other, and the first surface of the auxiliary circuit board is configured with an input rectifier filter circuit, where the auxiliary circuit board is disposed in parallel above the main circuit board, and the input rectifier filter circuit of the auxiliary circuit board is electrically connected to the first capacitor of the main circuit board. Under a condition of same electrical parameters and dimensions, the volume of the power adapter of the invention is only a half of that of the existing power adapter, which satisfies a demand for miniaturization of the electronic devices. 1. A power adapter , comprising:a main circuit board, having a first surface and a second surface opposite to each other, wherein the first surface of the main circuit board is configured with a transformer and a first capacitor; andan auxiliary circuit board, having a first surface and a second surface opposite to each other, wherein the first surface of the auxiliary circuit board is configured with an input rectifier filter circuit,wherein the auxiliary circuit board is disposed in parallel above the main circuit board, and the input rectifier filter circuit of the auxiliary circuit board is electrically connected to the first capacitor of the main circuit board.2. The power adapter as claimed in claim 1 , wherein the first surface of the main circuit board is further configured with a first inductor and an output terminal claim 1 , the transformer claim 1 , the first inductor claim 1 , and the output terminal are disposed adjacent to the first capacitor and are electrically connected to each other claim 1 , and the ...

MAGNETIC ELEMENT

A magnetic element of the present invention includes a magnetic core member and a winding. The magnetic core member includes a central post, at least one lateral post and a winding space, and the winding is disposed in the winding space and around the central post. The central post includes a plurality of central air gaps, and the at least one lateral post includes a plurality of lateral air gaps.

Power detection and transmission circuit coupling analog input signal on primary side to secondary side for power information calculation and related power supply apparatus

A power detection and transmission circuit is provided. The power detection and transmission circuit includes a first conversion circuit, a second conversion circuit and a signal coupling circuit. The first conversion circuit is electrically connected to a power supply module to receive an analog input signal, and is arranged for converting the analog input signal to a first pulse width modulation (PWM) signal. The second conversion circuit is arranged for converting a second PWM signal to an analog regenerated signal, and transmitting the analog regenerated signal to a microcontroller, wherein the microcontroller calculates power information of the power supply module according to the analog regenerated signal. The signal coupling circuit is coupled between the first conversion circuit and the second conversion circuit, and is arranged for coupling the first PWM signal to the second conversion circuit and accordingly generating the second PWM signal.

MANUFACTURING METHOD OF MAGNETIC ELEMENT

A manufacturing method of a magnetic element includes the following steps: forming a block including a central post and at least one lateral post with magneto-conductive materials; cutting the block along a first plane passing through the central and lateral posts to form a first half body and a second half body; combining the first half body with the second half body to form a first air gap between the central post of the first half body and the central post of the second half body and a second air gap between the lateral post of the first half body and the lateral post of the second half body; and cutting or grinding the combined first half body and second half body along a second plane passing through the central post and the lateral post to form a third half body including the first and second air gaps. 1. A manufacturing method of a magnetic element , comprising:forming a block with magneto-conductive materials, wherein the block comprises a central post and at least one lateral posts;cutting the block along a first plane passing through the central post and the lateral posts to form a first half body and a second half body;combining the first half body with the second half body to form a first air gap between the central post of the first half body and the central post of the second half body and a second air gap between the lateral post of the first half body and the lateral post of the second half body; andcutting or grinding the combined first half body and second half body along a second plane passing through the central post and the lateral post to form a third half body comprising the first air gap and the second air gaps.2. The manufacturing method according to claim 1 , wherein the block comprises a first connecting portion connecting the central post and the lateral post and a second connecting portion connecting the central post and the lateral post claim 1 , the first half body comprises the first connecting portion claim 1 , and the second half ...

Transistor structure and related transistor packaging method thereof

The invention discloses a transistor structure and a related transistor packaging method thereof. The transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

SNUBBER CIRCUIT

A snubber circuit is provided. The snubber circuit includes a transistor structure and a first capacitor. The transistor structure includes a chip package and two pins. The chip package includes a transistor die and a molding compound encapsulating the transistor die. A first pin of the two pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin of the two pins is electrically connected to a third bonding pad of the transistor die. The first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor. 1. A snubber circuit , comprising: a chip package, comprising a transistor die and a molding compound encapsulating the transistor die; and', 'two pins, wherein a first pin is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin is electrically connected to a third bonding pad of the transistor die; and, 'a transistor structure, comprisinga first capacitor, wherein the first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor.2. The snubber circuit of claim 1 , wherein the snubber circuit is connected to an active component or a load in parallel; and the snubber circuit absorbs spikes or noise generated by the active component or the load to the first capacitor claim 1 , and transmits energy of the absorbed spikes or the absorbed noise from the first capacitor to the active component or the load.3. The transistor structure of claim 2 , wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) claim 2 , a diode claim 2 , a Bipolar Junction Transistor (BJT) claim 2 , an Insulated Gate Bipolar Transistor (IGBT) claim 2 , a Static Induction Transistor (SIT) claim 2 , or a thyristor; and the load is or is assembled by an inductor claim 2 , a resistor claim 2 , or a second capacitor.4. The ...

Power supply management circuit utilizing multistage activation and related management method

A management circuit for a power supply is provided. The power supply includes a power factor correction circuit and a power conversion circuit. An output of the power factor correction circuit is coupled to an input of the power conversion circuit. The management circuit includes a power factor correction controller, a pulse width modulation controller and a control circuit. The power factor correction controller controls power factor correction of the power factor correction circuit. The pulse width modulation controller controls power conversion of the power conversion circuit. The control circuit selectively activates the pulse width modulation controller according to a first activated signal generated by an input power of the power supply. After the pulse width modulation controller is activated, the control circuit generates a second activated signal based on the first activated signal. The control circuit activates the power factor conversion controller according to the second activated signal.

Snubber circuit and method of using bipolar junction transistor in snubber circuit

A snubber circuit includes: at least one impedance component, a capacitor, and a Bipolar Junction Transistor (BJT). The snubber circuit is utilized for protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency. In particular, the at least one impedance component in the snubber circuit can be at least one zener diode, where regarding protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency, the performance of the snubber circuit in a situation where the zener diode is utilized is better than that of the snubber circuit in a situation where other types of impedance components are utilized.

POWER DETECTION AND TRANSMISSION CIRCUIT COUPLING ANALOG INPUT SIGNAL ON PRIMARY SIDE TO SECONDARY SIDE FOR POWER INFORMATION CALCULATION AND RELATED POWER SUPPLY APPARATUS

A power detection and transmission circuit is provided. The power detection and transmission circuit includes a first conversion circuit, a second conversion circuit and a signal coupling circuit. The first conversion circuit is electrically connected to a power supply module to receive an analog input signal, and is arranged for converting the analog input signal to a first pulse width modulation (PWM) signal. The second conversion circuit is arranged for converting a second PWM signal to an analog regenerated signal, and transmitting the analog regenerated signal to a microcontroller, wherein the microcontroller calculates power information of the power supply module according to the analog regenerated signal. The signal coupling circuit is coupled between the first conversion circuit and the second conversion circuit, and is arranged for coupling the first PWM signal to the second conversion circuit and accordingly generating the second PWM signal. 1. A power detection and transmission circuit , comprising:a first conversion circuit, electrically connected to a power supply module to receive an analog input signal, the first conversion circuit arranged for converting the analog input signal to a first pulse width modulation (PWM) signal;a second conversion circuit, for converting a second PWM signal to an analog regenerated signal, and transmitting the analog regenerated signal to a microcontroller, wherein the microcontroller calculates power information of the power supply module according to the analog regenerated signal; anda signal coupling circuit, coupled between the first conversion circuit and the second conversion circuit, the signal coupling circuit arranged for coupling the first PWM signal to the second conversion circuit and accordingly generating the second PWM signal.2. The power detection and transmission circuit of claim 1 , wherein the first conversion circuit comprises:a signal processing circuit, for processing the analog input signal to ...

SWITCH CONTROL CIRCUIT, SWITCH CONTROL METHOD, POWER CONVERTER, AND POWER CONVERSION METHOD FOR CONTROLLING CONDUCTING STATUSES OF SWITCH ELEMENTS IN BRIDGELESS SWITCHING CIRCUIT

A switch control circuit for controlling a first switch element and a second switch element within a bridgeless switching circuit is provided. The bridgeless switching circuit generates an output signal according to an alternating current signal. The switch control circuit includes a current generating element and a phase generating element. The current generating element is for sensing a first current flowing through the first switch element and a second current flowing through the second switch element, and generating a phase comparison result according to the first and the second currents. The phase generating element generates a first control signal and a second control signal according to a power factor correction signal and the phase comparison result to control conducting status of the first and the second switch elements, respectively. 1. A switch control circuit for controlling conducting statuses of a first switch element and a second switch element within a bridgeless switching circuit , the bridgeless switching circuit generating an output signal according to an alternating current signal , the switch control circuit comprising:a current generating element, coupled to the bridgeless switching circuit, for sensing a first current flowing through the first switch element and a second current flowing through the second switch element, respectively, and generating a phase comparison result according to the first current and the second current; anda phase generating element, coupled to the current generating element, for generating a first control signal and a second control signal according to a power factor correction signal and the phase comparison result to control the conducting statuses of the first switch element and the second switch element, respectively.2. The switch control circuit of claim 1 , wherein the first control signal and the second control signal generated by the phase generating element do not make both of the first switch element and ...

MONITOR AND METHOD OF DISPLAYING PIXELS ON DISPLAYING DEVICE

A monitor and a method of displaying a plurality of pixels on a displaying device are disclosed. The monitor includes a displaying device including a controlling module and a displaying panel electrically connected to the controlling module. The controlling module displaying the plurality of pixels on the displaying device partially according to a brightness adjustment relation and partially according to an original gray level-brightness relation. Therefore, the invention can adjust input images only in partial gray levels, not all gray levels, by a user's request, for example making dark portions become bright or making bright portions become dark, especially for games. 1. A method of displaying a plurality of pixels on a displaying device , the method comprising:(a) providing an original gray level-brightness relation between a video input in gray levels and a video output in brightness levels, the original gray level-brightness relation comprising a first input gray-level range and a second input gray-level range;(b) providing a first brightness adjustment relation corresponding to the first input gray-level range; and(c) displaying the plurality of pixels whose gray levels are within the first input gray-level range according to the first brightness adjustment relation and simultaneously displaying the plurality of pixels whose gray levels are within the second input gray-level range according to the original gray level-brightness relation on the displaying device.2. The method of claim 1 , wherein the video input is expressed in an amount of gray levels claim 1 , and the first input gray-level range is within a range ranging substantially from 0.875 to 1 of the amount.3. The method of claim 2 , wherein for any input gray-level value within the first input gray-level range claim 2 , an adjusted output brightness-level value according to the first brightness adjustment relation is smaller than an original output brightness-level value according to the original ...

SWITCHING POWER SUPPLY APPARATUS

A switching power supply apparatus including an AC-to-DC conversion circuit, a hysteretic relay and a relay control circuit is provided. The AC-to-DC conversion circuit includes a current limit resistor, and the current limit resistor is configured to suppress an inrush current generated during the AC-to-DC conversion circuit converts an AC input voltage into a DC output voltage. The hysteretic relay is coupled with the current limit resistor in parallel. The relay control circuit is coupled to the AC-to-DC conversion circuit and the hysteretic relay, and configured to control the hysteretic relay to turn on in response to one of an over drive pulse signal and a holding modulation signal when the DC output voltage reaches to a predetermined value, so as to bypass the current limit resistor, wherein an enabling time of the over drive pulse signal is different from that of the holding modulation signal. 1. A switching power supply apparatus , comprising:an AC-to-DC conversion circuit, comprising a current limit resistor, wherein the current limit resistor is configured to suppress an inrush current generated during the AC-to-DC conversion circuit converts an AC input voltage into a DC output voltage;a hysteretic relay, coupled with the current limit resistor in parallel; anda relay control circuit, coupled to the AC-to-DC conversion circuit and the hysteretic relay, configured to control the hysteretic relay to turn on in response to one of an over drive pulse signal and a holding modulation signal when the DC output voltage reaches to a predetermined value, so as to bypass the current limit resistor,wherein an enabling time of the over drive pulse signal is different from that of the holding modulation signal.2. The switching power supply apparatus according to claim 1 , wherein the enabling time of the over drive pulse signal is substantially greater than that of the holding modulation signal.3. The switching power supply apparatus according to claim 2 , wherein:the ...

TRANSISTOR STRUCTURE AND RELATED TRANSISTOR PACKAGING METHOD THEREOF

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit. 1. A transistor structure , comprising:a chip package, comprising a transistor die and a molding compound encapsulating the transistor die; andtwo pins, wherein a first pin is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin is electrically connected to a third bonding pad of the transistor die.2. The transistor structure of claim 1 , wherein the chip package further comprises:a capacitor die, wherein a first bonding pad of the capacitor die is electrically connected to the first bonding pad or the third bonding pad of the transistor die, a second bonding pad of the capacitor die is electrically connected to the first pin or the second pin, and the molding compound further encapsulates the capacitor die.3. The transistor structure of claim 2 , wherein the chip package further comprises:a zener diode die, wherein a first bonding pad of the zener diode die is electrically connected to the first bonding pad of the capacitor die and the first bonding pad or the third bonding pad of the transistor die, a second bonding pad of the zener diode die is electrically connected to the ...

SNUBBER CIRCUIT AND METHOD OF USING BIPOLAR JUNCTION TRANSISTOR IN SNUBBER CIRCUIT

A snubber circuit includes: at least one impedance component, a capacitor, and a Bipolar Junction Transistor (BJT). The snubber circuit is utilized for protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency. In particular, the at least one impedance component in the snubber circuit can be at least one zener diode, where regarding protecting electric/electronic components, reducing high frequency interference and spike voltage, and enhancing efficiency, the performance of the snubber circuit in a situation where the zener diode is utilized is better than that of the snubber circuit in a situation where other types of impedance components are utilized. An associated method of using a BJT in a snubber circuit is also provided. 1. A snubber circuit , comprising:at least one impedance component;a capacitor, having a first terminal and a second terminal, wherein the first terminal of the capacitor is electrically connected to a first terminal of the snubber circuit; anda bipolar junction transistor (BJT), wherein one of an emitter and a collector of the BJT is electrically connected to the second terminal of the capacitor, and another of the emitter and the collector of the BJT is electrically connected to a second terminal of the snubber circuit;wherein the at least one impedance component is connected to the capacitor in parallel, or connected to the emitter and the collector of the BJT in parallel.2. The snubber circuit in claim 1 , wherein the at least one impedance component is at least a zener diode.3. The snubber circuit in claim 1 , wherein the base and the emitter of the BJT are electrically conducted.4. The snubber circuit in claim 1 , wherein based on at least one junction characteristic between the base and the collector of the BJT claim 1 , the snubber circuit utilizes the BJT as a fast diode.5. The snubber circuit in claim 4 , wherein the at least one junction characteristic includes a ...

SNUBBER CIRCUIT AND METHOD OF USING BIPOLAR JUNCTION TRANSISTOR IN SNUBBER CIRCUIT

A snubber circuit includes: a capacitor including a first terminal and a second terminal, where the first terminal of the capacitor is electrically connected to a first terminal of the snubber circuit; and a Bipolar Junction Transistor (BJT), where one of the emitter and the collector of the BJT is electrically connected to the second terminal of the capacitor, and the other one of the emitter and the collector of the BJT is electrically connected to a second terminal of the snubber circuit. The snubber circuit can be electrically connected in parallel to an active component or a load to protect the circuitry connected to the load, and more particularly to absorb spike or noise generated during high-frequency switching of the active component to recycle energy, in order to achieve the goal of reducing spike voltages and enhancing efficiency. 1. A snubber circuit , comprising:a capacitor, having a first terminal and a second terminal, wherein the first terminal of the capacitor is electrically connected to a first terminal of the snubber circuit; anda bipolar junction transistor (BJT), wherein one of an emitter and a collector of the BJT is electrically connected to the second terminal of the capacitor, and another of the emitter and the collector of the BJT is electrically connected to a second terminal of the snubber circuit.2. The snubber circuit of claim 1 , wherein based on at least one junction characteristic between the base and the collector of the BJT claim 1 , the snubber circuit utilizes the BJT as a fast diode.3. The snubber circuit of claim 2 , wherein the at least one junction characteristic includes a characteristic of fast turning on claim 2 , a characteristic of long storage time claim 2 , a characteristic of slow switching and a characteristic of small base-collector junction capacitance; and the snubber circuit transfers leakage inductor energy to the capacitor rapidly by using the characteristic of fast turning on claim 2 , and pushes energy of ...

SNUBBER CIRCUIT AND BUFFERING METHOD FOR SNUBBER CIRCUIT

A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal. 1. A snubber circuit , comprising:a capacitor; anda buffer device, having a first terminal and a second terminal, wherein the first terminal is electrically connected to the capacitor; when the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device; and when the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.2. The snubber circuit of claim 1 , wherein when the buffer device operates in the first conduction mode claim 1 , the charge current flows through the buffer device to charge the capacitor; and when the buffer device operates in the second conduction mode claim 1 , the discharge current flows through the buffer device to discharge the capacitor.3. The snubber circuit of claim 1 , wherein the relative ...

CIRCUIT HAVING SNUBBER CIRCUIT IN POWER SUPPLY DEVICE

A snubber circuit is provided. The snubber circuit includes a transistor structure and a first capacitor. The transistor structure includes a chip package and two pins. The chip package includes a transistor die and a molding compound encapsulating the transistor die. A first pin of the two pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin of the two pins is electrically connected to a third bonding pad of the transistor die. The first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor. 1. A circuit in a power supply device , comprising: [ a chip package, comprising a transistor die and a molding compound encapsulating the transistor die;', 'a first pin; and', 'a second pin, wherein the transistor structure electrically connects three different bonding pads of the transistor die to only two pins of the transistor structure by electrically connecting the three different bonding pads to the first pin and the second pin each having a part embedded in the molding compound and another part outside the molding compound; the three different bonding pads of the transistor die comprises a first bonding pad, a second bonding pad and a third bonding pad; the part of the first pin embedded in the molding compound is simultaneously and directly connected to the first bonding pad and the second bonding pad of the transistor die within the molding compound; and the part of the second pin embedded in the molding compound is electrically connected to the third bonding pad of the transistor die different from each of the first bonding pad and the second bonding pad; and, 'a transistor structure, comprising, 'a first capacitor, wherein the another part of the first pin or the another part of the second pin of the transistor structure outside the molding compound is electrically connected to a first terminal of the first capacitor; and, 'a snubber circuit, ...

POWER CONVERTER AND CONTROL CIRCUIT THEREOF

A power converter including: an output unit outputs a converted voltage; a transformer includes a first primary wiring, second primary wiring, and a secondary wiring; a first switch unit is coupled between first primary wiring and a second node; a delay unit is coupled to a control terminal of first switch unit; a first control unit generates a first control signal according to the converted voltage to control ON/OFF state of the first switch unit via the delay unit; the processing unit, coupled between the input voltage and the first node, receives, stores induced power of first induced voltage and releases the stored energy; and the second control unit generates a second control signal to control ON/OFF state of a second switch unit of processing unit to control receiving or releasing the energy according to the input voltage and induced power of first primary wiring. 1. A power converter , comprising:an output unit, for outputting a converted voltage; a first primary winding, coupled to an input voltage and a first node;', 'a second primary winding, coupled to a second node; and', 'a secondary winding, coupled to the output unit and the second node;, 'a first transformer comprisinga first switch unit, coupled between the first primary winding and the second node, for controlling magnetic flux direction of the first primary winding;a delay unit, coupled to a control node of the first switch unit;a first control unit, coupled to the converted voltage and coupled to the first switch unit via the delay unit, for generating a first control signal according to the converted voltage to control ON/OFF of the first switch unit via the delay unit;a processing unit, coupled between the input voltage and the first node, the processing unit being used for receiving a first induced voltage of the first node and storing induced power of the first induced voltage through a first path and isolating the first induced voltage from feeding in through a second path different from the ...

Rectifier and associated rectifying circuit

A rectifier, including: a first and a second input terminal, a first output terminal and at least one rectifying circuit. Each rectifying circuit including: a switching circuit including a transistor, and a driving circuit. The driving circuit is coupled to the switching circuit and controls a switching status of the switching circuit, and includes a totem-pole circuit and an input transistor. The totem-pole circuit includes an input terminal and an output terminal coupled to the transistor. The input transistor is coupled between the totem-pole circuit and the switching circuit. The at least one rectifying circuit includes a first and a second rectifying circuit. The transistors of the first rectifying circuit and the second rectifying circuit are coupled to the first output terminal. The input transistors of the first rectifying circuit and the second rectifying circuit are coupled to the first input terminal and the second input terminal, respectively.

Method for controlling transformer excitation cycles and circuit for controlling the same

The present invention discloses a method for controlling transformer excitation cycles and a circuit for controlling the same, wherein the excitation cycle and the demagnetization cycle, which determine the rise and fall of the excitation current, are modified to prevent the coil from being saturated. In the present invention, a sense current is acquired from the excitation current of the transformer coil, and a demagnetization reference value is set. The sense current is used to determine whether the excitation current is lowered to the demagnetization reference value in the demagnetization cycle. A cycle modifying circuit is used to modify the duty cycle signal output by a pulse control unit until the excitation current is lowered to a preset level.

Simple zero current switch circuit

A simple zero current switch circuit includes a first coil set and a second coil set that are wound at a selected coil ratio and bridge electrically an energy storing inductor, an output diode and a conduction switch of a power-factor corrector. The leaking inductance of the first coil set generates a back electromotive force to make the conduction switch in a zero current switching condition. An energy conversion circuit is provided to store reverse energy according to the coil ratio of the second coil set and the first coil set and reclaims the energy to an output capacitor of the power-factor corrector while the output diode generates a reverse recovery condition. Thereby reverse recovery time of the output diode can be shortened.

Multiplier-divider having error offset function

A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is reduced. More than one processing signal can be obtained from the same power supply to reduce loss of external sampling.

Chop wave control circuit

A chop-wave control circuit includes a feedback unit, a ramp generation unit, a latchup unit and a voltage transformation unit that is used on a forward transformation circuit which includes at least a main output unit and at least one auxiliary output unit. The feedback unit captures a feedback signal from an output end of the auxiliary output unit to generate a slope regulation signal. The ramp generation unit alters the trigger time sequence of the latchup unit through the slope regulation signal to set an auxiliary flywheel switch ON or OFF. The voltage transformation unit detects potential variations of the latchup unit to set a chop-wave switch ON or OFF. By controlling the auxiliary flywheel switch and the chop-wave switch a power output cycle of the auxiliary output unit can be formed.

Switch control circuit and control method for bridgeless switching circuit, power converter and power control method

Active peak voltage-limiting clamp circuit

The present invention discloses an active peak voltage-limiting clamp circuit, which comprises a primary switch unit and a secondary switch unit that are used to control the coil current of a transformer, wherein a signal acquisition unit, a zero-point decision unit, a feedback unit and a pulse control unit are used to control the turn-on periods of the primary switch unit and the secondary switch unit; thus, the turn-on period of the primary switch unit is separated from the turn-on period of the secondary switch unit, and a buffer interval for the transient voltage variation is formed therebetween.

Post regulation control circuit

A post regulation control circuit aims to monitor ancillary output power generated from a power supply. The power supply includes at least one primary output circuit to provide a primary output power. A post regulation circuit obtains the primary output power and regulate to an ancillary output power. The monitor circuit sets an abnormal level and obtains a detection power from the post regulation circuit to compare with the abnormal level. Determining whether to output a driving pulse wave according to the detection power is over the abnormal level or not, or stop outputting the driving pulse wave.

Circuit and method for controlling the start-up cycle of a power supply

The present invention discloses a method and a circuit for controlling a start-up cycle of an integrated circuit in a circuit system. The method and circuit determine whether or not an input power of the circuit system and a bias voltage power of the integrated circuit have reached a normal operating voltage range to control the bias voltage power to produce a start-up cycle of the integrated circuit. The method and circuit also provides a protection mechanism for an overload of the circuit system overload, so that the integrated circuit can moderate surges and prevent damages.

阻尼器電路以及用於阻尼器電路的緩衝方法

一種阻尼器電路包含一電容以及一緩衝元件。該緩衝元件具有一第一端點以及一第二端點，該第一端點係電連接於該電容。當該緩衝元件操作於一第一導通模式時，一充電電流係自該第二端點經由該緩衝元件而流向該第一端點。當該緩衝元件從該第一導通模式切換至一第二導通模式時，該緩衝元件係產生自該第一端點經由該緩衝元件朝該第二端點流動超過一特定時間的一放電電流，以使得在該緩衝元件進入該第二導通模式之後，於該第二端點第一次出現的一相對極大電壓準位會小於該第一端點之電壓準位。

Multiplier-divider with error compensation function

電晶體之封裝方法

Forward converter with synchronous rectifier and reverse current control

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Method and an electric circuit of switching on time sequence control

阻尼器電路及將雙極性接面電晶體用於阻尼器電路之方法

本發明提供一種阻尼器電路，其包含有：一電容器，該電容器具有一第一端子與一第二端子，其中該電容器之該第一端子係電氣連接至該阻尼器電路之一第一端子；以及一雙極性接面電晶體，其中該雙極性接面電晶體之射極與集極中之一者係電氣連接至該電容器之該第二端子，且其射極與集極中之另一者係電氣連接至該阻尼器電路之一第二端子。該阻尼器電路可並聯於一主動元件或一負載以保護負載所連接的電路，尤其可吸收主動元件在高頻切換時所產生之突波或雜訊以做能量回收，而可達到降低突波電壓、提高效率之功效。

電晶體結構

電晶體結構

一種電晶體結構，係包含一晶片封裝體以及二導腳，其中該晶片封裝體係包含一電晶體晶粒及一包覆該電晶體晶粒之封裝膠體；而該導腳之其中一導腳係電性連接該電晶體晶粒之第一焊墊與第二焊墊，另一導腳係電性連接該電晶體晶粒之第三焊墊。而可將該電晶體結構使用於阻尼器電路以並接一主動元件或一負載，而可吸收主動元件在高頻切換時產生之突波或雜訊。藉此，該電晶體結構在封裝上可達到簡化製程、縮小體積以及增加耐壓距離之功效，且可讓使用阻尼器電路之電源供應器達到提高效率及降低突波電壓之功效。

電晶體結構及其封裝方法

一種電晶體結構，係包含一晶片封裝體以及二導腳，其中該晶片封裝體係包含一電晶體晶粒及一包覆該電晶體晶粒之封裝膠體；而該導腳之其中一導腳係電性連接該電晶體晶粒之第一焊墊與第二焊墊，另一導腳係電性連接該電晶體晶粒之第三焊墊。而可將該電晶體結構使用於阻尼器電路以並接一主動元件或一負載，而可吸收主動元件在高頻切換時產生之突波或雜訊。藉此，該電晶體結構在封裝上可達到簡化製程、縮小體積以及增加耐壓距離之功效，且可讓使用阻尼器電路之電源供應器達到提高效率及降低突波電壓之功效。

適配器電源

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顯示器及於顯示裝置上顯示畫素之方法

本發明揭露一顯示器及於顯示裝置上顯示畫素之方法。該顯示器包含一顯示裝置，該顯示裝置包含一控制模組及一顯示面板，該顯示面板電連接該控制模組。該控制模組部分根據一亮度調整關係、部分根據一原始灰階-亮度關係以顯示畫素於該顯示裝置上。因此，本發明能應使用者需求而僅於部分灰階範圍，非整個灰階範圍，來調整輸入影像。例如使黑暗部分變亮，或使明亮部分變暗些，此特別適合遊戲場合。

阻尼器電路及將雙極性接面電晶體用於阻尼器電路之方法

Pulse controller with dual latches

A pulse controller with dual latches includes a first latch unit and a second latch unit, in which two latch units are used to latch signal level for ensuring a sufficient conducting amount of the switching element in the rear end power output unit, and through a mutual interaction between the first and the second latch units, a complementary turning-on and turning-off situation therebetween is formed, and further, the signal from a trigger signal source and the feedback from the power output unit are employed to generate the duty cycle signal for the power output unit so as to replace the conventional pulse width modulation circuit.

Method and control circuit to control the excitation cycle of transformer

阻尼器電路及將雙極性接面電晶體用於阻尼器電路之方法

本發明提供一種阻尼器電路，其包含有：至少一阻抗元件／齊納二極體、一電容器、以及一雙極性接面電晶體。該阻尼器電路係用於保護電力／電子元件、降低高頻干擾及突波電壓、以及改善效率。尤其是，該阻尼器電路中之該至少一阻抗元件／齊納二極體可為至少一齊納二極體，而非至少一阻抗元件；針對保護電力／電子元件、降低高頻干擾及突波電壓、以及改善效率，該阻尼器電路在採用齊納二極體的情況下之效能較在採用阻抗元件的情況下之效能更佳。本發明另提供一種將雙極性接面電晶體用於阻尼器電路之方法。

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