System and method for boot loading of programs within a host operating environment having one or more linked guest operating systems

A system and method for loading programs during a system boot using stored configuration data in a predetermined file system from a prior session and providing the stored configuration data to a guest operating system capable of communication with a host operating system, during start-up, within a computing environment having a hypervisor, in a predetermined manner.

Ester compounds, method for the preparation thereof and use thereof

Ester compounds, such as for use in a lubricant, are based on di-, tri- or higher functional carboxylic acids according to formula (I).

Detecting data dependencies of instructions associated with threads in a simultaneous multithreading scheme

Detecting data dependencies of instructions associated with threads in a simultaneous multithreading (SMT) scheme is disclosed, including: dividing a plurality of comparators of an SMT-enabled device into groups of comparators corresponding to respective ones of threads associated with the SMT-enabled device; simultaneously distributing a first set of instructions associated with a first thread of the plurality of threads to a corresponding first group of comparators from the plurality of groups of comparators and distributing a second set of instructions associated with a second thread of the plurality of threads to a corresponding second group of comparators from the plurality of groups of comparators; and simultaneously performing data dependency detection on the first set of instructions associated with the first thread using the corresponding first group of comparators and performing data dependency detection on the second set of instructions associated with the second thread using ...

Gate and field electrode trench formation process

An upper portion of a field electrode trench and a gate trench are simultaneously formed in the main surface of a substrate to approximately the same depth. A first protective layer is formed that completely fills the gate trench and lines the upper field electrode trench. The first protective layer is removed from the bottom of the upper trench and semiconductor material is removed thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer. An electrically conductive field electrode and a field electrode dielectric are formed in the field electrode trench. At least some of the first protective layer is removed from the gate trench. A conformal gate dielectric layer is formed on the substrate. An electrically conductive gate electrode is formed in the gate trench while the field electrode remains covered by the gate dielectric layer.

Method of adjusting recession of an element of a slider

A method and apparatus are provided for adjusting recession of an element, such as a pole tip, in a transducer structure formed in a plurality of thin film layers on an edge of a slider. A pre-stressed structure is formed as part of the plurality of thin film layers on the edge of the slider. The pre-stressed structure has a level of material stress. The recession is measured relative to a bearing surface of the slider, and then the level of material stress is adjusted as a function of the measured to effect a corresponding change in the recession.

Buck converter power package

One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

SEMICONDUCTOR DEVICE HAVING A SHIELDING LAYER AND A METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric. A method of producing the semiconductor device is also described.

Trench FET with Ruggedness Enhancement Regions

According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches. 1. A field-effect transistor (FET) comprising:first and second gate trenches extending to a drift region of a first conductivity type;a base region of a second conductivity type that is situated between said first and second gate trenches;a ruggedness enhancement region situated between said first and second gate trenches, said ruggedness enhancement region configured to provide an enhanced avalanche current path from a drain region to said base region when said FET is in an avalanche condition, said enhanced avalanche current path being away from said first and second gate trenches.2. The FET of claim 1 , wherein said ruggedness enhancement region is of said second conductivity type.3. The FET of claim 1 , wherein said ruggedness enhancement region is of said second conductivity type that comprises a higher dopant concentration than said base region.4. The FET of claim 1 , wherein said ruggedness enhancement region extends below said first and second gate trenches.5. The FET of claim 1 , wherein said ruggedness enhancement region comprises a highest dopant concentration at least ...

ISOLATION STRUCTURE FOR SEPARATING DIFFERENT TRANSISTOR REGIONS ON THE SAME SEMICONDUCTOR DIE

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Method of Forming a Semiconductor Structure Having Integrated Snubber Resistance

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

Trench field electrode termination structure for transistor devices

A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Method and apparatus for sharing user information in browsers of a mobile terminal

A method for sharing user information in browsers of a mobile terminal is disclosed in the present invention and comprises steps of: receiving a second operating command for importing the user information to a second browser; executing a first operating command for exporting the user information from the first browser in accordance with the second operating command for importing the user information to the second browser, and the first operating command is a command for exporting the user information from the first browser.

Power semiconductor device with endless gate trenches

A power semiconductor device which includes endless gate trenches.

Novel Ester Compounds, Method for the Production Thereof and Use Thereof

The invention relates to novel ester compounds of the general formula (I) 5. The mixture of ester compounds as claimed in claim 1 , characterized in that two of the at least two ester compounds in each case are regioisomers of one another.7. The process as claimed in claim 6 , characterized in that claim 6 , as a further reaction step (D) claim 6 , the Rgroup is subjected to an esterification or transesterification reaction.8. The process as claimed in claim 6 , characterized in that claim 6 , as a further reaction step (E) claim 6 , in the case of a free hydroxyl group in the Rradical claim 6 , the further esterification thereof is conducted.9. The process as claimed in claim 6 , characterized in that the starting compound used is at least one unsaturated fatty acid selected from the group consisting of oleic acid claim 6 , linoleic acid claim 6 , linolenic acid claim 6 , erucic acid claim 6 , nervonic acid claim 6 , gadoleic acid and/or another ω-n-fatty acid.11. The process as claimed in claim 10 , characterized in that claim 10 , as a further reaction step (D) claim 10 , the Rgroup is subjected to an esterification or transesterification reaction.12. The process as claimed in claim 10 , characterized in that claim 10 , as a further reaction step (E) claim 10 , in the case of a free hydroxyl group in the Rradical claim 10 , the further esterification thereof is conducted.13. The process as claimed in claim 10 , characterized in that the starting compound used is at least one unsaturated fatty acid selected from the group consisting of oleic acid claim 10 , linoleic acid claim 10 , linolenic acid claim 10 , erucic acid claim 10 , nervonic acid claim 10 , gadoleic acid and/or another ω-n-fatty acid.14. The process as claimed in claim 6 , characterized in that a biocatalyst selected from the enzyme class of the hydrolases is used for at least one of the esterification reactions involved.15. The process as claimed in claim 6 , characterized in that at least one of ...

Semiconductor Transistor Device and Method of Manufacturing the Same

A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode. 1. A semiconductor transistor device , comprising:a source region;a drain region;a channel region vertically between the source region and the drain region;a gate electrode in a vertical gate trench; anda gate dielectric lying laterally between the channel region and a sidewall of the gate electrode,wherein the channel region extends vertically along the gate dielectric, a silicon gate region made of a conductive silicon gate material; and', 'a metal inlay region made of a metal material,, 'wherein the gate electrode compriseswherein the silicon gate region forms at least a section of the sidewall of the gate electrode,wherein the metal inlay region extends up from a lower end of the gate electrode.2. The semiconductor transistor device of claim 1 , wherein the entire sidewall of the gate electrode claim 1 , between which the channel region and the interlayer dielectric are arranged claim 1 , is formed by the silicon gate region.3. The semiconductor transistor device of claim 2 , wherein the silicon gate region has an inner sidewall facing away from the channel region claim 2 , and wherein the entire inner sidewall is laterally covered by the metal inlay region.4. The semiconductor transistor device of claim 3 , wherein an upper end of the metal inlay region lies vertically above an upper end of the silicon gate region.5. The semiconductor transistor device of claim 1 , wherein the lower end of the gate electrode lies vertically below a lower end of the channel region.6. The semiconductor transistor device of claim 5 , wherein a lower end of the metal inlay region lies vertically below a lower end of the silicon gate region claim 5 , and wherein the gate ...

Method for Fabricating a Shallow and Narrow Trench FET

According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench; forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench; forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench. Trench FETs formed by the method are also disclosed. 120-. (canceled)21. A method for fabricating a trench field-effect transistor (trench FET) , the method comprising:forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench;forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench;forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; andforming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench.22. The method of claim 21 , wherein the channel region is formed by dopant implantation.23. The method of claim 21 , further comprising:forming a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench before forming the gate dielectric in the trench, the ...

Power Semiconductor Device with Source Trench and Termination Trench Implants

A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.

Power semiconductor device with contiguous gate trenches and offset source trenches

Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.

Trench FET with ruggedness enhancement regions

According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.

MULTI-THREAD PROCESSING

A computer-implemented method for multi-thread processing, the method including: compiling a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; and fusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread including thread portions corresponding to each thread of the first plurality of threads, in which the first instructions include load effective address instructions and control transfer instructions, in which the load effective address instructions and the control transfer instructions are compiled using a second register set, and in which jump operations between thread portions are implemented by the control transfer instructions inserted into the machine instruction code of the fused thread. 1. A computer-implemented method for multi-thread processing , the method comprising:compiling, by a computing device, a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; andfusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread comprising thread portions corresponding to each thread of the first plurality of threads,wherein the first instructions are inserted into the machine instruction code of the fused thread, andwherein the first instructions comprise load effective address instructions and control transfer instructions, wherein the load effective address instructions and the control transfer instructions are compiled using a second ...

Method, server, smart terminal and storage device for access authentication

Disclosed is a method for access authentication. The method includes: receiving profile information of a visitor through a server, and generating a visitor code and transmitting the same to a visitor terminal, and generating a random code based on a valid visitor code, and receiving a decoding result based on decoding the random code and the visitor code by the visit terminal, and predetermining an access authority for the visitor for a predetermined time as the decoding result is successfully matched.

Power semiconductor device with buried source electrode

A power semiconductor device that includes a buried source electrode disposed at the bottom of a trench below a respective gate electrode, and a source connector including a finger electrically connecting the buried source to the source contact of the device, and a process for fabricating the device.

POLY(ESTER UREA) MICROCAPSULES

Described herein are a process for the preparation of poly(ester urea) microcapsules, and such poly(ester urea) microcapsules. Perfuming compositions and consumer products including such microcapsules, in particular perfumed consumer products in the form of home care or personal care products, are also described. 1. A process for the preparation of a poly(ester urea) based core-shell microcapsule slurry , the process comprising the following steps:a) dissolving at least one polyisocyanate having at least two isocyanate groups in a hydrophobic material to form an oil phase;b) preparing a dispersing phase comprising a stabilizer, wherein the dispersing phase is not miscible with the oil phase;c) adding the oil phase obtained in step a) into the dispersing phase to form a two-phases dispersion; andd) performing a curing step to form core-shell microcapsules in the form of a slurry,wherein a polyaminoester is added in step a) and/or in the two-phases dispersion of step c).2. The process according to claim 1 , wherein the polyaminoester is obtained by a reaction between a polyol and an amino-acid.3. The process according to claim 2 , wherein the polyol is selected from the group consisting of glycerol claim 2 , pentaerythritol claim 2 , 1 claim 2 ,1 claim 2 ,1-tris(hydroxymethyl)ethane claim 2 , 1 claim 2 ,4-butanediol claim 2 , diethylene glycol claim 2 , and mixtures thereof.4. The process according to claim 2 , wherein the amino-acid is selected from the group consisting of glycine claim 2 , phenylalanine claim 2 , alanine claim 2 , valine claim 2 , leucine claim 2 , isoleucine and mixtures thereof claim 2 , and mixtures thereof.6. The process according to claim 1 , wherein the polyaminoester is used in an amount of between 0.1 and 15% claim 1 , these percentages being defined by weight relative to the total weight of the slurry.7. The process according to claim 1 , characterized in that the polyisocyanate is selected from the group consisting of a polyisocyanurate of ...

Conditional data caching using transactional memory in a multiprocessor system

A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Conditional data caching transactional memory in a multiple processor system

A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Method and apparatus for updating shared data in a multi-core processor environment

Embodiments of the specification provide a method and an apparatus for updating shared data in a multi-core processor environment. The multi-processor environment comprises a multi-core processor. The multi-core processor comprises a plurality of separate processing units (referred to as cores, or core processing units (CPUs) in the specification); the multi-core processor is configured to process a multi-threaded task; the multi-threaded task has shared data to update. The method is executed by any CPU. The method may comprise: requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; and setting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index.

Power Semiconductor Device with Low RDSON and High Breakdown Voltage

A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench.

Semiconductor device having needle-shape field plate trenches and needle-shaped gate trenches

A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.

Semiconductor Transistor Device and Method of Manufacturing the Same

The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region. 1. A semiconductor transistor device , comprising:a source region;a drain region;a body region;a drift region comprising a drift zone vertically between the body region and the drain region;agate region laterally aside the body region and configured to form a vertical channel in the body region; anda Schottky diode electrically connected in parallel to a body diode formed between the body region and the drift region,wherein a diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.2. The semiconductor transistor device of claim 1 , wherein the diode junction of the Schottky diode is formed at an upper surface of the drift region claim 1 , the upper surface lying in a horizontal plane.3. The semiconductor transistor device of claim 1 , wherein the diode junction of the Schottky diode has an area of at least 0.01 μmand not more than 100 μm.4. The semiconductor transistor device of claim 1 , wherein the diode junction of the Schottky diode is arranged vertically above an upper end of the body region.5. The semiconductor transistor device of claim 4 , wherein the diode junction of the Schottky diode is arranged on a same vertical level as an upper end of the source region.6. The semiconductor transistor device of claim 1 , further comprising field electrode regions which respectively extend vertically into the drift region and are arranged consecutively in a first lateral direction claim 1 , and wherein the diode junction of the Schottky diode extends in the first lateral direction over a whole distance between two neighboring ones of the field ...

MATRIX VIEW OF ITEMS

Apparatus, systems, and methods may operate to present a plurality of searched items by a plurality of points in a matrix view, which includes a first axis and a second axis, respectively representing a price attribute and one of other attributes of the plurality of items. Additional apparatus, systems, and methods are disclosed.

Trench MOSFET and method for fabricating same

According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

Multi-branched mannich base corrosion inhibitor and preparation method thereof

The present invention relates to a multi-branched Mannich base corrosion inhibitor and the method for preparing thereof. The method comprises (1) adding 3˜7 moles ketone and 3˜7 moles aldehyde to reaction kettle, adjusting pH to 2˜6 with acid, controlling temperature to 20˜50° C. and stirring for 20˜30 mins; (2) adding 1 mole organic polyamine to the reaction kettle under stirring, or adding the pH-adjusted ketone, aldehyde and organic solvent to organic polyamine, controlling temperature to 60˜90° C. and reacting for 1˜3 hrs, and after completion of the reaction, heating the system to 110° C. under nitrogen to remove water; the organic polyamine is organic compound comprising three or more primary amine groups and/or secondary amine groups. The Mannich base corrosion inhibitor of the present invention shows characters of strong adsorption force, high film strength, high film compactness, increase in corrosion inhibition efficiency by at least 2%, and overcomes the disadvantages in prior ...

Trench Fet Having Merged Gate Dielectric

In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode. 1. A trench FET comprising:a semiconductor substrate including a drain region and a drift zone over said drain region;a plurality of depletion trenches over said drain region, each of said plurality of depletion trenches having a depletion trench dielectric and a depletion electrode;a respective bordering gate trench situated alongside each of said plurality of depletion trenches, each said bordering gate trench having a gate electrode and a gate dielectric;said gate dielectric being merged with said depletion trench dielectric between said depletion electrode and said gate electrode.2. The trench FET of claim 1 , wherein said gate dielectric is substantially thinner than said depletion trench dielectric.3. The trench FET of claim 1 , wherein said respective bordering gate trench comprises only one bordering gate trench situated alongside each of said plurality of depletion trenches.4. The trench FET of claim 1 , wherein said depletion electrode is electrically coupled to a source of said trench FET.5. The trench FET of claim 1 , wherein said plurality of depletion trenches are at least one and a half times deeper than said respective bordering gate trench.6. The trench FET of claim 1 , further comprising a channel layer including source regions formed over said drift zone.7. The trench FET of claim 1 , wherein said drift zone comprises an epitaxial silicon layer.8 ...

Superjunction Device with Oxygen Inserted Si-Layers

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. 1. A semiconductor device , comprising:a source region and a drain region of a first conductivity type;a body region of a second conductivity type between the source region and the drain region;a gate configured to control current through a channel of the body region;a drift zone of the first conductivity type between the body region and the drain region;a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone; anda diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer adjacent the alternating layers of Si and oxygen-doped Si.2. The semiconductor device of claim 1 , wherein the diffusion barrier structure is also disposed along a bottom face of the regions of the second conductivity type.3. The semiconductor device of claim 1 , wherein the drift zone contacts a bottom face of the regions of the second conductivity type.4. The semiconductor device of claim 1 , wherein the drain region is ...

Combined gate trench and contact etch process and related structure

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

FIELD ELECTRODE TERMINATION STRUCTURE FOR TRENCH-BASED TRANSISTOR DEVICES

A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING CPU PERFORMANCE

Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread. 120.-. (canceled)21. A computer-implemented method comprising:at each of a plurality of CPU components of a CPU: enabling threads awaiting execution on the CPU component to compete for a respective mutex of the CPU component, wherein each CPU component is operable to execute one thread at any given time;identifying a plurality of threads that have each obtained the respective mutex;enabling the plurality of threads that have each obtained the respective mutex of a CPU component to compete for a spin lock of the CPU;identifying, from the plurality of threads, a target thread holding a mutex of a CPU component that has also obtained the spin lock of the CPU; andexecuting, at the CPU, a critical section corresponding to the target thread that has obtained the spin lock while remaining threads that have not obtained the respective mutexes are sleeping.22. The method according to claim 21 , further comprising releasing the mutex of the CPU component and the spin lock of the CPU that are obtained by the target thread only after execution of the critical section corresponding to the target thread is completed.23. The method according to claim 22 , wherein the releasing the mutex of the CPU component and the spin lock of the ...

Buried Bus and Related Method

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer. 1. A semiconductor structure , comprising:a semiconductor substrate having a gate electrode in a gate trench;a buried bus in said semiconductor substrate, said buried bus having a bus conductive filler in a bus trench; andan adhesion promotion layer in said bus trench and interposed between said bus conductive filler and said gate electrode,wherein said bus conductive filler is electrically coupled to said gate electrode.2. The semiconductor structure of claim 1 , wherein said bus conductive filler is surrounded by said gate electrode.3. The semiconductor structure of claim 1 , wherein said gate trench intersects said bus trench in said semiconductor substrate.4. The semiconductor structure of claim 1 , wherein said gate electrode comprises polysilicon.5. The semiconductor structure of claim 1 , wherein said bus conductive filler comprises tungsten.6. (canceled)7. The semiconductor structure of claim 1 , wherein said adhesion promotion layer comprises titanium and titanium nitride.8. The semiconductor structure of claim 1 , further comprising a dielectric ...

Combined gate trench and contact etch process and related structure

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

Sucrose monoesters microemulsions

An oil in water (o/w) micro-emulsion comprising: a. water; b. from about 3% up to about 30% oil; c. from about 0.1% up to about 10% lecithin; d. sucrose monoester as an emulsifier wherein the ratio of the combined amount of a lecithin and sucrose monoester to oil is less than 1; e. propylene glycol wherein the propylene glycol to water ratio by weight is greater than 1; and f. from about 14% up to about 40%, by weight, a sugar selected from the group consisting of fructose, glucose, and sucrose, and combinations thereof; wherein the mean droplet size of the o/w micro-emulsion is about 10 to about 80 nm.

Ester compounds, method for the production thereof and use thereof

The invention relates to novel ester compounds of the general formula (I) to a process for preparation thereof and to the use thereof. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Controlled resistance integrated snubber for power switching device

A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.

Termination trench structure for mosgated device and process for its manufacture

A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof.

SLIDER HAVING ADJUSTED TRANSDUCER RECESSION AND METHOD OF ADJUSTING RECESSION

A method and apparatus are provided for adjusting recession of an element, such as a pole tip, in a transducer structure formed in a plurality of thin film layers on an edge of a slider. A pre-stressed structure is formed as part of the plurality of thin film layers on the edge of the slider. The pre-stressed structure has a level of material stress. The recession is measured relative to a bearing surface of the slider, and then the level of material stress is adjusted as a function of the measured to effect a corresponding change in the recession.

Method for fabricating a semiconductor device

A process for fabricating a power semiconductor device is disclosed.

Mannich-base inhibitor for decalcification, preparation method and application thereof

A mannich-base inhibitor for decalcification, a preparation method and application thereof are provided. The inhibitor comprises 10-80% mannich-base component calculated in the total weight percent of the inhibitor, while the rest is at least one compound selected from imidazoline inhibitor with molecular weight between 110 and 750, and alkynyloxy amine inhibitor. The mannich-base inhibitor component is prepared through mannich reaction with 1 mol organic polyamine containing three or more primary amine bases and/or secondary amine bases, 3-7 mol ketones, and 3-7 mol aldehydes. The inhibitor which can be effectively compounded and cooperated with oil demulsifying agent and oil decalcifying agent, have the advantages of stable property, strong absorbability, high film strength and film density with its inhibition rate exceeding 90%. The inhibitor is especially adapted for inhibiting the steel corrosion caused by the mixed medium of salt, acid and water from the desalination and dehydration ...

Matrix view of items

Apparatus, systems, and methods may operate to present a plurality of searched items by a plurality of points in a matrix view, which includes a first axis and a second axis, respectively representing a price attribute and one of other attributes of the plurality of items. Additional apparatus, systems, and methods are disclosed.

Slider having adjusted transducer recession and method of adjusting recession

A method and apparatus are provided for adjusting recession of an element, such as a pole tip, in a transducer structure formed in a plurality of thin film layers on an edge of a slider. A pre-stressed structure is formed as part of the plurality of thin film layers on the edge of the slider. The pre-stressed structure has a level of material stress. The recession is measured relative to a bearing surface of the slider, and then the level of material stress is adjusted as a function of the measured to effect a corresponding change in the recession.

CONDITIONAL DATA CACHING TRANSACTIONAL MEMORY IN A MULITPLE PROCESSOR SYSTEM

A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors. 1. A method for reducing data traffic among multiple processors with transactional memory for processing data , the method comprising: reading first data into a private cache of the first processor,', performing a write operation on the first data in the private cache of the first processor, and', 'setting a cache line state index string to indicate a special state of the first data written in the private cache of the first processor, the special state signaling that the first data is modified and is to be exclusively written in a last level cache (LLC) when the transaction is committed;, 'upon detecting a preset condition of recent modifications on the first data,'}], 'processing a transaction using a first processor, wherein the transaction includescommitting the transaction to a transactional memory system by writing the first data in the private cache of the first processor into the LLC accessible by the multiple processors, and invalidating the first data in the private cache of the first processor; andmodifying the first data by modifying a copy of the first data in the LLC.2. The method as recited in claim 1 , ...

IDENTIFYING USER PREFERENCES AND CHANGING SETTINGS OF A DEVICE BASED ON NATURAL LANGUAGE PROCESSING

A method, a computer program product, and a computer system for identifying user preferences and changing settings of a device based on natural language processing. One or more programs running in background on the device capture an input of natural language from a user of the device, match the input of the natural language to a user frustration, map the user frustration to one or more solutions that make one or more changes of settings on the device, apply the one or more changes of settings to set user preference settings on the device, and store the user preference settings in a common store for the user. 1. A method for identifying user preferences and changing settings of a device based on natural language processing , the method comprising:capturing, by one or more programs running in background on the device, an input of natural language from a user of the device;matching, by the one or more programs, the input of the natural language to a user frustration;mapping, by one or more programs, the user frustration to one or more solutions that make one or more changes of settings on the device;applying, by one or more programs, the one or more changes of settings, so as to set user preference settings on the device; andstoring, by one or more programs, the user preference settings in a common store for the user.2. The method of claim 1 , wherein the one or more programs comprise natural language processing and semantic analysis.3. The method of claim 1 , wherein the input of the natural language from the user of the device is a speech of the user.4. The method of claim 1 , wherein the input of the natural language from the user of the device is a text input of the user.5. The method of claim 1 , wherein the user preference settings in the common store are shared by applications on the device.6. The method of claim 1 , wherein a knowledge base of potential user frustrations is used by the one or more programs for matching the input of the natural language to the ...

Split electrode gate trench power device

A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

Accessing cache with access delay reduction mechanism

A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.

Novel Ester Compounds, Method for the Production Thereof and Use Thereof

The invention relates to ester compounds of the general formula (I) 5. The mixture of at least two ester compounds as claimed in claim 1 , wherein two of the at least two ester compounds in each case are regioisomers of one another.6. The mixture of least two ester compounds as claimed in claim 2 , wherein two of the at least two ester compounds in each case are regioisomers of one another.7. The mixture of least two ester compounds as claimed in claim 3 , wherein two of the at least two ester compounds in each case are regioisomers of one another.8. The mixture of least two ester compounds as claimed in claim 4 , wherein two of the at least two ester compounds in each case are regioisomers of one another.9. The mixture of least two ester compounds as claimed in claim 1 , further comprising at least one further ester not having the general formula (I).10. The mixture of least two ester compounds as claimed in claim 9 , wherein the at least one further ester is selected from the group consisting of trimethylolpropane and pentaerythritol esters claim 9 , TMP complex esters in fully or partly esterified form with saturated and/or mono- or polyunsaturated carboxylic acids of chain length C6-C36 claim 9 , where these may be linear or branched claim 9 , complex esters of dimer acids claim 9 , dimer acid esters claim 9 , ethylhexyl dimerate claim 9 , aliphatic carboxylic claim 9 , dicarboxylic esters claim 9 , phosphate esters claim 9 , trimellitic and pyromellitic esters claim 9 , and natural glyceride ester. This application is a divisional of co-pending U.S. application Ser. No. 16/493,830, which issued as U.S. Pat. No. 10,829,436, on Nov. 10, 2020, and which is a 35 U.S.C. 371 National Stage application of PCT/EP2018/000197, filed Apr. 11, 2018 and claiming priority to German Application Nos. DE 10 2017 003 647.0, filed on Apr. 13, 2017, DE 10 2018 002 891.8, filed on Apr. 10, 2018. The entire contents of the above-mentioned patent applications are incorporated herein ...

Combined Gate Trench and Contact Etch Process and Related Structure

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

MONITORING ACCESSES OF A THREAD TO MULTIPLE MEMORY CONTROLLERS AND SELECTING A THREAD PROCESSOR FOR THE THREAD BASED ON THE MONITORING

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed. 1. An apparatus comprising:a plurality of thread processors of a multi-core processor to run a plurality of threads;a first memory controller coupled with the plurality of thread processors, the first memory controller to couple with and to provide access to a first memory;a second memory controller coupled with the plurality of thread processors, the second memory controller to couple with and to provide access to a second memory;a memory controller access monitor unit coupled with a first thread processor of the plurality of thread processors, the memory controller access monitor unit to monitor accesses, by a given thread of the plurality of threads that is to run on the first thread processor, to both the first memory controller and the second memory controller; anda thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a second thread processor of the plurality of thread processors of the multi-core processor for a thread based on the monitored accesses by the given thread to both the first memory controller and the second memory controller, wherein the second thread processor is coupled with the first memory controller through at least one intervening thread processor and is coupled with the second ...

VIDEO CLIPS GENERATION SYSTEM

A method for generating a preview associated with a media file is provided. The method may include receiving a plurality of social comments associated with a plurality of frames corresponding to the media file. The method may also include storing the received plurality of social comments in a repository, whereby the received plurality of social comments is stored with a frame marker. The method may further include analyzing the stored plurality of social comments. The method may additionally include classifying the analyzed plurality of social comments according to at least one sentiment and at least one keyword in the media file. 1. A processor-implemented method for generating a preview associated with a media file , the method comprising:receiving, by a processor, a plurality of social comments associated with a plurality of frames corresponding to the media file;storing the received plurality of social comments in a repository, wherein the received plurality of social comments is stored with a frame marker;analyzing the stored plurality of social comments; andclassifying the analyzed plurality of social comments according to at least one sentiment and at least one keyword in the media file.2. The method of claim 1 , further comprising:receiving a search string regarding a media file preference, wherein the search string is inputted by a user;collecting a first plurality of frames that are associated with a positive sentiment and wherein the first plurality of frames match a criteria associated with the received search string;collecting a second plurality of frames that include a set of frames directly before and a set of frames directly after the collected first plurality of frames that match the criteria associated with the search string;creating a set of snippets based on the collected second plurality of frames;appending the created set of snippets together into a preview; andpresenting the preview to the user, wherein the presented preview is generated from ...

Airbag device mounted on dashboard

An airbag device mounted on dashboard, comprising an inflatable bag and a gas generator arranged inside a dashboard; wherein upon being filled with gas, the inflatable bag is provided with an upper convex chamber, a lower convex chamber and a concave chamber formed by a pull strap between the upper convex chamber and the lower convex chamber; rear of the upper convex chamber and the lower convex chamber are supported against a dashboard surface; and front of the upper convex chamber and the lower convex chamber form a protective surface. The inflatable bag of the airbag device has a reduced volume, and the gas generator matching the inflatable bag has a reduced output. Moreover, the inflatable bag can maintain the scope and effect of protection to occupant due to its adequate energy absorption ability.

Method, apparatus, and electronic device for improving CPU performance

Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

Power semiconductor device with interconnected gate trenches

A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.

Buried bus and related method

A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.

TRANSISTOR DEVICE AND METHOD FOR PRODUCING A TRANSISTOR DEVICE

A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

POWER SEMICONDUCTOR DEVICE HAVING COUNTER-DOPED REGIONS IN BOTH AN ACTIVE CELL REGION AND AN INACTIVE CELL REGION

A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings. Methods of producing the ...

System and method for boot loading of programs within a host operating environment having one or more linked guest operating systems

A system and method for loading programs during a system boot using stored configuration data in a predetermined file system from a prior session and providing the stored configuration data to a guest operating system capable of communication with a host operating system, during start-up, within a computing environment having a hypervisor, in a predetermined manner.

Method for replenishing a thread queue with a target instruction of a jump instruction

Methods and electronic circuits for executing instructions in a central processing unit (CPU) are provided. One of the methods includes forming an instruction block by sequentially fetching, from a current thread queue, one or more instructions including one jump instruction, wherein the jump instruction is the last instruction in the instruction block; transmitting the instruction block to a CPU execution unit for execution; replenishing the current thread queue with at least one instruction to form a thread queue to be executed; determining a target instruction of the jump instruction according to an execution result of the CPU execution unit; determining whether the target instruction is contained in the thread queue to be executed; and if not, flushing the thread queue to be executed, obtaining the target instruction and adding the target instruction to the thread queue to be executed.

MANNICH-BASE INHIBITOR FOR DECALCIFICATION, PREPARATION METHOD AND APPLICATION THEREOF

A mannich-base inhibitor for decalcification, a preparation method and application thereof are provided. The inhibitor comprises 10-80% mannich-base component calculated in the total weight percent of the inhibitor, while the rest is at least one compound selected from imidazoline inhibitor with molecular weight between 110 and 750, and alkynyloxy amine inhibitor. The mannich-base inhibitor component is prepared through mannich reaction with 1 mol organic polyamine containing three or more primary amine bases and/or secondary amine bases, 3-7 mol ketones, and 3-7 mol aldehydes. The inhibitor which can be effectively compounded and cooperated with oil demulsifying agent and oil decalcifying agent, have the advantages of stable property, strong absorbability, high film strength and film density with its inhibition rate exceeding 90%. The inhibitor is especially adapted for inhibiting the steel corrosion caused by the mixed medium of salt, acid and water from the desalination and dehydration apparatus of oil refinery below 160° C. 1. A Mannich-base inhibitor for decalcification , comprising: a multi-branched Mannich base inhibiting component of 10% to 80% of the total weight of the Mannich-base inhibitor for decalcification and one or more of imidazoline corrosion inhibitors and alkynoxy amine corrosion inhibitors as the balance.2. The Mannich-base inhibitor for decalcification according to claim 1 , wherein the multi-branched Mannich-base inhibiting component is prepared from 1 mol of an organic polyamine containing three or more primary amino groups and/or secondary amino groups claim 1 , 3 to 7 mol of a ketone and 3 to 7 mol of an aldehyde through a Mannich reaction.3. The Mannich-base inhibitor for decalcification according to claim 1 , wherein the molecular weight of the imidazoline corrosion inhibitor is 110 to 750.4. The Mannich-base inhibitor for decalcification according to claim 1 , wherein the alkynoxy amine corrosion inhibitor comprises one or more of an ...

Reduced Gate Charge Trench Field-Effect Transistor

In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET.

Power semiconductor device with interconnected gate trenches

A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.

FIELD PLATE ANCHORING STRUCTURE FOR TRENCH-BASED SEMICONDUCTOR DEVICES

A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Semiconductor Device with Superjunction and Oxygen Inserted Si-Layers

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. 1. A semiconductor device , comprising:a source region and a drain region of a first conductivity type;a body region of a second conductivity type between the source region and the drain region;a gate configured to control current through a channel of the body region;a drift zone of the first conductivity type between the body region and the drain region;a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone; anda diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.2. The semiconductor device of claim 1 , wherein the diffusion barrier structure is also disposed along a bottom face of the regions of the second conductivity type.3. The semiconductor device of claim 1 , wherein the drift zone contacts a bottom face of the regions of the second conductivity type.4. The semiconductor device of claim 1 , wherein the drain region is formed ...

Method for fabricating a shallow and narrow trench FET and related structures

Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

CONCURRENTLY ACCESSING MEMORY

When a first transaction needs to conduct a writing operation to first data, after there is a determination that there exists a second transaction that has conducted a reading operation of the first data or is to conduct a reading operation of the first data, a record that indicates a conflict between the writing operation of the first transaction and the reading operation of the second transaction is generated. A processing of the second transaction is performed. After the processing is completed, the second transaction is submitted and the first transaction is notified according to the record. A processing of the first transaction is performed. After the processing is completed and a notification of the second transaction is received, the first transaction is submitted. The present techniques improve concurrently visiting transaction memory at a multi-core system, avoid rollbacks incurred by conflicts, and improve overall system performance. 1. A method comprising:generating a record that indicates a conflict between the writing operation of a first transaction and the reading operation of a second transaction when the first transaction needs to conduct a writing operation to first data, after determining that the second transaction has conducted a reading operation of the first data or is to conduct the reading operation of the first data;performing a processing of the second transaction, and, after the processing of the second transaction is completed, submitting the second transaction and notifying the first transaction according to the record; andperforming a processing of the first transaction, and, after the processing of the first transaction is completed and a notification of the second transaction is received, submitting the first transaction.2. The method of claim 1 , wherein the generating the record that indicates the conflict between the writing operation of the first transaction and the reading operation of the second transaction comprises:setting a ...

Trench MOSFET technology for DC-DC converter applications

A trench power semiconductor device including a recessed termination structure.

Test strip detection system

A test strip detection system, comprising a test strip card (1) and a detection device (2); the test strip card (1) comprises a card box (16), a built-in test strip (15) and an electronic label (20) matched with the built-in test strip (15); the electronic label (20) stores parameters such as the standard working curve of an object to be detected and the like; the detection device (2) comprises an optical system (3), a photoelectric detector (4), an analog/digital converter (5), a data processing device (6), an electronic label read-write module (10) with an aerial (11), a voice module (34), a cell box (7) and an output display device (8). The system further comprises a wireless communication module (12) and a wireless network system (13) connected with the wireless communication module (12) and comprising a remote server (14). The data processing device (6) calculates a sample detection result according to the characteristic frequency optical signals transmitted by a test strip detection ...

Controlled resistance integrated snubber for power switching device

A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.

SEMICONDUCTOR DEVICE HAVING NEEDLE-SHAPE FIELD PLATE TRENCHES AND NEEDLE-SHAPED GATE TRENCHES

A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches. 1. A semiconductor device , comprising:a semiconductor substrate;a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another;a first dielectric layer above the semiconductor substrate;a gate interconnect structure comprising electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; anda field plate interconnect structure electrically isolated from the gate interconnect structure and comprising second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.2. The semiconductor device of claim 1 , further comprising:a second dielectric layer on the first dielectric layer,wherein the electrically conductive lines of the gate interconnect structure are sandwiched between the second dielectric layer and the first dielectric layer, ...

Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches

Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.

Trench FET having merged gate dielectric

In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode.

Semiconductor structure having integrated snubber resistance

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

Monitoring accesses of a thread to multiple memory controllers and selecting a thread processor for the thread based on the monitoring

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

Flip chip semiconductor device and process of its manufacture

A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.

Combined Gate Trench and Contact Etch Process and Related Structure

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench. 1. A method of forming a semiconductor device , said method comprising:forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer;forming a gate conductive filler in said gate trench;forming a deep body region below said contact trench;forming a contact conductive filler in said contact trench.2. The method of further comprising forming a gate trench dielectric liner in said gate trench.3. The method of further comprising forming an interlayer dielectric layer (IDL) over said gate conductive filler.4. The method of further comprising forming a contact implant at a bottom of said contact trench.5. The method of further comprising forming a barrier layer in said contact trench.6. The method of further comprising forming a body region and a source region in said semiconductor substrate.7. The method of wherein said gate conductive filler comprises doped polycrystalline silicon.8. The method of wherein said contact conductive filler comprises tungsten.9. The method of further comprising forming a metalization layer over the contact trench.10. The method of wherein said gate trench extends through a source region and a body region claim 1 , and into a drift region of said semiconductor substrate.11. The ...

Method and device for measurement compensation for inter-system reselection and handover in dual-mode terminal

Method and device for measurement compensation for inter-system reselection and handover in a dual-mode terminal are disclosed. The method comprises: a GSM physical layer reporting measured RSCP and Ec/No values of a 3G neighbor cell to a radio resource management layer with inter-layer primitives; the radio resource management layer receiving the inter-layer primitives carrying the RSCP and Ec/No values reported by the physical layer, and performing measurement compensation for the inter-layer primitives in the radio resource management layer. Since the measurement compensation is performed in the radio resource management layer of the terminal, the terminal preferably resides on 3G network when detecting the 3G network. It can be applied to measurement compensation for the inter-system reselection and handover when 2G and 3G mobile communication systems co-exist. The terminal is more easily retained on the network of one of the systems and allowed to make a priority selection of the networks ...

Controlled Resistance Integrated Snubber for Power Switching Device

A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode. 1. A method of forming a semiconductor device , comprising:providing a semiconductor substrate comprising a main surface, a rear surface vertically spaced apart from the main surface, an active device region, and an inactive region that is laterally adjacent to the active device region;forming a switching device in the active device region, the switching device comprising doped source, body, drift and drain regions, and electrically conductive gate and field electrodes, the gate and field electrodes being insulated from one another and from the substrate, the gate electrode being adjacent to the body region and configured to control and electrical connection between the source and drain regions, the field electrode being adjacent to the drift region;forming an intermetal dielectric layer disposed on the main surface over the active and inactive regions;forming an electrically conductive source pad in a first metallization layer, the first metallization layer being formed on the intermetal dielectric layer; andforming a resistor that is connected between the source pad and the field electrode of the ...

PROCESS FOR PREPARING MICROCAPSULES

Described herein are a process for the preparation of a microcapsule slurry, and the microcapsule slurry. Perfuming compositions and consumer products including the microcapsule slurry, in particular perfumed consumer products in the form of home care or personal care products, are also described. 1. A process for the preparation of a core-shell microcapsule slurry , the process comprising the following steps:a) dissolving at least an amino-acid derived polyisocyanate having at least two isocyanate functional groups in a hydrophobic material to form an oil phase;b) preparing a dispersing phase comprising a stabilizer, wherein the dispersing phase is not miscible with the oil phase;c) adding the oil phase into the dispersing phase to form a two-phases dispersion;d) optionally, adding a reactant to the dispersion obtained in step c); ande) performing a curing step to form core-shell microcapsules in the form of a slurry.2. The process according to claim 1 , characterized in that a reactant chosen in the group consisting of an amino acid claim 1 , a polyamine claim 1 , a polyol claim 1 , and mixtures thereof is added in step d).3. The process according to claim 1 , characterized in that the reactant is used an amount of between 0.1 and 15% claim 1 , these percentages being defined by weight relative to the total weight of the slurry.4. The process according to claim 2 , characterized in that the reactant is a polyamine selected from the group consisting of water soluble guanidine salts claim 2 , guanidine claim 2 , tris-(2-aminoethyl)amine claim 2 , N claim 2 ,N claim 2 ,N′ claim 2 ,N′-tetrakis(3-aminopropyl)-1 claim 2 ,4-butanediamine and N claim 2 ,N′-bis(3-aminopropyl)-ethylenediamine claim 2 , a polyaminoester claim 2 , and mixtures thereof.6. The process according to claim 2 , characterized in that the reactant is an amino acid.7. The process according to claim 1 , characterized in that the amino-acid derived polyisocyanate is selected from the group consisting of ...

Power FET Having Reduced Gate Resistance

In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including a gate pad, a gate highway, and multiple gate buses. The gate buses are formed from a first metal layer having a first thickness, while the gate pad and the gate highway each include a metal stack including the first metal layer and a second metal layer. The second metal layer has a second thickness substantially greater than the first thickness, thereby reducing the gate resistance of the power FET. 1. A power field-effect transistor (FET) comprising:a drain, a source, and a gate;a gate contact including a gate pad, a gate highway, and a plurality of gate buses;said plurality of gate buses being formed from a first metal layer having a first thickness;said gate pad and said gate highway each including a metal stack comprising said first metal layer and a second metal layer;said second metal layer having a second thickness substantially greater than said first thickness, thereby reducing a gate resistance of said power FET.2. The power FET of claim 1 , wherein said second thickness is at least three times greater than said first thickness.3. The power FET of claim 1 , wherein said first metal layer and said second metal layer comprise a same metal.4. The power FET of claim 1 , wherein at least one of said first metal layer and said second metal layer comprises aluminum.5. The power FET of claim 1 , wherein at least one of said first metal layer and said second metal layer comprises aluminum-silicon.6. The power FET of claim 1 , wherein at least one of said first metal layer and said second metal layer comprises copper.7. The power FET of claim 1 , further comprising a source contact formed from said second metal layer and situated over and electrically isolated from said plurality of gate buses.8. The power FET of claim 1 , wherein said power FET is a vertical group IV FET.9. The power FET of claim 1 , wherein ...

Power devices having trench-based source and gate electrodes

A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

Identifying user preferences and changing settings of a device based on natural language processing

A method, a computer program product, and a computer system for identifying user preferences and changing settings of a device based on natural language processing. One or more programs running in background on the device capture an input of natural language from a user of the device, match the input of the natural language to a user frustration, map the user frustration to one or more solutions that make one or more changes of settings on the device, apply the one or more changes of settings to set user preference settings on the device, and store the user preference settings in a common store for the user.

Controlled Resistance Integrated Snubber for Power Switching Device

A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region. 1. A semiconductor device , comprising:a semiconductor substrate comprising a main surface, a rear surface vertically spaced apart from the main surface, an active device region, and an inactive region that is laterally adjacent to the active device region;a switching device disposed in the active device region, the switching device comprising doped source, body, drift and drain regions, and electrically conductive gate and field electrodes, the gate and field electrodes being insulated from one another and from the substrate, the gate electrode being adjacent to the body region and configured to control an electrical connection between the source and drain regions, the field electrode being adjacent to the drift region;an intermetal dielectric layer disposed on the main surface over the active and inactive regions;an electrically conductive source pad formed in a first metallization layer, the first metallization layer being formed on the intermetal dielectric layer; anda resistor connected between the source pad and the ...

Method, apparatus, and electronic device for improving parallel performance of CPU

Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

Method and device for measurement compensation for inter-system reselection and handover in dual-mode terminal

Method and device for measurement compensation for inter-system reselection and handover in a dual-mode terminal are disclosed. The method comprises: a GSM physical layer reporting measured RSCP and Ec/No values of a 3G neighbor cell to a radio resource management layer with inter-layer primitives; the radio resource management layer receiving the inter-layer primitives carrying the RSCP and Ec/No values reported by the physical layer, and performing measurement compensation for the inter-layer primitives in the radio resource management layer. Since the measurement compensation is performed in the radio resource management layer of the terminal, the terminal preferably resides on 3G network when detecting the 3G network. It can be applied to measurement compensation for the inter-system reselection and handover when 2G and 3G mobile communication systems co-exist. The terminal is more easily retained on the network of one of the systems and allowed to make a priority selection of the networks. 1. A method for measurement compensation for inter-system reselection and handover in a dual-mode terminal , the method comprising the steps of:A. a GSM physical layer reporting measured RSCP and Ec/No values of a 3G neighbor cell to a radio resource management layer with inter-layer primitives;B. the radio resource management layer receiving the inter-layer primitives carrying the RSCP and Ec/No values reported by the physical layer, and performing measurement compensation for the inter-layer primitives in the radio resource management layer to form a new measurement report; andC. the radio resource management layer reporting the measurement report to a network.2. The method of claim 1 , wherein it further comprises the following steps before the step A:a. adding three NV items to non-volatile random access memory of the terminal, the first NV item being a compensation switch item used for determining whether to perform measurement compensation, the second NV item being a ...

Methods and Formulations for Inhibiting Degradation of Photosensitive Sweeteners and Sweetener Enhancers

Methods of inhibiting the degradation of a photosensitive sweetener or a sweetness enhancer in a food or beverage formulation, the method comprising adding a photodegradation-inhibiting amount of one or more antioxidants to the food or beverage formulation; and/or packaging the food or beverage formulation in a UV absorbing container are provided. Food or beverage formulations comprising an antioxidant and a photosensitive sweetener or sweetness enhancer, and/or that is packaged in a UV absorbing package or dark-colored package are also provided. 1. A method of inhibiting the degradation of a photosensitive sweetener or sweetness enhancer in a food or beverage formulation , the method comprising packaging the food or beverage formulation in a UV absorbing container and/or adding a photodegradation-inhibiting amount of one or more antioxidants to the food or beverage formulation.2. The method of claim 1 , wherein the method comprises packaging the food or beverage formulation in a UV absorbing container.3. The method of claim 1 , wherein the method comprises adding a photodegradation-inhibiting amount of one or more antioxidants to the food or beverage formulation.4. The method of claim 1 , wherein the photosensitive sweetener is monatin.5. The method of claim 1 , wherein the photosensitive sweetness enhancer is 3-((4-amino-2 claim 1 ,2-dioxido-1H-benzo[c][1 claim 1 ,2 claim 1 ,6]thiadiazin-5-yl)oxy)-2 claim 1 ,2-dimethyl-N-propylpropanamide.6. The method of claim 1 , wherein the UV absorbing container is a polyethylene terephthalate (PET) container with a UV barrier.7. The method of claim 6 , wherein the container is green-colored.8. The method of claim 6 , wherein the container is brown-colored.9. The method of claim 1 , wherein the UV absorbing container comprises one or more UV absorbing compounds.10. The method of claim 1 , wherein the UV absorbing container is a container at least partially covered with a film impregnated with one or more UV absorbing compounds ...

Novel Ester Compounds, Method for the Preparation Thereof and Use Thereof

Ester compounds, such as for use in a lubricant, are based on di-, tri- or higher functional carboxylic acids according to formula (I) 2. The ester compound as claimed in claim 1 , in which the radical Z is selected from the group consisting of hydrogenated or non-hydrogenated dimer acid claim 1 , hydrogenated or non-hydrogenated trimer acid claim 1 , phthalic acid claim 1 , itaconic acid claim 1 , oxalic acid claim 1 , 2 claim 1 ,2′-thiodiacetic acid claim 1 , 3 claim 1 ,3′-thiodipropionic acid claim 1 , admergic acid claim 1 , 2 claim 1 ,5-furandicarboxylic acid claim 1 , cyclohexane-1 claim 1 ,4-dicarboxylic acid claim 1 , cyclohexane-1 claim 1 ,2-dicarboxylic acid claim 1 , phenyl succinic acid claim 1 , diglycolic acid.4. The ester compound as claimed in claim 3 , in which the radical Z is selected from the group consisting of hydrogenated or non-hydrogenated dimer acid claim 3 , phthalic acid claim 3 , oxalic acid claim 3 , 2 claim 3 ,2′- thiodiacetic acid claim 3 , 3 claim 3 ,3′-thiodipropionic acid claim 3 , admergic acid claim 3 , cyclohexane-1 claim 3 ,4-dicarboxylic acid claim 3 , cyclohexane-1 claim 3 ,2-dicarboxylic acid claim 3 , phenylsuccinic acid claim 3 , diglycolic acid.6. The method for producing the ester compound of the general formula (I) or (II) as claimed in claim 5 , in which the unsaturated fatty acid is selected from the group consisting of oleic acid and erucic acid; the alcohol is selected from the group consisting of 2-ethylhexan-1-ol claim 5 , 2-hexyldecan-1-ol claim 5 , 2-octyldodecan-1-ol claim 5 , 2-propylheptan-1-ol and isoamyl alcohol and the catalyst in reaction step (A) is perchloric acid and in reaction step (D) is p-toluenesulfonic acid.7. A method for producing the ester compound of the general formulae (I) or (II) obtainable by(A) reacting a di-, tri- or higher functional carboxylic acid with a long-chain fatty acid having hydroxyl groups in the presence of a catalyst at 120 to 150° C.,(B) reducing the pressure,(C) ...

Multi-core processor supporting cache consistency, method, apparatus and system for data reading and writing by use thereof

A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.

Combined gate and source trench formation and related structure

A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.

Method of manufacturing a trench FET having a merged gate dielectric

In one implementation, a method for fabricating a trench FET includes providing a semiconductor substrate including a drain region and a drift zone over the drain region, forming a plurality of depletion trenches over the drain region, each of the plurality of depletion trenches having a depletion trench dielectric and a depletion electrode, and forming a respective bordering gate trench alongside each of the plurality of depletion trenches, each bordering gate trench having a gate electrode and a gate dielectric.

MONITORING ACCESSES OF A THREAD TO MULTIPLE MEMORY CONTROLLERS AND SELECTING A THREAD PROCESSOR FOR THE THREAD BASED ON THE MONITORING

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed. 1. A method comprising:running a plurality of threads on a plurality of thread processors;monitoring memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, to both a first memory through a first memory controller and a second memory through a second memory controller;selecting a second thread processor of the plurality for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory; andinitiating installation of the thread, for which the second thread processor was selected, on the second thread processor.2. The method of claim 1 , wherein selecting comprises selecting the second thread processor to improve overall memory access latency from the second thread processor to the first and second memories.3. The method of claim 1 , wherein selecting comprises selecting the second thread processor based on a relative proportion of the monitored memory accesses to the first and second memories.4. The method of claim 1 , wherein selecting comprises selecting the second thread processor based on a first queuing delay associated with memory accesses to the first memory and a second queuing delay associated with memory accesses to the second memory.5. The method of claim 1 , wherein ...

METHOD AND PROCESSOR FOR PROCESSING DATA

A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors. 1. A method for processing data using multiple processors with transactional memory , the method comprising:processing a transaction using a first processor, wherein the transaction includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor; andcommitting the transaction to the transactional memory system, wherein the committing includes, in response to detecting a preset condition of recent modifications on the first data prior to the write operation, writing the first data in the private cache of the first processor into a last level cache (LLC) accessible by the multiple processors, and invalidating the first data in the private cache of the first processor.2. The method as recited in claim 1 , wherein the preset condition of recent modifications comprises that claim 1 , prior to the write operation claim 1 , the first data was last modified by a second processor different from the first processor.3. The method as recited in claim 1 , wherein the committing the transaction further includes:setting a cache line ...

Video clips generation system

A method for generating a preview associated with a media file is provided. The method may include receiving a plurality of social comments associated with a plurality of frames corresponding to the media file. The method may also include storing the received plurality of social comments in a repository, whereby the received plurality of social comments is stored with a frame marker. The method may further include analyzing the stored plurality of social comments. The method may additionally include classifying the analyzed plurality of social comments according to at least one sentiment and at least one keyword in the media file.

Semiconductor device including a voltage controlled termination structure and method for fabricating same

According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device.

Flip chip semiconductor device and process of its manufacture

A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.

PROCESS FOR PRODUCING 2-(CYCLOHEX-1'-ENYL)CYCLOHEXANONE

The present invention discloses a process for producing 2-(cyclohex-1′-enyl)cyclohexanone by an auto-condensation of cyclohexanone at a certain temperature in the presence of a certain solid acidic catalyst. 1. A process for producing 2-(cyclohex-1′-enyl)cyclohexanone by an auto-condensation of cyclohexanone at a certain temperature in the presence of a solid acidic catalyst.3. The process according to claim 2 , wherein x is 1 to 2 claim 2 , and y is 1 to 2.4. The process according to claim 1 , wherein the solid acidic catalyst is present at an amount of 2% by weight or above claim 1 , based on the total weight of the reaction solution.5. The process according to claim 1 , wherein the reaction is carried out at a temperature of from 100 to 160° C.6. The process according to claim 5 , wherein the reaction is carried out at a temperature of from 130 to 150° C. The present invention relates to a process for producing 2-(cyclohex-1′-enyl)cyclohexanone by an auto-condensation of cyclohexanone at a certain temperature in the presence of a certain solid acidic catalyst.2-(cyclohex-1′-enyl)cyclohexanone is an important, widely used chemical product. In addition to being used as a modifying agent for epoxy resins, a plasticizer, and a crosslinking agent for polymers, it is also an intermediate in the synthesis of o-phenylphenol, which is an important fine organic chemical. O-phenylphenol can be widely used in synthesizing dyes, surfactants, fire retardants, plastic stabilizing agents, pharmaceuticals, etc., and its market demand also increases continuously as its uses are developed unceasingly.O-phenylphenol can be produced: 1. by dehydro-condensation of cyclohexanone, 2. by sulfonation- or halogenation-hydrolysis of phenylbenzene, 3. by diazotization-hydrolysis of aminophenylbenzene, 4. by hydrolysis of chlorobenzene under high pressure, 5. from dibenzofuran, or 6. by coupling of chlorobenzene and phenol. Among the aforementioned synthesis processes, the most widely used ...

Trench MOSFET and Method for Fabricating Same

According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. 1. A trench field-effect transistor (trench FET) comprising:a trench formed in a semiconductor substrate, said trench including a gate dielectric disposed therein;a source region disposed adjacent said trench;a gate electrode including a lower portion disposed in said trench and a proud portion extending laterally over said source region.2. The trench FET of further comprising a silicide gate contact formed over said proud portion of said gate electrode.3. The trench FET of claim 1 , wherein a portion of said gate dielectric extends laterally over said semiconductor substrate.4. The trench FET of further comprising dielectric spacers formed adjacent respective sidewalls of said proud portion of said gate electrode.5. The trench FET of further comprising a dielectric cap formed over said proud portion of said gate electrode.6. The trench FET of claim 1 , wherein a silicide source contact extends vertically along a sidewall of said source region.7. The trench FET of further comprising a channel region disposed adjacent said trench below said source region.8. The trench FET of claim 7 , wherein said silicide source contact extends laterally over said channel region.9. A method for fabricating a trench field-effect transistor (trench FET) comprising:forming a trench in a semiconductor ...

METHOD TO QUANTIFY TELOMERE LENGTH AND GENOMIC MOTIFS

The present invention provides novel compositions and methods for assessing the size of tandem repeat sequences, e.g., telomeres, within a genome, using specially designed Molecular Inversion Probes (MIPs) and reaction conditions. 1. A single-stranded DNA probe for determining telomere length and/or the copy number of a tandem repeat sequence , the probe comprising:i) a 5′ homology region that extends to the 5′ end of the probe and that comprises a nucleotide sequence complementary to the tandem repeat sequence;ii) a linker region; and upon binding of the 5′ homology region and the 3′ homology regions to the same strand of a template DNA such that the 3′ homology region is immediately 3′ of the 5′ homology region within a single repeat unit on the template, and the 3′ end of the 3′ homology region and the 5′ end of the 5′ homology region are thus separated by a nucleotide gap of less than one complete repeat unit on the template DNA,', 'the nucleotide gap of less than one complete repeat unit comprises at most two different bases., 'iii) a 3′ homology region that extends to the 3′ end of the probe and that comprises a nucleotide sequence complementary to the tandem repeat sequence, such that the 5′ homology region and 3′ homology region can bind to the same strand of a template DNA comprising the tandem repeat sequence; wherein'}2. The probe of claim 1 , wherein the tandem repeat sequence is a telomere sequence.3. The probe of claim 2 , wherein the telomere is a human telomere.4. The probe of claim 1 , wherein the nucleotide sequences of the 5′ and 3′ homology regions are 100% complementary to the tandem repeat sequence.5. The probe of claim 1 , wherein the 5′ and 3′ homology regions are each 15-25 nucleotides long.6. The probe of claim 1 , wherein each repeating unit of the tandem repeat sequence is 2-10 nucleotides long.7. The probe of claim 1 , wherein the linker region comprises one or more sequence elements selected from the group consisting of a common primer ...

Buck Converter Power Package

One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip. 1. A high power semiconductor package comprising:a vertical conduction control transistor comprising a control source and a control gate on a bottom surface thereof, and a control drain being electrically coupled to said bottom surface of said vertical conduction control transistor;a vertical conduction sync transistor comprising a sync drain on a top surface thereof and a sync source and a sync gate on a bottom surface thereof;wherein said control source, said control gate, and said control drain are electrically and directly surface mountable on a support surface.2. The high power semiconductor package of claim 1 , wherein said sync drain is coupled to said support surface through a conductive clip.3. The high power semiconductor package of claim 1 , wherein said control drain does not use a conductive clip for connection to said support surface.4. The high power semiconductor package of claim 1 , wherein said control drain does not use a bond wire for connection to said support surface.5. The high power ...

METHOD AND APPARATUS FOR SHARING USER INFORMATION IN BROWSERS OF A MOBILE TERMINAL

A method for sharing user information in browsers of a mobile terminal is disclosed in the present invention and comprises steps of: receiving a second operating command for importing the user information to a second browser; executing a first operating command for exporting the user information from the first browser in accordance with the second operating command for importing the user information to the second browser, and the first operating command is a command for exporting the user information from the first browser. 1. A method for sharing user passwords in browsers of a mobile terminal , comprising:A. installing a menu for importing and exporting saved user information, which includes user accounts and corresponding passwords for websites, in each of the browsers of the mobile terminal;B. exporting the user information saved in the browser to a file in a predetermined format and saving and encrypting the file when the user information is requested to be exported from the browser and the browser receives an operating command of the user from the menu;C. decrypting and importing the user information encrypted and saved in the file in the predetermined format into the browser when the exported user information is requested to be imported in the browser and the browser receives the operating command of the user from the menu.2. The method for sharing the user passwords in the browsers of the mobile terminal according to claim 1 , wherein Step B comprises:B1. choosing a menu to export saved user accounts and passwords for websites when the saved user information is requested to be exported from the browser and the browser receives the operating command of the user, and choosing a path for saving the file and the predetermined format to save the file;B2. adding a corresponding bit zone to the user information for each website in the browser and saving them in the file according to the chosen predetermined format;B3. encrypting the file saved in the predetermined ...

BLOCKCHAIN-BASED FINANCIAL TRADING EXECUTING METHOD AND APPARATUS, AND ELECTRONIC DEVICE

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based financial trading and applied to a distributed exchange set up based on a blockchain are provided. The distributed exchange includes a plurality of trading centers deployed in a distributed manner. One of the methods includes: receiving a trade order submitted by a user terminal in communication with a local trading center in the blockchain; transmitting the trade order to other trading centers in the blockchain and receiving trade orders from the other trading centers; generating an order book by performing an order matching process on the received trade orders, transmitting the generated order book to the other trading centers, and receiving order books from the other trading centers; and initiating a consensus process on the order books and executing the matched order in an order book for which consensus has been reached. 1. A method for blockchain-based financial trading , applied to a distributed exchange set up based on a blockchain , the distributed exchange comprising a plurality of trading centers deployed in a distributed manner , the method comprising:receiving, by a computing device associated with one of the plurality of trading centers, a trade order from a user terminal in communication with the trading center;calculating, by the computing device associated with the trading center, a propagation delay of the received trade order, wherein the propagation delay represents a propagation time of the trade order transmitted from the user terminal to the trading center in communication therewith;transmitting, by the computing device associated with the trading center, the received trade order and the propagation delay of the trade order to computing devices associated with other ones of the plurality of trading centers in the blockchain;receiving, by the computing device associated with the trading center, a plurality of trade orders and ...

METHOD, SERVER, SMART TERMINAL AND STORAGE DEVICE FOR ACCESS AUTHENTICATION

Disclosed is a method for access authentication. The method includes: receiving profile information of a visitor through a server, and generating a visitor code and transmitting the same to a visitor terminal, and generating a random code based on a valid visitor code, and receiving a decoding result based on decoding the random code and the visitor code by the visit terminal, and predetermining an access authority for the visitor for a predetermined time as the decoding result is successfully matched. 1. A server , including a processor , a memory and instructions stored in the memory , wherein the processor executes the instructions to implement following steps:receiving profile information of a visitor from a management terminal;generating a corresponding visitor code based on the profile information of the visitor and transmitting the same to a visitor terminal, wherein the visitor code carries authentication information;receiving a visit time change request from the visit terminal, and forwarding the visit time change request to the management terminal;receiving confirmation information of the management terminal, and regenerating the visitor code based on the profile information of the visitor and a changed visit time, and transmitting the visitor code to the visitor terminal;receiving the visitor code from the visitor terminal, and generating a random code and delivering the random code to the visitor terminal as determining that the visitor code is valid;receiving a decoding result from the visit terminal, and determining that the visitor is a legitimate visitor and predetermining an access authority for the visitor for a predetermined time as the decoding result is successfully matched;issuing an alarm prompt as the predetermined time is up;extending or terminating the access authority of the visitor according to a response of the management terminal to the alarm prompt;wherein the authentication information includes at least an access password, access ...

AN AIRBAG DEVICE MOUNTED ON DASHBOARD

An airbag device mounted on dashboard, comprising an inflatable bag and a gas generator arranged inside a dashboard; wherein upon being filled with gas, the inflatable bag is provided with an upper convex chamber, a lower convex chamber and a concave chamber formed by a pull strap between the upper convex chamber and the lower convex chamber; rear of the upper convex chamber and the lower convex chamber are supported against a dashboard surface; and front of the upper convex chamber and the lower convex chamber form a protective surface. The inflatable bag of the airbag device has a reduced volume, and the gas generator matching the inflatable bag has a reduced output. Moreover, the inflatable bag can maintain the scope and effect of protection to occupant due to its adequate energy absorption ability. 1. An airbag device mounted on dashboard , comprising:{'b': 1', '2, 'an inflatable bag () and a gas generator () arranged inside a dashboard; wherein'}{'b': 1', '10', '11', '12', '13', '10', '11, 'upon being filled with gas, the inflatable bag () is provided with an upper convex chamber (), a lower convex chamber () and a concave chamber () formed by a pull strap () between the upper convex chamber () and the lower convex chamber ();'}{'b': 10', '11', '7, 'the rear of the upper convex chamber () and the lower convex chamber () are supported against a dashboard surface (); and'}{'b': 10', '11', '4, 'the front of the upper convex chamber () and the lower convex chamber () form a protective surface ().'}21210112212. The airbag device mounted on dashboard according to claim 1 , wherein there is at least one concave chamber () that is adjacent to the upper convex chamber () or the lower convex chamber () with an intermediate convex chamber () formed between each adjacent two concave chambers ().3. The airbag device mounted on dashboard according to claim 1 , wherein{'b': 1', '14', '15', '13, 'said inflatable bag () is formed by sewing side edges of two side pieces () with ...

Trench Field Electrode Termination Structure for Transistor Devices

A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode. 1. A semiconductor device , comprising:a trench formed in a first main surface of a semiconductor substrate and extending lengthwise in a direction parallel to the first main surface;a body region of a second conductivity type adjoining the trench;a source region of a first conductivity type adjoining the trench above the body region;a drift region of the first conductivity type adjoining the trench below the body region;a field electrode disposed in a lower part of the trench and separated from the semiconductor substrate; anda gate electrode disposed in an upper part of the trench and separated from the semiconductor substrate and the field electrode,wherein a first section of the field electrode is buried below the gate electrode in the trench,wherein a second section of the field electrode transitions upward from the first section in a direction toward the first main surface,wherein the separation between the second section of the field electrode and the gate electrode is greater than the separation between the first section of the field electrode and the gate electrode.2. (canceled)3. The semiconductor device ...

LIGHTING DEVICE AND BULB

A light-emitting device and a bulb include a light engine structure. The light engine structure includes a first seal cavity and a light source which is provided in the first seal cavity. The first seal cavity filled with an insulating liquid or gas. The light source is exposed to the insulating liquid or gas. A second seal cavity is provided outside the first seal cavity, which is filled with an insulating liquid or gas. This invention provides a sealed light-emitting engine filled with heat-dissipating liquid or gas, in which a second layer of sealed heat-dissipating structure is disposed outside the light-emitting engine, and the die structure exposed to the heat-dissipating liquid or gas, which solves the heat-dissipating problem of lamps. Furthermore, a design of the light-emitting engine provides a foundation for various applications of bulb lamps, and solves defects of cost and light efficiency of common bulb lamps at present. 1. A light-emitting device comprising:a light engine structure, wherein the light engine structure comprises a light source and a first seal cavity, the light source is provided in the first seal cavity, and the first seal cavity is filled with an insulating liquid or gas, and the light source in the first seal cavity is exposed to the insulating liquid or gas;a second seal cavity is provided outside the first seal cavity, and the second seal cavity is filled with an insulating liquid or gas; andthe light source comprises a pin which extends from the first seal cavity to the second seal cavity, and the first seal cavity and the second seal cavity are light-permeable seal cavities;wherein the insulating liquid is a liquid with a high heat capacity and light permeability;wherein the insulating liquid is a high temperature resistant liquid.2. The light-emitting device according to claim 1 , wherein the light source comprises a plurality of light-emitting diodes and a substrate claim 1 , the light-emitting diodes are arranged on the ...

VIDEO CLIPS GENERATION SYSTEM

A method for generating a preview associated with a media file is provided. The method may include receiving a plurality of social comments associated with a plurality of frames corresponding to the media file. The method may also include storing the received plurality of social comments in a repository, whereby the received plurality of social comments is stored with a frame marker. The method may further include analyzing the stored plurality of social comments. The method may additionally include classifying the analyzed plurality of social comments according to at least one sentiment and at least one keyword in the media file. 1. A processor-implemented method for generating a preview associated with a media file , the method comprising:receiving, by a processor, a plurality of social comments associated with a plurality of frames corresponding to the media file, wherein the received plurality of social comments comprises collecting a plurality of input from a plurality of different users, wherein the plurality of input is obtained live via an internet, a graphical user interface, an online communication system, or a use of social media via a secondary device connected to a service streaming the media file;storing the streaming media file in a first repository with a plurality of frame markers corresponding to the stored streaming media file;storing the received plurality of social comments in a second repository,analyzing the stored plurality of social comments;annotating each social comment within the analyzed plurality of social comments with at least one sentiment and at least one keyword in the media file;classifying the analyzed annotated plurality of social comments according to the at least one sentiment and the at least one keyword in the media file, wherein classifying the annotated plurality of social comments comprises determining a plurality of positive sentiments about a plurality of frames associated with the media file;receiving a search string ...

Semiconductor Structure Having Integrated Snubber Resistance and Related Method

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions. 1. A semiconductor structure comprising:a source trench in a drift region, said source trench having a source trench dielectric liner and a source trench conductive filler surrounded by said source trench dielectric liner;a source region in a body region over said drift region;a patterned source trench dielectric cap forming an insulated portion and an exposed portion of said source trench conductive filler;a source contact layer coupling said source region to said exposed portion of said source trench conductive filler, said insulated portion of said source trench conductive filler increasing resistance between said source contact layer and said source trench conductive filler under said patterned source trench dielectric cap.2. The semiconductor structure of wherein said insulated portion of said source trench conductive filler is configured to increase damping of output signals generated by said semiconductor structure during electrical operation.3. The semiconductor structure of wherein said insulated portion of said source trench ...

METHOD AND APPARATUS FOR ENABLING PRECISE FOCUSING

Method and apparatus for enabling precise focusing are provided. The method includes obtaining an operation time of the photographing device in real time by a processor, searching a relationship table of preset times and focus range based on the obtained operation time to obtain a focus range corresponding to the obtained operation time; sending the obtained focus range to a driver by the processor, adjusting the distance between a lens and an image sensor based on the focus range by the driver, so that the lens may be located in the focus range, and to adjust the focus range in real time and improve the accuracy of focusing between the lens and the image sensor. 1. A focusing method being used in a photographing device , the photographing device comprising a lens , an image sensor , a processor , a motor , and a driver , wherein the processor is coupled to the image sensor and the driver , respectively , wherein the driver is configured to drive the motor , and wherein the motor is configured to adjust a distance between the lens and the image sensor , the method comprising: search a relationship table of preset times and focus ranges based on the obtained operation time, thereby obtaining a focus range corresponding to the obtained operation time; and', 'send the obtained focus range to the driver; and, 'obtaining, using the processor, an operation time of the photographing device, wherein the processor is further configured tousing the driver to control the motor to adjust the distance between the lens and the image sensor based on the obtained focus range, wherein the distance is within the obtained focus range.2. The method according to claim 1 , wherein the obtaining the operation time comprising:acquiring, using the processor, the operation time of the photographing device based on a preset time interval.4. The method according to claim 3 , wherein the obtaining the focus range corresponding to the obtained operation time further comprises:obtaining, using ...

ACCESSING CACHE

A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance. 1. A method for accessing a cache , the method comprising:reading an access instruction for acquiring data;determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay;accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation in response to determining that the access instruction produces the delay; andmodifying, according to a location of the data acquired by the access instruction, the delay identifier and the location identifier carried by the access instruction.2. The method for accessing the cache of claim 1 , wherein the delay includes a delay produced upon a level-by-level cache access in case of data missing.3. The method for accessing the cache of claim 1 , wherein the delay includes a delay produced when the access instruction executes a computation.4. The method for accessing the cache of claim 1 , wherein the delay identifier and the location identifier carried by the access instruction are identifiers claim 1 , marked with bits claim ...

METHOD AND APPARATUS FOR UPDATING SHARED DATA IN A MULTI-CORE PROCESSOR ENVIRONMENT

Embodiments of the specification provide a method and an apparatus for updating shared data in a multi-core processor environment. The multi-processor environment comprises a multi-core processor. The multi-core processor comprises a plurality of separate processing units (referred to as cores, or core processing units (CPUs) in the specification); the multi-core processor is configured to process a multi-threaded task; the multi-threaded task has shared data to update. The method is executed by any CPU. The method may comprise: requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; and setting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index. 1. A method for updating shared data in a multi-core processor environment , wherein the multi-core processor comprises a plurality of CPUs , the method comprising:requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; andsetting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index.2. The method according to claim 1 , wherein the requesting for a lock comprises:requesting, by the first CPU, for the lock through a lock requesting command, wherein the lock requesting command includes the memory index corresponding to the critical section function.3. The method according to claim 2 , wherein the setting a memory index corresponding to the critical ...

STSCI PROTEIN FOR CHANGING SELF-INCOMPATIBILITY OF DIPLOID POTATO MATERIALS

Provided is a StSCI protein for changing the self-incompatibility of diploid potato materials, wherein the amino acid sequence of the StSCI protein includes or consists of the following sequence: 1) the amino acid sequence represented by SEQ ID NO: 1; or 2) a functional homologous sequence having at least 95% sequence identity with the amino acid sequence represented by SEQ ID NO: 1; or 3) a protein in which one or more (e.g., 1-10) amino acids are added, deleted, or replaced in the amino acid sequence represented by SEQ ID NO: 1 and has the activity of inhibiting self-incompatibility. The advantage of the application is that the StSCI protein may inhibit the cytotoxicity of multiple types of S-RNase, which is hereditary and fundamentally overcomes the defect of self-incompatibility of diploid potatoes, thereby facilitating to realize the cultivation of a high-generation homozygous inbred line of diploid potatoes. 1. A StSCI protein for changing the self-incompatibility of diploid potato materials , wherein the amino acid sequence of the StSCI protein comprises or consists of the following sequence:1) the amino acid sequence represented by SEQ ID NO: 1; or2) a functional homologous sequence having at least 95% sequence identity with the amino acid sequence represented by SEQ ID NO: 1; or3) a protein in which one or more (e.g., 1-10) amino acids are added, deleted, or replaced in the amino acid sequence represented by SEQ ID NO: 1 and has the activity of inhibiting self-incompatibility.2. A nucleotide sequence encoding the StSCI protein of claim 1 , wherein the nucleotide sequence encoding the StSCI protein comprises or consists of the following sequence:1) the nucleotide sequence represented by SEQ ID NO: 2; or2) a complementary sequence, a degenerate sequence, or a homologous sequence of the nucleotide sequence represented by SEQ ID NO: 2;wherein the homologous sequence is a polynucleotide sequence having at least 90% or more, 91% or more, 92% or more, 93% or more, ...

METHOD FOR IDENTIFYING WHETHER A DIPLOID POTATO IS SELF-COMPATIBLE

The present application relates to the technical field of genetic breeding, and provides a method for identifying whether a diploid potato is self-compatible. The method relates to identifying whether a StSCI gene in the diploid potato is transcribed and expressed. Also disclosed is a method for identifying whether a StSCI gene is expressed by using molecular marker, and a method of screening for the molecular marker, which includes: obtaining the genome sequence information of parental materials, screening for difference sites of the parental materials, screening for the molecular marker, and identifying whether the screened molecular marker are usable. As for the identification of the self-compatibility of a diploid potato by using the screened molecular marker, the identification workload is small, a lot of time is saved, and the identification result is not affected by the environment, and it is accurate and reliable. 1. A method for identifying whether a diploid potato is self-compatible , comprising identifying whether the StSCI gene in the diploid potato is transcribed and expressed.2. The method according to claim 1 , wherein the nucleotide sequence of the StSCI gene comprises or consists of the following sequence:1) the nucleotide sequence represented by SEQ ID NO: 1; or2) the complementary sequence, degenerate sequence or homologous sequence of the nucleotide sequence represented by SEQ ID NO: 1;wherein the homologous sequence is a polynucleotide sequence having at least 90% or more, 91% or more, 92% or more, 93% or more, 94% or more, 95% or more, 96% or more, 97% or more, 98% or more, 99% or more, 99.1% or more, 99.2% or more, 99.3% or more, 99.4% or more, 99.5% or more, 99.6% or more, 99.7% or more, 99.8% or more, 99.9% or more identity with the nucleotide sequence represented by SEQ ID NO: 1.3. The method according to claim 1 , wherein the presence of a molecular marker is used to predict whether the StSCI gene is expressed.4. The method according to ...

MULTI-CORE PROCESSOR SUPPORTING CACHE CONSISTENCY, METHOD, APPARATUS AND SYSTEM FOR DATA READING AND WRITING BY USE THEREOF

A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus. 1. A multi-core processor supporting cache consistency , the processor comprising:a plurality of cores; and a plurality of local caches corresponding to the plurality of cores respectively, wherein a local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of cores via an interconnected bus.2. The multi-core processor of claim 1 , wherein a core of the plurality of cores is allocated with memory space memory sections at ranges of addresses corresponding to a local cache of the core.3. The multi-core processor of claim 1 , further comprising a memory controller operably coupled to the plurality of cores for providing data from the memory space to the plurality of cores.412. The multi-core processor of claim 1 , wherein a local cache of a core of the plurality of core comprises a level cache and a level cache.5. A method of data reading by use of a multi-core processor claim 1 , the method comprising the steps of:determining, by a core of a multi-core processor to execute a data read operation, based upon a memory address of data to be read, whether the core is responsible for caching the data;in response to a determination that the core is responsible for caching the data, reading the data from a local cache ...

INTELLIGENT SYSTEMS CAPABLE OF AUTOMATIC LOCALIZATION AND METHODS USING THE SAME

Intelligent systems capable of automatic localization and methods using the same are disclosed. An intelligent system includes an intelligent robot and a plurality of face recognition devices each in a wireless connection with the intelligent robot. Each face recognition device is disposed at the entrance of a room, and is configured to identify face information of people in the room and transmit the face information to the intelligent robot. The intelligent robot thus updates a database according to the face information and automatically identifies a location of a subject to be served based on the database. Thus, the present disclosure can automatically identify the location of the subject to be served. 1. An intelligent system capable of automatic localization , comprising an intelligent robot and a plurality of face recognition devices each in a wireless connection with the intelligent robot , wherein each face recognition device is installed at an entrance of a corresponding room , and is configured to identify face information of people present in the corresponding room and transmit the face information to the intelligent robot , and the intelligent robot is configured to update a database according to the face information and automatically identify a location of a subject to be served based on the database;each face recognition device comprises a first processor, a first memory, a transmitter, and a first bus, wherein the first processor, the transmitter, and the first memory are coupled to the first bus, respectively, wherein the first memory is configured to store a first program, and the first processor is configured to execute the first program, the first program being configured to:collect face information of people entering and leaving the corresponding room; andtransmit via the transmitter the face information to the intelligent robot; andthe intelligent robot comprises a second processor, a second memory, a receiver, and a second bus, wherein the ...

TEST STRIP DETECTION SYSTEM

A test strip detection system, comprising a test strip card () and a detection device (); the test strip card () comprises a card box (), a built-in test strip () and an electronic label () matched with the built-in test strip (); the electronic label () stores parameters such as the standard working curve of an object to be detected and the like; the detection device () comprises an optical system (), a photoelectric detector (), an analog/digital converter (), a data processing device (), an electronic label read-write module () with an aerial (), a voice module (), a cell box () and an output display device (). The system further comprises a wireless communication module () and a wireless network system () connected with the wireless communication module () and comprising a remote server (). The data processing device () calculates a sample detection result according to the characteristic frequency optical signals transmitted by a test strip detection band () and a quality control band () in combination with an electronic label () transmission parameter; the detection result is displayed on the output display device (); the voice module () vocally prompts the detection result at the same time; the detection result is transmitted to the remote server () via the wireless communication module () for data management and information feedback. 112116151620162345610117892344556678921011734510116. A test strip testing system , comprising a test strip card () and a testing device () , wherein the test strip card () comprises a test strip card box () , a test strip () inserted into the test strip card box () , and an electronic tag () that is installed on the test strip card box () and configured to store test strip information; and the testing device () comprises an optical system () , a photoelectric detector () , an analog-to-digital converter () , a data processor () , an electronic tag reading and writing module () with an antenna () , a cell box () , an output ...

SUBSTITUTED 5-(HET-)ARYLPYRAZOLAMIDES AND SALTS THEREOF AND THEIR USE AS HERBICIDAL ACTIVE SUBSTANCES

The invention relates to substituted 5-(Het-)arylpyrazolamides of general formula (I) and to the their use as herbicides, in particular for controlling weeds and/or weed grasses in crops of useful plants and/or as plant growth regulators for influencing the growth of crops of useful plants. The present invention further relates to herbicidal and/or plant growth-regulating agents comprising one or more of the compounds of general formula (I). 2. A compound of formula (I) as claimed in or salt thereof claim 1 , in whichW represents oxygen,Q for phenyl, 2-chloro-4-fluorophenyl, 4-fluorophenyl, 4-chlorophenyl, 2,4-difluorophenyl, 3,4-dichlorophenyl, 2-chlorophenyl, 3,5-difluoropyridin-2-yl, 3,5-dichloropyridin-2-yl, 4-methylphenyl, 2-chloro-5-fluorophenyl, 4-chloro-2-fluorophenyl, 3,5-difluorophenyl, 2,4-dichlorophenyl,X-Z for phenyl, 3-chlorophenyl, cyclopentyl, 2-chloro-5-methylphenyl, 2-fluorophenyl, 4-fluorophenyl, 2,5-difluorophenyl, 5-chloro-2-methylphenyl, 3-methylpyridin-2-yl, 3-fluoropyridin-2-yl, 4-fluoropyridin-2-yl, 2,6-dichlorophenyl, 2,6-difluorophenyl, 2-methylphenyl, 2,5-dichlorophenyl, cyclohexyl, 3,5-dichlorophenyl, 5-chloro-2-fluorophenyl, 3-methylphenyl, 6-fluoropyridin-3-yl, 4-chlorophenyl, 2,4,6-trifluorophenyl, 3-fluorophenyl, 2-chloro-6-methylphenyl, 2-chlorophenyl, 2,3-dimethylphenyl, 2-fluoropyridin-3-yl, 5-fluoropyridin-3-yl, 3-(4-chlorophenyl)-1-ethoxy-1-oxopropan-2-yl, 2,4-dichlorophenyl, 2-fluoro-4-methoxyphenyl, 6-methylpyridin-2-yl, 4-methylpyridin-2-yl, 1-(4-chlorophenyl)-2-ethoxy-2-oxoethyl, 2-(trifluoromethyl)phenyl, 1,1,3-trimethylindan-4-yl, 5-cyano-1,3-thiazol-2-yl, 2-[3-chloro-5-(trifluoromethyl)pyridin-2-yl]ethyl, 4-chloro-2-fluorophenyl, 3,4-dichlorophenyl, 2-chloro-4-fluorophenyl, pyridin-2-yl, [3-(4-chlorophenyl)oxetan-3-yl]methyl, 2,4-difluorophenyl, 3-bromo-2-chlorophenyl, 3-methoxyphenyl, 3-bromo-4-chlorophenyl, 5-methylpyridin-2-yl, 6-cyanopyridin-3-yl, 3-methylpyridin-4-yl, 3,5-dimethylphenyl, 1,1,3-trimethyl-3H-2- ...

SUBSTITUTED 3-HETEROARYLOXY-1H-PYRAZOLES AND SALTS THEREOF AND THEIR USE AS HERBICIDAL ACTIVE SUBSTANCES

A substituted 3-heteroaryloxy-1H-pyrazole of the general formula (I) or salt thereof 4. A herbicidal composition comprising a herbicidally active content of at least one compound of formula (I) or salt as claimed in .5. The herbicidal composition as claimed in in a mixture with one or more formulation auxiliaries.6. The herbicidal composition as claimed in claim 4 , comprising at least one further pesticidally active substance from the group consisting of insecticides claim 4 , acaricides claim 4 , herbicides claim 4 , fungicides claim 4 , safeners claim 4 , and growth regulators.7. The herbicidal composition as claimed in claim 6 , comprising a safener.8. The herbicidal composition as claimed in claim 7 , comprising cyprosulfamide claim 7 , cloquintocet-mexyl claim 7 , mefenpyr-diethyl or isoxadifen-ethyl.9. The herbicidal composition as claimed in claim 4 , comprising a further herbicide.10. A method of controlling one or more unwanted plants claim 1 , comprising applying an effective amount of at least one compound of formula (I) or salt as claimed in or a herbicidal composition thereof to the plants or to a site of unwanted vegetation.11. A product comprising one or more compounds of formula (I) or salts as claimed in or one or more herbicidal compositions thereof for controlling one or more unwanted plants.12. The product as claimed in claim 11 , wherein the one or more compounds of formula (I) or salts are used for controlling one or more unwanted plants in one or more crops of useful plants.13. The product as claimed in claim 12 , wherein the useful plants are transgenic useful plants. The invention relates to the technical field of crop protection agents, in particular that of herbicides for the selective control of broad-leaved weeds and weed grasses in crops of useful plants.Specifically, the present invention relates to substituted 3-heteroaryloxy-1H-pyrazoles and salts thereof, to processes for their preparation and to their use as herbicides.In their ...

Combined Gate and Source Trench Formation and Related Structure

A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region. 1. A semiconductor device comprising:a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type;a gate trench in said semiconductor substrate and extending into said drift region to a first depth in said semiconductor substrate;a source trench in said semiconductor substrate and extending into said drift region, said source trench having a first portion and a second portion under said first portion, said first portion being wider than said gate trench, said second portion being narrower than said first portion, said first portion extending to said same first depth in said semiconductor substrate as said gate trench, said second portion extending to a second depth in said semiconductor substrate greater than said first depth; anda conductive filler in said source trench and insulated from the surrounding semiconductor substrate by a dielectric material, said dielectric material lining sidewalls of said first portion, ...

A MULTI-BRANCHED MANNICH BASE CORROSION INHIBITOR AND PREPARATION METHOD THEREOF

The present invention relates to a multi-branched Mannich base corrosion inhibitor and the method for preparing thereof. The method comprises (1) adding 3˜7 moles ketone and 3˜7 moles aldehyde to reaction kettle, adjusting pH to 2˜6 with acid, controlling temperature to 20˜50° C. and stirring for 20˜30 mins; (2) adding 1 mole organic polyamine to the reaction kettle under stirring, or adding the pH-adjusted ketone, aldehyde and organic solvent to organic polyamine, controlling temperature to 60˜90° C. and reacting for 1˜3 hrs, and after completion of the reaction, heating the system to 110° C. under nitrogen to remove water; the organic polyamine is organic compound comprising three or more primary amine groups and/or secondary amine groups. The Mannich base corrosion inhibitor of the present invention shows characters of strong adsorption force, high film strength, high film compactness, increase in corrosion inhibition efficiency by at least 2%, and overcomes the disadvantages in prior art of few adsorption centers, single adsorption group and weak adsorption force to metal surfaces. 2. The multi-branched Mannich base corrosion inhibitor of claim 1 , characterized in that R claim 1 , Rand Rare selected from ketone groups within the ring of alicyclic ketone groups.4. The multi-branched Mannich base corrosion inhibitor of claim 1 , characterized in that R′ is selected from ketone groups within the ring of alicyclic ketone groups.6. A method for preparing the multi-branched Mannich base corrosion inhibitor of claim 1 , characterized by claim 1 ,(1) adding 3˜7 moles ketone and 3˜7 moles aldehyde to reaction kettle, adjusting pH to 2˜6 with acid, controlling temperature to 20˜50° C. and stirring for 20˜30 mins;(2) adding 1 mole organic polyamine to the reaction kettle under stirring, or adding the pH-adjusted ketone, aldehyde and organic solvent to organic polyamine, controlling temperature to 60˜90° C. and reacting for 1˜3 hrs, and after completion of the reaction, ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure. 1. A semiconductor device package , comprising:a substrate;a partition structure disposed on the substrate and defining a space for accommodating a semiconductor device; anda polymer film adjacent to a side of the partition structure distal to the substrate, wherein a first side surface of the polymer film substantially aligns with a first side surface of the partition structure.2. The semiconductor device package of claim 1 , wherein the polymer film is composed of fluoropolymer.3. The semiconductor device package of claim 1 , wherein the semiconductor device comprises an optical device configured to emit or receive light through the polymer film.4. The semiconductor device package of claim 1 , wherein the first side surface of the polymer film substantially aligns with a first side surface of the substrate.5. The semiconductor device package of claim 1 , further comprising:a bonding layer disposed between the partition structure and the polymer film.6. The semiconductor device package of claim 5 , wherein a first side surface of the bonding layer substantially aligns with the first side surface of the polymer film.7. The semiconductor device package of claim 5 , wherein a portion of the bonding layer extends into the space of the partition structure.8. The semiconductor device package of claim 1 , further comprising a hardcoat layer disposed on the polymer film.9. The semiconductor device package of claim 1 , wherein an end portion of the polymer film is embedded in the partition structure claim 1 , and the partition structure comprises a first through ...

METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING CPU PERFORMANCE

Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread. 1. A method for improving performance of a CPU comprising a plurality of CPU dies , the method comprising: 'enabling threads in the CPU die to compete for a respective mutex of the CPU die;', 'for each CPU dieidentifying the plurality of threads that have obtained the respective mutexes;enabling the plurality of threads that have obtained the respective mutexes to compete for a spin lock of the CPU;identifying, from the plurality of threads, a target thread that has obtained the spin lock;executing a critical section corresponding to the target thread that has obtained the spin lock; andreleasing the mutex and the spin lock that are obtained by the target thread.2. The method according to claim 1 , wherein the releasing the mutex and the spin lock that are obtained by the target thread comprises:first releasing the spin lock obtained by the target thread, and then releasing the mutex obtained by the target thread.3. The method according to claim 2 , further comprising:enabling one or more threads that have not obtained the spin lock to continuously detect whether the spin lock is released.4. The method according to claim 3 , further comprising:in response to detecting that the spin lock is released, re-competing, by ...

SUCROSE MONOESTERS MICROEMULSIONS

An oil in water (o/w) micro-emulsion comprising: 1. An oil in water (o/w) micro-emulsion comprising:a. water;b. from 3% up to 30%, by weight oil, of the total weight of the emulsion;c. from 0.1% up to 10% of a lecithin;d. a sucrose monoester as an emulsifier wherein the ratio, by weight, of the combined amount of the lecithin and sucrose monoester to the oil is less than 1;e. propylene glycol wherein the propylene glycol to water ratio by weight is greater than 1:1; and 'wherein the mean droplet size of the o/w micro-emulsion is about 10 to about 80 nm.', 'f. from 14% up to 40%, by weight, a sugar selected from the group consisting of fructose, glucose, sucrose, and combinations thereof, by total weight of the emulsion;'}2. The emulsion as recited in further comprising from 0.1% up to 20% by weight glycerin of the total weight of the emulsion.3. The emulsion as recited in comprising from 10% up to 20% claim 2 , by weight claim 2 , glycerin of the total weight of the emulsion.4. The emulsion as recited in claim 1 , further comprising from 0.08% up to 1% claim 1 , by weight claim 1 , of the total weight of the emulsion claim 1 , a Calcohol soluble alcohol.5. The emulsion as recited in further comprising 0.1-0.5% of a soluble Calcohol.6. The emulsion as recited in wherein the alcohol is selected from the group consisting of ethanol claim 5 , a propanol and a butanol.7. The emulsion as recited in wherein the butanol is selected from the group consisting of n-butanol claim 6 , sec-butanol claim 6 , isobutanol and tert butanol.8. The emulsion as recited in claim 1 , wherein the droplet size is 10 to 80 nm.9. The emulsion as recited in wherein droplet size is 10 to 50 nm.10. The emulsion as recited in claim 1 , wherein the emulsion is provided in the substantial absence of sucrose.11. A beverage comprising from 0.002% to 0.1% of the emulsion as defined in .12. A process for making an oil/water (o/w) emulsion comprising:a. mixing a sucrose monoester into propylene glycol at ...

PYRIDONE DERIVATIVES AND USES THEREOF IN THE TREATMENT OF TUBERCULOSIS

A compound of Formula (I) is provided that has been shown to be useful for treating a disease, disorder or syndrome that is mediated by the inhibition of mycolic acid biosynthesis through inhibition of Enoyl Acyl Carrier Protein Reductase enzyme (InhA): 2. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris H.3. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris phenyl.4. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris (Ia).5. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris (Ic) claim 1 , and Rand Rare both H.6. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris H.7. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris (C-C)alkyl claim 1 , phenyl claim 1 , tetrahydro-2H-pyran or pyridine.8. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris cycloalkyl.9. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris cyclohexane.10. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris cyclohexane which is substituted with one or more substituents independently selected from (C-C)alkyl claim 1 , cycloalkyl or F.11. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris cyclohexane which is substituted with one or more substituents independently selected from methyl claim 1 , cyclopropane or F.12. The compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , wherein Ris cyclohexane which is substituted with two methyl substitutents.17. A pharmaceutical composition comprising a compound of claim 1 , or a pharmaceutically acceptable salt thereof claim 1 , and a pharmaceutically acceptable carrier or excipient.18. The pharmaceutical composition ...

Method of Manufacturing a Trench FET Having a Merged Gate Dielectric

In one implementation, a method for fabricating a trench FET includes providing a semiconductor substrate including a drain region and a drift zone over the drain region, forming a plurality of depletion trenches over the drain region, each of the plurality of depletion trenches having a depletion trench dielectric and a depletion electrode, and forming a respective bordering gate trench alongside each of the plurality of depletion trenches, each bordering gate trench having a gate electrode and a gate dielectric. 110-. (canceled)11. A method for fabricating a trench FET , said method comprising:providing a semiconductor substrate including a drain region, and a drift zone over said drain region;forming a plurality of depletion trenches over said drain region, each of said plurality of depletion trenches having a depletion trench dielectric and a depletion electrode; andforming a respective bordering gate trench alongside each of said plurality of depletion trenches, each said bordering gate trench having a gate electrode and a gate dielectric.12. The method of claim 11 , wherein said gate dielectric is substantially thinner than said depletion trench dielectric.13. The method of claim 11 , wherein forming said respective bordering gate trench comprises forming only one bordering gate trench situated alongside each of said plurality of depletion trenches.14. The method of claim 11 , wherein said depletion electrode is electrically coupled to a source of said trench FET.15. The method of claim 11 , wherein said plurality of depletion trenches are at least one and a half times deeper than said respective bordering gate trench.16. The method of claim 11 , further comprising forming a channel layer including source regions over said drift zone.17. The method of claim 11 , wherein said drift zone comprises an epitaxial silicon layer.18. The method of claim 11 , wherein at least one of said gate dielectric and said depletion trench dielectric comprises silicon oxide.19. ...

METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING PARALLEL PERFORMANCE OF CPU

Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing. 1. A method for improving parallel performance of a CPU , the method comprising:attempting, by a CPU core, to acquire data requests that are of a same type and that are allocated to the CPU core;determining, by the CPU core, a number of data requests that are acquired; andin response to determining that the number of data requests that are acquired is greater than or equal to a maximum degree of parallelism:executing, by the CPU core, executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.2. The method according to claim 1 , further comprising:in response to determining that the number of data requests that are acquired is less than the maximum degree of parallelism, and a number of attempts made by the CPU core to acquire data requests is less than the maximum degree of parallelism:attempting, by the CPU core, to acquire data requests that ...

DETECTING DATA DEPENDENCIES OF INSTRUCTIONS ASSOCIATED WITH THREADS IN A SIMULTANEOUS MULTITHREADING SCHEME

Detecting data dependencies of instructions associated with threads in a simultaneous multithreading (SMT) scheme is disclosed, including: dividing a plurality of comparators of an SMT-enabled device into groups of comparators corresponding to respective ones of threads associated with the SMT-enabled device; simultaneously distributing a first set of instructions associated with a first thread of the plurality of threads to a corresponding first group of comparators from the plurality of groups of comparators and distributing a second set of instructions associated with a second thread of the plurality of threads to a corresponding second group of comparators from the plurality of groups of comparators; and simultaneously performing data dependency detection on the first set of instructions associated with the first thread using the corresponding first group of comparators and performing data dependency detection on the second set of instructions associated with the second thread using the corresponding second group of comparators. 1. A simultaneous multithreading (SMT)-enabled device , comprising: an instruction comparing unit comprising a plurality of comparators of the SMT-enabled device, the plurality of comparators being divided into a plurality of groups of comparators corresponding to respective ones of a plurality of threads associated with the SMT-enabled device; and', a first set of instructions associated with a first thread of the plurality of threads to a corresponding first group of comparators from the plurality of groups of comparators; and', 'a second set of instructions associated with a second thread of the plurality of threads to a corresponding second group of comparators from the plurality of groups of comparators;, 'simultaneously distribute to, 'an instruction distributing unit to, 'wherein, simultaneously, the corresponding first group of comparators is used to perform data dependency detection on the first set of instructions associated ...

ORNAMENT PIECE AND MANUFACTURE METHOD

An ornament piece includes a base and a pattern layer formed on at least one surface of the base. The pattern layer includes at least one pattern. The at least one pattern is formed on the surface of the base by carbon powder with colors different from that of the base and infiltrating into the surface of the base. A manufacture method of the ornament piece is also provided. 1. An ornament piece comprising:a base; anda pattern layer formed on at least one surface of the base, the pattern layer comprising at least one pattern;wherein the at least one pattern is formed on the surface of the base by carbon powder with colors different from that of the base and infiltrating into the surface of the base.2. The ornament piece as claimed in claim 1 , wherein the pattern comprises at least one color zone claim 1 , the at least one color zone is divided by color claim 1 , portions of the pattern with a same color are regarded as a same color zone claim 1 , a same color zone is formed by infiltrating carbon powder with a same color to the surface of the base; different color zones are formed by infiltrating carbon powder with different colors to surface of the base.3. The ornament piece as claimed in claim 2 , wherein the at least one color zone is formed by laser marking4. The ornament piece as claimed in claim 1 , wherein the base is made of glass or metal material claim 1 , the metal material is aluminum or aluminum alloy.5. A manufacture method of an ornament piece comprising:providing a base and at least one film having a color different from that of the base;attaching the at least one film to at least one to at least one surface of the base;airing the at least one film;laser marking the film to infiltrate a predetermined figure of the film into the surface of the base to form a pattern; andremoving portions of the film that beyond the figure from the base to finish manufacturing the ornament piece.6. The manufacture method as claimed in claim 5 , further comprising ...

INSTRUCTION AND LOGIC FOR FILTERING OF SOFTWARE PREFETCHING INSTRUCTIONS

A processor includes an execution unit and a filter module. The filter module includes logic to receive an instruction, determine whether the instruction was previously executed to prefetch information from a cache, and discard the instruction based on a determination that the instruction was previously executed to prefetch the information from the cache. 1. A processor , comprising:an execution unit;a front end; receive a first instruction through the front end;', 'determine whether the first instruction was previously executed to prefetch a first information from a cache; and', 'discard the first instruction based on a determination that the first instruction was previously executed to prefetch the first information from the cache., 'a filter module including circuitry to2. The processor of claim 1 , wherein the filter module further includes circuitry to:receive a second instruction to prefetch a second information;determine whether the second information is likely absent from the cache; androute the second instruction to the execution unit for execution based upon a determination that the second information is likely absent from the cache.3. The processor of claim 1 , wherein the filter module further includes circuitry to:determine whether the first instruction was previously executed to prefetch the first information from the cache, the determination made by accessing a cache-hit indicator for the first instruction;set the cache-hit indicator based upon a successful execution of the first instruction.4. The processor of claim 1 , wherein the filter module further includes circuitry to:determine whether the first instruction was previously executed to prefetch the first information from the cache, the determination made by accessing a cache-hit indicator for the first instruction;set the cache-hit indicator based upon a successful execution of the first instruction; anddiscard the first instruction further based on a determination that the first instruction was ...

METHODS AND COMPOSITIONS FOR TREATING C-MET ASSOCIATED CANCERS

The present invention provides the use of a fungal immunomodulatory protein (FIP) in manufacturing a medicament for inhibiting hepatocyte growth factor receptor (HGFR) activity in a cell, and for treating HGFR-associated cancer. 1. A method for inhibiting hepatocyte growth factor receptor (HGFR) activity in a cell , comprising contacting an effective amount of a fungal immunomodulatory protein (FIP) with the cell.2. The method according to claim 1 , wherein the cell is derived from an HGFR-associated cancer selected from the group consisting of hepatocellular carcinoma claim 1 , hereditary and sporadic human papillary renal carcinomas claim 1 , ovarian cancer claim 1 , prostate carcinoma claim 1 , gallbladder carcinoma claim 1 , breast carcinoma claim 1 , melanoma claim 1 , glioblastoma claim 1 , head-and-neck squamous carcinoma claim 1 , esophageal cancer claim 1 , gastric cancer claim 1 , pancreatic cancer claim 1 , mesothelioma claim 1 , colorectal cancer claim 1 , osteogenic sarcoma claim 1 , lymphoma and multiple myeloma.3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. A method for inhibiting metastasis of hepatocellular carcinoma in a subject claim 1 , comprising administering to said subject an effective amount of a fungal immunomodulatory protein (FIP).8. A method for preventing recurrence of hepatocellular carcinoma in a subject claim 1 , comprising administering to said subject an effective amount of a fungal immunomodulatory protein (FIP).9. The method according to or claim 1 , wherein the hepatocellular carcinoma is an HGFR-positive hepatocellular carcinoma.10. The method according to or claim 1 , wherein the hepatocellular carcinoma is an HGFR-negative hepatocellular carcinoma.11. The method according to anyone of claim 1 , and claim 1 , wherein the FIP has an amino acid homology of at least 57% to the amino acid sequence of SEQ ID NO: 1.12. The method according to claim 11 , wherein the FIP has an amino acid sequence selected from the group ...

METHOD, APPARATUS, AND ELECTRONIC DEVICE FOR IMPROVING PARALLEL PERFORMANCE OF CPU

Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing. 130-. (canceled)31. A method for improving parallel performance of a CPU , the method comprising:determining that an attempt by a CPU core to acquire a predetermined number of data requests is successful, wherein the predetermined number is dependent on a maximum degree of parallelism of the CPU, and wherein the maximum degree of parallelism of the CPU is a maximum number of parallel threads executable by the CPU; andin response to determining that the attempt is successful, executing, by the CPU core, executable codes corresponding to the maximum degree of parallelism of the CPU, wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism prior to executing the executable codes.32. The method according to claim 31 , wherein the predetermined number of data requests is greater than or equal to the maximum degree of parallelism.33. The method according to claim 31 , further comprising claim 31 , prior to determining that the attempt is successful claim 31 ,repeatedly attempting, by the CPU core, to acquire data requests that are of a same type and that are allocated to the ...

New ester compounds, process for their preparation and their use

Die Erfindung betrifft neue Esterverbindungen der allgemeinen Formel (I)ein Verfahren zu ihrer Herstellung sowie ihre Verwendung. Diese Esterverbindungen können ein Gemisch aus mindestens zwei Verbindungen, der allgemeinen Formel (I) enthalten. The invention relates to new ester compounds of general formula (I) a process for their preparation and their use. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Multi-touch touchscreen incorporating pen tracking

The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Multi-touch touchscreen incorporating pen tracking

The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Multi-touch touchscreen incorporating pen tracking

The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Multi-touch touchscreen incorporating pen tracking

Multi-touch touchscreen incorporating pen tracking

e The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to "write" on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Multi-touch touchscreen incorporating pen tracking

The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Pyridone derivatives and uses thereof in the treatment of tuberculosis

A compound of Formula (I) is provided that has been shown to be useful for treating a disease, disorder or syndrome that is mediated by the inhibition of mycolic acid biosynthesis through inhibition of M. tuberculosis EnoyI Acyl Carrier Protein Reductase enzyme (InhA): wherein R1, R2, R3, R4 and R5 are as defined herein.

Method and device for measurement compensation for different-system reselection and handover by dual-mode terminals

Method and device for measurement compensation for inter-system reselection and handover in a dual-mode terminal are disclosed. The method comprises: a GSM physical layer reporting measured RSCP and Ec/No values of a 3G neighbor cell to a radio resource management layer with inter-layer primitives; the radio resource management layer receiving the inter-layer primitives carrying the RSCP and Ec/No values reported by the physical layer, and performing measurement compensation for the inter-layer primitives in the radio resource management layer. Since the measurement compensation is performed in the radio resource management layer of the terminal, the terminal preferably resides on 3G network when detecting the 3G network. It can be applied to measurement compensation for the inter-system reselection and handover when 2G and 3G mobile communication systems co-exist. The terminal is more easily retained on the network of one of the systems and allowed to make a priority selection of the networks.

Nail polish bottle holder

A holder for a nail polish bottle that allows the bottle to be tipped at any angle wanted by the user and that allows viewing of an applicator extracting polish from the bottle. It has a fixed post attached to a base that stabilizes the holder against unwanted motion during use. There is a pivoting post also. The top of the fixed post and the bottom of the pivoting post form a ball and socket joint that allows the pivoting post to tilt at any angle wanted by a user. The pivoting post is attached to a spring-loaded clip. The clip contains arms with non-slip inner surfaces. The arms have an arcuate hollow elliptical oval shape that allows the user to view the transferring of polish to the applicator so that a proper amount is transferred. The clip is opened by pressing its lever portions together to stress the spring. When the pressure on the lever portions ceases, the arcuate arms close to hold the bottle securely.

Pyridone derivatives and uses thereof in the treatment of tuberculosis

A compound of Formula (I) is provided that has been shown to be useful for treating a disease, disorder or syndrome that is mediated by the inhibition of mycolic acid biosynthesis through inhibition of M. tuberculosis EnoyI Acyl Carrier Protein Reductase enzyme (InhA): wherein R1, R2, R3, R4 and R5 are as defined herein.

Chair cushion structure

Method and processor for processing data

A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Method, apparatus, and electronic device for improving CPU performance

Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

Blockchain-based financial trading executing method and apparatus, and electronic device

Split electrode gate trench power device

A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

Sucrose monoesters microemulsions

Substituted 3-heteroaryloxy-1h-pyrazoles and salts thereof and their use as herbicidal active substances

The invention relates to substituted 3-heteroaryloxy-1H-pyrazoles of general formula (I). Disclosed are substituted 3-heteroaryloxy-1H-pyrazoles of general formula (I), their use as herbicides, in particular for controlling weeds and/or weed grasses in crops of useful plants and/or as plant growth regulators for influencing the growth of crops of useful plants. The present invention further relates to herbicidal and/or plant growth-regulating agents comprising one or more compounds of general formula (I).

Novel ester compounds, method for the production thereof and use thereof

The invention relates to novel ester compounds of general formula (I), to methods for the production thereof, and to their use. These ester compounds can contain a mixture of at least two compounds of general formula (I).

Method and processor for processing data

3-heteroaryloxy-1h-substituted pyrazoles and salts thereof and their use as herbicidal active substances

Um 3-heteroariloxi-1H-pirazol substituído da fórmula geral (I) ou sal do mesmo São descritos 3-heteroariloxi-1H-pirazóis substituídos da fórmula geral (I), bem como seus usos como herbicidas, em particular para controle de ervas daninhas de folhas amplas e/ou gramíneas daninhas em culturas de plantas úteis e/ou como reguladores de crescimento vegetal para influenciar o crescimento de culturas de plantas úteis descritas. A presente invenção também se refere a composições herbicidas e/ou de regulação de crescimento vegetal que compreendem um ou mais compostos da fórmula geral (I). A substituted 3-heteroaryloxy-1H-pyrazole of the general formula (I) or salt thereof Substituted 3-heteroaryloxy-1H-pyrazoles of the general formula (I) are described, as well as their uses as herbicides, in particular for controlling broadleaf weeds and / or weeds in useful plant cultures and / or as regulators of plant growth to influence the growth of useful plant crops described. The present invention also relates to herbicidal and / or plant growth regulation compositions that comprise one or more compounds of the general formula (I).

Lamp

A lamp provided includes a lamp base, a light-transmitting housing, a light-emitting component, a lens and a bracket. The bracket fixes the light-emitting component, the light-emitting component is arranged towards a light incident surface of the lens; and the light incident surface of the lens is arranged in parallel to or at an angle with the light-emitting component. The housing includes a convex part opposite to the lamp base, and the lens is arranged on the inner surface of the convex part. A bulb lamp with condensing effect is provided.

Blockchain-based financial trading executing method and apparatus, and electronic device

A method for blockchain-based financial trading, applied to a distributed exchange set up based on a blockchain is disclosed. The distributed exchange includes a plurality of trading centers deployed in a distributed manner. The method includes: receiving a trade order submitted by a user terminal in communication with a local one of the plurality of trading centers; transmitting the received trade order to other ones of the plurality of trading centers in the blockchain and receiving trade orders transmitted from the other ones of the plurality of trading centers submitted by user terminals in communication therewith; generating an order book by performing an order matching process on the received trade orders, transmitting the generated order book to each of the other ones of the plurality of trading centers in the blockchain, and receiving order books transmitted from the other ones of the plurality of trading centers that are generated through performing order matching processes on the corresponding received trade orders; and initiating a consensus process on the order books generated by the plurality of trading centers and executing the matched order in each of the order books for which consensus has been reached.

Ester compounds, method for the production thereof and use thereof

The invention relates to novel ester compounds of general formula (I), to methods for the production thereof, and to their use. These ester compounds can contain a mixture of at least two compounds of general formula (I).

Novel ester compounds, method for the production thereof and use thereof

The invention relates to novel ester compounds of general formula (I), to methods for the production thereof, and to their use. These ester compounds can contain a mixture of at least two compounds of general formula (I).