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Применить Всего найдено 62. Отображено 59.
27-02-2018 дата публикации

Memory cell comprising first and second transistors and methods of operating

Номер: US0009905564B2
Автор: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie, WIDJAJA YUNIARTO, HAN JIN WOO, LOUIE BENJAMIN S, Widjaja Yuniarto, Han Jin-Woo, Louie Benjamin S.
Принадлежит: Zeno Semiconductors, Inc., ZENO SEMICONDUCTOR INC, ZENO SEMICONDUCTORS INC, Zeno Semiconductor, Inc.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

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Номер записи: 1
16-03-2017 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20170076784A1
Автор: Benjamin S. Louie, Yuniarto Widjaja, LOUIE BENJAMIN S, WIDJAJA YUNIARTO, Louie Benjamin S., Widjaja Yuniarto
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 2
13-02-2018 дата публикации

Memory device having electrically floating body transistor

Номер: US0009893067B2
Автор: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie, WIDJAJA YUNIARTO, HAN JIN WOO, LOUIE BENJAMIN S, Widjaja Yuniarto, Han Jin-Woo, Louie Benjamin S.
Принадлежит: Zeno Semiconductor, Inc., ZENO SEMICONDUCTOR INC

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

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Номер записи: 3
11-07-2017 дата публикации

NAND string utilizing floating body memory cell

Номер: US0009704578B2
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja, LOUIE BENJAMIN S, HAN JIN-WOO, WIDJAJA YUNIARTO, Louie Benjamin S., Han Jin-Woo, Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc., ZENO SEMICONDUCTOR INC

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

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Номер записи: 4
09-01-2018 дата публикации

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

Номер: US0009865332B2
Автор: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach, LOUIE BENJAMIN S, WIDJAJA YUNIARTO, OR-BACH ZVI, Louie Benjamin S., Widjaja Yuniarto, Or-Bach Zvi
Принадлежит: Zeno Semiconductor, Inc., ZENO SEMICONDUCTOR INC

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

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Номер записи: 5
04-05-2017 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20170125421A1
Автор: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie, WIDJAJA YUNIARTO, HAN JIN-WOO, LOUIE BENJAMIN S, Widjaja Yuniarto, Han Jin-Woo, Louie Benjamin S.
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. A semiconductor memory array comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;', 'a first region in electrical contact with said floating body region; and', 'a back-bias region configured to maintain a charge in said floating body region;', 'wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;', 'wherein said back bias region is commonly connected to at least two of said memory cells, and', 'wherein said back bias region has a lower band gap than said floating body region., 'a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes31. The semiconductor memory array of claim 30 , wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states claim 30 , and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first ...

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Номер записи: 6
30-03-2017 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20170092359A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja, LOUIE BENJAMIN S, HAN JIN-WOO, WIDJAJA YUNIARTO, Louie Benjamin S., Han Jin-Woo, Widjaja Yuniarto
Принадлежит: Law Office Of Alan W Cannon, Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 7
15-09-2016 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20160267982A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja, LOUIE BENJAMIN S, HAN JIN-WOO, WIDJAJA YUNIARTO, Louie Benjamin S., Han Jin-Woo, Widjaja Yuniarto
Принадлежит:

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 1. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line;wherein serial connections between at least two of said semiconductor memory cells are contactless.2. The NAND string configuration of claim 1 , wherein all serial connections between said semiconductor memory cells are contactless claim 1 , so that only a contact to said select gate drain device and a contact to said select gate source device are provided.3. The NAND string configuration of claim 1 , said NAND string being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one semiconductor memory cell.4. The NAND string configuration of claim 1 , wherein said at least one of said semiconductor memory devices each comprise a floating body region configured to store data as charge therein to define a state of said semiconductor memory cell; and a back bias region configured to perform said at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.5. The NAND string configuration of claim 4 , wherein said floating body region is provided in a fin structure that extends vertically above said back bias region.6. A semiconductor memory array comprising:a plurality of NAND string configurations, each said NAND string configuration comprising:a plurality of semiconductor memory ...

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Номер записи: 8
10-08-2017 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20170229466A1
Автор: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie, WIDJAJA YUNIARTO, HAN JIN-WOO, LOUIE BENJAMIN S, Widjaja Yuniarto, Han Jin-Woo, Louie Benjamin S.
Принадлежит:

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series. 18-. (canceled)9. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns , wherein each of said semiconductor memory cells comprises:a first transistor having a first body;a second transistor having a second body;a substrate underlying both of said first and second bodies;a buried layer interposed between said substrate and at least one of said first and second bodies;a first source region contacting said first body;a first drain region separated from said first source region and contacting said first body;a first gate insulated from said first body;an insulating member insulating said first body from said second body;a second source region contacting said second body;a second drain region separated from said second source region and contacting said second body; anda second gate insulated from said second body;wherein said first drain region is electrically connected to said second source region.10. The semiconductor memory array of claim 9 , wherein said first gate is positioned between said first source region and said first drain region and said second gate is positioned between said second source region and said second drain region.11. The semiconductor memory array of claim 9 , wherein said first transistor is a floating body transistor and said second transistor is an access transistor.12. The semiconductor memory array of claim 9 , wherein said first body is a floating body and said second body is a well region electrically connected to said substrate.1323-. (canceled)24. A method of operating a semiconductor memory cell having a bi-stable floating body transistor and an access transistor claim 9 , said method ...

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Номер записи: 9
12-10-2017 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20170294438A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja, LOUIE BENJAMIN S, HAN JIN-WOO, WIDJAJA YUNIARTO, Louie Benjamin S., Han Jin-Woo, Widjaja Yuniarto
Принадлежит:

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 123-. (canceled)24. An integrated circuit comprising: a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;', 'a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and', 'a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;', 'wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;', 'wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;', 'wherein each said at least one of said plurality of semiconductor memory cells has only one gate;', 'wherein serial connections between at least two of said semiconductor memory cells are contactless;', 'wherein said semiconductor memory array comprises at least one of: at least two of said select gate drain devices connected to a common bit line; or at least two of said select gate source devices connected to a common source line; and, 'a semiconductor memory array comprisinga control ...

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Номер записи: 10
03-01-2017 дата публикации

Systems and methods for reducing standby power in floating body memory devices

Номер: US0009536595B2
Автор: Benjamin S. Louie, Yuniarto Widjaja, LOUIE BENJAMIN S, WIDJAJA YUNIARTO, Louie Benjamin S., Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc., ZENO SEMICONDUCTOR INC

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 11
21-02-2017 дата публикации

Memory device having electrically floating body transistor

Номер: US0009576962B2
Автор: Yuniarto Widjaja, Jin-Woo Han, Benjamin S. Louie, WIDJAJA YUNIARTO, HAN JIN-WOO, LOUIE BENJAMIN S, Widjaja Yuniarto, Han Jin-Woo, Louie Benjamin S.
Принадлежит: Zeno Semiconductor, Inc., ZENO SEMICONDUCTOR INC

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

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Номер записи: 12
05-09-2013 дата публикации

System and method for reducing pin-count of memory devices, and memory device testers for same

Номер: US20130229878A1
Автор: Adam D. Johnson, Benjamin S. Louie, Scott N. Gatzemeier, Wallace E. Fister
Принадлежит: Micron Technology Inc

Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

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Номер записи: 13
10-10-2013 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20130264656A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

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Номер записи: 14
15-01-2015 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20150016207A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells storing charge representative of data , said method comprising:counting bits of data before data enters the array, wherein said counting comprises counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0;detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0;setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; andinverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.2. The method of claim 1 , wherein said floating body memory cells comprise bi-stable SRAM floating body memory cells.3. The method of claim 1 , further comprising outputting contents of the bits of data from the memory array claim 1 , wherein said method further comprising inverting the bits of data ...

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Номер записи: 15
22-01-2015 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20150023105A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor, Inc.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

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Номер записи: 16
24-01-2019 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20190027476A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 123-. (canceled)24. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;wherein each said at least one of said plurality of semiconductor memory cells has only one gate; andwherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.25. The NAND string configuration of claim 24 , wherein all serial connections between said semiconductor memory cells are not connected to any terminals claim 24 , so that only said select gate drain device and said select gate source device are connected ...

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Номер записи: 17
25-02-2021 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20210057027A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 18
05-03-2020 дата публикации

SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS

Номер: US20200075091A1
Автор: Louie Benjamin S., OR-BACH Zvi, Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc.

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided. 1. A semiconductor memory array comprising a plurality of floating body memory cells , each of said floating body memory cells comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;a first region in electrical contact with said floating body region, said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;a first transistor connected to said second region of said floating body memory cell; anda second transistor connected to said first transistor.2. The semiconductor memory array of claim 1 , each said floating body memory cell further comprising:a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type.3. The semiconductor memory array of claim 1 , wherein said second region has multiple contacts electrically connected thereto.4. The semiconductor memory array of claim 1 , wherein each said floating body memory cell further comprises:a gate positioned between said first and second regions.5. The semiconductor memory array of claim 2 , wherein each of said floating body memory cells further comprises:a first gate positioned between said first and second regions; anda second gate positioned between said first and third regions.6. The semiconductor memory array of claim 1 ...

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Номер записи: 19
14-03-2019 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20190080746A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 114-. (canceled)15. A semiconductor memory array configured for reducing standby power , said array comprising:a plurality of floating body memory cells configured to store charge representative of data; andat least two floating body cells serially connected to form a reference cell;wherein current conducted through said at least one of said plurality of floating body memory cells is reduced to a fraction of said current when passing through said reference cell.16. The array of claim 15 , wherein said at least two floating body cells of said reference cell are set to state 1.17. The array of claim 15 , wherein said reference cell is used for at least one of: a current reference claim 15 , a voltage reference or a monitor of transient response to bit line discharge.18. A semiconductor memory array configured for reducing standby power claim 15 , said array comprising:a plurality of floating body memory cells configured to store charge representative of data; andat least two more of said floating body memory cells interconnected by a segmented source line to form a reference cell.19. The array of claim 18 , comprising:a plurality of said reference cells ...

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Номер записи: 20
24-03-2016 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20160086954A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. A semiconductor memory cell comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;a first region in electrical contact with said floating body region; anda back-bias region configured to maintain a charge in said floating body region;wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity, andwherein said back bias region has a lower band gap than said floating body region.31. The semiconductor memory cell of claim 30 , wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states claim 30 , and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.32. The semiconductor memory cell of claim 30 , further comprising a second region in electrical contact with said floating body region and spaced apart from said first region.33. The semiconductor memory cell of claim 30 , further ...

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Номер записи: 21
05-04-2018 дата публикации

SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS

Номер: US20180096721A1
Автор: Louie Benjamin S., OR-BACH Zvi, Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc.

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided. 118-. (canceled)19. A method of selecting a floating body SRAM cell by a memory compiler for use in array design , said method comprising:a user inputting preferred design criteria to at least one processor of the memory compiler;the memory compiler evaluating the preferred design criteria by executing at least one algorithm configured to select a preferred floating body SRAM cell based on the design criteria inputs received;determining whether a preferred floating body SRAM cell can be identified based upon the preferred design criteria inputted and the at least one algorithm executed; andselecting the preferred floating body SRAM cell when identifiable, providing the user with an array design requested by the user, wherein the array design employs the preferred floating body SRAM cells; andwhen a preferred floating body SRAM cell cannot be clearly identified, providing the user with a report identifying floating body SRAM cell types that were eliminated base on the preferred design criteria, providing remaining SRAM cell type choices that were not eliminated and indicating which are preferable for selection; and requesting the user to adjust the preferred design criteria or provide an override so as to manually select a preferred floating body SRAM cell type.20. The method of claim 19 , wherein floating body SRAM cell types from which the preferred floating body SRAM cell type is selected include: one-transistor floating body SRAM cell claim 19 , two-transistor floating body SRAM cell claim 19 , three-transistor floating body SRAM cell claim 19 , four-transistor floating body SRAM cell claim 19 , dual-port floating body SRAM cell and pseudo dual port floating body SRAM cell.21. The method of claim 19 , wherein the array design is an array ...

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Номер записи: 22
17-07-2014 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20140198551A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. 1. A content addressable memory cell comprising:a first floating body transistor; anda second floating body transistor;wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; andwherein said first floating body transistor and said second floating body transistor store complementary data.2. The content addressable memory of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.3. The content addressable memory of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.4. The content addressable memory of claim 1 , wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.5. The content addressable memory of claim 1 , further comprising a third transistor.6. The content addressable memory of claim 5 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.7. The content addressable memory of claim 5 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.8. The content addressable memory of claim 1 , further comprising a third floating body transistor.9. A content addressable memory comprising:a first bi-stable floating body transistor; anda second bi-stable floating body transistor; ...

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Номер записи: 23
09-04-2020 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20200111792A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 123-. (canceled)24. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;wherein said third region is commonly connected to at least two of said semiconductor memory cells;wherein each of said at least one of said plurality of semiconductor memory cells has only one gate; andwherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.25. The NAND string configuration of claim 24 , wherein all serial connections between said semiconductor memory cells are not connected to any terminals ...

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Номер записи: 24
01-09-2022 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20220278104A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series. 137-. (canceled)38. A semiconductor memory cell comprising:a bipolar device having a floating body region, wherein an amount of charge stored in said floating body region represents a state of said memory cell;wherein said state of said memory cell is maintained by a holding operation;wherein accessing said memory cell does not interrupt said holding operation; andan access device;wherein said bipolar device and said access device are electrically connected in series.39. The semiconductor memory cell of claim 38 , wherein said access device comprises a metal-oxide-semiconductor transistor.40. The semiconductor memory cell of claim 38 , wherein said access device comprises a bipolar transistor.41. The semiconductor memory cell of claim 38 , wherein said bipolar device comprises a buried well region.42. The semiconductor memory cell of claim 38 , wherein said bipolar device comprises at least two stable states.43. The semiconductor memory cell of claim 38 , wherein an amount of current flow through said memory cell is determined by the amount of charge stored in said floating body region.44. The semiconductor memory cell of claim 38 , wherein said semiconductor memory cell is formed in fin structure.45. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns claim 38 , wherein each of said semiconductor memory cells comprises:a bipolar device having a floating body region, wherein an amount of charge stored in said floating body region represents a state of said memory cell;wherein said state of said memory cell is maintained by a holding operation;wherein accessing said memory cell does not interrupt said holding operation; ...

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Номер записи: 25
02-05-2019 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20190131305A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

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Номер записи: 26
26-05-2016 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20160148674A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells storing charge representative of data , said method comprising:counting bits of data before data enters the array, wherein said counting comprises counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0;detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0;setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; andinverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.2. The method of claim 1 , wherein said floating body memory cells comprise bi-stable SRAM floating body memory cells.3. The method of claim 1 , further comprisingoutputting contents of the bits of data from the memory array, wherein said method further comprising inverting the bits of data from the ...

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Номер записи: 27
26-05-2016 дата публикации

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

Номер: US20160148675A1
Автор: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
Принадлежит: Zeno Semiconductor Inc

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

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Номер записи: 28
16-05-2019 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20190148381A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. A semiconductor memory cell comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; anda back bias region;wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; andwherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states.31. The semiconductor memory cell of claim 30 , further comprising a gate region positioned above said floating body region.32. The semiconductor memory cell of claim 30 , wherein said back-bias region is configured to maintain a charge in said floating body region.33. The semiconductor memory cell of claim 30 , wherein said first and second states are ...

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Номер записи: 29
07-06-2018 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20180158825A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. An integrated circuit comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;', 'a first region in electrical contact with said floating body region; and', 'a back-bias region configured to maintain a charge in said floating body region;', 'wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;', 'wherein said back bias region is commonly connected to at least two of said memory cells,', 'wherein said back bias region has a lower band gap than a band gap of said floating body region; and, 'a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes, 'a semiconductor memory array comprisinga control circuit configured to provide electrical signals to said back bias region.31. The integrated circuit of claim 30 , wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states claim 30 , and wherein ...

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Номер записи: 30
15-07-2021 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20210217754A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

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Номер записи: 31
22-07-2021 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20210225844A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. A semiconductor memory cell comprising:a first bipolar device having a first floating base region, a first collector, and a first emitter, anda second bipolar device having a second floating base region, a second collector, and a second emitter,wherein said first floating base region is common to said second floating base region,wherein said first collector is common to said second collector,wherein a state of said memory cell is maintained through a back bias applied to said first and second collectors;wherein said first and second collectors are commonly connected to at least two of said memory cells; andwherein said first and second collector regions have a band gap that is lower than a band gap of said first and second floating base regions.31. The semiconductor memory cell of claim 30 , further comprising a gate region positioned above said first and second floating base regions.32. The semiconductor memory cell of claim 30 , wherein said first and second collectors are configured to maintain a charge in said floating base regions.33. The semiconductor memory cell of claim 30 , wherein said state of said memory cell is a state selected from at least first and second states claim 30 , and wherein said first and ...

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Номер записи: 32
19-07-2018 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20180204611A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells storing charge representative of data , said method comprising:counting bits of data before data enters the array, wherein said counting comprises counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0;detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0;setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; andinverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.2. The method of claim 1 , wherein said floating body memory cells comprise bi-stable SRAM floating body memory cells.3. The method of claim 1 , further comprisingoutputting contents of the bits of data from the memory array, wherein said method further comprising inverting the bits of data from the ...

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Номер записи: 33
16-10-2014 дата публикации

SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS

Номер: US20140307501A1
Автор: Louie Benjamin S., OR-BACH Zvi, Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc.

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided. 1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays , said cell comprising:a floating body memory cell comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;a first region in electrical contact with said floating body region; said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;a second transistor connected to said second region of said floating body memory cell; anda third transistor connected to said second transistor.2. The floating body SRAM cell of claim 1 , said floating body memory cell further comprising:a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type.3. The floating body SRAM cell of claim 1 , wherein said second region has multiple contacts electrically connected thereto.4. The floating body SRAM cell of claim 1 , wherein said floating body memory cell further comprises:a gate positioned between said first and second regions.5. The floating body SRAM cell of claim 2 , further comprising:a first gate positioned between said first and second regions; anda second gate positioned between said first and third regions.6. The floating body SRAM cell of claim 1 , wherein said second transistor ...

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Номер записи: 34
06-11-2014 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20140328128A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит: Zeno Semiconductor, Inc.

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 1. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line;wherein serial connections between at least two of said semiconductor memory cells are contactless.2. The NAND string configuration of claim 1 , wherein all serial connections between said semiconductor memory cells are contactless claim 1 , so that only a contact to said select gate drain device and a contact to said select gate source device are provided.3. The NAND string configuration of claim 1 , said NAND string being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one semiconductor memory cell.4. The NAND string configuration of claim 1 , wherein said at least one of said semiconductor memory devices each comprise a floating body region configured to store data as charge therein to define a state of said semiconductor memory cell; and a back bias region configured to perform said at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.5. The NAND string configuration of claim 4 , wherein said floating body region is provided in a fin structure that extends vertically above said back bias region.6. A semiconductor memory array comprising:a plurality of NAND string configurations, each said NAND string configuration comprising:a plurality of semiconductor memory ...

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Номер записи: 35
16-07-2020 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20200227415A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states. 129-. (canceled)30. A semiconductor memory cell comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; anda back bias region;wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;wherein said back-bias region acts as a collector region of said first bipolar transistor and has a band gap that is lower than a band gap of said floating body region;wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell;wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; andwherein states of said memory cell are maintained upon repeated read operations.31. The semiconductor memory cell of claim 30 , further comprising a gate region positioned above said floating body region.32. The semiconductor memory cell of claim 30 , wherein said back-bias region is configured to maintain a charge in said floating ...

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Номер записи: 36
18-11-2021 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20210358547A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 37
26-09-2019 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20190295629A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 120-. (canceled)21. A system for reducing standby power , said system comprising:a memory array comprising a plurality of floating body memory cells each comprising a floating body configured to store charge representative of data, wherein said charge is maintained by a vertical bipolar holding mechanism;a reference cell configured to measure a potential level of said floating body;a high level floating body potential detector and a low level floating body potential detector; anda controller configured to turn on or turn off said vertical bipolar holding mechanism based on comparison between said potential level measured by said reference cell and said high level floating body potential detector and said low level floating body potential detector.22. The system of claim 21 , further comprising:a voltage regulator;wherein when the low level floating body potential detector inputs a signal to the controller indicating that a predetermined low potential has been measured, said controller controls said voltage regulator to lower a voltage level input to a source line connected to said floating body memory cell or a bit line connected to said floating body ...

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Номер записи: 38
18-10-2018 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20180301192A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. 124-. (canceled)25. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns , wherein each said content addressable memory cell comprises:a first floating body transistor;a second floating body transistor; anda third transistor;wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node;wherein said third transistor is electrically connected to said common node; andwherein said first floating body transistor and said second floating body transistor store complementary data.26. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.27. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.28. The content addressable memory array of claim 25 , wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.29. The content addressable memory array of claim 25 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.30. The content addressable memory array of claim 25 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.31. The content ...

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Номер записи: 39
10-10-2019 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20190311769A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. 25. A content addressable memory cell comprising:a first floating body transistor;a second floating body transistor;a third transistor; anda fourth transistor;wherein said first floating body transistor is connected to a gate of said third transistor; andwherein said second floating body transistor is connected to a gate of said fourth transistor.26. The content addressable memory cell of claim 25 , wherein said first floating body transistor and said second floating body transistor store complementary data.27. The content addressable memory cell of claim 25 , wherein said first floating body transistor and said second floating body transistor store the same data.28. The content addressable memory cell of claim 25 , wherein said third and fourth transistors are connected in parallel.29. The content addressable memory cell of claim 25 , wherein said third and fourth transistors are connected in series.30. The content addressable memory cell of claim 25 , wherein said content addressable memory cell may function as binary content addressable memory cell or ternary content addressable memory cell.31. The content addressable memory cell of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.32. The content addressable memory cell of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.33. The content addressable memory cell of claim 25 , further comprising a third floating body transistor.34. A content addressable memory cell comprising:a first bipolar device having a first ...

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Номер записи: 40
22-10-2020 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20200335156A1
Автор: Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state and a total number of all bits; a total number of bits at state and the total number of all bits; or the total number of bits at state and the total number of bits at state . This method further includes detecting whether the total number of bits at state is greater than the total number of bits at state ; setting an inversion bit when the total number of bits at state is greater than the total number of bits at state ; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. 120-. (canceled)21. A semiconductor memory array configured for reducing standby power , said array comprising:a plurality of floating body memory cells each having at least two stable floating body charge levels, wherein the standby power of one of said at least two stable floating body charge levels is lower than another of said at least two stable floating body charge levels; andmeans for reducing standby power of said floating body memory cells, wherein said means for reducing standby power comprises means for setting the states of said memory cells to said state with lower standby power.22. The semiconductor memory array of claim 21 , wherein each of said plurality of floating body memory cells further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type.23. The semiconductor memory array of claim 22 , wherein each of said plurality of floating body memory cells further comprises a back-bias region having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type claim 22 , wherein said second conductivity type is different from ...

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Номер записи: 41
31-12-2020 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20200411521A1
Автор: Han Jin-Woo, Louie Benjamin S., Widjaja Yuniarto
Принадлежит:

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series. 18-. (canceled)10. The integrated circuit of claim 9 , wherein said first gate is positioned between said first source region and said first drain region and said second gate is positioned between said second source region and said second drain region.11. The integrated circuit of claim 9 , wherein said first transistor is a floating body transistor and said second transistor is an access transistor.12. The integrated circuit of claim 9 , wherein said first body is a floating body and said second body is a well region electrically connected to said substrate.1337-. (canceled)38. The integrated circuit of claim 11 , wherein said buried layer generates impact ionization when said floating body transistor is in one of first and second states claim 11 , and wherein said buried layer is configured so as not to generate impact ionization when said floating body transistor is in the other of said first and second states.39. The integrated circuit of claim 11 , wherein said semiconductor memory cells are at least partially formed in fin structures.40. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns claim 11 , wherein each of said semiconductor memory cells comprises:a first transistor having a floating body;a buried layer below said floating body, wherein application of voltage on said buried layer maintains a state of said memory cell; anda second transistor;wherein said first transistor having a floating body comprises a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization ...

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Номер записи: 42
24-05-2022 дата публикации

Systems and methods for reducing standby power in floating body memory devices

Номер: US11342018B2
Автор: Benjamin S. Louie, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 43
16-07-2019 дата публикации

Systems and methods for reducing standby power in floating body memory devices

Номер: US10354718B2
Автор: Benjamin S. Louie, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 44
01-02-2024 дата публикации

NAND String Utilizing Floating Body Memory Cell

Номер: US20240040767A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

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Номер записи: 45
14-04-2022 дата публикации

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

Номер: US20220115061A1
Автор: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
Принадлежит: Zeno Semiconductor Inc

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

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Номер записи: 46
28-12-2023 дата публикации

Content Addressable Memory Device Having Electrically Floating Body Transistor

Номер: US20230420048A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 47
07-12-2023 дата публикации

Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Номер: US20230395138A1
Автор: Benjamin S. Louie, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 48
23-01-2024 дата публикации

Content addressable memory device having electrically floating body transistor

Номер: US11881264B2
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 49
30-04-2024 дата публикации

Memory cell comprising first and second transistors and methods of operating

Номер: US11974425B2
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

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Номер записи: 50
14-11-2023 дата публикации

NAND string utilizing floating body memory cell

Номер: US11818878B2
Автор: Benjamin S Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

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Номер записи: 51
14-05-2024 дата публикации

Memory device having electrically floating body transistor

Номер: US11985809B2
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

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Номер записи: 52
18-07-2024 дата публикации

Memory Cell Comprising First and Second Transistors and Methods of Operating

Номер: US20240243492A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

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Номер записи: 53
01-08-2024 дата публикации

Memory Device Having Electrically Floating Body Transistor

Номер: US20240260252A1
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

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Номер записи: 54
26-09-2023 дата публикации

Systems and methods for reducing standby power in floating body memory devices

Номер: US11769550B2
Автор: Benjamin S. Louie, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 55
28-09-2023 дата публикации

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

Номер: US20230307039A1
Автор: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
Принадлежит: Zeno Semiconductor Inc

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

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Номер записи: 56
13-08-2024 дата публикации

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

Номер: US12062392B2
Автор: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
Принадлежит: Zeno Semiconductor Inc

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

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Номер записи: 57
03-09-2024 дата публикации

Content addressable memory device having electrically floating body transistor

Номер: US12080349B2
Автор: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

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Номер записи: 58
17-04-2018 дата публикации

Systems and methods for reducing standby power in floating body memory devices

Номер: US09947387B2
Автор: Benjamin S. Louie, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

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Номер записи: 59