CURRENT TESTS FOR I/O INTERFACE CONNECTORS

Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface. 1. A method comprising:applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die;sensing the energy caused by the forced energy at a second pin of the interface; andcomparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.2. The method of claim 1 , wherein the forced energy is a forced current and the sensed energy is a sensed voltage.3. The method of claim 1 , wherein the forced energy is a forced voltage and the sensed energy is a sensed voltage.4. The method of claim 1 , wherein applying a forced energy comprises applying the forced energy to the first pin through a multiplexer claim 1 , each pin being coupled to a multiplexer to determine to which pin the forced energy is applied.5. The method of claim 4 , further comprising disabling the multiplexers for pins other than the first pin and driving the forced energy also to the disabled multiplexers.6. The method of claim 4 , wherein the forced energy is a forced voltage and the sensed energy is a sensed voltage and wherein sensing the voltage comprises sensing the voltage through an observability pin claim 4 , the method further comprising calibrating the observability pin by:disabling a plurality of the multiplexers;driving a voltage onto the disabled multiplexers; andmeasuring current leaked through the observation pin.7. The method of claim 6 , further comprising:repeating calibrating an observability pin to calibrate a plurality of different observability ...

Method, system and apparatus for evaluation of input/output buffer circuitry

Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

METHOD AND APPARATUS FOR AN OPTICAL INTERCONNECT SYSTEM

Provided are a method and a system, in which a first device aligns a chip to a socket along a first axis. A second device aligns the chip to the socket along a second axis, and a third device aligns the chip to the socket along a plane formed by the first axis and a third axis. Also provided is a system comprising a first optical element, and a second optical element, where a first elastic element is coupled to the first optical element, and a second elastic element is coupled to the second optical element, and where the first elastic element is aligned to the second elastic element via elastic coupling. 1. A system , comprising:a first device to align a chip to a socket along a first axis;a second device to align the chip to the socket along a second axis; anda third device to align the chip to the socket along a plane formed by the first axis and a third axis.2. The system of claim 1 , wherein the first axis represents a vertical dimension that is perpendicular to a plane formed by the second axis and the third axis claim 1 , wherein the socket is an optical socket claim 1 , and wherein the chip is a device under test (DUT).3. The system of claim 2 , wherein the first device applies vertical actuation that compresses the DUT along the vertical dimension onto the optical socket.4. The system of claim 2 , wherein the second device comprises a cam mechanism that engages a cam to two rods to apply a lateral force on the DUT.5. The system of claim 2 , wherein the third device comprises elastic coupling elements to perform alignment of the DUT to the socket to a tolerance of less than two microns.6. The system of claim 5 , wherein the alignment via the elastic coupling elements is based on patterns that include protrusions.7. The system of claim 5 , wherein the third device also includes an optical jumper assembly having a hole to which a pin of the DUT is aligned.8. The system of claim 2 , the system further comprising:a fourth device comprising a direct current (DC) ...

INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENERATION

I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing. 1. An apparatus comprising:a plurality of I/O buffer circuits, at least one of the plurality of buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; andtesting circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver; a delay line to provide a plurality of delay values from a transmit clock signal for the testing of the at least one buffer circuit,', 'a counter to provide a count to choose one of the plurality of delay values, and', 'test logic for the loop-back testing., 'wherein the testing circuitry includes2. The apparatus of claim 1 , wherein the test logic is to determine whether a result of the loop-back testing for the at least one buffer circuit is a match or a mismatch.3. The apparatus of claim 2 , wherein the test logic includes a first logic to determine whether all results of the loop-back testing are matches and a second logic to determine whether all results of the loop-back testing are mismatches.4. The apparatus of ...

Integrated circuit device having supports for use in a multi-dimensional die stack

Provided is an integrated circuit (IC) device having a support structure for use in a multi-dimensional (e.g., 3-D) die stack. The IC device includes a first chip (e.g., a memory die) positioned over a second chip (e.g., a logic layer), and a set of support structures between the memory die and the logic layer, wherein the set of support structures is arranged so as to radiate from a center of the memory die. In one approach, the set of support structures comprises two linear arrays each including a plurality of support members coupled to the memory die, the two linear arrays arranged in a standardized diagonal crossing configuration to provide increased stability between the memory die and the logic layer. In an exemplary embodiment, the set of support structures is connected to a power grid to help deliver power to circuitry of the memory die.

Device testing

A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.

Method, system and apparatus for evaluation of input/output buffer circuitry

Method, system and apparatus for evaluation of input/output buffer circuitry

Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Method, system and apparatus for evaluation of input/output buffer circuitry

Input/output delay testing for devices utilizing on-chip delay generation

I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Memory cell structural test

AN APPARATUS AND METHOD FOR TESTING MEMORY CELLS COMPRISING COUPLING A FIRST AND A SECOND MEMORY CELL (160, 162) TO A FIRST AND A SECOND BIT LINES (170, 172), RESPECTIVELY, READING DATA FROM THE FIRST AND SECOND MEMORY CELLS (160, 162) THROUGH THE FIRST AND SECOND BIT LINES (170, 172), AND COMPARING THE VOLTAGE LEVELS OF THE FIRST AND SECOND BIT LINES (270, 272) (FIGURE 2B)

Current tests for I/O interface connectors

Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.