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Применить Всего найдено 11. Отображено 11.
22-03-2012 дата публикации

PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS

Номер: US20120070993A1
Автор: Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region. 1. A process of forming an integrated circuit , comprising:providing a partially processed integrated circuit having an FeCap region, a buffer region, and a logic region with an overlying first hydrogen barrier layer;forming a photoresist pattern that is closed over said FeCap region and over said buffer region but is open over a portion of said logic region; andetching said first hydrogen barrier layer from said portion of said logic region.2. The process of further comprising:forming said photoresist pattern over said logic region for a second contact landing pad; andetching said first hydrogen barrier layer to form a second contact landing pad.3. The process of wherein said providing step includes a second hydrogen barrier layer that overlies said first hydrogen barrier layer claim 1 , and further wherein said etching step includes etching a second dielectric hydrogen barrier layer from said portion of said logic region.4. The process of further comprising the steps:forming said photoresist pattern over said logic region for a second contact landing pad; andetching said first hydrogen barrier layer and said second hydrogen barrier layer to form a second contact landing pad.5. The process of further comprising:depositing at least one of a hydrogen releasing layer and a deuterium releasing layer over said integrated circuit after said step of etching said first hydrogen barrier layer; anddepositing a second hydrogen barrier over said at least one of a hydrogen releasing layer and a deuterium releasing layer.6. The process of where said hydrogen releasing layer is SiNxHy with more Si—H bonds than N—H bonds and where said deuterium releasing layer is SiNxDy with more Si—D bonds than N—D bonds.7. The process of where said hydrogen releasing layer is formed using an HDP process with about 1850 watts of low frequency ...

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Номер записи: 1
14-06-2012 дата публикации

HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS

Номер: US20120149189A1
Автор: Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. 1. A process of forming an integrated circuit , comprising:providing a partially processed integrated circuit having a transistor and a PMD layer overlying said transistor;passivating said partially processed integrated circuit; andafter said passivating step, depositing a passivation trapping layer over said PMD layer.2. The process of further comprising:forming contacts within said PMD layer before said step of depositing said passivation trapping layer.3. The process of further comprising:forming contacts within said PMD layer after said step of depositing said passivation trapping layer.4. The process of further comprising:depositing a capping layer on said passivation trapping layer before said step of forming contacts.5. The process of where said passivating step is a HDP process including at least one of hydrogen and deuterium.6. The process of where said passivating step is depositing at least one of a hydrogen releasing layer and a deuterium releasing layer.7. The process of where said hydrogen releasing layer is a HDP SiNxHy film with more Si—H bonds than N—H bonds.8. The process of where said deuterium releasing layer is a HDP SiNxDy film with more Si-D bonds than N-D bonds.9. The process of where said passivating step is annealing said integrated circuit in at least one of a hydrogen and a deuterium containing ambient.10. The process of where said passivation trapping layer is a film selected from the group consisting of:AlO,AlON,SiNx, andSiNxHy.11. A process of forming an integrated circuit claim 1 , comprising:providing a partially processed integrated circuit that includes a transistor;passivating said partially processed ...

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Номер записи: 2
12-07-2012 дата публикации

HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS

Номер: US20120175689A1
Автор: Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. 1a substrate;a transistor coupled to said substrate, where an interface between said substrate and a gate dielectric of said transistor is passivated;a passivation trapping layer overlying said transistor; anda PMD layer overlying said passivation trapping layer.. An integrated circuit, comprising: This is a divisional of U.S. application Ser. No. 12/890,137, filed on Sep. 24, 2010, which claims the benefit of priority under U.S.C. §119(e) of U.S. Provisional Application 61/249,482, filed Oct. 7, 2009, both of which are incorporated herein by reference.Moreover, this application is related to patent application Ser. No. 12/890,219 (Attorney Docket Number TI-67739, filed Sep. 24, 2010) entitled “Ferroelectric Capacitor Encapsulated with a Hydrogen Barrier” and patent application Ser. No. 12/717,604 (Attorney Docket Number TI-67319, filed Mar. 4, 2010) entitled “Passivation of Integrated Circuits Containing Ferroelectric Capacitors and Hydrogen Barriers”. With their mention in this section, these patent applications are not admitted to be prior art with respect to the present invention.These embodiments relate to the field of integrated circuits. More particularly, these embodiments relate to the hydrogen passivation of integrated circuits.The example embodiments are described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the example embodiments. Several aspects are described below with reference to example applications for illustration. It should be understood ...

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Номер записи: 3
27-09-2012 дата публикации

FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER

Номер: US20120241907A1
Автор: Aggarwal Rajni J., Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. 1. An integrated circuit , comprising:an FeCap;an underlying hydrogen barrier coupled to a bottom surface of said FeCap; andan overlying hydrogen barrier layer in contact with a portion of a top surface of said underlying hydrogen barrier.2. The integrated circuit of wherein said overlying hydrogen barrier layer is also coupled to side and top surfaces of said FeCap.3. The integrated circuit of wherein said underlying hydrogen barrier is in contact with a PMD layer of said integrated circuit.4. The integrated circuit of wherein said underlying hydrogen barrier is selected from the group consisting ofAlO,AlON,SiNx,SiNxHy, andany combination thereof.5. The integrated circuit of wherein said overlying hydrogen barrier layer is comprised of a nitrided AlO film and a SiNxHy film.6. The integrated circuit of wherein said overlying hydrogen barrier layer is a SiNxHy film.7. The integrated circuit of wherein said underlying hydrogen barrier is in contact with a bottom plate of said FeCap claim 1 , and said overlying hydrogen barrier layer is in contact with a top plate of said FeCap.8. An integrated circuit claim 1 , comprising:an FeCap;an underlying hydrogen barrier coupled to a bottom surface of said FeCap;a hydrogen releasing film coupled to a bottom surface of said underlying hydrogen barrier; andan overlying hydrogen barrier layer in contact with a portion of said underlying hydrogen barrier.9. The integrated circuit of wherein said hydrogen releasing film is in contact with said bottom surface of said underlying hydrogen barrier.10. The integrated circuit of wherein an oxide capping layer is coupled between said underlying hydrogen barrier and said bottom surface of said FeCap.11. The ...

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Номер записи: 4
14-03-2013 дата публикации

MEMS DEVICE FABRICATED WITH INTEGRATED CIRCUIT

Номер: US20130062996A1
Автор: Denison Marie, Moise Ted S., Udayakumar Kezhakkedath R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element. 1. A MEMS device integrated on a same substrate as an integrated circuit , comprising:a semiconductor substrate;a dielectric isolation layer disposed over the substrate;a proof mass disposed in a portion of the substrate;a flexible element disposed adjacent to the proof mass, the flexible element being attached to the proof mass so that a bottom surface of the flexible element is higher than a bottom surface of the proof mass; a planar ferroelectric element having a perovskite structure;', 'a first electrode having at least a portion disposed on one of a top or bottom surface of the ferroelectric element; and', 'a second electrode having at least a portion disposed on the top surface of the ferroelectric element;', 'a hydrogen barrier disposed over the piezoelectric element;', 'a first contact establishing electrical connection to the first electrode; and', 'a second contact establishing electrical connection to the second electrode., 'a piezoelectric element disposed on the dielectric isolation layer, so that at least a portion of the piezoelectric element overlaps the flexible element, the piezoelectric element including2. The device of claim 1 , further including a ...

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Номер записи: 5
27-06-2013 дата публикации

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

Номер: US20130164933A1
Автор: Jain Manoj K., Moise Ted S., SUMMERFELT Scott R., Udayakumar Kezhakkedath R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. 1. A process for forming an integrated circuit , comprising:providing a substrate having transistors, a first pre-metal dielectric, and a contact photoresist pattern for a contact wall seal surrounding a FeCap area;forming at least one contact wall seal that is at least partially filled with a first hydrogen barrier material wherein said first hydrogen barrier material covers the walls of said at least one contact wall seal;forming at least one metal wall seal that is at least partially filled with a second hydrogen barrier material wherein said second hydrogen barrier material covers the walls of said at least one metal wall seal;forming at least one via wall seal that is at least partially filled with a third hydrogen barrier material wherein said third hydrogen barrier material covers the walls of said at least one via wall seal;forming a top plate seal over said FeCap array, said top plate seal being over and in contact with one of said at least one via wall seal.2. The process of wherein said first hydrogen barrier is at least one of TiN claim 1 , TiAlN claim 1 , and TiAlON claim 1 , and wherein said contact wall seal is filled with CVD-W.3. The process of wherein said third hydrogen barrier material is at least one of TaN claim 1 , TaON claim 1 , and TiN and wherein said at least one via wall seal is filled with Cu.4. The process of wherein said forming said top plate seal further comprises:forming a photoresist pattern on top of a dielectric layer, said dielectric layer containing a trench for a via wall seal;etching said dielectric layer to form a trench for an interconnect signal lead and a trench for said top plate seal;forming a TaN barrier layer on a bottom ...

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Номер записи: 6
20-02-2014 дата публикации

HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS

Номер: US20140051234A1
Автор: Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит:

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. 1. A process of forming an integrated circuit , comprising:providing a partially processed integrated circuit that includes a transistor;passivating said partially processed integrated circuit;after said passivating step, depositing a passivation trapping layer over said transistor; andforming a PMD layer over said passivation trapping layer.2. The process of where said passivating step is a HDP process including at least one of hydrogen and deuterium.3. The process of where said passivating step is depositing at least one of a hydrogen releasing layer and a deuterium releasing layer.4. The process of where said hydrogen releasing layer is a HDP SiNxHy film with more Si—H bonds than N—H bonds.5. The process of where said deuterium releasing layer is a HDP SiNxDy film with more Si-D bonds than N-D bonds.6. The process of where said passivating step is annealing said integrated circuit in at least one of a hydrogen and a deuterium containing ambient.7. The process of where said passivation trapping layer is a film selected from the group consisting of:AlO,AlON,SiNx, andSiNxHy. This is a divisional of U.S. application Ser. No. 13/396,420 filed Feb. 14, 2012 which is a divisional of U.S. application Ser. No. 12/890,137, filed on Sep. 24, 2010, which claims the benefit of priority under U.S.C. §119(e) of U.S. Provisional Application 61/249,482, filed Oct. 7, 2009, all of which are incorporated herein by reference.Moreover, this application is related to patent application Ser. No. 12/890,219 (Attorney Docket Number TI-67739, filed Sep. 24, 2010) entitled “Ferroelectric Capacitor Encapsulated with a Hydrogen Barrier” and patent application Ser. ...

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Номер записи: 7
18-12-2014 дата публикации

FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER

Номер: US20140370621A1
Автор: Aggarwal Rajni J., Basim Gul B., Moise Ted S., SUMMERFELT Scott R.
Принадлежит:

An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. 1providing a partially processed integrated circuit having a PMD layer;depositing an underlying hydrogen barrier on said PMD layer; andforming a FeCap over said underlying hydrogen barrier.. A process of forming an integrated circuit, comprising: This application is a divisional of U.S. patent application Ser. No. 13/485,068 filed May 31, 2012, which is a divisional of U.S. patent application Ser. No. 12/890,219 filed Sep. 24, 2010 which claims priority, under U.S.C. §119(e) of U.S. Provisional Application 61/249,478 (Texas Instruments docket number TI-67739 PS and entitled “Ferroelectric Capacitor Encapsulated with a Hydrogen Barrier”), filed Oct. 7, 2009).Moreover, this application is related to patent application Ser. No. 12/890,137 (Attorney Docket Number TI-68285, filed simultaneously with this application) entitled “Hydrogen Passivation of Integrated Circuits” and patent application Ser. No. 12/717,604 (Attorney Docket Number TI-67319, filed Mar. 4, 2010) entitled “Passivation of Integrated Circuits Containing Ferroelectric Capacitors and Hydrogen Barriers”. With their mention in this section, these patent applications are not admitted to be prior art with respect to the present invention.These embodiments relate to the field of integrated circuits. More particularly, these embodiments relate to protecting a ferroelectric capacitor from hydrogen degradation.The example embodiments are described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the example embodiments. Several aspects are described below ...

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Номер записи: 8
11-12-2008 дата публикации

Method for etching a substrate and a device formed using the method

Номер: US20080303141A1
Автор: Francis G. Celii, K.R. Udayakumar, Martin G. Albrecht, Scott R. Summerfelt, Ted S. Moise, William W. Dostalik, JR.
Принадлежит: Texas Instruments Inc

The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155 , in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130 . The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

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Номер записи: 9
07-04-2011 дата публикации

Ferroelectric capacitor encapsulated with a hydrogen barrier

Номер: US20110079878A1
Автор: Gul B. Basim, Rajni J. Aggarwal, Scott R. Summerfelt, Ted S. Moise
Принадлежит: Texas Instruments Inc

An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

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Номер записи: 10
30-03-2017 дата публикации

集積回路の水素パッシベーション

Номер: JP2017063200A
Автор: Bahar Basim Gul, S Moise Ted, Scott R Summerfelt, アール サマーフェルト スコット, アール サマーフェルト スコット, エス モイーズ テッド, エス モイーズ テッド, バハル バシム グル, バハル バシム グル
Принадлежит: Texas Instruments Inc, Texas Instruments Japan Ltd

【課題】集積回路において、水素パッシベーションを他に影響がないように実施する構造を提供する。【解決手段】基板２００２に結合されたトランジスタ２０１０上にプレメタル誘電体２０１２を設け、その上に水素放出層２０１４及びパッシベーショントラッピング層を設ける。【選択図】図２Ａ

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Номер записи: 11