SIGNAL DEGRADATION DETECTION

Implementations are directed to predicting signal degradation at receivers used to display a programming service. The receivers capture signal strength data that is then transmitted to a processing location, which may be associated with a provider of the programming service. A signal degradation detector at the provider operates to predict whether or not a future unacceptable signal quality will occur within a time interval. The prediction may be based on a test quantity calculated from signals captured at the receiver and based on a figure of merit for the geographic locale in which the receiver is located. A maintenance call may be initiated for those receivers that have such a poor signal quality. 1. A method to predict a maintenance condition of a receiver , comprising:determining a time series of test quantities for the receiver, the test quantities based on signal strength measurements collected at the receiver at a plurality of time instances;receiving a figure of merit for the receiver, the figure of merit indicating an expected signal quality for the receiver;eliminating the receiver as a candidate for failure prediction if the time series of test quantities is equal or greater than the figure of merit for a predetermined period of time;determining a failure prediction for the receiver based on the time series of test quantities and the figure of merit, the act of determining the failure prediction only performed if the receiver is not eliminated as a candidate for failure prediction; andidentifying the receiver if the failure prediction indicates a future unacceptable signal strength for the receiver.2. The method of claim 1 , further comprising:eliminating the receiver as a candidate for failure prediction if the time series of test quantities trends level or trends upward for a predetermined number of time instances.3. The method of claim 1 , further comprising:applying recursive linear regression to the time series of test quantities and the figure of ...

Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Verify to Program Transition

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float. 1. In a non-volatile memory circuit having non-volatile memory cells formed along a plurality of bit lines and a plurality of word lines according to a NAND type architecture , a method of programming the memory cells along a selected word line comprising:individually biasing the bit lines to one of a plurality of values, including a program inhibit level and a program enable level;biasing a common source line for the bit lines to a first non-zero voltage level; andapplying a series of a plurality of programming pulses to the selected word line while the bit lines and common source line are so biased, wherein the series of programming pulses are applied without intervening verify operations, wherein the common source line is maintained at the first non-zero voltage level between the individual pulses of the series of programming pulses, and wherein bit lines biased at the program inhibit level are maintained at the program inhibit level between the individual pulses of the series of programming pulses.2. The method of claim 1 , further comprising:subsequent to a first pulse of the series and prior to the pulse subsequent to the first pulse, changing the biasing on one or more of the bit lines from the program enable level to the program inhibit level.3. The method of claim 2 , wherein which of the one or more bit lines have the bias level changed from the program enable level to the program inhibit level and after which ...

Temperature based compensation during verify operations for non-volatile storage

A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

Compact High Speed Sense Amplifier for Non-Volatile Memory

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level. 1. A sense amplifier for a memory circuit , comprising:a latch circuit;an intermediate circuit, including a first node selectively connectable to one or more bit lines, a second node connectable to the latch circuit, and an internal node connectable to the first node;bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;a first switch connected to the latch circuit and the second node, whereby a value held in the latch circuit can be connected to the second node when on and isolate the latch circuit from the second node when off;a second switch, whereby the latch circuit can be connected to a data bus; anda third switch whereby the second node can be connected to a node of the latch that holds the inverse of said value held in the latch circuit.2. The sense amplifier circuit of claim 1 , further comprising:a fourth switch whereby the internal node is selectively connectable to a high voltage supply level.3. The sense amplifier circuit of claim 2 , further comprising:a capacitor connected between the internal node and a third node.4. The sense amplifier circuit of claim 3 , further comprising:a first transistor and a ...

Compact High Speed Sense Amplifier for Non-Volatile Memory and Hybrid Lockout

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch's supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies. 1. A sense amplifier for a memory circuit , comprising:an intermediate circuit, including a first node selectively connectable to one or more bit lines;bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;a pre-charge switch by which the first node can be connected to a first supply level for pre-charging of the first node for a sensing operation;a first latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node;a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; andfirst and second switches whereby the value latched in the first and second latch circuits can respectively be transferred to a data bus,wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits can sequentially be connected to have the value latched therein set according to the level of the first node.2. The sense amplifier of claim 1 , wherein the first latch circuit is connected between a second supply level and ground claim 1 , and the second latch circuit is ...

Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced layout Area and Power Consumption

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Memory System with Unverified Program Step

In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.

Prefabricated immediate no-drill dental implant

The invention concerns a dental implant comprising an apical end tapered conical portion axially connected to a coronal end cylindrical body wherein the coronal end cylindrical body has ridges on the proximal sides and has no ridges on the mesial and distal sides. The invention further concerns a series of manual pilot tools for the preparation of the tooth socket prior to implantation. The invention further concerns an undercut pilot tool for placing notches in the proximal walls of the tooth socket to prepare the socket to receive the dental implant. The invention also concerns methods for replacing a tooth with a prefabricated implant immediately upon removal of the tooth without the necessity for drilling by virtue of the initial retention of the prefabricated implant inside the jaw bone.

Temperature based compensation during verify operations for non-volatile storage

A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

Custom dental implants, systems, devices and methods

The invention concerns an anatomically shaped dental implant section custom shaped to fit the tooth socket of a particular individual and having a ridge circumferentially located that is complementary in size and location to a notch prepared in the tooth socket. The invention further concerns a pilot tool for the removal of soft tissue from the tooth socket prior to implantation, as well as an undercut pilot tool for placing a notch in the proximal walls of the tooth socket. The invention also concerns a dental implant system containing at least two separate dental implant sections that can be joined together to form a dental implant custom shaped to fit the tooth socket of a particular individual. The invention also concerns a method of implanting a dental implant of the present invention by sequentially positioning anatomically shaped implant sections in the root voids of the tooth socket and then joining the coronal ends of the anatomically shaped implant sections to form an anatomically shaped implant. The invention also concerns a dental implant system comprising a custom shaped dental implant, one or more soft tissue pilot tools and one or more undercut pilot tools. 1. A dental implant , comprising: a first anatomically shaped implant section and a second anatomically shaped implant section , wherein said first anatomically shaped implant section can be reversibly joined to said second anatomically shaped implant section to form an anatomically shaped implant.2. The dental implant of claim 1 , wherein said anatomically shaped implant has a coronal end claim 1 , and further comprising an abutment attached to said coronal end of the anatomically shaped implant so that the first anatomically shaped implant section and the second anatomically shaped implant section are attached to the abutment.3. The dental implant of claim 1 , wherein said first anatomically shaped implant section further comprises a first apical portion and wherein said first apical portion is ...

Segmentation of Blocks for Faster Bit Line Settling/Recovery in Non-Volatile Memory Devices

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced Layout Area and Power Consumption

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Techniques for Programming of Select Gates in NAND Memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Operational Amplifier Methods for Charging of Sense Amplifier Internal Nodes

Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages. 1. (canceled)2. The A sense amplifier circuit for a memory circuit , comprising:a latch circuit;an intermediate circuit having an internal node connectable to one or more bit lines of an array of memory cells and connectable to the latch circuit;bit line selection circuitry connected to the internal node, whereby the internal node can selectively be connected to the one or more bit lines;an operational amplifier having a first input connected to receive a reference voltage and a second input connected to receive feedback from an output of the operational amplifier; anda first switch whereby the internal node is connectable to the output of the operational amplifier, wherein during a pre-charge phase of a sensing operation the first switch is turned on to set the internal node to a level of the operational amplifier's output, andwherein, during the pre-charge phase, the reference voltage is initially set to a first value and subsequently set to a second value, where the second value corresponds to a pre-charge level for the internal node and the first value is lower than the second.3. The sense amplifier circuit of claim 2 , wherein the operational amplifier includes a pull up device and a pull down device connected in series between a first voltage supply level and ground.4. The sense amplifier circuit or claim 3 , where the memory circuit includes a charge pump from which is supplied the first voltage ...

Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge

In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current. 1. A method of operating a non-volatile memory circuit , the non-volatile memory circuit having a plurality of bit lines by each of which a corresponding plurality of individually selectable NAND strings are connectable to an associated sense amp circuit , the NAND stings each comprising a plurality of memory cells connected in series between the corresponding bit line and a source line , the method comprising: pre-charging each of a set of one or more bits lines by the associated sense amp circuits; and', 'concurrently pre-charging each of the set of bit lines by one or more of the corresponding NAND strings connected thereto from the source line., 'performing a sensing operation including a pre-charge phase, wherein the pre-charge phase comprises2. The method of claim 1 , wherein the NAND strings used to pre-charge the set of bit lines are non-selected for the sensing operation.3. The method claim 2 , wherein the NAND strings used to pre-charge the set of bit lines are not assigned by the memory circuit for the storage of data.4. The method of claim 3 , ...

VOLTAGE GENERATOR TO COMPENSATE FOR PROCESS CORNER AND TEMPERATURE VARIATIONS

The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor. 1. A system comprising:a bus;a data latch comprising a plurality of transistors coupled to the bus; anda voltage generator comprising a tracking transistor,wherein one or more physical characteristics of the tracking transistor substantially match one or more respective physical characteristics of at least one of the plurality of transistors in the data latch, andwherein the voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.2. The system of claim 1 , wherein the system further comprises:a sensing circuit coupled to the data latch via the bus, wherein the sensing circuit comprises a strobe transistor controlled by a strobe control signal, wherein the strobe control signal comprises a strobe control signal timing window based on a discharge rate of the pre-charged voltage, and wherein the discharge rate is based on the electrical characteristic of the tracking transistor.3. The system of claim 1 , wherein the voltage generator comprises an adjustable resistor circuit coupled to the tracking transistor and a current source claim 1 , wherein the adjustable resistor circuit is configured to change a resistor value between the tracking transistor and the current source based on monitored ...

SENSE AMPLIFIER WITH COMPARISON NODE BIASING FOR NON-VOLATILE MEMORY

Apparatuses, systems, and methods are disclosed for current sensing for non-volatile memory. A current to voltage conversion circuit may convert a current coupled to a sense amplifier to an analog voltage at a sense node. A voltage to digital conversion circuit may convert an analog voltage at a sense node to a digital signal, based on a voltage difference between the sense node and a comparison node during a strobe time. A bias circuit may bias a comparison node to a bias voltage other than a reference voltage, at least during a strobe time. 1. An apparatus comprising: a current to voltage conversion circuit configured to convert a current coupled to the sense amplifier to an analog voltage at a sense node;', 'a voltage to digital conversion circuit configured to convert the analog voltage at the sense node to a digital signal based on a voltage difference between the sense node and a comparison node during a strobe time; and', 'a bias circuit configured to bias the comparison node to a bias voltage other than a reference voltage at least during the strobe time., 'a sense amplifier comprising2. The apparatus of claim 1 , wherein the voltage to digital conversion circuit comprises a sense transistor claim 1 , the sense transistor comprising a source terminal claim 1 , a gate terminal claim 1 , and a drain terminal claim 1 , the gate terminal coupled to the sense node and the source terminal coupled to the comparison node.3. The apparatus of wherein the bias voltage decreases the voltage difference between the sense node and the comparison node during the strobe time4. The apparatus of claim 1 , wherein the bias voltage is within a range from 0.1 volts to 0.5 volts.5. The apparatus of claim 1 , wherein the current to voltage conversion circuit comprises:a capacitor coupled to the sense node;a boost circuit configured to couple a clock signal to the capacitor across from the sense node such that a sense node voltage is boosted by a boost amount when the clock signal ...

Sense amplifier with negative threshold sensing for non-volatile memory

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Techniques for programming of select gates in nand memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Techniques For Programming Of Select Gates In NAND Memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

USER CONTROL DEVICE WITH CASE CONTAINING CIRCUIT BOARD EXTENDING INTO MOUNTING LOCATION

A thermostat includes a housing having a base, a display mount cantilevered from the base, and a case defining an interior volume extending between a front surface and a rear surface, a touch-sensitive display configured to display visual media and receive user inputs, wherein the touch-sensitive display is attached to the display mount, processing electronics on a circuit board positioned at least partially within the interior volume of the case, wherein the processing electronics are configured to operate the touch-sensitive display, and a mounting bracket configured to attach to a mounting location, wherein the mounting bracket includes a frame defining an aperture and the case extends through the aperture so that the frame is located between the front and rear surfaces of the case. 1. A thermostat , comprising: a base;', 'a display mount cantilevered from the base; and', 'a case defining an interior volume extending between a front surface and a rear surface;, 'a housing, comprisinga touch-sensitive display configured to display visual media and receive user inputs, wherein the touch-sensitive display is attached to the display mount;processing electronics on a circuit board positioned at least partially within the interior volume of the case, wherein the processing electronics are configured to operate the touch-sensitive display; anda mounting bracket configured to attach to a mounting location, wherein the mounting bracket includes a frame defining an aperture and the case extends through the aperture so that the frame is located between the front and rear surfaces of the case.2. The thermostat of claim 1 , wherein the case is attached to the base and the case is attached to frame.3. The thermostat of claim 2 , wherein the mounting bracket further includes a second frame defining a second aperture and the case extends through the second aperture so that the second frame is located between the base and the rear surface of the case.4. The thermostat of claim 3 ...

Cancer Treatment Targeted to Tumor Adaptive Responses to Protein Synthesis Stress

In cancers such as prostate cancer, the combination of PTEN loss and activation of Myc activates an adaptive stress response that enables tumor cells to escape the stress of massively upregulated protein synthesis. This pro-survival response is mediated by the PERK-phosphorylated eIF2α axis of the UPR adaptive response. Agents that disrupt PERK-eIF2α pathways disrupt the adaptive response and lead to cancer cell death from uncontrolled growth. For example, ISRIB and derivatives may be employed as therapeutic agents to disrupt PERK-mediated adaptive mechanisms. Additionally PTEN loss and activation of Myc provides a diagnostic marker that enables better prognosis and the selection of amenable treatments.

Method and apparatus for acquiring and collecting biometric data sensed at a user's chin

A method and apparatus for collecting and evaluating biometric data of members of a group uses a mobile ad hoc network to relay information collected from each group member to a monitoring device. The information is collected from each group member using a chin strap biometric sensing device. The monitoring device is an endpoint of the mobile ad hoc network, and organizes the collected data for evaluation and display to a supervisor of the group. Any biometric parameter for a given group member that exceeds a preferred value can be flagged for immediate attention by the supervisor.

Serial communications protocol for safety critical systems

A method and system of establishing communications between at least two i ndependent software modules in a safety critical system, such as a medical s ystem, is provided. The design comprises providing a media connection betwee n software modules, wherein the software modules employ a communications pro tocol and participate in a bi-directional master-slave relationship between a master module and a slave module. The design further comprises sending arb itrary data between the master and slave modules, wherein the arbitrary data is used by the master module to control and obtain status from the slave mo dule, and sending arbitrary data further enables the slave module to return data and status information to the master module. The design also employs a safety critical communications watchdog between the master and slave modules , wherein the safety critical communications watchdog monitors communication s quality between the master and slave modules. The bandwidth efficient comm unications protocol comprises bytes transmitted using a packet consisting of a start indication, a message identifier, an optional service identifier, a class identifier, an optional length of data pertinent to the medical devic e, a checksum, and a checksum complement.

Low Noise Sense Amplifier Array and Method for Nonvolatile Memory

In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

Signal degradation detection.

Las implementaciones se dirigen a predecir degradación de señales en receptores utilizados para desplegar un servicio de programación. Los receptores capturan datos de resistencia de señales que entonces se transmiten a una ubicación de procesamiento, los cuales pueden asociarse con un proveedor del servicio de programación. Un detector de degradación de señales en el proveedor opera para predecir si ocurrirá o no una calidad de señal inaceptable futura dentro de un intervalo de tiempo. La predicción puede basarse en una cantidad de prueba calculada a partir de señales capturadas en el receptor y basarse en un factor de calidad para la ubicación geográfica en la cual se ubica el receptor. Puede iniciarse un plan de mantenimiento para aquellos receptores que tienen una calidad de señal deficiente.

Memory system with unverified program step

In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.

Regulation of Recovery Rates in Charge Pumps

A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value.

Method and system for providing maintenance to a receiver

Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (V SS ) noise from the locked out bit lines to the not yet locked out bit lines.

Method and apparatus for dynamically maintaining and executing data definitions and/or business rules for an electronic procurement system

An apparatus, method, and computer readable storage medium for dynamically maintaining data structures and executing business rules in an electronic procurement system. The method includes (a) dynamically maintaining a plurality of organizational profiles containing data structures, a plurality of users each being associated with a particular organizational profile; and (b) implementing a user requested transaction on a hosted e-procurement system with an application system by using information from the data structures stored in an organizational profile associated with the user.

Thermostat

Automated bonding for wireless devices

A method and apparatus for managing the establishment of a wireless connection between an instrument host and a non-fixed device is provided. The method comprises acquiring the non-fixed medical device address over a fixed wire by replacing the traditional wireless searching mechanism. The method also comprises providing an authentication mechanism between the instrument host and the non-fixed device, for example, across a wireless communications network.

Multiple bit line voltages based on distance

An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

Memory cell sensing

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Automated bonding for wireless devices

A method and apparatus for managing the establishment of a wireless connection between an instrument host and a non-fixed device is provided. The method comprises acquiring the non-fixed medical device address over a fixed wire by replacing the traditional wireless searching mechanism. The method also comprises providing an authentication mechanism between the instrument host and the non-fixed device, for example, across a wireless communications network.

Non-volatile storage with source bias all bit line sensing

A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Automated bonding for wireless devices

A method and apparatus for managing the establishment of a wireless connection between an instrument host and a non-fixed device is provided. The method comprises acquiring the non-fixed medical device address over a fixed wire by replacing the traditional wireless searching mechanism. The method also comprises providing an authentication mechanism between the instrument host and the non-fixed device, for example, across a wireless communications network.

High Speed Sense Amplifier Array and Method for Nonvolatile Memory

Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Memory devices with four data line bias levels

Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

High speed sense amplifier array and method for nonvolatile memory

Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

High speed sense amplifier array and method for nonvolatile memory

Memory devices with four data line bias levels

Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

Memory cell sensing

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Non-volatile storage with source bias all bit line sensing and the related method therefor

Speichervorrichtungen mit vier datenleitungsvorspannungspegeln

Speichervorrichtungen könnten ein erstes Latch zum Speichern eines ersten Datenbits; ein zweites Latch zum Speichern eines zweiten Datenbits; eine Datenleitung, die selektiv mit dem ersten Latch, dem zweiten Latch und einem String von in Reihe verbundenen Speicherzellen verbunden ist; und eine Steuerung, die dazu konfiguriert ist, die Datenleitung während einer Programmieroperation einer ausgewählten Speicherzelle vorzuspannen, beinhalten. Die Steuerung kann, wenn das erste Datenbit gleich 0 und das zweite Datenbit gleich 0 ist, die Datenleitung auf einen ersten Spannungspegel vorspannen; wenn das erste Datenbit gleich 1 und das zweite Datenbit gleich 0 ist, die Datenleitung auf einen zweiten Spannungspegel vorspannen; wenn das erste Datenbit gleich 0 und das zweite Datenbit gleich 1 ist, die Datenleitung auf einen dritten Spannungspegel vorspannen; und, wenn das erste Datenbit gleich 1 und das zweite Datenbit gleich 1 ist, die Datenleitung auf einen vierten Spannungspegel vorspannen.

Voltage generator to compensate for process corner and temperature variations

The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics-e.g., gate width and gate length dimensions-of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Memory cell sensing

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Memory cell sensing

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Cancer Treatment Targeted to Tumor Adaptive Responses to Protein Synthesis Stress

In cancers such as prostate cancer, the combination of PTEN loss and activation of Myc activates an adaptive stress response that enables tumor cells to escape the stress of massively upregulated protein synthesis. This pro-survival response is mediated by the PERK-phosphorylated eIF2α axis of the UPR adaptive response. Agents that disrupt PERK-eIF2α pathways disrupt the adaptive response and lead to cancer cell death from uncontrolled growth. For example, ISRIB and derivatives may be employed as therapeutic agents to disrupt PERK-mediated adaptive mechanisms. Additionally PTEN loss and activation of Myc provides a diagnostic marker that enables better prognosis and the selection of amenable treatments.

Voltage generator to compensate for process corner and temperature variations

The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Techniques for programming of select gates in NAND memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Stereographic image detail uniformity of a panoramic video capture device having an optical gradient

A stereographic image associated with a panoramic camera can be identified. The panoramic camera can include of a set of lenses and an image sensor. A pixel degradation curve associated with the image and/or the hardware of the panoramic camera can be determined, as can a sensor geometry of an image sensor used by the panoramic camera. A fixed smoothing function based on the pixel degradation curve and/or the sensor geometry can be created. The fixed smoothing function can be applied to a stereographic image to modify the image so it includes substantially uniform image detail per image region.

Self-healing job executor pool

Aspects of the present disclosure relate to a self-healing job executor pool. A server detects that a job executing on an executor failed. The server determines, based on at least one factor from a predetermined set of executor-related factors, that the job executing on the executor failed due to a state of the executor. The server adjusts, in response to determining that the job executing on the executor failed due to the state of the executor, the state of the executor to a known good state, where the known good state is selected from a stored set of known good states.

Techniques for programming of select gates in NAND memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Utilizing NAND strings in dummy blocks for faster bit line precharge

In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Wearable alert device having selectable alert volume and method of operating same

A wearable alert device includes an audio transducer and driver circuit that allows selection of either a high or low volume setting for driving the transducer. The driver circuit is operable in a single ended mode for low volume and a double ended mode for high volume. The single ended mode holds one terminal of the transducer low while the other is driven in correspondence with a clock signal, while the double ended mode drives one terminal in correspondence with the clock signal and the other terminal is inverted from the clock signal. The transducer is activated in response to an alert event, and can be driven according to a profile or pattern.

Alert puck system with VOIP callback for emergency response

A system of an alert puck, a mobile communication device, and an alert server for facilitating a VOIP session with the mobile communication device responsive to an emergency event triggered by the alert puck. The alert puck comprises a housing enclosing a sealed volume, a power supply and control circuitry that includes a personal area network (PAN) interface. The mobile communication device comprises an operating system, an alert application executing upon the operating system, and a wireless transceiver. The alert server contacts a set of one or more previously defined contact devices, conveys an emergency message, and facilitates the VOIP session with the alert application, when a button is pressed on the alert puck.