Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 24. Отображено 21.
29-12-2016 дата публикации

SEMICONDUCTOR PACKAGES INCLUDING INTERPOSER AND METHODS OF MANUFACTURING THE SAME

Номер: US20160379845A1
Автор: Tac Keun OH, Seung Taek YANG, OH TAC KEUN, YANG SEUNG TAEK, OH Tac Keun, YANG Seung Taek
Принадлежит:

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided. 1. A method of manufacturing a semiconductor package , the method comprising:forming via holes extending from a first surface of an interposer wafer into a body of the interposer wafer;forming interconnection structures in the via holes and on the first surface of the interposer wafer, each of the interconnection structures including a through electrode portion filling one of the via holes, an external connection portion disposed on the first surface of the interposer wafer, and an extension portion connecting the through electrode portion to the external connection portion;recessing a second surface of the interposer wafer opposite to the external connection portions to expose end portions of the through electrode portions at the recessed second surface;mounting a semiconductor die on the recessed second surface of the interposer wafer to electrically connect die connection portions of the semiconductor die to the end portions of the through electrode portions; andforming a protection portion covering the semiconductor die on the recessed second surface of the interposer wafer.2. The method of claim 1 , wherein the interposer wafer includes a silicon ...

Подробнее
Номер записи: 1
05-10-2017 дата публикации

SEMICONDUCTOR PACKAGES INCLUDING INTERPOSER AND METHODS OF MANUFACTURING THE SAME

Номер: US20170287734A1
Автор: Tac Keun OH, Seung Taek YANG, OH TAC KEUN, YANG SEUNG TAEK, OH Tac Keun, YANG Seung Taek
Принадлежит: SK hynix Inc.

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided. 1. A method of manufacturing a semiconductor package , the method comprising:attaching a semiconductor die to a first surface of an interposer wafer so that die connection portions of the semiconductor die face towards the first surface;forming a protecting portion covering the semiconductor die on the first surface of the interposer wafer;reducing a thickness of the interposer wafer by recessing a second surface of the interposer wafer opposite to the semiconductor die;forming via holes in the interposer wafer having the recessed second surface to expose the die connection portions; andforming interconnection structures in the via holes and on the recessed second surface of the interposer wafer, each of the interconnection structures including a through electrode portion filling one of the via holes, an external connection portion disposed on the recessed second surface of the interposer wafer, and an extension portion connecting the through electrode portion to the external connection portion.2. The method of claim 1 , wherein forming the interconnection structure comprises forming a conductive layer filling the via holes to provide the through ...

Подробнее
Номер записи: 2
19-01-2012 дата публикации

FLEXIBLE SEMICONDUCTOR PACKAGE APPARATUS HAVING A RESPONSIVE BENDABLE CONDUCTIVE WIRE MEMBER AND A MANUFACTURING THE SAME

Номер: US20120013016A1
Автор: KIM Sung Min, OH Tac Keun
Принадлежит:

A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted. 1. A flexible semiconductor package , comprising:a first flexible substrate;a second flexible substrate opposed to the first flexible substrate;a first semiconductor chip disposed on an upper surface of the first flexible substrate and which has a first bonding pad;a second semiconductor chip disposed on a lower surface of the second flexible substrate faced with the upper surface of the first flexible substrate and which has a second bonding pad;a conductive wire electrically connecting together the first and second bonding pads to each other and which has at least one elastic portion; anda flexible filling member interposed between the first and second flexible substrates.2. The flexible semiconductor package according to claim 1 , wherein the flexible filling member includes a gel.3. The flexible semiconductor package according to claim 1 , wherein the conductive wire comprises at least two elastic portions.4. The flexible semiconductor package according to claim 1 , wherein the conductive wire comprises an insulation film covering the conductive wire.5. The flexible semiconductor package ...

Подробнее
Номер записи: 3
07-06-2012 дата публикации

Semiconductor chip, stack-type semiconductor package, and method for manufacturing the same

Номер: US20120138925A1
Автор: Tac Keun OH
Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.

Подробнее
Номер записи: 4
16-08-2012 дата публикации

SEMICONDUCTOR CHIP AND FABRICATING METHOD THEREOF

Номер: US20120205816A1
Автор: OH Tac Keun, SON Ho Young
Принадлежит: HYNIX SEMICONDUCTOR INC.

A semiconductor chip includes a substrate having a front surface and a back surface opposite the front surface, a conductive column part passing through the substrate from the front surface to the back surface, a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity, a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed, and a back electrode electrically connected to the exposed end portion of the conductive column part. 1. A semiconductor chip comprising:a substrate having a front surface and a back surface opposite the front surface;a conductive column part passing through the substrate from the front surface to the back surface;a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity;a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed; anda back electrode electrically connected to the exposed end portion of the conductive column part.2. The semiconductor chip of claim 1 , wherein the first insulation layer coats the cavity and the back surface of the substrate.3. The semiconductor chip of claim 1 , wherein the first insulation layer includes an organic insulation material including photoresist.4. The semiconductor chip of claim 1 , wherein the back electrode covers a part of an upper surface of the first insulation layer.5. The semiconductor chip of claim 1 , wherein the conductive column part includes a plurality of columns spaced apart from one another.6. The semiconductor chip of claim 1 , further comprising:a second insulation layer formed on the first insulation layer, a part of an upper surface of the second insulation layer being coated with the back ...

Подробнее
Номер записи: 5
28-03-2013 дата публикации

WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME

Номер: US20130078807A1
Автор: CHOI Hyeong Seok, HAN Kwon Whan, KIM Seong Cheol, KIM Sung Min, LEE Ha Na, LIM Sang Joon, OH Tac Keun, PARK Chang Jun
Принадлежит: SK HYNIX INC.

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. 1. A method for fabricating a wafer level chip scale package , comprising the steps of:forming through holes passing through an upper face of a semiconductor chip and through a lower face opposite to the upper face, wherein the upper surface of the semiconductor chip is formed with bonding pads electrically connected to a circuit unit;to forming a metal seed layer over an inner surface of the semiconductor chip formed by the through holes and the upper face of the semiconductor chip;forming mask patterns having a band shape over the metal seed layer along a periphery of the redistribution regions respectively connecting the through hole and the bonding pad corresponding to the through hole;forming through electrodes inside the through holes exposed by using the mask patterns, forming redistribution units within each redistribution region and forming a dummy conductive pattern outside of each mask pattern;removing the mask patterns from the metal seed layer; andremoving the metal seed layer formed at a position corresponding to the mask pattern from the upper face of the semiconductor chip.2. The method according to claim 1 , wherein the step of forming the mask patterns over the metal seed layer includes the steps of:forming a photoresist film over the metal seed layer; andpatterning the photoresist film by exposing and developing the photoresist film.3. The ...

Подробнее
Номер записи: 6
20-06-2013 дата публикации

Semiconductor stack packages and methods of fabricating the same

Номер: US20130154074A1
Автор: Tac Keun OH
Принадлежит: SK hynix Inc

Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Подробнее
Номер записи: 7
07-11-2013 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20130292844A1
Автор: OH Tac Keun
Принадлежит: SK HYNIX INC.

A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers. 1. A semiconductor package comprising:a first interposer;first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; anda second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips,wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, andwherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers.2. The semiconductor package according to claim 1 , wherein the first interposer comprises first wiring lines electrically connecting one part of the first through electrodes with one part of the second through electrodes which correspond to the one part of the first through electrodes claim 1 , and the second interposer comprises second wiring lines electrically connecting an other part of the first through electrodes with an other part of the second through electrodes which correspond to the other part of the ...

Подробнее
Номер записи: 8
16-01-2014 дата публикации

Semiconductor chip module and semiconductor package having the same

Номер: US20140014958A1
Автор: Jae Sung OH, Kwon Whan Han, Seon Kwang Jeon, Tac Keun OH, Woong Sun Lee
Принадлежит: SK hynix Inc

A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Подробнее
Номер записи: 9
05-03-2015 дата публикации

Stack packages and methods of manufacturing the same

Номер: US20150061120A1
Автор: Jong Hoon Kim, Seung Taek Yang, Song Na, Tac Keun OH
Принадлежит: SK hynix Inc

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Подробнее
Номер записи: 10
13-11-2014 дата публикации

Semiconductor stack packages and methods of fabricating the same

Номер: US20140335656A1
Автор: Tac Keun OH
Принадлежит: SK hynix Inc

Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Подробнее
Номер записи: 11
22-10-2015 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20150303181A1
Автор: KIM Jong Hoon, LEE Jeong Hwan, OH Tac Keun
Принадлежит:

A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer. 1. A semiconductor package comprising:an interposer having a first surface and a second surface that is opposite to the first surface;a plurality of through-silicon vias (TSVs) penetrating the interposer;a recess having a predetermined depth from the second surface of the interposer toward the first surface of the interposer and disposed within the interposer between two adjacent TSVs so that outer walls of the TSVs are surrounded by the interposer;first and second semiconductor chips disposed over the first surface of the interposer, the second semiconductor chip being spaced apart from the first semiconductor chip horizontally over the first surface of the interposer; anda thermal expansion reinforcing pattern filling the recess.2. (canceled)3. (canceled)4. The semiconductor package of claim 1 , wherein the thermal expansion reinforcing pattern is disposed in the interposer and disposed a predetermined distance from each of the outer walls of the two adjacent TSVs between which the recess is disposed.5. The semiconductor package of claim 1 , wherein the plurality of TSVs has portions protruding from the second surface of the interposer by a predetermined distance.6. The semiconductor package of claim 5 , wherein the thermal expansion reinforcing pattern is disposed between protruding portions of two adjacent TSVs.7. The semiconductor package of claim 6 , wherein the thermal expansion reinforcing pattern is level with ends of the protruding portions of the two adjacent TSVs.8. The semiconductor package of claim 1 , wherein the thermal expansion reinforcing pattern comprises a material having a coefficient of thermal expansion (CTE) of 5 ppm/° C. or ...

Подробнее
Номер записи: 12
29-10-2015 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20150311182A1
Автор: LEE Jeong Hwan, OH Tac Keun
Принадлежит:

A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole. 1. A semiconductor package comprising:an interposer;a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed on the first surface and at a predefined distance from the first semiconductor chip;a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein; anda thermal expansion buffer pattern filling the trench hole.2. The semiconductor package of claim 1 , further comprising a plurality of first connecting electrodes disposed between the first semiconductor chip and the interposer and a plurality of second connecting electrodes disposed between the at least one second semiconductor chip and the interposer.3. The semiconductor package of claim 1 , wherein the first semiconductor chip comprises a system integrated circuit (IC) claim 1 , and the at least one second semiconductor chip comprises a memory semiconductor chip.4. The semiconductor package of claim 1 , wherein the first semiconductor chip is disposed in substantially the center of the interposer claim 1 , and at least two second semiconductor chips are disposed on either side of the first semiconductor chip and face each other.5. The semiconductor package of claim 1 , wherein the interposer comprises silicon.6. The semiconductor package of claim 1 , wherein the molding part comprises epoxy molding compound (EMC).7. The semiconductor package of claim 1 , wherein the trench hole is formed to expose the ...

Подробнее
Номер записи: 13
26-11-2015 дата публикации

MULTI CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20150340303A1
Автор: KIM Jong Hoon, LEE Jeong Hwan, OH Tac Keun, SON Ho Young
Принадлежит:

A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces. 1. A multi chip package comprising:a first chip mounted over an upper surface of a first substrate;a second chip mounted over the upper surface of the first substrate;a protective layer disposed to surround the first chip and the second chip, the protective layer exposing an upper surface of the first chip and an upper surface of the second chip;a thermal interface material disposed over the upper surface of the first chip, the upper surface of the second chip, and an upper surface of the protective layer; anda heat spreader disposed over the thermal interface material,wherein the first chip is positioned beside the second chip, andwherein the first substrate has an interposer structure including an interconnection and a through electrode, and the interconnection couples the first chip to the second chip.2. The multi chip package of claim 1 , wherein the upper surface of the first chip claim 1 , the upper surface of the second chip claim 1 , and the upper surface of the protective layer form a global planar surface.3. The multi chip package of claim 1 , wherein the upper surface of the first chip claim 1 , the upper surface of the second chip claim 1 , and the upper surface of the protective layer form a rough surface of convex and concave shapes.4. The multi chip package of claim 1 , wherein the upper surface of the first chip claim 1 , the upper surface of the second chip claim 1 , and the upper surface of the protective layer are substantially level with one another.5. The multi chip package of claim 1 , wherein a size of the first chip is different from a size of ...

Подробнее
Номер записи: 14
14-02-2017 дата публикации

Multi chip package and method for manufacturing the same

Номер: US9570370B2
Автор: Ho Young SON, Jeong Hwan Lee, Jong Hoon Kim, Tac Keun OH
Принадлежит: SK hynix Inc

A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.

Подробнее
Номер записи: 15
01-12-2015 дата публикации

Multi chip package and method for manufacturing the same

Номер: TW201545309A
Автор: Ho-Young Son, Jeong-Hwan Lee, Jong-Hoon Kim, Tac-Keun Oh
Принадлежит: SK hynix Inc

一種多晶片封裝包括：保護層，其具有環繞第一晶片和第二晶片的上表面，其中第一晶片和第二晶片安裝在第一基板上，以暴露所述第一晶片的上表面和所述第二晶片的上表面；散熱器，其佈置在所述上表面上；以及熱界面材料，其配置在所述散熱器和所述上表面之間的界面處。

Подробнее
Номер записи: 16
10-02-2011 дата публикации

Stacked semiconductor package electrically connecting semiconductor chips using outer surfaces thereof and method for manufacturing the same

Номер: US20110033978A1
Автор: Tac Keun OH
Принадлежит: Hynix Semiconductor Inc

A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips.

Подробнее
Номер записи: 17
01-03-2012 дата публикации

Wafer level chip scale package having an enhanced heat exchange efficiency with an emf shield and a method for fabricating the same

Номер: US20120049385A1
Автор: Chang Jun Park, Ha Na Lee, Hyeong Seok Choi, Kwon Whan Han, Sang Joon LIM, Seong Cheol Kim, Sung Min Kim, Tac Keun OH
Принадлежит: Hynix Semiconductor Inc

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Подробнее
Номер записи: 18
25-07-2017 дата публикации

Semiconductor packages including interposer and methods of manufacturing the same

Номер: US09716017B2
Автор: Seung Taek Yang, Tac Keun OH
Принадлежит: SK hynix Inc

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

Подробнее
Номер записи: 19
29-11-2016 дата публикации

Semiconductor package and method for manufacturing the same

Номер: US09508699B2
Автор: Jeong Hwan Lee, Jong Hoon Kim, Tac Keun OH
Принадлежит: SK hynix Inc

A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.

Подробнее
Номер записи: 20
02-08-2016 дата публикации

Semiconductor package and method for manufacturing the same

Номер: US09406584B2
Автор: Jeong Hwan Lee, Tac Keun OH
Принадлежит: SK hynix Inc

A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole.

Подробнее
Номер записи: 21