METHOD FOR DEHUMIDIFYING MOIST AIR

Procédé de déshumidification d'un gaz comprenant de la vapeur d'eau, ce procédé comprenant : - une étape d'aspiration du gaz à déshumidifier dans les sécheurs, - une étape de refroidissement du gaz dans les sécheurs au moyen du système de refroidissement jusqu'à une température de solidification de l'eau contenue dans le gaz à déshumidifier, - une étape de compression du gaz ainsi déshumidifié, - une étape de dégivrage pendant laquelle la glace dans les sécheurs est liquéfiée lorsque la quantité de glace accumulée dans les sécheurs atteint un seuil prédéterminé, le procédé comprend une étape de séchage primaire du gaz aspiré.

METHOD OF MOLDING A THERMOPLASTIC COMPOSITE ELASTOMERIC TIRE

Procédé de moulage d'un composite thermoplastique élastomérique pour pneumatique comportant une étape dans laquelle une couche d'élastomère thermoplastique (TPE) est appliquée contre une des faces du composite suivie d'une étape de moulage pour vulcanication du composite et réticulation de la couche d'élastomère thermoplastique (TPE) avec la couche voisine de matériau caoutchoutique. Le procédé comporte par ailleurs une étape consistant à appliquer une couche de protection anti-adhésive (12) contre la face d'élastomère thermoplastique (TPE) destinée à être en contact avec le moule.

ADAPTER OF SYRINGE WITH A VALVE OF THE TYPE HAS BALL

BOARD STRUCTURE FOR USE IN AN ELECTROMECHANICAL RELAY AND AN ELECTROMECHANICAL RELAY CARD COMPRISING THE STRUCTURE

Un relais électromécanique (100) comprenant une structure de carte (200) ayant au moins une partie de contact (300, 301) sur celle-ci, l'au moins une partie de contact (300, 301) étant destinée à venir en contact avec au moins un élément électroconducteur du relais électromécanique (100) et l'au moins une partie de contact (300, 301) étant formée en un matériau qui possède un point de fusion non inférieur à 400°C ; et un élément excitable (104) couplé à la structure de carte (200) pour transmettre une force mécanique à la structure de carte (200) de manière à déplacer l'élément électroconducteur lorsque l'élément excitable (104) commute depuis un état non-excité vers un état excité.

ELECTRIC CIRCUIT SUPPLY

La présente invention concerne un circuit électrique d'alimentation (1) d'une unité de contrôle électronique (3), ledit circuit (1) comprenant : - une première borne de connexion (B1) destinée à être reliée à une première source d'alimentation associée à un premier niveau de tension, - une deuxième borne de connexion (B2) destinée à être reliée à une deuxième source d'alimentation associée à un deuxième niveau de tension différent du premier niveau de tension, - une troisième borne de connexion (B3) destinée à être reliée à l'unité de contrôle électronique, - un premier élément de commutation (5a) agencé pour mettre en conduction la première (B1) et la troisième (B3) borne de connexion ou interrompre la conduction entre la première (B1) et la troisième (B3) borne de connexion, - un deuxième élément de commutation (5b) agencé pour mettre en conduction la deuxième (B2) et la troisième (B3) borne de connexion ou interrompre la conduction entre la deuxième (B2) et la troisième (B3) borne de ...

METHOD FOR MOLDING A COMPOSITE THERMOPLASTIC ELASTOMERIC TIRE

COVER CUP AND CONTAINER HAVING A COVER CUP

Le récipient ayant un couvercle en coupelle (10) selon la présente invention comprend au moins : un couvercle en coupelle (10), un premier corps en forme de coupelle (20), et un deuxième corps en forme de coupelle (30) ; une première surface périphérique sur un bord du couvercle (10) aménagée sous la forme d'au moins une première portion à enclenchement (11), et une deuxième surface périphérique sur un autre bord de ce couvercle (10) est aménagée sous la forme d'au moins une deuxième portion à enclenchement (12). La première et la deuxième surfaces périphériques sont décalées de manière unidirectionnelle l'une par rapport à l'autre. Le premier corps (20) vient en prise avec la première portion à enclenchement (11), le deuxième corps (30) venant en prise avec la deuxième portion à enclenchement (12).

THE DIGITAL FORM PROCESS AND SYSTEM OF SETTING OF BEAMS

INSPECTING DEVICE OF the TEMPERATURE Of an ELECTRIC FRYER

DISTANCE-TO-BED-BOUNDARY INVERSION SOLUTION PIXELATION

Une approche basée sur la pixellisation pour résumer les résultats d'inversion de fond de puits acquiert des solutions d'inversion et génère un modèle initial. Chaque solution stratifiée est pixellisée en pixels où chaque pixel contient la valeur de résistivité du modèle initial. Une fonction de pondération qui pondère les pixels en fonction de leur proximité avec l'outil de diagraphie peut être utilisée pour générer le modèle pixellisé afin d'améliorer ainsi la précision. Une étude de synthèse statistique est réalisée pour identifier le meilleur modèle pixellisé, qui est ensuite utilisé pour déterminer une ou plusieurs caractéristiques de la formation.

NOZZLE AND SWITCHES HAS VETERINARY USE EQUIPEE OF THE AFORESAID THE NOZZLE

MANUFACTURING METHOD OF SCINTILLATORS CSL: TL HAS HIGH LUMINOUS EFFICIENCY AND POST LUMINESCENT REDUCED, AND USE FOR DETECTING RADIATION

La présente invention concerne les procédés de fabrication de scintillateurs à iodure de césium (CsI:T1) dopés au thallium à rendement lumineux élevé et à remanence réduite ainsi que les applications à la détection par rayonnement afférentes.

AN ACCELEROMETER MAGNETIC LEVITATION SYSTEM HAVING HIGH ACCURACY

La présente invention concerne un accéléromètre de lévitation magnétique à haute précision destiné à mesurer l'accélération linéaire de l'appareil volant, comportant un système de chambre à vide de blindage magnétique, un système de détection de déplacement par interférences lumineuses, un système de commande magnétique et un petit corps magnétique servant comme une masse d'épreuve. Avec la mise en œuvre la technique de détection par interférences lumineuse, l'accéléromètre mesure précisément la position et l'attitude du petit corps magnétique en temps réel, et la technologie à lévitation magnétique est appliquée pour remettre précisément le petit corps magnétique dans sa position et son attitude, de sorte que le petit corps servant comme une masse d'épreuve soit toujours dans le centre de la chambre du système de commande.

BI-MODE HIGH FREQUENCY DIELECTRIC TOOL

Un transmetteur/récepteur pour une utilisation dans un outil de diagraphie diélectrique. Le transmetteur/récepteur comprend généralement un logement, une séparation, une première antenne et une deuxième antenne. Lorsqu'il fonctionne comme un transmetteur, un premier et un deuxième signaux électromagnétiques sont émis par la première et la deuxième antennes, respectivement. Le logement et la séparation sont formés pour combiner le premier et le deuxième signaux électromagnétiques en un signal combiné ayant diverses orientations dépendamment de la différence de phase entre le premier et le deuxième signaux électromagnétiques. Lorsqu'il fonctionne comme un récepteur, un signal électromagnétique entrant est divisé en un premier et un deuxième composants de signal. Le premier et le deuxième composant de signaux sont orientés vers la première et la deuxième antennes, respectivement, où ils sont transformés en un premier et un deuxième signaux électriques. Le premier et le deuxième signaux électriques ...

HOT PLUGGABLE VIDEO CARD AND COMPUTER SYSTEM THEREOF

DEHUMIDIFICATION METHOD OF MOIST AIR

CONDUCTING BODIES OF GRILL

Le corps conducteur du dispositif de gril; ledit grill comprenant un châssis et une plaque de cuisson amovible ; le dos de ladite plaque de cuisson a plusieurs tubes électrothermiques réglables ; un tube électrothermique se compose d'un corps d'un tube et deux électrodes aux deux extrémités ; l'extrémité d'électrode comporte des premier-contacts métalliques ; ledit châssis comprend une pluralité de second-contacts métalliques, lorsque le châssis et la plaque de cuisson sont assemblés, les deux peuvent devenir conducteur électrique respectivement avec le premier-contact métallique. Les utilisateurs peuvent choisir différents programmes pour régler la température de la plaque de cuisson. Lorsque le gril est connecté, ce dispositif de programmation permet de minimiser l'arc instantané généré lors du branchement et d'éviter une température élevée susceptible de détériorer l'appareil, et ainsi améliorer la durée de vie du gril multi-usages.

DOMESTIC IRON

TACTILE SENSORS AND METHOD FOR MANAGING THE COMFORT OF SUCH A MOTOR VEHICLE SEAT

La présente invention concerne un siège de véhicule automobile comprenant plusieurs zones individualisées de surface du siège (101 à 106 ; 201 à 205), des moyens de climatisation (3, 5), et au moins un capteur de température et/ou du taux d'humidité (4). Les moyens de climatisation (3, 5) et le capteur de température et/ou du taux d'humidité (4) sont disposés dans les zones individualisées de surface du siège (101 à 106 ; 201 à 205) et on commande les moyens de climatisation de chaque zone pour adapter indépendamment dans chaque zone l'intensité du chauffage, du refroidissement et de la ventilation, en fonction d'un état local de température et d'humidité déterminé au niveau de chaque zone à partir des mesures effectuées par les capteurs (4).

CATALYTIC REFORMING OF NAPHTHA

A SEAT IRON STAND TO BE PASSED BY AGAIN.

APPARATUS AND PROCESS OF PILOTING Of a PLASMA DISPLAY SCREEN INTERLACES

COVER CUP AND CONTAINER HAVING A COVER CUP

DERIVED From ALCOXYSILANE OF the ACIDS AMINES HAS GROUPING N-ACYLE, OF the DIPEPTIDES HAS GROUPING N-ACYLE AND OF the TRIPEPTIDES GROUPING N-ACYLE HAS, AS WELL AS the PARTICLES AND FORMULATIONS OILS IN WATER STABLE USING THEM

Un acide aminé à groupement N-acyle, un dipeptide à groupement N-acyle, et un tripeptide à groupement N-acyle hydrophiles substitués par des silanes ont été préparés, lesquels peuvent être utilisés en tant que traitements de surface réactifs pour des particules de pigments, de minéraux, et de charges. Ces particules traitées forment des dispersions stables dans la phase aqueuse de mélanges huile dans l'eau qui sont adaptés à des applications en cosmétique. Les particules traitées peuvent également être utilisées dans des formulations de poudre comprimée et de produit cosmétique de couleur.

DEVICE FOR MEASURING DEGREES OF DISSOCIATION OF GAS COMPRISING AN OPTICAL SPECTROMETER

Ce dispositif comprend : un chemin principal de gaz (1) pour mettre en œuvre les processus de dépôt assisté par plasma, de gravure de membrane et de modification de surface de matériau afin d'obtenir des fonctions et des effets spéciaux dans la fabrication de circuits intégrés à semi-conducteurs ; un deuxième chemin de gaz (6) relié au chemin principal de gaz (1) pour stocker du gaz réactif (A) ; un organe de détection (8) et un dispositif optique (9) de mesure de dissociation de gaz plasmatique par spectre optique disposé entre le chemin principal de gaz (1) et le deuxième chemin de gaz (6), l'organe de détection (8) détectant un degré de dissociation de gaz dans un corps de tube (7) et le dispositif (9) de mesure de dissociation de gaz plasmatique par spectre optique calcule une valeur relative de quantité de dissociation.

Cushion device for e.g. treadmill, has elastic member e.g. spring, with ends urging exercise machine and linkage, to be elastically deformed when linkage is swung, where angle between linkage and ground is less than ninety degrees

Un dispositif d'amortissement pour machine d'exercice, par exemple un tapis de course, comprend un dispositif de liaison (20), un ressort (24) et une monture (26). Le dispositif de liaison est monté à pivotement sur le fond de la machine d'exercice, et une roue (22) est montée à pivotement sur l'extrémité distale du dispositif de liaison. La monture sur laquelle est monté le ressort destiné à pousser sur le dispositif d'amortissement, est fixée sur le fond de la machine d'exercice. Lorsqu'un utilisateur fait de l'exercice sur la machine, les vibrations provenant de différentes directions se transmettent au dispositif de liaison et le font osciller de telle manière que le ressort est comprimé en vue d'absorber les vibrations.

TACTILE SENSORS AND METHOD FOR MANAGING THE COMFORT OF SUCH A MOTOR VEHICLE SEAT

Exercise treadmill for use as e.g. entertainment equipment, has processor that counts number of instantaneous speed variations which are displayed by screen so that user knows number of footsteps walked or run by user on belt conveyor

Tapis roulant d'exercice (1) comprenant un socle (2), un ensemble de mouvement (3) et un système de podomètre. Le système de podomètre comporte un détecteur (32) monté sur le socle (2) pour contrôler la vitesse d'un élément de l'ensemble de mouvement (3), tel qu'un moteur (24), un dispositif de transmission (26), des rouleaux (28) ou un tapis roulant (30), un processeur monté sur le socle (2) pour détecter des variations instantanées de la vitesse de l'élément de l'ensemble de mouvement (3) et compter les variations instantanées, et un écran (22) monté sur le socle (2) pour afficher un certain nombre des variations instantanées. De la sorte, les personnes courant ou marchant sur le tapis d'exercice (1) selon la présente invention sont informées du nombre de pas effectués en courant ou en marchant.

Catalytically reforming naphtha, comprises contacting naphtha with reforming catalyst, in presence of hydrogen gas for performing surface catalytic reforming reaction to obtain naphthenes, and hydrocarbon arenes and paraffins

La présente invention divulgue un procédé de reformage catalytique de naphta comprenant, en présence de gaz hydrogène, la mise en contact de naphta avec un catalyseur de reformage dans les conditions d'une pression de 0,15 à 3,0 MPa, d'une température de 300 à 540 °C, d'une vitesse spatiale en volume de 2,1 à 50 h-1, pour effectuer une réaction de reformage catalytique superficielle de manière à obtenir un rapport de conversion de naphtène supérieur à 85 % en masse et un rapport de conversion des paraffines en arènes et en hydrocarbures en C4- inférieur à 30 % en masse. Ce procédé peut être utilisé pour produire au maximum des paraffines à partir de naphta tout en produisant des arènes à partir de naphta, de manière que les naphtas deviennent les matières premières pour produire à la fois des arènes et des matériaux de craquage d'éthylène de bonne qualité.

UNIT OF SOLE Of a DOMESTIC IRON ELECTRIC

Foldable treadmill for e.g. women, has two handle bars turned along axial direction between two positions, where bars are also turned toward deck to folded position and turned away from deck to extended position

Tapis roulant pliable comprenant un élément principal ayant une base et une plate-forme fixée à la base, la plate-forme comprenant une courroie mobile, et deux poignées dont les extrémités pivotent sur l'élément principal. Les poignées sont tournées le long d'une direction axiale entre une première position et une seconde position, et les poignées sont également tournées vers la plate-forme vers une position pliée et tournées à distance de la plate-forme vers une position déployée. Les poignées sont dans un état déployé quand les poignées sont déplacées vers la position déployée et la première position, et les poignées sont dans un état plié quand les poignées sont déplacées vers la position pliée et la seconde position. Un panneau est monté de manière amovible sur les poignées avec un fil reçu dans la poignée et relié à un moteur dans la plate-forme.

Syringe adapter for use in needleless syringe for injecting liquid medicine into patient, has plunger formed on bendable portion, and air chamber defined in ring, portion and plunger and communicating with exhaust channel of base

L'invention porte sur un adaptateur de seringue avec une soupape de type à bille, qui a une base (10), un tube de dosage (20) monté autour de la base (10) et une soupape élastique (30) montée dans la base (10) et le tube de dosage (20). La base (10) a une rainure de guidage (112) et un canal de liquide interne (122) en communication l'un avec l'autre, ainsi qu'un canal d'évacuation. Un médicament liquide injecté dans l'adaptateur de seringue s'écoule à travers la rainure de guidage (112) et le canal de liquide interne (122), puis est injecté dans le corps d'un patient. L'air dans l'adaptateur de seringue s'écoule vers l'extérieur à travers le canal d'évacuation (16, 16') et n'est pas injecté dans le corps du patient, de sorte que le patient ne ressent pas de douleur. De plus, les éléments et les procédés d'assemblage de l'adaptateur de seringue sont simplifiés et le coût de fabrication de l'adaptateur de seringue est abaissé.

PROCESS OF ADAPTIVE SELECTION FOR the ORDERING OF PRIORITY Of ACCESS TO the MEMORY IN a TREATMENT UNIT MPEG

MECHANISM Of SLOPE FOR a Travelator

CONDUCTING BODIES GRILL

A SEAT IRON STAND TO BE PASSED BY AGAIN.

Siège porte-fer à repasser, qui comporte un siège et un panneau d'isolation thermique. Le panneau d'isolation thermique sert à poser un fer à repasser, le siège et le panneau d'isolation thermique constituent la connexion rotative. En plus, entre le siège et le panneau d'isolation thermique, on installe une unité d'ajustage d'angle servant à régler et localiser l'angle de rotation relative entre le siège et le panneau d'isolation thermique. Grâce à la connexion rotative entre le panneau d'isolation thermique et le siège, et à l'angle de rotation relative entre le panneau d'isolation thermique et le siège réglé et localisé par l'unité d'ajustage d'angle, après que les consommateurs règlent le panneau d'isolation thermique pour l'angle convenable ou préféré, le fer à repasser peut être posé sur le panneau d'isolation thermique commodément. Par conséquent, le produit est plus pratique, plus commode, plus applicable, et peut satisfaire les consommateurs divers, et être facile à encaisser et ...

UNE LAMPE A EFFET FLAMME

La présente invention concerne une lampe à effet flamme comprenant un abat-jour, une base, une carte mère, une pluralité de plaques de source lumineuse et une plaque de connexion, cette plaque de connexion est munie d'un socle de connexion; les extrémités supérieures de ces plusieurs plaques de source lumineuse sont connectés à la plaque de connexion et disposés en cercle; l'extrémité supérieure du carte mère est couplée avec le socle de connexion pour contrôler l'intervalle d'éclairage de chaque plaque de source lumineuse afin de présenter un effet de flamme; La base est fixé à la plaque de connexion; cet abat-jour est gainé à l'extérieur des plusieurs plaques de source lumineuse et est fixé à la base. Un socle de connexion et des fentes sont disposés sur la plaque de connexion, respectivement, pour coupler la carte mère et les plaques de source lumineuse, avec une structure de connexion à fiche, sans avoir besoin d'un conducteur à fil ouvert et d'une structure de connexion à câble, ce ...

POLYHYDROXY FATTY ACID AMIDES IN SOIL RELEASE AGENT-CONTAINING DETERGENT COMPOSITIONS

MULTI-LAYER DISTANCE TO BED BOUNDARY (DTBB) INVERSION WITH MULTIPLE INITIAL GUESSES

L'invention concerne un système et des procédés pour une inversion de géoguidage. Une réponse d'un outil de fond de puits le long d'un trajet d'un puits de forage à forer à travers une formation est prédite sur différentes étapes d'une opération de fond de puits, sur la base de chacun d'une pluralité de modèles initiaux de la formation. Chaque modèle initial représente un nombre différent de couches de formation sur une plage spécifiée. La réponse réelle d'un outil par rapport à un ou plusieurs paramètres de formation est déterminée, sur la base de mesures obtenues pendant une étape actuelle de l'opération. La réponse réelle est comparée à celle prédite à partir de chacun des modèles initiaux. Au moins un des modèles est sélectionné comme un modèle d'inversion, sur la base de la comparaison et d'un critère de sélection. Une inversion est réalisée pour des étapes subséquentes de l'opération le long du trajet de puits de forage, sur la base du modèle sélectionné. Le trajet de puits de forage ...

Polymere, die substituierte Indenofluorenderivate als Struktureinheit enthalten, Verfahren zu deren Herstellung sowie deren Verwendung

"DEATH-DOMAIN"-ENTHALTENDER REZEPTOR 4 (DR4), EIN MITGLIED DER TNF-REZEPTOR SUPERFAMILIE, WELCHER AN TRAIL (APO-2L) BINDET

Steel plate for preventing vertebral column and spinal cord

It is composed of an oblong loop body and a multi-hole arch plate which is connected to the middle part of the oblong loop body. The said oblong loop body on use has the concave troughs on its two ends inserted into the sectioned vertebral lamina and its lower border neighbours in-between two spinous processes and is fixed with steel wire. The arch plate covers the back side of vertebras and actsthe action of artificial vertebral lamina, so that it effectively protects spinal cord and the bone can be grofted in the back side.

Printhead For Generating Ink Drops With Reduced Tails

A printhead ( 10 ) for use in an inkjet printing process includes a substrate ( 12 ) having at least one ink feed opening ( 14 ) defined therein, an ink chamber ( 16 ) in operative and fluid communication with the ink feed opening(s) ( 14 ), and a nozzle plate ( 18 ) disposed on a portion (P 1 ) of the substrate ( 12 ). The nozzle plate ( 18 ) has a plurality of orifices ( 20 ) defined therein. The printhead ( 10 ) further includes a firing resistor ( 22 ) disposed on another portion (P 2 ) of the substrate ( 12 ) and proximate to the ink feed opening(s) ( 14 ) and a barrier structure ( 24 ) disposed on the other portion (P 2 ) of the substrate ( 12 ) and positioned adjacent to the firing resistor ( 22 ).

INKJET PRINTHEAD AND METHOD EMPLOYING CENTRAL INK FEED CHANNEL

An inkjet printhead () and a method () of supplying viscous ink employ a central ink feed channel (). The inkjet printhead () includes a bridge beam () that supports an ejector element (), a pair of lateral ink feed channels () adjacent to the bridge beam (), and a central ink feed channel () through the ejector element () and bridge beam (). The pair of lateral ink feed channels () and the central ink feed channel () connect between an ink reservoir () below the bridge beam () and the bubble expansion chamber (). The method () includes providing () a central ink feed channel in a bridge beam of a printhead and flowing () viscous ink from an ink reservoir through a combination of the provided central ink feed channel and a pair of lateral ink feed channels. 1100. An inkjet printhead () comprising:{'b': 110', '106', '104', '102, 'a bridge beam () that supports an ejector element () within a bubble expansion chamber () below a nozzle ();'}{'b': 120', '110', '120', '110', '110, 'a pair of lateral ink feed channels () adjacent to the bridge beam (), the pair of lateral ink feed channel () being spaced apart by and located on opposite sides of the bridge beam () to define a width of the bridge beam (); and'}{'b': 130', '106', '110', '130', '102, 'a central ink feed channel () through the ejector element () and bridge beam (), the central feed channel () being coaxial with the nozzle (),'}{'b': 120', '130', '140', '110', '104, 'wherein the pair of lateral ink feed channels () and the central ink feed channel () connect between an ink reservoir () below the bridge beam () and the bubble expansion chamber ().'}2100130110130. The inkjet printhead () of claim 1 , wherein a ratio of a width of the central ink feed channel () to a width of a portion of the bridge beam () on either side of the central ink feed channel () is between about 0.5 and 2.0.3100. The inkjet printhead () of claim 2 , wherein the ratio of the widths is between about 1.0 and 1.5.4100106110130. The inkjet ...

MEMORY EDGE CELL

A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively. 1. A circuit comprising:a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate;a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate;a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate;a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate;a third NMOS transistor having a third NMOS drain, a third NMOS source, and a third NMOS gate; anda fourth NMOS transistor having a fourth NMOS drain, a fourth NMOS source, and a fourth NMOS gate, the first PMOS drain, the first PMOS source, a voltage source, the second PMOS gate, and the second NMOS gate are coupled together;', 'the first PMOS gate, the first NMOS gate, the second PMOS drain, the second NMOS drain, and the fourth NMOS source are coupled together;', 'the third NMOS gate, the third NMOS drain, the first NMOS drain, and the second NMOS source are coupled together and serve as a first voltage reference node;', 'the fourth NMOS drain is coupled to a second voltage reference node;', 'a first voltage of the first voltage reference node serves as a first reference voltage of a memory cell; and', 'a second voltage of the second voltage reference node serves as a second reference voltage of the memory cell., 'wherein'}2. The circuit of further comprising a fifth NMOS transistor having a fifth PMOS drain coupled to the first ...

FLUID EJECTION DEVICE

A fluid ejection device includes a thin film heater resistor portion having a heater resistor, and a two-layer structure disposed over the heater resistor. The two-layer structure includes a top layer and a bottom layer, with the top layer having a hardness that is at least 1.5 times greater than the hardness of the bottom layer. 1. A fluid ejection device comprising:a thin film heater resistor portion that includes a heater resistor; anda two-layer structure disposed over the heater resistor that includes a top layer and a bottom layer, the top layer having a hardness that is at least 1.5 times greater than the hardness of the bottom layer.2. A fluid ejection device as recited in wherein the top layer has a hardness of greater than about 12 gigapascals and the bottom layer has a hardness of less than about 6.8 gigapascals.3. A fluid ejection device as recited in wherein the top layer comprises a platinum-ruthenium alloy.4. A fluid ejection device as recited in wherein the bottom layer comprises platinum.5. A fluid ejection device as recited in claim 1 , wherein:the top layer comprises a material selected from the group consisting of a titanium aluminum alloy, titanium nitride, tantalum nitride, hafnium oxide, silicon carbide, tantalum carbide, zirconium oxide and diamond like carbon; andthe bottom layer comprises platinum.6. A fluid ejection device as recited in claim 1 , wherein the top layer has a thickness in the range of about 200 Angstroms to about 1000 Angstroms claim 1 , and the bottom layer has a thickness in the range of about 1000 Angstroms to about 2 microns.7. A fluid ejection device as recited in claim 1 , further comprising a dielectric passivation layer disposed over the heater resistor between the bottom layer and the heater resistor.8. A fluid ejection device as recited in claim 7 , further comprising an adhesion layer between the dielectric passivation layer and the bottom layer to adhere the bottom layer to the dielectric passivation layer.9. A ...

COMPOSITIONS AND METHODS FOR LEUKOCYTE-TARGETING MULTI-VALENT IMAGING PROBES

The present application discloses a new multivalent peptide ligand specifically targeting polymorphonuclear leukocytes (PMNs) with favorable pharmacological parameters to monitor sites of inflammation for imaging. The detailed synthesis, characterization, and pharmacological evaluation of the ligands are reported here. Two separate peptide binding ligands for formyl peptide and tuftsin receptors were chosen to link together based on the high expression levels of the two receptors on activated PMNs The heterobivalency and pegylated links were incorporated in the structural design to improve the sensitivity of the detection and to improve the bioavailability along with blood clearance profile, respectively. Two chemical constructs: cFLFLF-(PEG)-TKPPR-Tc (n=4, 12) were evaluated in vitro with human PMNs for binding affinity and bioavailability. As a result, FLFLF-(PEG)-TKPPRTc was found to have more favorable pharmacological properties and was therefore used for further in vivo studies. Preliminary in vivo assessment of the agent was performed using Single Gamma Emission Computed Tomography (SPECT) imaging of a mouse model of ear inflammation. The results of these studies indicate cFLFLF-(PEG)-TKPPR-Tc may be a desirable imaging agent for binding to PMNs to identify sites of inflammation by SPECT. 1. A nuclear or NI (near infrared) optical imaging agent for imaging a site of inflammation in a mammalian body , the imaging agent comprising two neutrophil-binding peptide sequences linked by a hydrophilic polyethyleneglycol (PEG) moiety , and a radionuclide or a near infrared fluorophore (NIF).2. The imaging agent of claim 1 , wherein the neutrophile-binding peptide sequences comprise a formyl peptide receptor (FPR) binding sequence claim 1 , cF(D)LF(D)LF claim 1 , or a tuftsin receptor binding sequence claim 1 , TKPPR.3. The imaging agent of claim 1 , wherein the PEG is either linear or branched with a molecular weight from 500 to 10 claim 1 ,000.4. The imaging agent of ...

METHOD AND APPARATUS FOR CORRECTING CORNER POINT OF IMAGE AND IMAGE PROCESSING DEVICE

The present invention discloses a method and apparatus for correcting a corner point of an image and an image processing device. The method includes: determining first candidate corner points of an initial corner point in a first local region; obtaining information related to the image in a second local region; selecting, among the first candidate corner points of the initial corner point, the first candidate corner points meeting a predetermined condition, as second candidate corner points of the initial corner point according to the information; and correcting the initial corner point using the second candidate corner points of the initial corner point. The apparatus is configured to perform the processes of the method. The image processing device includes the apparatus for correcting a corner point of an image. With the technology, a roughly detected corner point can be corrected. 1. A method for correcting a corner point of an image , comprising:with regard to each initial corner point of the image, determining first candidate corner points of the initial corner point in a first local region that contains the initial corner point, wherein the first local region has a first predetermined size;with regard to each initial corner point of the image, obtaining information related to the image in a second local region that contains the initial corner point, wherein the second local region has a second predetermined size and contains the first local region;selecting, among the first candidate corner points of each initial corner point, first candidate corner points which meet a predetermined condition, as second candidate corner points of the initial corner point according to the obtained information related to the image; andcorrecting each initial corner point using the second candidate corner points of the initial corner point.2. The method for correcting a corner point of an image according to claim 1 , wherein the determining first candidate corner points of the ...

MASK BOX HAVING A BUCKLING STRUCTURE

A mask box having a buckling structure includes a base, a cover and a plurality of buckling elements. The base is configured to support a mask and has a plurality of troughs. The cover covers the base and has a plurality of pivotal portions. The buckling elements are positioned to correspond to the troughs. Each buckling element includes an engaging block and an elastic arm connected to the pivotal portion. The engaging block moves away from the periphery of the cover when the engaging block is subjected to an external force. The engaging block is buckled into the trough via an elastic restoring force of the at least one elastic arm when the external force is removed. By this arrangement, the assembly of the buckling elements is simplified and its product cost is reduced. Further, the present invention conforms to the requirements for environmental protection. 1. A mask box having a buckling structure , including;a base, configured to support a mask, a bottom edge of the base having a plurality of troughs;a cover, covering the base, an inner periphery of the cover having a plurality of pivotal portions; anda plurality of buckling elements, positioned to correspond to the troughs, each buckling element comprising an engaging block and at least one elastic arm extending from the engaging block, the other end of the at least one elastic arm being connected to the pivotal portion;wherein the engaging block moves away from the periphery of the cover when the engaging block is subjected to an external force, the engaging block is buckled into the trough via an elastic restoring force of the at least one elastic arm when the external force is removed.2. The mask box having a buckling structure according to claim 1 , wherein the cover has an inner wall adhered to an outer edge of the base and an outer wall provided outside the inner wall by an interval claim 1 , an accommodating trough is formed between the inner wall and the outer wall claim 1 , and the pivotal portion is ...

MEMORY EDGE CELL

A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell. 1. A column of a memory comprising:a first edge cell located at a first edge of the column and including a first edge cell reference node and a second edge cell reference node; andat least one memory cell, each of the at least one memory cells including a first memory reference node,whereinthe first edge cell reference node is coupled to one or more corresponding first memory reference nodes of the at least one memory cell;the second edge cell reference node serves as second memory reference nodes of the at least one memory cell; andfront-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.2. The column of further comprising a second edge cell located at a second edge of the column.3. The column of claim 2 , wherein the first edge cell is different from the second edge cell.4. The column of claim 1 , wherein:a memory cell of the at least one memory cell includes a first memory PMOS transistor, a second memory PMOS transistor, a first memory NMOS transistor, a second memory NMOS transistor, a third memory NMOS transistor, and a fourth memory NMOS transistor;the first edge cell includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;the first memory PMOS ...

Method of Simultaneously Removing Sulfur and Mercury from Hydrocarbon Material Using Catalyst by Means of Hydrotreating Reaction

Disclosed herein is a method of simultaneously removing sulfur and mercury from a hydrocarbon material, including: hydrotreating the hydrocarbon material containing sulfur and mercury in the presence of a catalyst including a metal supported with a carrier to convert sulfur into hydrogen sulfide, and adsorb mercury on a metal active site or a carrier of the catalyst in the form of mercury sulfide.

Image Processing Device, Image Processing Method, Scanner and Storage Medium

The disclosure provides an image processing device, image processing method, scanner and storage medium. The image processing device is used for tracing a boundary of an object image in an image, the boundary being continuous and the rate of change in slope between adjacent points on the boundary being slow. The image processing device includes: a boundary estimation unit, adapted to estimate the location of the boundary of the object image; an interfering gradient processing unit, adapted to process an interfering gradient near the estimated boundary, so as to reduce the interfering gradient or remove the interfering gradient from the image; and a boundary tracing unit, adapted to trace the boundary in the image having the interfering gradient processed. By using the technique of the disclosure, the accuracy of tracing a boundary of an image is improved significantly. 1. An image processing device for tracing a boundary of an object image in an image , the boundary being continuous and the rate of change in slope between adjacent points on the boundary being slow , the image processing device comprising:a boundary estimation unit, adapted to estimate the location of the boundary of the object image;an interfering gradient processing unit, adapted to process an interfering gradient near the estimated boundary, so as to reduce the interfering gradient or remove the interfering gradient from the image; anda boundary tracing unit, adapted to trace the boundary in the image having the interfering gradient processed.2. The image processing device according to claim 1 , wherein the boundary estimation unit comprises:a segmentation unit, adapted to segment a portion of the image between two corners on the boundary into a predetermined number of segments; anda segment boundary estimation unit, adapted to estimate the location of the boundary respectively in each of the segments.3. The image processing device according to claim 2 , wherein the segment boundary estimation ...

APPARATUS, METHOD FOR EXTRACTING BOUNDARY OF OBJECT IN IMAGE, AND ELECTRONIC DEVICE THEREOF

The invention provides an apparatus and method for extracting a boundary of an object in an image and an electronic device. The apparatus includes: a position determining unit, configured to determine a start point and an end point of a boundary of an object in an image and to determine a position of a reference point relevant to the start point and the end point; a first direction determining unit, configured to determine a first direction of the boundary; a gradient map obtaining unit, configured to obtain a gradient map of a first region; a gradient attenuating unit, configured to attenuate in the gradient map the gradients of a second region; and an extracting unit, configured to extract a boundary of an object. The technology of the invention can improve the accuracy of boundary extracting, and can be applied in the field of image processing. 1. An apparatus for extracting a boundary of an object in an image , comprising:a position determining unit, configured to determine a start point and an end point of the boundary of the object in the image and to determine a position of a reference point relevant to the start point and the end point;a first direction determining unit, configured to determine a first direction of the boundary;a second direction determining unit, configured to determine a second direction intersecting the first direction;a gradient map obtaining unit, configured to determine in the image a first region comprising the start point, the end point and the reference point and to obtain a gradient map of the first region;a gradient attenuating unit, configured to determine at least one second region on at least one of two sides of the reference point along the second direction and to attenuate in the gradient map the gradients of the second region; andan extracting unit, configured to extract a boundary between the start point and the end point based on the attenuated gradient map to obtain the boundary of the object.2. The apparatus for ...

Image processing method, apparatus, and storage medium

The present disclosure discloses an image processing method, apparatus, and a non-transitory computer readable medium. The method can includes: acquiring a three-dimensional (3D) model and original texture images of an object, wherein the original texture images are acquired by an imaging device; determining a mapping relationship between the 3D model and the original texture images of the object; determining, among the original texture images, a subset of texture images associated with a first perspective of the imaging device; splicing the subset of texture images into a spliced texture image corresponding to the first perspective; and mapping the spliced texture image to the 3D model according to the mapping relationship.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin. 1. A semiconductor device , comprising:a substrate comprising a first semiconductor fin;a first dielectric fin disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, wherein a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin; andan isolation structure in contact with the first semiconductor fin and the first dielectric fin, wherein a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.2. The semiconductor device of claim 1 , wherein the top surface of the first semiconductor fin and the top surface of the first dielectric fin are substantially coplanar.3. The semiconductor device of claim 1 , wherein:the first semiconductor fin has a second sidewall connected to the first sidewall; andthe first dielectric fin has a sidewall connected to the second sidewall of the first semiconductor fin, wherein the second sidewall of the first semiconductor fin and the sidewall of the first dielectric fin are substantially coplanar.4. The semiconductor device of claim 1 , wherein the first semiconductor fin comprises a base portion and a protruding portion protruding upward from the base portion claim 1 , and the first dielectric fin is over the base ...

SEMICONDUCTOR DEVICE AND METHOD

A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer. 1. A method comprising:providing a substrate having a gate structure over a first side of the substrate;forming a recess adjacent to the gate structure;forming a first semiconductor layer comprising a dopant in the recess, the first semiconductor layer contacting surfaces of the substrate exposed by the recess, the first semiconductor layer being a non-conformal single layer, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess; andforming a second semiconductor layer comprising the dopant in the recess, the second semiconductor layer disposed over and contacting the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being ten times or more higher than a first concentration of the dopant in the first semiconductor layer.2. (canceled)3. The method of claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise silicon claim 1 , and the dopant comprises phosphorous.4. The method of claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise silicon germanium claim 1 , and the dopant comprises boron.5. The method of claim 1 , wherein forming the first semiconductor layer comprises:depositing in the recess a semiconductor material ...

MEMORY CELL ARRAY

A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line. 1. A semiconductor memory cell array comprising: an active region;', 'a first transistor formed on the active region;', 'a second transistor formed on the active region;', 'a gate structure formed on the active region and between the first transistor and the second transistor; and', 'an interconnect connecting the gate structure and at least one of sources of the first transistor and the second transistor to a power line., 'a memory cell unit comprising2. The semiconductor memory cell array of claim 1 , further comprising:at least one contact formed between the interconnect and the power line.3. The semiconductor memory cell array of claim 1 , wherein the interconnect connects the gate structure and the sources of the first transistor and the second transistor to the power line.4. The semiconductor memory cell array of claim 3 , further comprising:a plurality of contacts, wherein the gate structure and the sources of the first transistor and the second transistor are connected through the interconnect and the plurality of contacts to the power line.5. The semiconductor memory cell array of claim 1 , wherein the gate structure is configured to receive a reference voltage through the interconnect from the power line to electrically isolate the first transistor from the second transistor.6. The semiconductor memory cell array of claim 1 , further comprising:a plurality of contacts connecting a drain of the first transistor and a drain of ...

PROTON ACTIVATED ATOMIC MEDICINE

The present application provides compositions and methods for preparing and using “heavy” nucleotide derivatives of thymidine or uridine by replacing the oxygen atom attached to one or more of positions with non-radioactive oxygen-18 (O), administering it to a subject to target a tumor including incorporation into tumor cell DNA, and then treating the tumor with proton beam therapy to transmutate the O to F, resulting in a break of the new fluorine-phosphorous bond. This chemical event destabilizes ribose-phosphate DNA back-bone and base pairing thus produce single- and double strand breaks, clusters lesions that can lead to irreparable DNA damage and enhanced tumor cell killing. The atomic, chemical, and physical aspects result in the use of lower radiation doses and significantly alter acute and late morbidity of radiotherapy. Heavy thymidine and heavy uridine derivatives labeled with O have been made and tested. 2. The compound of claim 1 , wherein said compound comprises at least one additional O.3. (canceled)4. The compound of claim 2 , wherein three oxygens are O.5. The compound of claim 2 , wherein four oxygens are O.6. The compound of claim 1 , wherein said compound is deuterated.8. (canceled)9. (canceled)10. A method of treating a tumor using proton beam therapy in a subject in need thereof claim 1 , said method comprising administering to said subject a pharmaceutical composition comprising an effective amount of a compound of and subjecting said tumor to proton beam therapy claim 1 , thereby treating a tumor using proton beam therapy.12. The method of claim 10 , wherein said compound is deuterated.13. The method of claim 10 , wherein said tumor is imaged using positron emission tomography (PET) or computerized tomography (CT).14. The method of claim 10 , wherein an O of said compound is transmutated to F upon exposure to said proton beam.15. (canceled)16. The method of claim 10 , wherein said treatment is used in combination with another treatment ...

Method for Detecting Presence and Location of Defects in a Substrate

A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison. 1. A method , comprising:forming a dielectric layer over a wafer;forming a plurality of openings extending through the dielectric layer and into the wafer;epitaxially forming a semiconductor material within the plurality of openings;performing one or more measurements for each of the plurality of openings having the semiconductor material formed therein; anddetermining a presence of a defect over a substrate based on the one or more measurements.2. The method of claim 1 , wherein the one or more measurements comprises a wavelength-dispersive X-ray spectroscopy measurement.3. The method of claim 1 , wherein the epitaxially forming the semiconductor material comprises at least one of molecular beam epitaxy claim 1 , liquid phase epitaxy claim 1 , vapor phase epitaxy claim 1 , or selective epitaxial growth.4. The method of claim 1 , wherein the forming the dielectric layer over the wafer comprises at least one of a chemical vapor deposition claim 1 , a plasma enhanced chemical vapor deposition claim 1 , a low-pressure chemical vapor deposition claim 1 , or a sub-atmospheric chemical vapor deposition.5. The method of claim 1 , wherein a thickness of the dielectric layer is in a range from about 3 ...

Implantations for Forming Source/Drain Regions of Different Transistors

A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack. 1. A method comprising: forming a silicon oxide layer on a semiconductor region;', 'depositing a hafnium oxide layer over the silicon oxide layer;', 'depositing a lanthanum oxide layer over the hafnium oxide layer; and', 'depositing a work-function layer over the lanthanum oxide layer; and, 'forming a first gate stack of a first transistor comprisingforming first source/drain regions on opposite sides of the first gate stack.2. The method of further comprising depositing a hafnium silicate layer between the silicon oxide layer and the hafnium oxide layer.3. The method of claim 2 , wherein the hafnium silicate layer has a hafnium atomic percentage lower than about 10 percent.4. The method of claim 1 , wherein the silicon oxide layer is free from hafnium.5. The method of further comprising depositing a lanthanum silicon oxide layer over the lanthanum oxide layer.6. The method of further comprising:removing the lanthanum oxide layer and the hafnium oxide layer; anddepositing an additional hafnium oxide layer over the silicon oxide layer.7. The method of further comprising depositing a titanium silicon nitride layer over the lanthanum oxide layer.8. A method comprising:forming a silicon oxide layer comprising a first portion and a second portion over a first semiconductor region and a second semiconductor region, respectively;depositing a first hafnium oxide layer comprising a first portion and a second portion over the first portion and the second portion, respectively, of the silicon oxide layer;depositing a lanthanum oxide layer comprising a first portion ...

Buried Interconnect Conductor

Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect. 1. A device comprising:a fin disposed on a substrate, wherein the fin includes an active device;a plurality of isolation features disposed on the substrate and below the active device;an interconnect disposed on the substrate and between the plurality of isolation features such that a topmost surface of the interconnect is below a topmost surface of the plurality of isolation features, wherein the interconnect is electrically coupled to the active device; anda dielectric feature disposed between the plurality of isolation features and extending from the topmost surface of the interconnect to a height above the topmost surface of the plurality of isolation features.2. The device of further comprising:a gate stack of the active device disposed over a channel region of the active device, wherein the gate stack of the active device is electrically coupled to the interconnect.3. The device of claim 2 , wherein the gate stack is directly electrically coupled to the interconnect.4. The device of claim 2 , wherein a gate electrode of the gate stack extends between the plurality of isolation features to electrically couple to ...

STRUCTURE AND FORMATION METHOD OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure. 1. A semiconductor device structure , comprising:a fin structure over a semiconductor substrate;active gate stacks over covering a top and sidewalls of the fin structure;a dummy gate stack over covering a top and sidewalls the fin structure, wherein the dummy gate stack is between the active gate stacks;spacer elements over sidewalls of the dummy gate stack and the active gate stacks; andan isolation feature below the dummy gate stack, the active gate stacks and the spacer elements, wherein the isolation feature extends into the fin structure from a bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure, and wherein the isolation feature has two opposing sloped sidewalls that intersect each other in the fin structure.2. The semiconductor device structure as claimed in claim 1 , wherein the isolation feature is in contact with the bottom of the dummy gate stack.3. The semiconductor device structure as claimed in claim 1 , wherein the dummy gate stack comprises a gate electrode and a gate dielectric layer claim 1 , and a portion of the gate dielectric layer is sandwiched ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer. 1. A semiconductor device , comprising:a substrate;a gate structure over the substrate;a plug disposed over and electrically connected to the gate structure; anda hard mask structure over the gate structure, comprising a first hard mask layer and a second hard mask layer, wherein the first hard mask layer surrounds and is in contact with the plug, the second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.2. The semiconductor device as claimed in claim 1 , wherein a k constant of the material of the first hard mask layer is lower than a k constant of the material of the second hard mask layer.3. The semiconductor device as claimed in claim 1 , wherein the material of the first hard mask layer includes SiOC claim 1 , SiCN claim 1 , SiN claim 1 , SiOor a combination thereof.4. The semiconductor device as claimed in claim 1 , wherein the material of the second hard mask layer includes ZrO claim 1 , HfO claim 1 , HfSiO claim 1 , ZrSiO or a combination thereof.5. The semiconductor device as claimed in ...

COMPOSITIONS AND METHODS FOR IMAGING INFLAMMATION OF TRAUMATIC BRAIN INJURY

The present application provides compositions and methods for imaging traumatic brain injury using PET. The present application discloses using PET ligands targeting infiltrating neutrophils, such as a ligand of FPR, is useful for imaging inflammation. In one aspect, the ligand and imaging agent cFLFLF-PEG-Cu. 1. A method for imaging inflammation in the brain , said method comprising administering to a subject a composition comprising a ligand for the formyl peptide receptor , wherein said ligand comprises a neutrophil-binding peptide linked to a hydrophilic polyethyleneglycol (PEG) moiety , and a detectable label , and submitting said subject to an imaging technique.2. The method of claim 1 , wherein said detectable label is a radionuclide selected from the group consisting of In claim 1 , In claim 1 , Lu claim 1 , F claim 1 , Fe claim 1 , Cu claim 1 , Cu claim 1 , Cu claim 1 , Ga claim 1 , Ga claim 1 , Y claim 1 , Y claim 1 , Zr claim 1 , Tc claim 1 , Tc claim 1 , Tc claim 1 , I claim 1 , I claim 1 , I claim 1 , I claim 1 , I claim 1 , Gd claim 1 , P claim 1 , C claim 1 , N claim 1 , O claim 1 , Re claim 1 , Re claim 1 , Mn claim 1 , mMn claim 1 , Co claim 1 , As claim 1 , Br claim 1 , Br claim 1 , mRb claim 1 , Sr claim 1 , or other gamma- claim 1 , beta- claim 1 , or positron-emitters.3. The method of claim 2 , wherein said label is Cu.4. The method of claim 1 , wherein the neutrophil-binding peptide is cinnamoyl-F(D)LF(D)LF.5. The method of claim 4 , wherein the neutrophil-binding peptide is linked to said PEG via a lysine.6. The method of claim 5 , wherein the neutrophil-binding peptide linked to PEG via a lysine has the formula cF(D)LF(D)LFK-PEG.7. The method of claim 1 , wherein said imaging technique is selected from the group consisting of fluorescence claim 1 , positron emission tomography (PET) claim 1 , magnetic resonance imaging claim 1 , single photon emission computed tomography (SPECT/CT) claim 1 , intravital laser scanning microscopy claim 1 , ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer. 1. A semiconductor device , comprising:a fin structure;a gate electrode crossing over the fin structure;a source-drain region in the fin structure aside the gate electrode;a plug disposed over and electrically connected to the gate electrode; anda hard mask structure, surrounding the plug and disposed over the gate electrode, wherein the hard mask structure comprises a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.2. The semiconductor device as claimed in claim 1 , wherein the material of the first hard mask layer comprises oxide claim 1 , nitride or oxy-nitride.3. The semiconductor device as claimed in claim 1 , wherein the material of the first hard mask layer comprises SiN claim 1 , and the material of the second hard mask layer comprises ZrO.4. The semiconductor device as claimed in claim 1 , further comprising:a contact etch stop layer (CESL) aside the gate electrode; anda spacer disposed between the gate electrode and the contact etch stop layer, wherein the hard mask structure covers a top surface of the ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICE

A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires. 1. A method of forming a semiconductor device , the method comprising:forming semiconductor fins over a substrate and a patterned mask layer over the semiconductor fins, wherein the semiconductor fins comprise epitaxial layers over semiconductor strips, wherein the epitaxial layers comprise alternating layers of a first semiconductor material and a second semiconductor material;forming hybrid fins over isolation regions on opposing sides of the semiconductor fins, wherein each of the hybrid fins comprises a dielectric fin and a dielectric structure over the dielectric fin;forming a gate structure over the semiconductor fins and over the hybrid fins;removing first portions of the patterned mask layer, first portions of the epitaxial layers, and first portions of the dielectric structures that are disposed beyond sidewalls of the gate structure without substantially removing the dielectric fins;forming an interlayer dielectric (ILD) layer over the dielectric fins and around the gate structure;removing a gate ...

SEMICONDUCTOR DEVICE STRUCTURE WITH HARD MASK LAYER OVER FIN STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure. 1. A semiconductor device structure , comprising:a fin structure formed over a substrate;a hard mask layer formed over the fin structure;a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer; anda source/drain (S/D) structure formed adjacent to the gate structure.2. The semiconductor device structure as claimed in claim 1 , wherein the gate structure further comprises:a high-k dielectric layer surrounding the hard mask layer and the fin structure; anda work function layer surrounding the high-k dielectric layer, wherein the hard mask layer and the fin structure are separated by the high-k dielectric layer and the work function layer.3. The semiconductor device structure as claimed in claim 1 , further comprising:a contact etch stop layer (CESL) formed over the S/D structure; andan inter-layer dielectric (ILD) structure formed over the CESL, wherein a sidewall of the hard mask layer is in direct contact with the CESL and the ILD structure.4. The semiconductor device structure as claimed in claim 1 , wherein sidewalls of the hard mask layer are substantially aligned with sidewalls of the fin structure.5. The semiconductor device structure as claimed in claim 1 , further comprising:an inner spacer formed between the gate structure and the S/D structure, wherein the inner spacer is formed along a sidewall of the portion of ...

Nanosheet CMOS Device and Method of Forming

A method of forming a semiconductor device includes providing a fin extruding from a substrate, the fin having first epitaxial layers alternating with second epitaxial layers, the first epitaxial layers including a first semiconductor material, the second epitaxial layers including a second semiconductor material different from the first semiconductor material; etching sidewalls of at least one of the second epitaxial layers in a channel region of the fin, such that a width of the at least one of the second epitaxial layers in the channel region after etching is smaller than a width of the first epitaxial layers contacting the at least one of the second epitaxial layers; and forming a gate stack over of the fin, the gate stack engaging both the first epitaxial layers and the second epitaxial layers. 1. A method of forming a semiconductor device , comprising:forming a first fin and a second fin, each of the first fin and the second fin having first epitaxial layers and second epitaxial layers, the first epitaxial layers and the second epitaxial layers being alternately arranged;forming a dielectric layer over the first fin and the second fin;exposing a channel region of the first fin;removing the second epitaxial layers in the channel region of the first fin;exposing a channel region of the second fin;recessing the second epitaxial layers between the adjacent first epitaxial layers in the channel region of the second fin;forming a first gate stack over the first fin, the first gate stack surrounding each of the first epitaxial layers in the channel region of the first fin; andforming a second gate stack over the second fin, the second gate stack extending along sidewalls of the first epitaxial layers and the second epitaxial layers in the channel region of the second fin, the second gate stack including a first metal layer, the first metal layer extending directly below at least one of the first epitaxial layers.2. The method of claim 1 , wherein the sidewalls of the ...

Isolation Structures

Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors. 1. A semiconductor structure , comprising:a first cell disposed over a first well doped with a first-type dopant, the first cell comprising a first plurality of transistors;a second cell disposed over the first well, the second cell comprising a second plurality of transistors; anda tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant, the tap cell being sandwiched between the first cell and the second cell.2. The semiconductor structure of claim 1 ,wherein the first cell comprises a first active region,wherein the second cell comprises a second active region,wherein the tap cell comprises a third active region,wherein the first active region, the second active region and the third active region are doped with the second-type dopant.3. The semiconductor structure of claim 2 , wherein the first-type dopant is n-type and the second-type dopant is p-type.4. The semiconductor structure of claim 2 , wherein the first-type dopant is p-type and the second-type dopant is n-type.5. The semiconductor structure of claim 1 , wherein the first well comprises a first shape that includes a base portion and at least one letter-shaped branch extending from the base portion.6. The semiconductor structure of claim 5 , wherein the second well comprises a second shape keyed to the first shape.7. The semiconductor structure of claim 5 , wherein each of the at least one letter-shaped branch is a T-shape portion.8 ...

Semiconductor Device Structure With Uniform Threshold Voltage Distribution And Method Of Forming The Same

An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure. 1. A method , comprising:forming a fin structure extending above a dielectric isolation structure disposed over a substrate;forming a semiconductor liner layer on exposed surfaces of the fin structure;forming a first capping layer over the dielectric isolation structure, the first capping layer laterally surrounding a bottom portion of the semiconductor liner layer, the bottom portion of the semiconductor liner layer laterally surrounding a bottom portion of the fin structure;forming a second capping layer over an upper portion of the semiconductor liner layer, the upper portion of the semiconductor liner layer laterally surrounding an upper portion of the fin structure; andannealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon to drive a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in the bottom portion of the fin structure is different from a dopant concentration profile in the upper portion of the fin structure.2. The method of claim 1 , wherein the second capping layer is a material different from the first capping layer.3. The method of claim 1 , wherein the first capping ...

FinFET Device and Methods of Forming Same

A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer. 1. A method , comprising:forming a gate dielectric layer;depositing a metal oxide layer over the gate dielectric layer;annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer;forming a work function layer over the doped gate dielectric layer; andforming a gate electrode over the work function layer.2. The method according to claim 1 , wherein the metal oxide layer comprises lanthanum oxide claim 1 , and wherein lanthanum ions diffuse from the metal oxide layer to the gate dielectric layer.3. The method according to claim 1 , wherein annealing the gate dielectric layer and the metal oxide layer comprises raising the temperature of the gate dielectric layer and the metal oxide layer to a temperature of about 300° C. to about 550° C.4. The method of according to claim 3 , wherein the anneal process has a duration of about 1 minute to about 3 minutes.5. The method according to claim 1 , further comprising:forming a silicon cap over the work function layer; ANDperforming a backside cleaning process.6. The method according to claim 5 , further comprising annealing the silicon cap claim 5 , the annealing causing silicon ions to diffuse from the silicon cap into the work function layer.7. The method according to claim 1 , wherein the work function layer covers sidewalls of the doped gate dielectric layer along an edge of ...

Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon. 1. An interconnect structure comprising:a first conductive feature and a second conductive feature of a multilayer interconnect (MLI) feature disposed over a substrate, wherein the first conductive feature includes cobalt; and 'a first via barrier layer disposed over the first conductive feature,', 'a via of the MLI feature, wherein the via is disposed between the first conductive feature and the second conductive feature, such that the via physically couples the first conductive feature to the second conductive feature, wherein the via includes 'a second via barrier layer disposed over the first via barrier layer,', 'wherein the first via barrier layer includes titanium,'} 'a via bulk layer disposed over the second via barrier layer.', 'wherein the second via barrier layer includes titanium and nitrogen, and'}2. The interconnect structure of claim 1 , wherein the via bulk layer includes tungsten.3. The interconnect structure of claim 1 , wherein the via bulk layer includes cobalt.4. The interconnect structure of claim 1 , further comprising a capping layer disposed over the first conductive feature claim 1 , wherein the via extends ...

SELF-ALIGNED STRUCTURE FOR SEMICONDUCTOR DEVICES

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins. 1. A semiconductor structure comprising:a substrate;first and second fins protruding from the substrate;a spacing layer formed over the substrate and on opposing sidewalls of the first and second fins;an isolation fin structure formed over the spacing layer and between the opposing sidewalls of the first and second fins;a dielectric isolation fin abutting the first and second fins and the isolation fin structure; anda gate structure formed over the isolation fin structure and the first and second fins.2. The semiconductor structure of claim 1 , wherein top surfaces of the first and second fins and the isolation structure are coplanar.3. The semiconductor structure of claim 1 , further comprising an isolation structure between the spacing layer and the substrate.4. The semiconductor structure of claim 1 , wherein a first distance between the isolation fin structure and the first fin is substantially equal to a second distance between the isolation fin structure and the second fin.5. The semiconductor structure of claim 1 , further comprising first and second epitaxial source/drain structures on the first and second fins claim 1 , respectively.6. The semiconductor structure of claim 5 , wherein the isolation fin structure is formed between the first and second epitaxial ...

FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME

Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth. 1. A semiconductor device , comprising:a substrate;an insulating layer formed over the substrate;a plurality of fins formed vertically from a surface of the substrate, the plurality of fins extending through the insulating layer and above a top surface of the insulating layer;a gate structure formed over a portion of fins and over the top surface of the insulating layer;a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting a portion of the fin;a dielectric layer formed over the insulating layer;a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material; and the second contact trench contains the electrical conductive material;', 'the second contact trench is spaced away from the gate structure such that electrical conductive material in the second contact trench is free from contact with the gate structure; and', 'the ...

STRUCTURE AND METHOD FOR HIGH-K METAL GATE

A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer. 1. A method of forming a gate dielectric material , the method comprising:forming an interface material in a first region over a substrate; and forming a first dielectric layer comprising hafnium lanthanum oxide over the substrate; and', 'forming a second dielectric layer comprising lanthanum over the first dielectric layer., 'forming a high-K dielectric material in the first region over the interface material, wherein forming the high-K dielectric material comprises2. (canceled)3. The method of claim 2 , wherein the second dielectric layer comprises lanthanum aluminum oxide.4. The method of claim 1 , wherein forming the high-K dielectric material further comprises forming a third dielectric layer comprising hafnium oxide under the first dielectric layer claim 1 , wherein the first dielectric layer is between the third dielectric layer and the second dielectric layer.5. The method of claim 1 , wherein forming a fourth dielectric layer comprising an oxide of the substrate; and', 'forming a fifth dielectric layer comprising a hafnium doped material of the fourth dielectric layer, wherein the fifth dielectric layer is between the fourth dielectric layer and the high-K dielectric material., 'forming the interface material comprises6. The method of claim 5 , wherein the fourth dielectric layer comprises silicon oxide claim 5 , and the fifth dielectric layer comprises hafnium silicate.7. The method of claim 1 , further comprising forming a capping layer comprising titanium silicon nitride over the high-K dielectric material.8. The method of claim 7 , further comprising performing a first anneal process after forming the capping ...

Hybrid Nanostructure and Fin Structure Device

A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure 1. A method comprising:depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material;removing a portion of the semiconductor stack from the second region to form a trench;with an epitaxial growth process, filling the trench with the second type of semiconductor material;patterning the semiconductor stack within the first region to form a nanostructure stack;patterning the second type of semiconductor material within the second region to form a fin structure; andforming a gate structure over both the nanostructure stack and the fin structure.2. The method of claim 1 , further comprising claim 1 , before forming the gate structure claim 1 , removing the first type of semiconductor material from the nanostructure stack.3. The method of claim 2 , further comprising claim 2 , after removing the first type of semiconductor material from the nanostructure stack claim 2 , forming an interfacial layer all around remaining nanostructures of the nanostructure stack.4. The method of claim 3 , further comprising claim 3 , forming a dielectric layer on the ...

WEARABLE ELECTRONIC DEVICE AND A REFLECTED-CAPACITIVE TOUCH PANEL THEREOF

A reflected-capacitive touch panel of a wearable electronic device includes a center touch sensing portion composed of a plurality of mutual-capacitance sensors; a border touch sensing portion composed of a plurality of hybrid self-capacitance and mutual-capacitance sensors; and a predetermined bonding area into which channels of the center touch sensing portion and the border touch sensing portion are routed. 1. A reflected-capacitive touch panel of a wearable electronic device , comprising:a center touch sensing portion composed of a plurality of mutual-capacitance sensors;a border touch sensing portion surrounding the center touch sensing portion, the border touch sensing portion being composed of a plurality of hybrid self-capacitance and mutual-capacitance sensors; anda predetermined bonding area into which channels of the center touch sensing portion and the border touch sensing portion are routed.2. The touch panel of claim 1 , wherein the center touch sensing portion comprises:a plurality of center transmitting channel arranged in a first direction; anda plurality of center receiving channels arranged in a second direction that is distinct from the first direction;wherein driving signals are sent via the center transmitting channels and sensing signals are then received via the center receiving channels to detect mutual-capacitance of the center touch sensing portion.3. The touch panel of claim 2 , wherein the second direction is substantially perpendicular to the first direction.4. The touch panel of claim 2 , wherein the border touch sensing portion comprises:at least one border transmitting channel;wherein the center receiving channels are shared between the center touch sensing portion and the border touch sensing portion, driving signals are sent via the border transmitting channel and sensing signals are received via the center receiving channels to detect mutual-capacitance of the border touch sensing portion, and sensing signals are received via the ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer. 1. (canceled)2. A semiconductor device structure , comprising:a first gate electrode layer;a second gate electrode layer adjacent the first gate electrode layer;a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature has a first surface;a first conductive layer disposed on the first gate electrode layer, wherein the first conductive layer has a second surface;a second conductive layer disposed on the second gate electrode layer, wherein the second conductive layer has a third surface, wherein the first surface, the second surface, and the third surface are coplanar;a third conductive layer disposed over the first conductive layer;a fourth conductive layer disposed over the second conductive layer;a dielectric layer disposed on the first surface of the dielectric feature, wherein the dielectric layer is disposed between the third conductive layer and the fourth conductive layer;a first plurality of semiconductor layers, wherein ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material. 1. A semiconductor device structure , comprising:a semiconductor fin comprising a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface;a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin;a first source/drain epitaxial feature in contact with the semiconductor fin;a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer, wherein the first inner spacer is in contact with the first source/drain epitaxial feature, and wherein the first inner spacer comprises a first material; anda first spacer in contact with the first inner spacer, wherein the first spacer comprises a second material different from the first material.2. The semiconductor device structure of claim 1 , further comprising:a dielectric material in contact with the second surface of the semiconductor fin;a ...

Isolation Structure for for Isolating Epitaxially Grown Source/Drain Regions and Method of Fabrication Thereof

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact. 1. A semiconductor device , comprising:a first source/drain structure disposed over a substrate;a second source/drain structure disposed over the substrate;an isolation structure disposed between the first source/drain structure and the second source/drain structure, wherein the first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear, and wherein the second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear;a first source/drain contact that surrounds the first source/drain structure in multiple directions, wherein a top surface of the first source/drain structure is more elevated vertically than a bottom surface of the first source/drain contact; anda second source/drain contact that surrounds the second source/drain structure in multiple directions, wherein a top surface of the second source/drain structure is more elevated vertically than a bottom surface of the second source/drain contact, and wherein the isolation structure is disposed between the first source/drain contact and the second source/drain contact.2. The ...

SEMICONDUCTOR DEVICE GATE STRUCTURE AND METHOD OF FABRICATING THEREOF

A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer. 1. A method of forming a gate structure of a semiconductor device , comprising:forming a dummy gate structure on a substrate;removing the dummy gate structure to form an opening;disposing a high-k dielectric layer over a substrate in the opening;forming a dummy metal layer over the high-k dielectric layer in the opening, wherein the dummy metal layer includes fluorine and a metal;driving fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer;forming at least one work function layer over the passivated high-k dielectric layer; andforming a fill metal layer over the at least one work function layer.2. The method of claim 1 , further comprising:forming a metal nitride layer over the high-k dielectric layer underlying the dummy metal layer.3. The method of claim 2 , further comprising:prior to forming the metal nitride layer, forming another metal nitride layer over the high-k dielectric layer.4. The method of claim 1 , wherein the metal is aluminum claim 1 , titanium or tantalum.5506. The method of claim 1 , wherein the forming the dummy metal layer [] includes performing an atomic layer deposition (ALD) process with precursors providing the fluorine and the metal.6. The method of claim 1 , further comprising removing the dummy metal layer after driving the fluorine.7602. The method of ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin. 1. A semiconductor device , comprising:a substrate comprising plural semiconductor fins;a first dielectric fin disposed over the substrate and between the semiconductor fins; anda second dielectric fin disposed over the substrate and between the semiconductor fins, wherein the first dielectric fin has a first dielectric constant that is higher than a second dielectric constant of the second dielectric fin.2. The semiconductor device of claim 1 , wherein the first dielectric fin has a first width that is smaller than a second width of the second dielectric fin.3. The semiconductor device of claim 1 , further comprising a pair of first epitaxy structures disposed on two of the semiconductor fins and in contact with the first dielectric fin.4. The semiconductor device of claim 3 , wherein a top surface of the first dielectric fin is higher than a portion of each first epitaxy structure that is contact with the first dielectric fin.5. The semiconductor device of claim 1 , further comprising a pair of second epitaxy structures sandwiching the second dielectric fin.6. The semiconductor device of claim 5 , wherein each second epitaxy structure lands on immediately-adjacent two of the semiconductor fins.7. The semiconductor device of claim 5 , wherein a top surface of the second dielectric fin is lower than a portion of each second epitaxy ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate. 1. A semiconductor device , wherein the semiconductor device comprises:a semiconductor substrate;a source, a gate and a drain fabricated on one side of the semiconductor substrate;a via hole region reserved in the region of the source; andan etching stopping layer made in the via hole region; anda via hole under the etching stopping layer, which penetrates through the semiconductor substrate.2. The semiconductor according to claim 1 , wherein the area of the etching stopping layer is smaller than that of the deserved via hole region and there is a gap between the etching stopping layer and the source claim 1 , so that the source and the etching stopping layer can't contact with each other directly.3. The semiconductor according to claim 1 , wherein the etching stopping layer covers the reserved via hole region claim 1 , so that the source and the etching stopping layer could connect to each other directly.4. The semiconductor according to claim 1 , wherein the area of the etching stopping layer is larger than the cross-sectional area of the via hole near the side of the semiconductor substrate where the source is disposed.5. The semiconductor according to claim 1 , wherein the reserved via hole region penetrates at least one end of the source in a direction parallel to the gate to make sure that at least one end of the source is open.6. The semiconductor according to claim 5 , wherein the reserved via hole region penetrates the source in a direction parallel to the gate to make sure that two ends of the source are open.7. The semiconductor according to claim 1 , wherein the deserved via hole region is ...

Dopant Concentration Boost in Epitaxially Formed Material

A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer. 1. A semiconductor device comprising: a plurality of doped first material layers; and', 'one or more boosting layers comprising a second material, each one of the one or more boosting layers being between two layers of the plurality of doped first material layers, each of the one or more boosting layers being thinner than the each of the plurality of doped first material layers,, 'a doped epitaxy embedded in a substrate, the doped epitaxy comprisingwherein a gradient of dopant concentration is formed within the doped epitaxy from layer to layer.2. The semiconductor device of claim 1 , wherein the plurality of doped first material layers each comprises an n-type dopant and silicon claim 1 , and wherein the second material comprises silicon claim 1 , silicon carbon claim 1 , or carbon.3. The semiconductor device of claim 1 , wherein the plurality of doped first material layers each comprises a p-type dopant and silicon germanium claim 1 , and wherein the second material comprises silicon germanium claim 1 , silicon germanium carbon claim 1 , or carbon.4. The semiconductor device of claim 1 , further comprising:a gate stack formed over a channel region of a transistor; anda source/drain feature on either side of the gate stack wherein the source/drain feature ...

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME

A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap. 1. A method for forming a fin field effect transistor (FinFET) device structure , comprising:forming a fin structure over a substrate;forming a gate structure across the fin structure;forming a first spacer over a sidewall of the gate structure;forming a second spacer over the first spacer;etching the second spacer to form a gap; andforming a mask layer over the gate structure and the first spacer after the gap is formed, wherein the mask layer extends into the gap such that the mask layer and the fin structure are separated by an air gap in the gap.2. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:recessing the gate structure before the gap is formed so that a top surface of the first spacer is higher than a top surface of the gate structure.3. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein an interface between the mask layer and the air gap is between a top surface of the gate structure and a top surface of the first spacer.4. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:forming a source/drain (S/D) structure in the fin ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer. 1. A method for forming a semiconductor structure , comprising:forming a first fin structure with a first composition and a second fin structure with a second composition over a substrate ;oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer;removing the second oxide layer formed on the second fin structure;oxidizing the second fin structure to form a third oxide layer over the second fin structure; andforming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.2. The method for forming the semiconductor structure as claimed in claim 1 , wherein:the first fin structure is made of Si and the second fin structure is made of SiGe, or{'sub': x', 'y, 'the first fin structure is made of SiGeand the second fin structure is made of SiGe, wherein x Подробнее

FinFET Structure with Controlled Air Gaps

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature. 1. An integrated circuit (IC) structure , comprising:first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; anda contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.2. The IC structure of claim 1 , wherein the contact feature includes a titanium nitride layer; and a cobalt plug being surrounded by the titanium nitride layer.3. The IC structure of claim 1 , wherein the contact feature includes a bulk portion and a tip portion underlying the bulk portion and extending from the bulk portion claim 1 , wherein the bulk portion has a first width and the tip portion has a second width less than the first width.4. The IC structure of claim 3 , whereinthe bulk portion of the contact feature is directly landing on the first fin and the second fin; andthe tip portion is distanced away from the first and second fins and is disposed between the first and second fins.5. The IC structure of claim 4 , wherein the bulk portion of the contact ...

ISOLATION WITH MULTI-STEP STRUCTURE

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion. 1. A semiconductor device structure , comprising:a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate; andan isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure; a first portion protruding above a top surface of the isolation structure;', 'a second portion in direct contact with a bottom surface of the first portion, so that an interface is formed between the first portion and the second portion; and', 'a third portion extending from a bottom of the second portion, wherein a top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion., 'wherein the first fin structure and the second fin structure each comprise2. The semiconductor device structure as claimed in claim 1 , wherein the interface is substantially level with a top surface of the isolation structure.3. The semiconductor device structure as claimed in claim 1 , wherein the first fin structure is formed in a first well region of the semiconductor substrate and the second fin structure is formed in a second well region of the semiconductor substrate claim 1 , and wherein ...

FULLY STRAINED CHANNEL

The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF) and ammonia (NH) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof. 1. A method comprising:providing a doped region on a top portion of a substrate;growing a first epitaxial layer on the doped region;forming a well in the first epitaxial layer that is aligned to the doped region, wherein the well comprises a bottom surface of the first epitaxial layer; exposing the well to a plasma; and', 'performing an anneal; and, 'performing one or more surface pre-clean treatment cycles, wherein each surface pre-clean treatment cycle comprises performing a prebake at a first temperature;', 'forming a seed layer on the bottom surface of the first epitaxial layer at a second temperature; and', 'forming the second epitaxial layer on the seed layer at a third temperature to fill the well., 'forming a second epitaxial layer in the well, wherein forming the second epitaxial layer comprises2. The method of claim 1 , further comprising:disposing a photoresist over the second epitaxial layer;forming at least two openings in the photoresist to expose at least two respective portions of the second epitaxial layer; and etching through the at least two openings in the photoresist to remove the second epitaxial layer, the seed layer, the first epitaxial layer, and a portion of the doped region; and', 'forming a dielectric layer around the fin., 'forming a fin, wherein forming the fin comprises3. The method of claim 2 , wherein the fin comprises a bottom section with the doped region claim ...

Contact Plugs and Methods Forming Same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate. 1. An integrated circuit device comprising:a first Inter-Layer Dielectric (ILD);a first gate spacer in the first ILD;a gate dielectric between opposite portions of the first gate spacer;a metal gate over the gate dielectric, wherein a top surface of the metal gate, a top end of the first gate spacer, and a top surface of the first ILD are in contact with a bottom surface of a same dielectric layer;a second ILD over the first ILD;a source/drain region adjacent to the metal gate;a source/drain contact plug over and electrically coupling to the source/drain region, wherein the source/drain contact plug penetrates through both the first ILD and the second ILD; anda contact spacer encircling the source/drain contact plug.2. The integrated circuit device of claim 1 , wherein the contact spacer is formed of a high-k dielectric material.3. The integrated circuit device of claim 2 , wherein the high-k dielectric material comprises AlOor HfO.4. The integrated circuit device of claim 2 , wherein the high-k dielectric material comprises SiOCN or SiN.5. The integrated circuit device of claim 1 , wherein the second ILD is in contact with the first ILD claim 1 , and the integrated circuit device further comprises a gate contact plug ...

STRUCTURE OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES

Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region. 1. A semiconductor device , comprising:a substrate;a gate structure over the substrate;a first recess and a second recess in the substrate and at opposite sides of the gate structure; a first doped region partially filling in the first recess;', 'a second doped region over the first doped region; and', 'a third doped region over the second doped region,', 'wherein the second doped region contains more dopants than the first doped region or the third doped region; and, 'two source/drain structures over the first recess and the second recess respectively, wherein at least one of the source/drain structures comprisesa liner layer between the first doped region and a sidewall of the first recess.2. The semiconductor device as claimed in claim 1 , further comprising:a metal-semiconductor compound layer over the third doped region, wherein the second doped region is spaced apart from the metal-semiconductor compound layer by the third doped region.3. The semiconductor device as claimed in claim 1 , wherein each of the first doped region claim 1 , the second doped region and the third doped region is made of SiP claim 1 , SiAs claim 1 , SiCP claim 1 , SiCAs claim 1 , or a combination thereof.4. The semiconductor device as claimed in claim 1 , wherein the second doped region is in direct contact with the ...

Image processing method, apparatus, and storage medium

The present disclosure discloses an image processing method, apparatus, and a non-transitory computer readable medium. The method can includes: acquiring a three-dimensional (3D) model and original texture images of an object, wherein the original texture images are acquired by an imaging device; determining a mapping relationship between the 3D model and the original texture images of the object; determining, among the original texture images, a subset of texture images associated with a first perspective of the imaging device; splicing the subset of texture images into a spliced texture image corresponding to the first perspective; and mapping the spliced texture image to the 3D model according to the mapping relationship.

Point Cloud Meshing Method, Apparatus, Device and Computer Storage Media

A method, an apparatus, a device and a computer storage media for point cloud meshing are provided. The method includes performing a mesh reconstruction on point cloud data corresponding to a target object to obtain a reconstruction model for characterizing a surface contour of the target object; performing image registration on the reconstruction model with respect to a standard model corresponding to the target object; determining a mesh portion in the registered reconstruction model that does not overlap with the standard model; and removing the determined mesh portion from the registered reconstruction model to obtain a resulting reconstruction model of the target object. The point cloud meshing method repairs a hole structure of an object surface without the need of post-editing manually, and thus is able to improve the efficiency of repairing the hole structure of the object surface.

FinFET Device and Methods of Forming Same

A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer. 1. A device comprising:a first fin protruding from a substrate;a lanthanum-doped gate dielectric layer over the first fin, wherein the lanthanum-doped gate dielectric layer comprises a concentration of lanthanum that is less than about 95 at %; anda gate electrode over the lanthanum-doped gate dielectric layer.2. The device of claim 1 , further comprising an interfacial layer over the first fin claim 1 , wherein the lanthanum-doped gate dielectric layer overlies the interfacial layer.3. The device of claim 1 , further comprising a work function layer over the lanthanum-doped gate dielectric layer claim 1 , wherein the gate electrode overlies the work function layer.4. The device of claim 3 , wherein the work function layer covers a sidewall of the lanthanum-doped gate dielectric layer.5. The device of claim 3 , wherein the work function layer is doped with silicon.6. The device of claim 5 , wherein the work function layer is further doped with nitrogen.7. The device of claim 1 , further comprising:a second fin protruding from the substrate; anda second gate dielectric layer over the second fin, wherein the second gate dielectric layer has a lower concentration of lanthanum than the lanthanum-doped gate dielectric layer.8. A device comprising:a first fin and a second fin protruding from a substrate;a first gate dielectric layer extending along sidewalls and a top surface of the first fin; anda second gate dielectric layer extending along ...

ISOLATION WITH MULTI-STEP STRUCTURE FOR FINFET DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion. 1. A semiconductor device structure , comprising:a semiconductor substrate comprising a first well region of a first conductivity type and a second well region of a second conductivity type that is the opposite of the first conductivity type adjacent to the first well region;a first fin structure protruding from the semiconductor substrate and formed in the first well region;a second fin structure protruding from the semiconductor substrate and formed in the second well region and adjacent to the first fin structure; and a first isolation portion formed between the first fin structure and the second fin structure; and', 'a second isolation portion extending from a bottom surface of the first isolation portion, wherein the second isolation portion has a top width that is narrower than a bottom width of the first isolation portion., 'a first multi-step isolation structure, comprising2. The semiconductor device structure as claimed in claim 1 , wherein a well interface is formed between the first well region and the second well region claim 1 , and the second isolation portion is directly above the well interface.3. The semiconductor ...

PRESENTING INFORMATION ON SIMILAR OBJECTS RELATIVE TO A TARGET OBJECT FROM A PLURALITY OF VIDEO FRAMES

Presenting information on similar objects relative to a target object is disclosed, including: obtaining a plurality of video frames; determining a target object in the plurality of video frames using a tracking recognition technique; determining time slice information corresponding to the target object; using the time slice information corresponding to the target object to determine one or more similar objects relative to the target object; receiving an indication to present information on the one or more similar objects relative to the target object; and outputting the information on the one or more similar objects relative to the target object. 1. A system , comprising: obtain a plurality of video frames;', 'determine a target object in the plurality of video frames using a tracking recognition technique;', 'determine time slice information corresponding to the target object;', 'use the time slice information corresponding to the target object to determine one or more similar objects relative to the target object;', 'receive an indication to present information on the one or more similar objects relative to the target object; and', 'output the information on the one or more similar objects relative to the target object; and, 'one or more processors configured toone or more memories coupled to the one or more processors and configured to provide the one or more processors with instructions.2. The system of claim 1 , wherein to use the time slice information corresponding to the target object to determine the one or more similar objects relative to the target object comprises to:determine a set of video frames that includes the target object based at least in part on the time slice information corresponding to the target object; anduse the set of video frames to search in a similar object library for the one or more similar objects relative to the target object.3. The system of claim 2 , wherein to use the set of video frames to search in the similar object library ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole. 1. A method , comprising:forming a source/drain region on a substrate;forming a dielectric layer over the source/drain region;forming a contact hole in the dielectric layer;forming a contact hole liner in the contact hole;removing a first portion of the contact hole liner to expose a sidewall of the contact hole;etching the exposed sidewall of the contact hole to laterally expand the contact hole; andforming a contact plug in the laterally expanded contact hole.2. The method of claim 1 , wherein after the removing the first portion of the contact hole liner claim 1 , a second portion of the contact hole liner in a position lower than the exposed sidewall of the contact hole remains in the contact hole.3. The method of claim 2 , wherein after the etching the exposed sidewall of the contact hole to laterally expand the contact hole claim 2 , the second portion of the contact hole liner remains in the contact hole.4. The method of claim 3 , wherein the laterally expanded contact hole has an upper sidewall non-parallel with the second portion of the contact hole liner.5. The method of claim 3 , wherein the second portion of the contact hole liner has a steeper slope than an upper sidewall of the laterally expanded contact hole.6. The method of claim 1 , wherein after the etching the exposed sidewall of the contact hole claim 1 , a recess is formed in the source/drain region.7. The method of claim 6 , wherein the contact plug fills the recess in the source/drain region.8. The method of claim 1 , wherein the ...

Data Processing Method, Apparatus, System and Storage Media

A data processing method includes determining feature points in first point cloud data and feature points in second point cloud data, the first point cloud data and the second point cloud data being used for representing different parts of a same object; performing feature matching between the first point cloud data and the second point cloud data to determine feature points satisfying feature matching condition(s) between the first point cloud data and the second point cloud data, and form a plurality of feature point pairs; determining a transformation matrix in which spatial distances between feature points in one or more feature point pairs of the plurality of feature point pairs conform to a proximity condition; and performing coordinate transformation on the one or more feature point pairs using the transformation matrix to register the first point cloud data with the second point cloud data. 1. A method implemented by one or more computing devices , the method comprising:determining feature points in first point cloud data and feature points in second point cloud data, the first point cloud data and the second point cloud data being used for representing different parts of a same object;performing feature matching between the first point cloud data and the second point cloud data to determine feature points that satisfy a feature matching condition between the first point cloud data and the second point cloud data, and form a plurality of feature point pairs;for one or more feature point pairs of the plurality of feature point pairs, determining a transformation matrix in which a spatial distance between feature points in the feature point pairs conform to a proximity condition; andperforming coordinate transformation on the one or more feature point pairs of the plurality of feature point pairs using the transformation matrix to register the first point cloud data with the second point cloud data.2. The method of claim 1 , wherein determining the feature ...

MULTI-GATE DEVICE AND RELATED METHODS

A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer. 1. A method of fabricating a semiconductor device , comprising:forming a first dielectric-filled trench within a first part of a dummy gate, wherein the first dielectric-filled trench covers a first part of a first hybrid fin;forming a metal-filled trench within a second part of the dummy gate; andetching-back a metal layer within the metal-filled trench, wherein a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the first hybrid fin after the etching-back the metal layer.2. The method of claim 1 , wherein the first dielectric-filled trench covers a second hybrid fin adjacent to the first hybrid fin.3. The method of claim 1 , further comprising:prior to forming the first dielectric-filled trench within the first part of the dummy gate, forming a second dielectric-filled trench within a third part of the dummy gate, wherein the second dielectric-filled trench covers a second part of the first hybrid fin, and wherein the third part of the dummy gate interposes the first part of the dummy gate and the second part of the dummy gate.4. The method of claim 3 , further ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin. 1. A semiconductor device , comprising:a substrate;a first dielectric fin and a second dielectric fin disposed over the substrate;a semiconductor fin disposed over the substrate, wherein the semiconductor fin is between the first dielectric fin and the second dielectric fin;an epitaxy structure covering at least two surfaces of the semiconductor fin, wherein the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin; anda metal gate structure crossing the first dielectric fin, the second dielectric fin, and the semiconductor fin.2. The semiconductor device of claim 1 , further comprising a contact etch stop layer in contact with a top surface of the semiconductor fin and a top surface of the second dielectric fin.3. The semiconductor device of claim 2 , wherein a first sidewall of the epitaxy structure is in contact with the first dielectric fin claim 2 , and the contact etch stop layer in contact with a second sidewall of the epitaxy structure opposite to the first sidewall.4. The semiconductor device of claim 1 , further comprising a contact etch stop layer and an interlayer dielectric layer claim 1 , wherein the epitaxy structure is separated from the second dielectric fin by the contact etch stop layer and ...

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE

A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure. 1. A fin field effect transistor (FinFET) device structure , comprising:a fin structure extending above a substrate, wherein the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials;an isolation structure formed on the substrate, wherein an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure; anda liner layer formed on sidewalls of the second portion of the fin structure, wherein the liner layer is made of nitrogen-containing material, carbon-containing material or combinations thereof.2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the liner layer has a young's modulus in a range from about 200 GPa to about 1000 GPa.3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the liner layer is made of silicon nitride claim 1 , silicon carbide (SiC) claim 1 , silicon oxynitride (SiON) claim 1 , silicon oxycarbide (SiOC) or combinations thereof.4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the first portion of the fin structure is made of silicon germanium (SiGe) claim 1 , and the second ...

METHOD, SYSTEM AND APPARATUS FOR AUTONOMOUS MESSAGE GENERATION

A method is provided in an application server, comprising: storing a plurality of primary class definitions in a memory, each primary class definition including a primary class identifier and a plurality of primary class attributes; storing a plurality of secondary class definitions in a memory, each secondary class definition including a secondary class identifier and a plurality of secondary class attributes; receiving a message from a client computing device via a network; based on the content of the message, selecting one of the primary class identifiers, and one of the secondary class identifiers; selecting primary response data corresponding to the selected primary class identifier; selecting secondary response data corresponding to the selected secondary class identifier; generating a response message by combining the primary response data and the secondary response data; and transmitting the response message to the client computing device. 1. A method in an application server , comprising:storing a plurality of primary class definitions in a memory, each primary class definition including a primary class identifier and a plurality of primary class attributes;storing a plurality of secondary class definitions in a memory, each secondary class definition including a secondary class identifier and a plurality of secondary class attributes;receiving a message from a client computing device via a network;based on the content of the message, selecting one of the primary class identifiers, and one of the secondary class identifiers;selecting primary response data corresponding to the selected primary class identifier;selecting secondary response data corresponding to the selected secondary class identifier;generating a response message by combining the primary response data and the secondary response data; andtransmitting the response message to the client computing device.2. The method of claim 1 , wherein generating the response message comprises appending the ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion. 1. A semiconductor device , comprising:a substrate comprising at least two fins;one hybrid fin disposed between the at least two fins;a gate covering portions of the at least two fins and the hybrid fin; anda dielectric structure landing on the hybrid fin to divide the gate into two segments, wherein the two segments are electrically isolated by the dielectric structure and the hybrid fin, wherein the hybrid fin comprises:a first portion, disposed between the two segments of the gate; anda second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.2. The semiconductor device of claim 1 , further comprising:an isolation region disposed on the substrate between the at least two fins, wherein a top surface of the isolation region is lower than top surfaces of the at least two fins; andsource/drain (S/D) regions disposed on the at least two fins at opposite sides of the gate.3. The semiconductor device of claim 2 , wherein the second portion electrically isolates two adjacent S/D regions from each other and the top surface of the second portion is lower than top surfaces of the S/D regions.4. The semiconductor device of claim 2 , wherein the hybrid fin comprises:a first material, partially ...

Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon. 1. A device comprising:a gate structure disposed over a substrate, wherein the gate structure is disposed between a first source/drain feature and a second source/drain feature;a cobalt-containing first interconnect feature disposed directly on the first source/drain feature, wherein the cobalt-containing first interconnect feature is disposed in a first interlayer dielectric layer and a first contact etch stop layer; a titanium-containing layer,', 'a titanium-and-nitrogen-containing layer disposed directly on the titanium-containing layer, wherein the titanium-containing layer is disposed between the second interlayer dielectric layer and the titanium-and-nitrogen-containing layer, and wherein a first thickness of the titanium-containing layer is different than a second thickness of the titanium-and-nitrogen-containing layer, and', 'a tungsten-containing layer disposed directly on the titanium-and-nitrogen-containing layer; and, 'a second interconnect feature disposed directly on the cobalt-containing first interconnect feature, wherein the second interconnect feature is disposed in a second interlayer dielectric layer and a second ...

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures. 1. A method for forming a fin field effect transistor (FinFET) device structure , comprising:forming a first fin structure in a core region of a substrate and a second fin structure in an input/output (I/O) region of the substrate with a fin top layer and a hard mask layer over the first fin structure and the second fin structure;forming a dummy oxide layer across the first fin structure and the second fin structure;forming a dummy gate structure over the dummy oxide layer across the first fin structure and the second fin structure;forming spacers on opposite sides of the dummy gate structure;removing the dummy gate structure over the first fin structure and the second fin structure;removing the dummy oxide layer and trimming the first fin structure and the second fin structure;forming a first oxide layer across the first fin structure and a second oxide layer across the second fin structure; andforming a first gate structure over the first oxide layer across the first fin structure and a second gate structure over the second oxide layer across the second fin structure.2. The method for forming the fin field effect transistor device ...

METHOD FOR IMPROVING TOUCH PERFORMANCE OF CAPACITIVE TOUCH SCREEN WITH NON-RECTANGULAR SHAPE

A method for improving touch performance of a capacitive touch screen with a non-rectangular shape is provided. The capacitive touch screen includes plural complete cells and at least one incomplete cell for sensing. The method includes: determining whether an active area of the incomplete cell is different from an active area of each of the complete cells; and performing a mutual capacitance compensation on the incomplete cell to compensate a mutual capacitance of the incomplete cell when the active area of the incomplete cell is different from the active area of each of the complete cells. 1. A method for improving touch performance of a capacitive touch screen with a non-rectangular shape , wherein the capacitive touch screen comprises a plurality of complete cells and at least one incomplete cell for sensing , the method comprising:determining whether an active area of the incomplete cell is different from an active area of each of the complete cells; andperforming a mutual capacitance compensation on the incomplete cell to compensate a mutual capacitance of the incomplete cell when the active area of the incomplete cell is different from the active area of each of the complete cells; determining whether the incomplete cell has a residual area; and', 'modifying a layout pattern of the incomplete cell of the capacitive touch screen to compensate the mutual capacitance of the incomplete cell when the incomplete cell has the residual area., 'wherein the capacitive touch screen comprises a plurality of receiver (RX) electrodes and a plurality of transmit (TX) electrodes; wherein an intersection of one of the RX electrodes and one of the TX electrodes corresponds to one of the complete cells or the incomplete cell; wherein performing the mutual capacitance compensation comprises2. (canceled)3. The method of claim 1 , wherein the mutual capacitance compensation is performed only when the active area of the incomplete cell is smaller than or equal to a half of the ...

TOUCH SENSING DEVICE

A touch sensing device including a plurality of first sensing electrode sets, a plurality of first conductive lines, and a plurality of sensing sets is provided. The first sensing electrode sets are arranged in an array. The first conductive lines are respectively connected to the first sensing electrode sets. The sensing sets are capacitively coupled to the first sensing electrode sets. Each of the first sensing electrode sets is capacitively coupled to at least two of the sensing sets. One of each of the first sensing electrode sets and each of the sensing sets is a signal transmitter, and the other of each of the first sensing electrode sets and each of the sensing sets is a signal receiver. 1. A touch sensing device comprising:a plurality of first sensing electrode sets arranged in an array;a plurality of first conductive lines respectively connected to the first sensing electrode sets; anda plurality of sensing sets capacitively coupled to the first sensing electrode sets, wherein each of the first sensing electrode sets is capacitively coupled to at least two of the sensing sets, one of each of the first sensing electrode sets and each of the sensing sets is a signal transmitter, and the other of each of the first sensing electrode sets and each of the sensing sets is a signal receiver.2. The touch sensing device according to claim 1 , wherein each of the first sensing electrode sets comprises a plurality of first sensing electrodes respectively capacitively coupled to the at least two of the sensing sets.3. The touch sensing device according to claim 2 , wherein each of the sensing sets comprises:a second conductive line; anda plurality of second sensing electrodes connected to the second conductive line, wherein the first sensing electrodes of each of the first sensing electrode sets are respectively capacitively coupled to some of the second sensing electrodes belonging to different sensing sets.4. The touch sensing device according to claim 3 , wherein the ...

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE

A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure. 1. A fin field effect transistor (FinFET) device structure , comprising:a fin structure extending above a substrate, wherein the fin structure comprises a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration; anda gate structure formed on the channel region of the fin structure, wherein the top surface and sidewall surfaces of the channel region are wrapped by the gate structure.2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gradient germanium (Ge) concentration is gradually increased from a bottom surface of the channel region to a top surface of the channel region.3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gradient germanium (Ge) concentration is gradually increased from about 10 atomic % to about 35 atomic %.4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the fin structure further comprises a well region below the channel region.5. The fin field effect transistor (FinFET) device structure as claimed in claim 4 , further comprises:an isolation structure formed on the substrate, wherein an interface between the channel region and the well region of the fin structure is above a top surface of the isolation structure.6. The fin field effect transistor (FinFET) device structure as claimed in claim 4 , further comprising:a liner layer formed on ...

SEMICONDUCTOR DEVICE GATE STRUCTURE AND METHOD OF FABRICATING THEREOF

A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer. 1. A method of forming a gate structure of a semiconductor device , comprising:depositing a high-k dielectric layer over a substrate;forming a dummy metal layer over the high-k dielectric layer, wherein the dummy metal layer includes fluorine;driving fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer;removing the dummy metal layer after the driving the fluorine;forming at least one work function layer over the passivated high-k dielectric layer; andforming a fill metal layer over the at least one work function layer.2. The method of claim 1 , further comprising:forming a metal nitride layer over the high-k dielectric layer underlying the dummy metal layer.3. The method of claim 2 , further comprising:prior to forming the metal nitride layer, forming another metal nitride layer over the high-k dielectric.4. The method of claim 1 , further comprising:forming a gate contact over the fill metal layer.5. The method of claim 1 , wherein the forming the dummy metal layer further includes forming a blocking layer over the dummy metal layer; and wherein the removing the dummy metal layer includes removing the blocking layer.6. The method of claim 5 , wherein the forming the blocking layer includes depositing TiN.7. The method of claim 1 , wherein the forming the dummy metal layer includes ...

FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH SEMICONDUCTOR NANOWIRE

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire. 1. A semiconductor device structure , comprising:a substrate;a first source portion and a first drain portion over the substrate;a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion, wherein the first semiconductor nanowire comprises a first portion over the substrate and a second portion over the first portion, wherein the first portion has a first width, and the second portion has a second width, wherein the second width is less than the first width; anda first gate structure over the second portion of the first semiconductor nanowire, wherein the first semiconductor nanowire has a first lattice distance, the substrate has a second lattice distance, and the first lattice distance of the first semiconductor nanowire is greater than the second lattice distance of the substrate.2. The semiconductor device structure as claimed in claim 1 , wherein the first portion has a first aspect ratio claim 1 , and the second portion has a second aspect ratio claim 1 , wherein the first aspect ratio is greater than the second aspect ratio.3. The semiconductor device structure as claimed in claim 1 , wherein the first portion has a greater height than the first width.4. The semiconductor device structure as claimed ...

METHOD FOR FORMING SIDEWALL SPACERS AND SEMICONDUCTOR DEVICES FABRICATED THEREOF

Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers. 1. A semiconductor device , comprising:a source/drain feature;first and second channel layers in contact with the source/drain feature; anda sidewall spacer in contact with the source/drain feature, wherein the sidewall spacer includes a first fin sidewall spacer portion, a second fin sidewall spacer portion, and a gate sidewall spacer portion connecting the first and second fin sidewall spacer portions, the first fin sidewall spacer portion contacts first sidewalls of the first and second channel layers, and the second sidewall fin portion contacts second sidewalls of the first and second channel layers.2. The semiconductor device of claim 1 , further comprising:an inner spacer in contact with the sidewall spacer.3. The semiconductor device of claim 2 , wherein the inner spacer includes a top surface claim 2 , a bottom surface opposing the top surface claim 2 , and first and second sidewalls connecting the top surface and the bottom surface claim 2 , the top surface is in contact with the first channel layer claim 2 , the bottom surface is in contact with the second channel layer claim 2 , the first sidewall is in contact with the first fin sidewall spacer portion claim 2 , and the second sidewall is in contact with the second fin sidewall spacer portion.4. The semiconductor device of claim 2 , wherein the inner spacer and the sidewall spacer include the same material.5. The semiconductor device of claim 2 , wherein the inner spacer and the sidewall spacer include different materials.6. The ...

METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) WITH A LINER LAYER

A method for forming a fin field effect transistor device structure includes forming a first fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the first fin structure. The method also includes forming a dummy oxide layer across the first fin structure. The method also includes forming a dummy gate structure over the dummy oxide layer across the first fin structure. The method also includes forming spacers on opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure over the first fin structure. The method also includes removing the dummy oxide layer and trimming the first fin structure. The method also includes forming a first oxide layer across the first fin structure. The method also includes forming a first gate structure over the first oxide layer across the first fin structure. 1. A method for forming a fin field effect transistor (FinFET) device structure , comprising:forming a first fin structure in an input/output (I/O) region of the substrate with a fin top layer and a hard mask layer over the first fin structure;forming a dummy oxide layer across the first fin structure;forming a dummy gate structure over the dummy oxide layer across the first fin structure;forming spacers on opposite sides of the dummy gate structure;removing the dummy gate structure over the first fin structure;removing the dummy oxide layer and trimming the first fin structure;forming a first oxide layer across the first fin structure; andforming a first gate structure over the first oxide layer across the first fin structure.2. The method for forming the fin field effect transistor device structure as claimed in claim 1 , further comprising:forming a second fin structure in a core region of the substrate;forming a fin top layer over the second fin structure;forming an isolation structure surrounding a base portion of the first fin structure and the second fin structure;forming a dummy ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height. 1. A semiconductor device structure , comprising:a plurality of semiconductor layers;a first source/drain epitaxial feature in contact with the plurality of semiconductor layers, wherein the first source/drain epitaxial feature comprises a bottom portion having substantially straight sidewalls;a spacer comprising a gate spacer portion and one or more source/drain spacer portions, wherein each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature; anda dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portions, wherein the dielectric feature has a second height substantially greater than the first height.2. The semiconductor device structure of claim 1 , further comprising a gate electrode layer surrounding at least a portion of each of the plurality of semiconductor layers.3. The semiconductor device structure ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate, at least one gate, and an insulating structure. The substrate includes at least one semiconductor fin. The gate is disposed on the semiconductor fin. The gate has at least one end sidewall. The insulating structure is disposed adjacent to the gate. The insulating structure has a sidewall facing the gate, and the end sidewall of the gate is in contact with a portion of the sidewall of the insulating structure while leaves another portion of the sidewall of the insulating structure uncovered. 1. A semiconductor device comprising:a substrate comprising at least one semiconductor fin;at least one gate disposed on the semiconductor fin, wherein the gate has at least one end sidewall; andan insulating structure disposed adjacent to the gate, wherein the insulating structure has a sidewall facing the gate, and the end sidewall of the gate is in contact with a portion of the sidewall of the insulating structure while leaves another portion of the sidewall of the insulating structure uncovered.2. The semiconductor device of claim 1 , wherein an extension direction of the insulating structure is in crossing with an extension direction of the gate.3. The semiconductor device of claim 1 , wherein the insulating structure is separated from the at least one semiconductor fin.4. The semiconductor device of claim 1 , further comprising at least one gate spacer disposed adjacent to the gate and the insulating structure claim 1 , wherein the at least one gate spacer is in contact with the portion of the sidewall of the insulating structure uncovered by the end sidewall of the gate.5. The semiconductor device of claim 4 , wherein at least a portion of the gate spacer is disposed on the insulating structure.6. The semiconductor device of claim 4 , wherein the insulating structure comprises:a first portion having the portion of the sidewall in contact with the end sidewall of the gate; anda second portion having the portion of the sidewall in ...

Sidewall Spacers for Self-Aligned Contacts

A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer. 1. A semiconductor device , comprising:a first gate of a transistor;a first sidewall spacer along a sidewall of the first gate;a first insulating layer in contact with the first sidewall spacer and having a top surface;a second sidewall spacer formed on the top surface of the insulating layer and over the first sidewall spacer, wherein a full width of the second sidewall spacer is equal to or greater than a full width of the first sidewall spacer.2. The semiconductor device of claim 1 , further comprising a second gate formed over the first gate claim 1 , wherein the second sidewall spacer is disposed along a sidewall of the second gate.3. The semiconductor device of claim 2 , wherein the second gate comprises tungsten.4. The semiconductor device of claim 2 , wherein the second gate has a thickness less than a height of the second sidewall spacer.5. The semiconductor device of claim 4 , wherein the thickness of the second gate is between 0 nm and 10 nm.6. The semiconductor device of claim 1 , further comprising a second insulating layer disposed over the first insulating layer claim 1 , wherein a thickness of the second insulating layer is greater than or equal to a height of the second sidewall spacer.7. The semiconductor device of claim 6 , wherein the first sidewall spacer and the second sidewall spacer each comprise a material that is different from a material of the first ...

Dopant Concentration Boost in Epitaxially Formed Material

A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer. 18-. (canceled)9. A method , comprising:forming a recess in a substrate, the recess corresponding to a source/drain feature;growing a first doped epitaxy layer comprising a first material in the recess;growing a boosting layer over the first doped epitaxy layer, the boosting layer comprising a second material different from the first material; andgrowing a second doped epitaxy layer comprising the first material over the boosting layer.10. The method of claim 9 , wherein the first doped epitaxy layer has a first crystalline structure claim 9 , the boosting layer has a second crystalline structure claim 9 , and the first and second crystalline structures are different.11. The method of claim 9 , wherein the recess is a first recess claim 9 , further comprising:forming a second recess in the substrate; andforming a gate stack between the first recess and the second recess.12. The method of claim 9 , wherein the second doped epitaxy layer protrudes from the recess about 0 nm to about 20 nm.13. The method of claim 9 , wherein the boosting layer comprises an epitaxy of silicon claim 9 , silicon germanium claim 9 , carbon claim 9 , or a combination thereof.14. The device of claim 9 , wherein a gradient of doping concentration occurs from one layer to a next layer ...

FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES

A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material. 1. A method for forming a semiconductor device , comprising:forming a gate stack to partially cover a semiconductor structure;forming a first semiconductor material over the semiconductor structure;forming a second semiconductor material over the first semiconductor material; andforming a third semiconductor material over the second semiconductor material, wherein the first semiconductor material and the third semiconductor material together surround the second semiconductor material, and the second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the first semiconductor material claim 1 , the second semiconductor material claim 1 , and the third semiconductor material are formed using one or more epitaxial growth processes.3. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising partially etching the semiconductor structure to form a recess in the semiconductor structure after the formation of the gate stack and before the formation of the first semiconductor material.4. The method for forming a ...

Gate Structure and Method

A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition. 1. A method of forming an integrated circuit structure , the method comprising:forming a plurality of fin active regions on a semiconductor substrate;forming a dummy gate stack on the fin active regions;forming an inter-layer dielectric (ILD) layer in gaps between the dummy gate stacks;removing the dummy gate stack to form a first trench in the ILD layer;filling the first trench by depositing a gate dielectric layer having a first dielectric material and depositing a conductive material layer on the gate dielectric layer, thereby forming a high-K metal gate stack;performing a first patterning process to the conductive material layer to form a second trench;filling the second trench with a second dielectric material being different from the first dielectric material in composition;performing a second patterning process to the conductive material layer to form a third trench; andfilling the third trench with a third dielectric material being different from the first and second dielectric material in composition.2. The method of claim 1 , whereinthe first dielectric material is a high-K dielectric material;the depositing of the gate dielectric layer further includes depositing an interfacial layer of silicon oxide on the high-K dielectric material layer; andthe depositing of the conductive material layer further includes ...

METHOD AND DEVICE FOR EXTRACTING DISTORTED STRAIGHT LINE FROM IMAGE

A method and a device for extracting a distorted straight line from an image. The method includes performing a line segment detection process on the image; for each line segment detected, finding adjacent line segments having a low non-collinear degree with a current line segment, so as to combine them together to obtain one or more line segment combinations; and extracting the distorted straight line according to the line segment combination. 1. A method for extracting a distorted straight line from an image , comprising:performing a line segment detection process on the image;for each line segment detected, finding adjacent line segments having a low non-collinear degree with a current line segment, so as to combine them together to obtain one or more line segment combinations; andextracting the distorted straight line according to the line segment combination.2. The method according to claim 1 , wherein before extracting:a refinement process for optimizing size of a gradient and smoothness is performed on the line segment combination.3. The method according to claim 2 , wherein the refinement process is performed by constructing and solving a balanced energy function for optimizing both of size of the gradient and smoothness.4. The method according to claim 2 , wherein the refinement process is performed when a discontinuity larger than a predetermined number of pixels is present in the line segment combination.5. The method according to claim 3 , wherein the refinement process is performed when a discontinuity larger than a predetermined number of pixels is present in the line segment combination.6. The method according to claim 1 , wherein finding adjacent line segments having a low non-collinear degree with a current line segment further comprises:defining an adjoining rectangular area along a slope direction of the current line segment; and the middle first, then both sides; and', 'from near to far., 'searching another line segment whose non-collinear degree ...

APPARATUS FOR AND METHOD OF PROCESSING DOCUMENT IMAGE

An apparatus for and a method of processing a document image are provided. The apparatus comprises: an estimation unit for estimating a brightness image from the document image; and a correction unit for correcting the brightness image by using brightness values of at least a part of edge pixels which lie on or in the adjacency of edges of the brightness image in parallel with x direction, wherein directions of neighboring two edges of the brightness image are set to be x, y directions respectively, and wherein compared with x direction, brightness values of pixels of the brightness image change relatively slightly or do not change along y direction; wherein the correction unit performs interpolation on a straight line extending along y direction by using the brightness values of the edge pixels on the straight line, thereby correcting brightness values of other pixels on the straight line. 1. An apparatus for processing a document image , comprising:an estimation unit to estimate a brightness image from the document image; anda correction unit to correct the brightness image by using brightness values of at least a part of edge pixels which lie one of on and in an adjacency of edges of the brightness image in parallel with an x direction, wherein directions of two neighboring edges of the brightness image are set to be x, y directions respectively, and wherein as compared with the x direction, brightness values of pixels of the brightness image change one of relatively slightly and do not change along the y direction;wherein the correction unit performs interpolation on a straight line extending along the y direction by using the brightness values of the edge pixels on the straight line to correct brightness values of other pixels on the straight line.2. The apparatus for processing a document image according to claim 1 , further comprising a modification unit to determine a position where a jump occurs in the brightness values of the edge pixels claim 1 , and to ...

SEMICONDUCTOR DEVICE INCLUDING A FINFET STRUCTURE AND METHOD FOR FABRICATING THE SAME

The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer. 118.-. (canceled)19. A semiconductor structure for forming a FinFET device comprising:a fin region extending from a semiconductor substrate, the fin region including at least a pair of fins, wherein the pair of fins are separated by a filled region filled with a first material, the first material has an etch rate that is higher than an etch rate of a material used to form at least one of the pair of fins, the first material is epitaxially grown to form a filled region, the fin region comprises a first set of surfaces and a second set of surfaces; anda source region and a drain region, the source region being adjacent to the first set of the surfaces of the fin region, and the drain region being adjacent to the second set of the surfaces of the fin region.20. The structure of claim 19 , wherein the first material comprises SiGe.21. The structure of claim 19 , further comprising an insulating material within the fin region claim 19 , the insulating material having a thickness greater than claim 19 , or equal to claim 19 , 1 nm and smaller than claim 19 , or equal to claim 19 , 100 nm.22. The structure of claim 21 , wherein the insulating material has high-etch selectivity relative to the first material.23. The structure of claim 19 , comprising a first insulating layer and a second insulating layer claim 19 , the first insulating layer being substantially parallel to the second ...

METHOD TO FORM A FULLY STRAINED CHANNEL REGION

The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth. 1. A method comprising:providing a first doped region on a top portion of a substrate, wherein the first doped region comprises a second doped top region;growing a first epitaxial layer on the second doped top region;forming a recess in the first epitaxial layer that is aligned to the second doped top region, wherein the forming the recess comprises etching the first epitaxial layer until the second doped top region is exposed; and forming a seed layer in the recess at a first temperature; and', 'forming the second epitaxial layer on the seed layer to fill the recess at a second temperature higher than the first temperature., 'forming a second epitaxial layer in the recess, wherein the forming the second epitaxial layer comprises2. The method of claim 1 , further comprising:disposing a photoresist over the second epitaxial layer;forming at least two openings in the photoresist to expose at least two respective portions of the second epitaxial layer; and etching through the at least two openings in the photoresist to remove the second epitaxial layer, the seed layer, the second doped top region of the first doped region, and a portion of the first doped region; and', 'forming an isolation layer between the fins., ' ...

Fully Strained Channel

The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF) and ammonia (NH) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof. 1. A structure , comprising: an n-type doped region formed on a top portion of the substrate;', 'a silicon epitaxial layer on the n-type doped region; and', 'an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer;, 'a fin formed on a substrate, wherein the fin comprisesa liner surrounding the n-type doped region of the fin; anda dielectric surrounding the liner.2. The structure of claim 1 , wherein the epitaxial stack comprises:a first sub-layer with a first germanium concentration greater than zero and less than 5 atomic %; anda second sub-layer with a second germanium concentration ranging from 20 atomic % to 40 atomic %.3. The structure of claim 1 , wherein the silicon epitaxial layer has a thickness between 50 Å and 100 Å.4. A method claim 1 , comprising:forming a first doped region and a second doped region in a top portion of a semiconductor substrate, wherein the first and second doped regions comprise different types of dopants and are formed adjacent to one other;growing a silicon epitaxial layer on the first and second doped regions;etching the silicon epitaxial layer to form a well within the silicon epitaxial layer, wherein the well is aligned to the first doped region;treating surfaces of the well with a plasma to remove contaminants from the etching;performing, at a ...

COMPOSITIONS AND METHODS FOR TUMOR IMAGING AND TARGETING BY A CLASS OF ORGANIC HEPTAMETHINE CYANINE DYES THAT POSSESS DUAL NUCLEAR AND NEAR-INFRARED PROPERTIES

The present invention provides for heptamethine cyanine dyes that possess both nuclear and near-infrared imaging capabilities. These dyes can be used for imaging, targeting and detecting tumors in patients. 9. A process of manufacturing the Dual Nuclear/NIR Agent of claim 1 , comprising:{'sub': 3', '4', '2', 'm', 'A', 'A', '3', '2', '3, 'providing a compound of Formula I or Formula II, wherein Rand Rare each independently in each instance, (CH)R, where m is an integer from 1 to 12, Ris independently CH, NH, SH, COOH, SOH, OH, halogen and CO—N-hydroxysuccinimide;'}reacting the compound with N-hydroxysuccimide to form a monocuccinimide ester of the compound;{'sup': 'ω', 'reacting monocuccinimide ester of the compound with N-(t-butoxyhydrazinonicotinyl)-lysine to form a labeling precursor compound; and'}{'sup': 99m', '−, 'sub': '4', 'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'reacting the labeling precursor compound with TcO to form the Dual Nuclear/NIR Agent of .'}10. A process of manufacturing the Dual Nuclear/NIR Agent of claim 1 , comprising:{'sub': 3', '4', '2', 'm', 'A', 'A', '3', '2', '3, 'providing a compound of Formula I or Formula II, wherein Rand Rare each independently in each instance, (CH)R, where m is an integer from 1 to 12, Ris independently CH, NH, SH, COOH, SOH, OH, halogen and CO—N-hydroxysuccinimide;'}reacting the compound with N-hydroxysuccimide to form a monocuccinimide ester of the compound;reacting monocuccinimide ester of the compound with N-α-tBoc-lysine for form a conjugated monocuccinimide ester of the compound;reacting the monocuccinimide ester of the compound with TFA to yield the compound-Lys;coupling of the compound-Lys with DOTA-Sulfo-NHS, in acetonitrile-water to yield the compound-DOTA;{'sup': 64', '111, 'sub': 2', '3, 'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'adding CuClor adding InClto obtain Dual Nuclear/NIR Agent of .'}11. A process of manufacturing the Dual Nuclear/NIR Agent of claim 1 , comprising: using a click ...

SELF-ALIGNED STRUCTURE FOR SEMICONDUCTOR DEVICES

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins. 1. A method of forming a semiconductor structure , the method comprising:forming first and second fins protruding from a top surface of a substrate;forming a spacing layer over the substrate and on opposing sidewalls of the first and second fins, wherein the spacing layer forms an opening between the opposing sidewalls of the first and second fins;forming an isolation fin structure in the opening, wherein a bottom surface of the isolation fin structure is above the top surface of the substrate;etching back the spacing layer such that the isolation fin structure and the first and second fins are protruding from the spacing layer;forming a gate structure over the isolation fin structure and the first and second fins; andforming a gate isolation structure in the gate structure, wherein the gate isolation structure is formed over the isolation fin structure.2. The method of claim 1 , further comprising growing first and second epitaxial source/drain structures on the first and second fins claim 1 , respectively.3. The method of claim 2 , further comprising forming a metal contact on the first and second epitaxial source/drain structures and on the isolation fin structure.4. The method of claim 3 , further comprising forming a contact etch stop layer between the metal contact ...

ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively 1. A method of forming a fin field effect transistor (finFET) on a substrate , the method comprising:forming a fin structure of the finFET on the substrate;forming a first oxide region with a first thickness on top surface of the fin structure;forming a second oxide region with a second thickness on sidewalls on the fin structure, wherein the first thickness is greater than the second thickness;forming a polysilicon structure on the first and second oxide regions;forming a source/drain region on a portion of the fin structure; andreplacing the polysilicon structure with a gate structure.2. The method of claim 1 , wherein forming the first oxide region comprises:forming an amorphous region on the fin structure, the amorphous region comprising an amorphous material;doping the amorphous region;depositing an oxide layer on the amorphous region and on sidewalls of the fin structure; andannealing the amorphous ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer. 1. A method for forming a semiconductor device structure , comprising:forming first and second fins from a substrate;forming a dielectric feature between the first and second fins;forming a first source region and a first drain region from first fin;forming a second source region and a second drain region from the second fin;forming a gate electrode layer between the first source region and the first drain region and between the second source region and the second drain region;recessing the gate electrode layer to a level below a top surface of the dielectric feature; andselectively forming a first conductive layer on the gate electrode layer, wherein the dielectric feature separates the first conductive layer into two segments.2. The method of claim 1 , wherein a top surface of the first conductive layer is substantially coplanar with a top surface of the dielectric feature.3. The method of claim 1 , further comprising forming a dielectric layer on the dielectric feature.4. The method of claim 3 , ...

Contact Plugs and Methods Forming Same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate. 1. A device comprising:a semiconductor region;a gate stack on the semiconductor region, wherein the gate stack comprises a metal-containing layer;a laminate low-k liner on a first sidewall of the gate stack; anda gate spacer on a second sidewall of the laminate low-k liner.2. The device of claim 1 , wherein the laminate low-k liner comprises two sub layers formed of different materials.3. The device of claim 2 , wherein each of the two sub layers has a bottom in physical contact with the semiconductor region.4. The device of claim 2 , wherein both of the two sub layers comprise silicon and nitrogen.5. The device of claim 1 , wherein the gate spacer comprises:an L-shaped layer comprising a horizontal leg and a vertical leg connecting to the horizontal leg, wherein the vertical leg contacts the laminate low-k liner; andan outer spacer overlapping the horizontal leg, wherein the outer spacer contacts the vertical leg to form a vertical interface.6. The device of claim 1 , wherein the laminate low-k liner comprises silicon claim 1 , carbon claim 1 , and nitrogen.7. The device of claim 6 , wherein the laminate low-k liner comprises SiOCN.8. The device of further comprising:a source/drain region adjacent to the gate stack;a ...

Semiconductor Device and Method

A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer. 1. A method comprising:forming a gate stack over a substrate;growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si;growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities;depositing a metal layer over the semiconductor cap layer;annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; andforming a metal contact electrically coupled to the silicide layer.2. The method of claim 1 , wherein the annealing the metal layer and the semiconductor cap layer comprises performing a plurality of annealing processes.3. The method of claim 2 , wherein each successive annealing process of the plurality of annealing processes is performed at a higher temperature.4. The method of claim 1 , wherein annealing the metal layer and the semiconductor cap layer consumes all of the semiconductor cap layer and the metal layer.5. The method of claim 1 , wherein annealing the metal layer and the semiconductor cap layer does not consume all of the semiconductor cap layer or the metal layer.6. The method of claim 1 , wherein the source/drain region is doped with P.7. The method of claim 1 , wherein the semiconductor ...

Gate-All-Around (GAA) Method and Devices

A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage. 1. A method of manufacturing a device , comprising:forming a first stack of alternating layers on a substrate, wherein forming the first stack of alternating layers comprises depositing alternating first layers of a first semiconductor material and second layers of a second semiconductor material different from the first semiconductor material on the substrate;forming a second stack of alternating layers on the substrate at a first distance from the first stack of alternating layers, wherein forming the second stack of alternating layers comprises depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material on the substrate, wherein the first layers of the second stack of alternating layers have a thickness greater than the first layers of the first stack of alternating layers; patterning a first fin from the first stack of alternating layers and a second fin from the second stack of alternating layers; and', 'removing the first layers from the first stack of alternating layers and removing the first layers from the second stack of alternating layers, such that the distances between adjacent remaining layers of the second stack of alternating layers are greater than the distances between adjacent remaining layers of the first stack of alternating layers; and, 'constructing a first stack of nanosheets from the first stack of alternating layers and a second ...

SEMICONDUCTOR CHIP, SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER

The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation. 1. A semiconductor chip , comprising:a substrate;a device provided on a side of the substrate;a via hole running through the substrate;conductive material filled in the via holes and contacted with the devices; anda backside metal layer provided on the other side of the substrate away from the device, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the device via the conductive material.2. The semiconductor chip according to claim 1 , wherein the amount of the conductive material filled in the via hole is 50% to 98% of the volume of the via hole.3. The semiconductor chip according to claim 1 , wherein the conductive material is any one or a combination of Cu claim 1 , Ti claim 1 , Ni claim 1 , W claim 1 , Pt and Au.4. The semiconductor chip according to claim 1 , wherein the conductive material comprises a multi-portion structure claim 1 , each portion being made of one or more kinds of metal.5. The semiconductor chip according to claim 4 , wherein the multi-portion structure is a multilayer structure in a direction from an ...

PREDICTION METHOD, APPARATUS, AND SYSTEM FOR PERFORMING AN IMAGE SEARCH

A prediction method, apparatus, and system for performing an image search is disclosed in the disclosure. In one embodiment, a method comprises: performing training in which domain adaptation learning is performed by using a source domain model to obtain a target domain model, wherein the source domain model comprises at least two network models, and the network models respectively correspond to different commodity categories; and setting an image under search and sample sets of commodities of a plurality of categories as input parameters for the target domain model to obtain a prediction result corresponding to the image. The disclosure solves the technical problem of inaccurate prediction in the process of using category prediction methods to perform a prediction on an image in current systems. 1. A method comprising:generating a target domain model using a domain adaptation training process, the domain adaptation training process using a source domain model as an input, the source domain model comprising at least two network models, each network model corresponding to at least one commodity category;receiving an image under search from a computing device;identifying sample sets of commodities of a plurality of categories;inputting the image under search and sample sets to the target domain model; andreturning a prediction result output by the target domain mode to the computing device.2. The method of claim 1 , wherein at least one of the at least two network models corresponds to multiple commodity categories.3. The method of claim 1 , wherein the at least two network models correspond to a same commodity category4. The method of claim 1 , wherein generating a target domain model comprises:initializing the target domain model using a model pre-trained by an image data set to obtain initial model parameters;inputting sample image data into the source domain model and the target domain model respectively to obtain a calculation result of a loss function between ...

PRODUCT OBJECT PUBLISHING AND RECOGNITION METHODS, APPARATUSES, ELECTRONIC DEVICES, AND STORAGE MEDIA

Embodiments of the specification provide a product object publishing method and a system. The method includes: obtaining an image of a product object; sending the image to a server; receiving a plurality of types of product attribute information obtained by image recognition on the image of the product object performed by an image recognizer set; displaying the plurality of types of product attribute information for selection by a user; generating structured information of the product object according to selection of the product attribute information; and publishing the product object, wherein the publishing comprises publishing the image and the structured information of the product object. Accuracy and efficiency of product object publishing can be improved. 1. A product object publishing method , comprising:obtaining, by a client, an image of a product object;sending, by the client, the image to a server;receiving, by the client from the server, a plurality of types of product attribute information obtained by image recognition on the image of the product object performed by an image recognizer set associated with the server;displaying, by the client, the plurality of types of product attribute information for selection by a user;generating, by the client, structured information of the product object according to selection of the product attribute information; andpublishing, by the client on the server, the product object, wherein the publishing comprises publishing the image and structured information of the product object.2. The method according to claim 1 , wherein the obtaining an image of a product object comprises:displaying a publishing setting page, wherein a shooting option is provided in the publishing setting page; andinvoking, according to triggering of the shooting option, a shooting component of the client to shoot an image of the product object.3. The method according to claim 1 , wherein:the sending the image comprises generating a recognition ...

Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same

A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer. 1. A semiconductor device , comprising:a substrate having a first region and a second region;a first transistor located in the first region, the first transistor having a first channel, a first gate dielectric layer over the first channel, and a first gate electrode layer over the first gate dielectric layer;a second transistor located in the first region, the second transistor having a second channel, a second gate dielectric layer over the second channel, and a second gate electrode layer over the second gate dielectric layer; anda third transistor located in the second region, the third transistor having a third channel, a third gate dielectric layer over the third channel, and a third gate electrode layer over the third gate dielectric layer,wherein a first thickness of the first gate dielectric layer is smaller than a second thickness of the second gate dielectric layer,wherein the second thickness of the second gate dielectric layer is smaller than a third thickness of the third gate dielectric layer.2. The semiconductor device of claim 1 ,wherein the first channel of the first transistor includes a first plurality of channel members and the first gate dielectric layer wraps the first plurality of channel members,wherein the second channel of the second transistor includes a second ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer. 1. A semiconductor device structure , comprising:an isolation structure formed over a substrate;a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure;an inner spacer layer surrounding the first stacked nanostructure;a dummy fin structure formed over the isolation structure, wherein the dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure; anda capping layer formed over the dummy fin structure, wherein the inner spacer layer is in direct contact with the dummy fin structure and the capping layer.2. The semiconductor device structure as claimed in claim 1 , further comprising:a first gate structure formed over first stacked nanostructure; anda second gate structure formed over the second stacked nanostructure, wherein the first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.3. The semiconductor device structure as claimed in claim 1 , further comprising:a source/drain structure formed adjacent to the inner spacer, wherein a portion of the source/drain structure is higher than a top surface of the dummy fin structure.4. The semiconductor device structure as claimed in claim 1 , further comprising:a first gate structure surrounding the first ...

FIELD EFFECT TRANSISTOR WHICH CAN BE BIASED TO ACHIEVE A UNIFORM DEPLETION REGION

A Field Effect Transistor includes a channel with one end designated the source and the other end designated the drain. The Field Effect Transistor also includes a means for connecting to said source end of said channel and a means for connecting to said drain end of said channel. A gate is divided into a plurality of segments each insulated from one another. A means for adjusting the bias of each of said segments independently of one another is configured whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor. 1. A Field Effect Transistor comprising:a channel with one end designated as a source end and another end designated as a drain end;a means for connecting electrically to the source end of the channel;a means for connecting electrically to the drain end of the channel;a gate divided into segments each insulated from one another;a means for connecting electrically to segments of the gate either externally or internally;a bias network connected to said segments, by the means for connecting electrically to segments of the gate, wherein the bias network is configured to apply to the segments of the gate one or more bias voltages that are selected to avoid pinch-off and to cause the depletion region to tend to uniformity along the channel,whereby the depletion region in the channel will be reduced, decreasing the ohmic losses in the channel.2. The Field Effect Transistor of claim 1 , wherein the bias network is comprised of one or more DC voltage sources claim 1 , each of the one or more DC voltage sources being connected to a different segment by the means for connecting electrically to the segments of the gate claim 1 , wherein the one or more DC voltage sources are configured to apply to the segments of the gate the one or more bias voltages that are selected to avoid pinch-off and to cause the depletion region to tend to uniformity along the channel.3. The Field Effect ...

SEMICONDUCTOR DEVICE STRUCTURE

A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer. 1. A semiconductor device structure , comprising:a fin structure protruding above a substrate;a semiconductive capping layer wrapping around three sides of a channel region of the fin structure;an oxide layer wrapping around three sides of the semiconductive capping layer, wherein a thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer; anda gate structure wrapping around three sides of the oxide layer.2. The semiconductor device structure of claim 1 , wherein the semiconductive capping layer and the fin structure are formed of a same material.3. The semiconductor device structure of claim 1 , wherein the semiconductive capping layer and the fin structure are formed of different materials.4. The semiconductor device structure of claim 1 , wherein the thickness of the top portion of the oxide layer is greater than a thickness of a sidewall portion of the oxide layer.5. The semiconductor device structure of claim 1 , wherein the gate structure comprises:a gate dielectric layer over the oxide layer; anda gate electrode over the gate dielectric layer.6. The semiconductor device structure of claim 5 , wherein the gate dielectric layer is in contact with the oxide layer.7. The semiconductor device structure of claim 5 , wherein the gate dielectric layer is spaced apart from the semiconductive capping layer.8. A semiconductor device structure claim 5 , comprising:a ...

WAFER SUPPORTING STRUCTURE, AND DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR

A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring. 1. A wafer supporting structure in semiconductor manufacturing , comprising:a transparent ring;at least two arms connected to the transparent ring; anda first pin disposed between at least one of the at least two arms and an outer surface of the transparent ring, and connecting the at least one of the at least two arms and the transparent ring.2. The wafer supporting structure of claim 1 , wherein the transparent ring is interposed into the at least two arms which are connected at a central point claim 1 , and the transparent ring is concentric to the central point.3. The wafer supporting structure of claim 2 , further comprising:a shaft connected to the at least two arms at the central point.4. The wafer supporting structure of claim 1 , wherein the transparent ring has a constant thickness defined by an upper surface and a lower surface of the transparent ring.5. (canceled)6. The wafer supporting structure of claim 1 , wherein the transparent ring has a width defined by an inner surface and the outer surface of the transparent ring.78-. (canceled)9. The wafer supporting structure of claim 6 , further comprising:a shaft connected to the inner surface of the transparent ring.10. The wafer supporting structure of claim 9 , further comprising:a second pin disposed between the shaft and the inner surface of the transparent ring, and connecting the shaft and the transparent ring.11. A device for manufacturing semiconductor claim 9 , comprising: a transparent ring; and', 'at least two arms connected to the transparent ring, wherein at least a portion of at least one of the at least two arms is disposed above the ...

PRODUCT RELEASE METHOD AND IMAGE PROCESSING METHOD, APPARATUS, DEVICE, AND STORAGE MEDIUM

Embodiments of this specification provide methods and apparatuses for processing images, devices, and storage media. A method includes: obtaining an image for processing; generating a first mask image corresponding to the image based on a machine-learning model and determining whether the image has a foreground object; in response to determining that the image has the foreground object, setting pixels corresponding to the foreground object to a first grayscale value range, and setting pixels corresponding to non-foreground objects in the first mask image to a second grayscale value range; determining an outline corresponding to the foreground object in the image according to a grayscale value range difference between the first grayscale value range of the foreground object and the second grayscale value range of the non-foreground objects in the first mask image; and sending, to a client device for display, the image with the determined outline for interaction by a user. 1. An method for processing an input image , comprising:obtaining an input image for processing;generating a first mask image corresponding to the input image based on a machine-learning model and determining whether the input image has a foreground object;in response to determining that the input image has the foreground object, setting pixels corresponding to the foreground object in the first mask image to a first grayscale value range, and setting pixels corresponding to one or more non-foreground objects in the first mask image to a second grayscale value range;determining an outline corresponding to the foreground object in the input image according to a grayscale value range difference between the first grayscale value range of the foreground object and the second grayscale value range of the one or more non-foreground objects in the first mask image; andsending, to a client device for display, the input image with the determined outline for interaction by a user.2. The method according to ...

APPARATUS FOR AND METHOD OF PROCESSING DOCUMENT IMAGE

An apparatus for and a method of processing a document image are provided. The method comprises: generating a luminance component image from the document image; estimating a luminance image from the luminance component image; and adjusting the luminance component image according to the estimated luminance image. Luminance values of pixels at least in horizontal edge areas of the luminance component image are estimated according to luminance values of pixels in a part of background of the luminance component image. If the estimated luminance values are acceptable according to a predetermined criterion, the luminance image is estimated according to the estimated luminance values. If the estimated luminance values are unacceptable, the luminance image is estimated by using the largest one of the luminance values of the pixels in each column of pixels in the luminance component image as the luminance values of all of the pixels in the column. 1. An apparatus for processing a document image , comprising:a generating unit to generate a luminance component image from the document image;an estimating unit to estimate a luminance image from the luminance component image; andan adjusting unit to adjust the luminance component image according to the luminance image estimated,wherein, the estimating unit estimates luminance values of pixels at least in horizontal edge areas of the luminance component image according to luminance values of pixels in a part of a background of the luminance component image, and if the estimated luminance values of the pixels in the horizontal edge areas are determined as acceptable according to a predetermined criterion, the estimating unit estimates the luminance image according to the estimated luminance values, and if the estimated luminance values are determined as unacceptable according to the predetermined criterion, the estimating unit estimates the luminance image by using a largest one of the luminance values of the pixels in each column ...

PREDICTIVE LOCATION SELECTION OPTIMIZATION SYSTEM

A system can receive, over one or more networks, location data from a computing device of a requesting user, where the location data indicates a current position of the requesting user. The system can repeatedly determine, based at least in part on location data corresponding to a directional heading of a proximate transport provider in relation to the current position of the requesting user, an optimal rendezvous location for the requesting user prior to the requesting user transmitting a service request to the network computer system. The system may then transmit, over the one or more networks, data corresponding to the optimal rendezvous location to the computing device of the requesting user. 1. A network computer system implementing a transport service , comprising:one or more processors; and receive, over one or more networks, location data from a computing device of a requesting user, the location data indicating a current position of the requesting user;', 'prior to the requesting user transmitting a service request to the network computer system, repeatedly determine, based at least in part on location data corresponding to a directional heading of a proximate transport provider in relation to the current position of the requesting user, an optimal rendezvous location for the requesting user; and', 'transmit, over the one or more networks, data corresponding to the optimal rendezvous location to the computing device of the requesting user., 'a memory storing instructions that, when executed by the one or more processors, cause the network computer system to2. The network computer system of claim 1 , wherein the executed instructions cause the network computer system to further determine the optimal rendezvous location by generating a plurality of probability scores for a plurality of possible rendezvous locations based at least in part on respective directional headings of a plurality of proximate transport providers in relation to the current location of ...