19-06-2014 дата публикации
Номер: US20140170834A1
Автор:
Claire Fenouillet-Beranger,
Stephane Denorme,
Nicolas Loubet,
Qing Liu,
Emmanuel Richard,
Pierre Perreau,
FENOUILLET-BERANGER CLAIRE,
DENORME STEPHANE,
LOUBET NICOLAS,
LIU QING,
RICHARD EMMANUEL,
PERREAU PIERRE
A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings. 1. A method for manufacturing a hybrid SOI/bulk substrate , comprising the steps of:a) starting from an SOI wafer comprising a single-crystal semiconductor SOI layer, on an insulating layer, on a single-crystal semiconductor substrate;b) depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate;c) growing, without forming spacers, by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material, up to the desired final level; andd) etching insulating trenches surrounding said openings filled with semiconductor material while encroaching inwards over the periphery of the openings.2. The method of claim 1 , wherein step c) is carried on until the central portion of the upper surface of the semiconductor material is at the same level as the upper surface of the SOI layer.3. The method of claim 1 , wherein the semiconductor material of the substrate and that of the SOI layer are silicon.4. The method of claim 1 , wherein the thickness of the SOI layer ranges between 3 and 10 nm.5. The method of claim 1 , wherein the thickness of the insulating layer ranges between 5 and 50 nm.6. The method of claim 3 , wherein the masking layer comprises a stack of a layer of a silicon ...
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