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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 28. Отображено 26.
25-05-2017 дата публикации

Simultaneous Multi-Layer Fill Generation

Номер: US20170147732A1
Автор: Eugene Anikin, Fedor G. Pikus, Laurence Grodd, David A. Abercrombie, John W. Stedman, ANIKIN EUGENE, PIKUS FEDOR G, GRODD LAURENCE, ABERCROMBIE DAVID A, STEDMAN JOHN W, Anikin Eugene, Pikus Fedor G., Grodd Laurence, Abercrombie David A., Stedman John W.
Принадлежит: Mentor Graphics Corporation

Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met. 1. A method of optimizing a pattern density in a circuit layout design , comprising:(a) generating a first fill region in a first layer of a circuit layout design;(b) generating a second fill region in a second layer of the circuit layout design, the second layer being different than the first layer; a representation of a first section of the multilayer fill structure to be inserted into the first fill region, and', 'a representation of a second section of the multilayer fill structure to be inserted into the second fill region;, '(b) generating a pattern of representations of a multilayer fill structure, the representations including'}(c) determining a target density for a window of the circuit layout design, the window including a first portion in ...

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Номер записи: 1
16-05-2017 дата публикации

Simultaneous multi-layer fill generation

Номер: US0009652574B2
Автор: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman, ANIKIN EUGENE, PIKUS FEDOR G, GRODD LAURENCE W, ABERCROMBIE DAVID A, STEDMAN JOHN W, Anikin Eugene, Pikus Fedor G., Grodd Laurence W., Abercrombie David A., Stedman John W.
Принадлежит: Mentor Graphics Corporation, ANIKIN EUGENE, PIKUS FEDOR G, GRODD LAURENCE W, ABERCROMBIE DAVID A, STEDMAN JOHN W, MENTOR GRAPHICS CORP, Anikin Eugene, Pikus Fedor G., Grodd Laurence W., Abercrombie David A., Stedman John W.

Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.

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Номер записи: 2
02-08-2012 дата публикации

Method For Improving Circuit Design Robustness

Номер: US20120198394A1
Автор: Fedor G. Pikus, Kareem Madkour
Принадлежит: Mentor Graphics Corp

Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various model-based simulations may be performed on the layout areas associated with the identified design critical devices to extract process sensitive and design critical devices. To make the circuit design more robust, various techniques may be employed to treat the extracted process sensitive and design critical devices.

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Номер записи: 3
18-10-2012 дата публикации

Logic Injection

Номер: US20120266117A1
Автор: Kresh Kobi, Pikus Fedor G.
Принадлежит: MENTOR GRAPHICS CORPORATION

A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object. 1. A method comprising:identifying, with a microprocessor, one or more occurrences of a predefined structure in first and second circuit listings, wherein the predefined structure is made up of a plurality of circuit components;creating, with the microprocessor, an injection data object corresponding to each of the identified one or more occurrences of the predefined structure in the first and second circuit listings;modifying the first and second circuit listings by substituting each injection data object for each corresponding identified occurrence of the predefined structure, respectively; andcomparing the modified first circuit listing with the modified second circuit listing to identify differences between the first circuit listing and the second circuit listing.2. The method of claim 1 , wherein the first circuit listing and second circuit listing include different representations of the occurrences of the predefined structure.3. The method of claim 2 , wherein the first circuit listing is a netlist derived from a schematic representation of a circuit claim 2 , and wherein the second circuit listing is a netlist derived from a layout representation of the circuit.4. The method recited in claim 1 , wherein each injection data object includes:at least one repeat information data object ...

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Номер записи: 4
31-01-2013 дата публикации

Hybrid Hotspot Detection

Номер: US20130031518A1
Автор: Beshay Peter Louiz Rezk, Ding Duo, Fahmy Salma Mostafa, Madkour Kareem, Pikus Fedor G., Robles Juan Andres Torres, Wuu Jen-Yi
Принадлежит:

Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category. 1. A method of hybrid hotspot detection , executed by at least one processor of a computer , comprising:receiving data of layout patterns of a layout design;classifying the layout patterns as preliminary hotspots, preliminary non-hotspots and potential hotspots based on machine learning;identifying false positives in the preliminary hotspots and false negatives in the preliminary non-hotspots based on pattern patching; andidentifying boundary hotspots in the potential hotspots based on process simulation.2. The method recited in claim 1 , further comprising:determining hotspot information for the layout design based on the preliminary hotspots, the preliminary non-hotspots, the false positives, the false negatives and the boundary hotspots; andstoring the hotspot information in a tangible processor-accessible medium, or displaying the hotspot information on a tangible medium.3. The method recited in claim 1 , wherein the machine learning comprises a support vector machine model.4. The method recited in claim 3 , wherein the support vector machine model is derived by a model calibration system.5. The method recited in claim 1 , wherein the potential hotspots is determined by using a predetermined value that defines a separation between hotspots and non-hotspots in a ...

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Номер записи: 5
28-03-2013 дата публикации

Electrostatic damage protection circuitry verification

Номер: US20130080985A1
Автор: Fedor G. Pikus, Patrick D. Gibson, Ziyang Lu
Принадлежит: Individual

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

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Номер записи: 6
01-08-2013 дата публикации

Virtual Flat Traversal Of A Hierarchical Circuit Design

Номер: US20130198703A1
Автор: Brooks Phillip A., Lu Ziyang, Pikus Fedor G.
Принадлежит:

Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria. 1. A method of identifying objects in a hierarchical circuit design , comprising: corresponding to a hierarchical cell in the hierarchical circuit design and', 'having configuration information describing relationships for objects associated with the corresponding hierarchical cell, the configuration information including instance specific configuration information for different instances of the corresponding hierarchical cell; and, 'generating object configuration templates for a hierarchical circuit design, each object configuration template'}analyzing the configuration information of an object configuration template to determine if an instance of an object associated with the corresponding hierarchical cell matches defined configuration criteria.2. The method recited in claim 1 , further comprising displaying the identified object instances.3. The method recited in claim 2 , further comprising displaying the identified object instances by displaying identification information for the object instances on a display monitor.4. The method recited in claim 2 , further ...

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Номер записи: 7
28-04-2016 дата публикации

Electrostatic Damage Protection Circuitry Verification

Номер: US20160117437A1
Автор: Fedor G. Pikus, Patrick D. Gibson, Ziyang Lu
Принадлежит: Mentor Graphics Corp

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

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Номер записи: 8
24-08-2017 дата публикации

Preserving Hierarchy And Coloring Uniformity In Multi-Patterning Layout Design

Номер: US20170242953A1
Автор: Pikus Fedor G.
Принадлежит:

Layout design data is seeded with sampling markers. The sampling markers are used to determine patterning scores for patterning clusters in the layout design data, such that a patterning score corresponds to a particular coloring arrangement, and the value of a patterning score corresponds to how many of the sampling markers have a given color. Coloring arrangements are then applied to the patterning clusters based upon the patterning scores. 1. A method of establishing coloring arrangements for layout design data , comprising:seeding geometric elements in layout design data with one or more sampling markers, such that multiple placements of a common cell include multiple instances of a sampling marker;using the one or more sampling markers to determine patterning scores for patterning clusters in the layout design data, wherein a patterning score corresponds to a coloring arrangement; andapplying coloring arrangements to the patterning clusters based upon the patterning scores.2. The method recited in claim 1 , such that determining patterning scores for a patterning cluster includes: determining a first color value based upon how many instances of the sampling marker have a given color with the first coloring arrangement;', 'determining a second color value based upon how many instances of the sampling marker have the given color with a second coloring arrangement different from the first coloring arrangement; and, 'for a sampling marker,'}determining patterning scores for the patterning cluster based upon the determined sampling marker score values.3. The method recited in claim 2 , wherein determining patterning scores for a patterning cluster further includes: determining a third color value based upon how many instances of the second sampling marker have a given color with the first coloring arrangement,', 'determining a fourth color value based upon how many instances of the sampling marker have the given color with the second coloring arrangement; and, 'for ...

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Номер записи: 9
13-11-2014 дата публикации

MODULAR PLATFORM FOR INTEGRATED CIRCUIT DESIGN ANALYSIS AND VERIFICATION

Номер: US20140337810A1
Автор: Pikus Fedor G.
Принадлежит: MENTOR GRAPHICS CORPORATION

A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for performing one or more desired electronic design automation operations. The platform may also provide export modules and import modules. An export module extracts relevant data from the database, and configures that data for use by a specific electronic design automation operation execution module. An import module then receives output data from a particular electronic design automation operation execution module, configures that data for integration into the unified database, and then imports the configured data into the database. 1. A method of analyzing a circuit design , comprising:exporting design data from a design database in a first data format native to the design database,providing input design data to a sequence of one or more electronic design automation processes, the input design data corresponding to the exported design data;executing the sequence of one or more electronic design automation processes using the input design data so as to produce output design data; andimporting design data into the design database in a second data format native to the design database, the imported design data corresponding to the output design data.2. The method recited in claim 1 , further comprising selecting a portion of a design as the exported design data.3. The method recited in claim 2 , wherein the exported design data is selected from a portion of the design according to one or more criteria selected from the group consisting of: a specific device claim 2 , a category of specific devices claim 2 , and a specified region of the design.4. The method recited in claim 1 , wherein executing the sequence of one ...

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Номер записи: 10
24-10-2019 дата публикации

SYSTEMS AND METHODS FOR PHOTOLITHOGRAPHIC DESIGN

Номер: US20190325106A1
Автор: Pikus Fedor G.
Принадлежит:

Systems and methods for generating coloring constraints for layout design data. A method includes receiving or determining a constraint rule, by a computer system, for a constraint between geometric elements in the layout design data. The method includes generating constraints according to the one or more constraint rules. The method includes creating one or more groups according to the generated constraints. The method includes storing the generated constraints and the one or more groups in a design layout database. Also systems and methods for identifying elements in a design layout having multiple levels of hierarchical cells. 1. A method of generating decomposition constraints for layout design data , comprising:receiving or determining a constraint rule, by a computer system, for a constraint between geometric elements in the layout design data, wherein the constraint rule is not based only on distance between geometric elements;generating constraints according to the one or more constraint rules;creating one or more groups according to the generated constraints; andstoring the generated constraints and the one or more groups in a design layout database.2. The method of claim 1 , wherein generating constraints includes identifying each geometric element claim 1 , cluster claim 1 , and group in at least a portion of the layout design data claim 1 , identifying each corresponding geometric element claim 1 , cluster claim 1 , and group in the layout design data in accordance with the one or more constraint rules claim 1 , and generating the constraints between each identified geometric element claim 1 , cluster claim 1 , and group and the corresponding geometric element claim 1 , cluster claim 1 , and group.3. The method of claim 1 , wherein determining the constraint rule includes receiving a constraint defined by a user input and automatically determining a corresponding constraint rule.4. The method of claim 1 , wherein the one or more constraint rules includes ...

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Номер записи: 11
24-10-2019 дата публикации

SYSTEMS AND METHODS FOR PATTERNING COLOR ASSIGNMENT

Номер: US20190325612A1
Автор: Pikus Fedor G.
Принадлежит:

Systems and methods for multi-patterning in layout design data. A method includes receiving a coloring rule by a computer system. The method includes applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system. The method includes, when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule. The method includes, when the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system. 1. A method for multi-patterning in layout design data , comprising:receiving a coloring rule by a computer system;applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system;when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule; andwhen the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system.2. The method of claim 1 , wherein the receiving claim 1 , applying claim 1 , and assigning processes are repeated until all geometric elements in at least a predetermined portion of the layout design data have been assigned a patterning color.3. The method of claim 1 , wherein the receiving claim 1 , applying claim 1 , and assigning processes are repeated until a stopping criterion is met.4. The method of claim 1 , further comprising propagating patterning coloring assignments though other uncolored geometric elements that connected to the unique uncolored geometric element directly or indirectly by coloring constraints.5 ...

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Номер записи: 12
28-11-2019 дата публикации

FABRIC-INDEPENDENT MULTI-PATTERNING

Номер: US20190361425A1
Автор: Pikus Fedor G.
Принадлежит:

Disclosed systems and methods may support fabric-independent multi-patterning. A system may include a coloring constraint access engine and a fabric-independent multi-patterning engine. The coloring constraint access engine may be configured to access a set of coloring constraints to apply to geometric elements of a circuit design without accessing a fabric layer that defines a layout of the geometric elements of the circuit design, the coloring constraints applicable to multi-patterning the geometric elements of the circuit design to support manufacture of circuit layers using multiple manufacturing steps (e.g., via complementary lithographic masks). The fabric-independent multi-patterning engine may be configured to perform, independent of the fabric layer, a pattern coloring process according to the set of coloring constraints to determine a respective color assignment for the geometric elements of the circuit design. 1. A method comprising: accessing a set of coloring constraints to apply to geometric elements of a circuit design without accessing a fabric layer that defines a layout of the geometric elements of the circuit design, the coloring constraints applicable to multi-patterning the geometric elements of the circuit design to support manufacture of circuit layers using multiple manufacturing steps; and', 'performing, independent of the fabric layer, a pattern coloring process according to the set of coloring constraints to determine a color assignment for the geometric elements of the circuit design., 'by a computing system2. The method of claim 1 , wherein claim 1 , for each given coloring constraint in the set of coloring constraints:the given coloring constraint includes one or more geometric identifiers to apply the given coloring constraint to; andeach geometric identifier corresponds to a respective geometric element in the circuit design.3. The method of claim 2 , performing the pattern coloring process independent of the fabric layer comprises ...

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Номер записи: 13
10-12-2020 дата публикации

Systems and methods for photolithographic design

Номер: US20200387661A1
Автор: Fedor G. Pikus
Принадлежит: Mentor Graphics Corp

A method of identifying elements in a design layout having multiple levels of hierarchical cells, each cell having one or more geometric elements, may include selecting a cell from a list of candidate cells for a level of a hierarchy; applying a local rule to the selected cell; identifying each selected cell that includes a geometric element that passes the local rule; building a list of candidate cells for a next-higher level of the hierarchy according to the identified cells; repeating the selecting, identifying, and building operations for each higher level of the hierarchy; and when a highest level of the hierarchy has been processed, returning and storing the list of candidate cells as the global solution for the applied local rule.

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Номер записи: 14
02-02-2021 дата публикации

Systems and methods for patterning color assignment

Номер: US10908511B2
Автор: Fedor G. Pikus
Принадлежит: Mentor Graphics Corp

Systems and methods for multi-patterning in layout design data. A method includes receiving a coloring rule by a computer system. The method includes applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system. The method includes, when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule. The method includes, when the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system.

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Номер записи: 15
22-11-2007 дата публикации

Analysis and optimization of manufacturing yield improvements

Номер: WO2007133423A2
Автор: Fedor G. Pikus, Robin Kirk Albrecht, Sridhar Srinivasan, Steven William Lobasso
Принадлежит: Mentor Graphics Corp.

Techniques for improving the design of circuits, such as integrated microcircuits. A proposed circuit design is analyzed to identify design features associated with yield loss in manufactured circuits. Corrective design changes that will reduce the yield losses associated with the yield loss features then are designated. Once the corrective design changes have been determined, the corrective design changes that will optimize the manufacturing yield of the circuit are selected and incorporated into the circuit design. This analysis and revision process may then be repeated for each revised circuit design, until no further reduction in the manufacturing can be obtained.

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Номер записи: 16
16-06-2011 дата публикации

Device Annotation

Номер: US20110145770A1
Автор: Fedor G. Pikus, Phillip A. Brooks
Принадлежит: Brooks Phillip A, Pikus Fedor G

An electronic design automation process, such as a layout-verses-schematic analysis process, may recognize a representation of a device from physical layout design data. Information, such as geometric information separately obtained from the physical layout design data, is then associated with the recognized device representation. The associated information can subsequently be used in a later electronic design automation operation involving the recognized device representation.

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Номер записи: 17
01-04-2008 дата публикации

Secure exchange of information in electronic design automation

Номер: US7353468B2
Автор: Fedor G. Pikus, John G. Ferguson, Kyohei Sakajiri, Laurence W. Grodd
Принадлежит: Mentor Graphics Corp

Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses). For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules.

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Номер записи: 18
19-02-2019 дата публикации

Electrostatic damage protection circuitry verification

Номер: US10210302B2
Автор: Fedor G. Pikus, Patrick D. Gibson, Ziyang Lu
Принадлежит: Mentor Graphics Corp

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

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Номер записи: 19
22-07-2009 дата публикации

Properties in electronic design automation

Номер: EP2080130A1
Автор: Ellis Cohen, Fedor G. Pikus, Gary S. Myron, Phillip A. Brooks
Принадлежит: Mentor Graphics Corp

One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property's value is not dependent upon the value of any other properties. Alternately, a property may be a compound property, where the definition of the property's value incorporates another, previously- determined property value. Still further, a property may be an alternative property, where the property is assigned one value definition under a first set of conditions and assigned another value definition under a second set of conditions. A first electronic design automation process may generate one or more property values. The generated property values then can be passed to another electronic design automation process in the design analysis flow for its use.

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Номер записи: 20
03-09-2009 дата публикации

Concealment of Information in Electronic Design Automation

Номер: US20090222927A1
Автор: Fedor G. Pikus
Принадлежит: Mentor Graphics Corp

In one exemplary embodiment disclosed herein, an electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.

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Номер записи: 21
22-07-2010 дата публикации

Electrostatic Damage Protection Circuitry Verification

Номер: US20100185995A1
Автор: Fedor G. Pikus, Patrick D. Gibson, Ziyang Lu
Принадлежит: Individual

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

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Номер записи: 22
20-05-2021 дата публикации

Adaptive penalty term determinations in applications of quantum computing to electronic design automation processes

Номер: US20210150001A1
Автор: Fedor G. Pikus, Shashank Jaiswal
Принадлежит: Siemens Industry Software Inc

A system may include a quantum model engine configured to generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design. The EDA process may be a multi-patterning process to assign colors to geometric elements of the circuit design, and the quantum computing model may include an objective function that specifies a cost value for a given state of the quantum computing model. Generation of the quantum computing model may include adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design. The quantum model engine may also be configured to generate a color assignment for the geometric elements of the circuit design through the quantum computing model. The system may also include a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.

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Номер записи: 23
21-08-2008 дата публикации

Model-based design verification

Номер: WO2008063651A9
Автор: David A Abercrombie, Fedor G Pikus
Принадлежит: David A Abercrombie, Fedor G Pikus, Mentor Graphics Corp

An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or 'cluster' these geometric elements together into an identifiable unit. For specified 'clusters' of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.

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Номер записи: 24
03-04-2008 дата публикации

Concealment of information in electronic design automation

Номер: WO2007130320A3
Автор: Fedor G Pikus
Принадлежит: Fedor G Pikus, Mentor Graphics Corp

An electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.

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Номер записи: 25
22-12-2020 дата публикации

Invariant property-based clustering of circuit images for electronic design automation (EDA) applications

Номер: US10872191B1
Автор: Fedor G. Pikus, Muhammad Shahir Rahman
Принадлежит: Mentor Graphics Corp

A system may include an image clustering engine and a cluster provision engine. The image clustering image may be configured to access a set of circuit images and cluster the circuit images into different groups via an unsupervised learning process, wherein clustering by the unsupervised learning process is invariant to each invariant property of an invariant property set. A given invariant property in the invariant property set may correspond to a given image transformation, the invariant properties in the invariant property set may be discrete, and the total number of invariant properties in the invariant property set may be finite. The cluster provision engine may be configured to provide the clustered circuit images for further processing or analysis by an electronic design automation (EDA) application.

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Номер записи: 26