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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 315. Отображено 108.
26-07-2016 дата публикации

Compact RRAM structure with contact-less unit cell

Номер: US0009401473B2
Автор: Shyue Seng Tan, Eng Huat Toh, Elgin Quek, TAN SHYUE SENG, TOH ENG HUAT, QUEK ELGIN, Tan Shyue Seng, Toh Eng Huat, Quek Elgin
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd., GLOBALFOUNDRIES SG PTE LTD

A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

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Номер записи: 1
21-11-2017 дата публикации

Fin selector with gated RRAM

Номер: US0009825223B2
Автор: Eng Huat Toh, Elgin Quek, Shyue Seng Tan, TOH ENG HUAT, QUEK ELGIN, TAN SHYUE SENG, Toh Eng Huat, Quek Elgin, Tan Shyue Seng
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE. LTD., GLOBALFOUNDRIES SG PTE LTD, GLOBALFOUNDRIES Singapore Pte. Ltd.

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

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Номер записи: 2
06-03-2013 дата публикации

Double gated flash memory

Номер: CN102956462A
Автор: Tan Shyue Seng Jason, Toh Eng Huat, Quek Elgin
Принадлежит:

A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

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Номер записи: 3
04-07-2012 дата публикации

Fin type transistor

Номер: CN102543753A
Автор: Toh Eng Huat, Lee Jae Gon, Tan Chung Foong, Quek Elgin
Принадлежит:

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.

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Номер записи: 4
30-08-2016 дата публикации

Transistor devices having an anti-fuse configuration and methods of forming the same

Номер: US0009431497B2
Автор: Eng Huat Toh, Shyue Seng Tan, Elgin Quek, TOH ENG HUAT, TAN SHYUE SENG, QUEK ELGIN, Toh Eng Huat, Tan Shyue Seng, Quek Elgin
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE. LTD., GLOBALFOUNDRIES SG PTE LTD, GLOBALFOUNDRIES Singapore Pte. Ltd.

Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.

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Номер записи: 5
02-08-2016 дата публикации

FinFET

Номер: US0009406801B2
Автор: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek, TOH ENG HUAT, LEE JAE GON, TAN CHUNG FOONG, QUEK ELGIN, Toh Eng Huat, Lee Jae Gon, Tan Chung Foong, Quek Elgin
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE. LTD., GLOBALFOUNDRIES SG PTE LTD, GLOBALFOUNDRIES Singapore Pte. Ltd.

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.

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Номер записи: 6
19-12-2017 дата публикации

Compact RRAM structure with contact-less unit cell

Номер: US0009847377B2
Автор: Shyue Seng Tan, Eng Huat Toh, Elgin Quek, TAN SHYUE SENG, TOH ENG HUAT, QUEK ELGIN, Tan Shyue Seng, Toh Eng Huat, Quek Elgin
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE. LTD., GLOBALFOUNDRIES SG PTE LTD, GLOBALFOUNDRIES Singapore Pte. Ltd.

A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

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Номер записи: 7
27-02-2018 дата публикации

Corner transistor suppression

Номер: US0009905642B2
Автор: Shyue Seng Tan, Ying Keung Leung, Elgin Quek, TAN SHYUE SENG, LEUNG YING KEUNG, QUEK ELGIN, Tan Shyue Seng, Leung Ying Keung, Quek Elgin
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE. LTD., GLOBALFOUNDRIES SG PTE LTD, GLOBALFOUNDRIES Singapore Pte. Ltd.

The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.

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Номер записи: 8
12-01-2012 дата публикации

Novel method to tune narrow width effect with raised S/D structure

Номер: US20120007185A1
Автор: Huang Guangyu, Lee Jae Gon, Quek Elgin, Tan Kian Ming, Yin Chunshan
Принадлежит: Globalfoundries Singapore PTE, LTD.

A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width. 1. A method for forming a semiconductor device , the method comprising:providing a substrate of a first conductivity type;forming thereon a field effect transistor (FET) structure including a gate, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;forming a halo region by implanting dopants of the first conductivity type within the substrate such that a doping concentration at a given depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the given depth below the channel surface near an edge of the first raised S/D region.2. The method in accordance with wherein forming the halo region further comprises:implanting the dopants of the first conductivity type at a predetermined twist angle.3. The method in accordance with wherein the predetermined twist angle is between about 20 and 70 degrees.4. The method in accordance with wherein the predetermined twist angle is about 45 degrees.5. The method in accordance with wherein forming the halo region further comprises:implanting first dopants of the first conductivity type at no twist angle, and then implanting second dopants of the first conductivity ...

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Номер записи: 9
26-01-2012 дата публикации

Semiconductor device with reduced contact resistance and method of manufacturing thereof

Номер: US20120018815A1
Автор: Lee Jae Gon, Ong Shiang Yang, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит:

A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface. 1. A method of forming a semiconductor device , the method comprising:providing a semiconductor substrate with dopants of a first conductivity type;forming a field-effect transistor (FET) structure on the substrate, the FET structure including a gate structure and first and second source/drain (S/D) regions with dopants of a second conductivity type;depositing metal on the first and second S/D regions;performing a thermal annealing process to form metal silicide within the first and second S/D regions;after metal silicide is formed, implanting an impurity in the first and second S/D regions; andafter impurity implantation, performing a spike annealing process.2. The method in accordance with wherein the impurity comprises nitrogen.3. The method in accordance with wherein the metal comprises nickel.4. The method in accordance with wherein the spike annealing process is at least a one of: laser spike annealing (LSA) or dynamic spike annealing (DSA).5. The method in accordance with further comprising:after impurity implantation and prior to the spike annealing process, performing a second thermal annealing process.6. The method in accordance with wherein the impurity comprises nitrogen and the metal comprises nickel.7. The method in accordance with further comprising:removing excess unreacted deposited metal; andafter removing excess unreacted metal and prior to impurity ...

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Номер записи: 10
16-02-2012 дата публикации

Novel methods to reduce gate contact resistance for AC reff reduction

Номер: US20120038009A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat, Yin Chunshan
Принадлежит:

A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff. 1. A method of forming a semiconductor device , the method comprising:providing a semiconductor substrate with dopants of a first conductivity type;forming first and second source/drain (S/D) regions with dopants of a second conductivity type; forming a gate dielectric having a high dielectric constant (K),', 'depositing metal to form a metal gate electrode, and', 'forming a gate contact layer;, 'forming a high-K/metal gate stack, wherein forming the high-K/metal gate stack further comprises,'}forming an impurity layer between the metal gate electrode and the gate contact layer, the impurity layer comprising an impurity; andperforming an anneal process to convert the impurity layer into a segregation layer.2. The method in accordance with wherein the impurity comprises at least a one of: nitrogen or aluminum.3. The method in accordance with wherein the gate contact layer comprises amorphous silicon.4. The method in accordance with wherein the anneal process is at least a one of: laser spike annealing (LSA) or dynamic spike annealing (DSA) or rapid thermal annealing (RTA).5. The method in accordance with wherein forming the gate dielectric further comprises:forming a layer of silicon oxynitride (SiON);forming a layer of hafnium silicon oxynitride (HfSiON); and{'sub': 2', '3, 'forming a ...

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Номер записи: 11
22-03-2012 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING

Номер: US20120070971A1
Автор: LEUNG Ying Keung, Pandey Shesh Mani, QUEK Elgin Kiok Boone, WANG TAO, YEO Chia Ching, YEONG Sai Hooi
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. 1. A method for fabricating a semiconductor device comprising:providing a substrate comprising a first device region;forming a first device in the first device region, the first device comprising first diffusion regions;forming a stressor layer covering the substrate in the first device region and the first device, the stressor layer having a first stress value;performing a laser anneal to memorize at least a portion of the first stress value in the first device; andperforming an activation anneal after the laser anneal to activate dopants in the first diffusion regions.2. The method of further comprising removing the stressor layer after performing the laser anneal and before performing the activation anneal.3. The method of claim 2 , wherein the activation anneal comprises a spike anneal.4. The method of claim 3 , wherein the activation anneal comprises a spike anneal and an activation laser anneal.5. The method of claim 1 , wherein the activation anneal causes the first diffusion regions to diffuse outward.6. The method of wherein the first device is a transistor of a first carrier type.7. The method of wherein the first device comprises a first gate electrode and the first diffusion regions are disposed within the substrate on opposed sides of the gate electrode.8. The method of claim 7 , further comprising amorphizing at least a portion of the first gate electrode and the substrate in the first device ...

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Номер записи: 12
10-05-2012 дата публикации

Control gate structure and method of forming a control gate structure

Номер: US20120112256A1
Автор: LEUNG Ying Keung, Quek Elgin, Tan Shyue Seng
Принадлежит: Globalfoundries Singapore PTE, LTD.

Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions. 1. A method of forming a semiconductor device , the method comprising:providing a substrate;forming a gate structure on the substrate, the gate structure comprising a control gate and a select gate;forming the control gate to comprise three or more gate regions having alternating field types.2. The method of claim 1 , wherein the step of forming the gate structure comprises forming a select gate and an adjacent control gate cavity claim 1 , and wherein the step of forming the control gate comprises providing a high-gate material in the control gate cavity claim 1 , removing a portion of the high-gate material to create a space claim 1 , and filling the space with a low-gate material.3. The method of claim 1 , wherein the step of forming the gate structure comprises forming a select gate and an adjacent control gate cavity claim 1 , and wherein the step of forming the control gate comprises providing a low-gate material in the control gate cavity claim 1 , removing a portion of the low-gate material to create a space claim 1 , and filling the space with a high-gate material.4. The method of claim 1 , wherein the formed control gate comprises two outwardly-disposed control gate portions having the same field type.5. The method of claim 4 , wherein the two outwardly-disposed control gate portions both comprise a high-gate material.6. The method of claim 4 , wherein the two outwardly-disposed control gate portions both comprise a low-gate ...

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Номер записи: 13
05-07-2012 дата публикации

FINFET

Номер: US20120168913A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance. 1. A method for forming a device comprising:providing a substrate prepared with a device region which includes a doped isolation well and a dielectric layer over the substrate, wherein the dielectric layer includes a second dielectric sub-layer over a first dielectric sub-layer;forming a fin structure in the dielectric layer;removing a portion of the dielectric layer, wherein removing the portion of the dielectric layer leaves an upper portion of the fin structure extending above a top surface of the first dielectric sub-layer;forming a gate which traverses the fin structure; andforming doped S/D regions in the fin structure adjacent to the gate.2. The method of wherein the dielectric sub-layers comprise materials which can be removed selectively to each other.3. The method of wherein:the first dielectric sub-layer comprises silicon oxide and the second dielectric sub-layer comprises silicon nitride, orthe first dielectric sub-layer comprises silicon nitride and the second dielectric sub-layer comprises silicon oxide.4. The method of wherein the thickness of the first dielectric sub-layer is Hand the thickness of the second dielectric sub-layer is H claim 1 , wherein Hdetermines the height of a device in the device region.5. The method of wherein forming the fin structure comprises:forming an opening in the dielectric layer to expose a portion of the substrate;forming a semiconductor layer over the substrate to fill the opening and cover the dielectric layer; andremoving excess semiconductor layer over the dielectric ...

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Номер записи: 14
30-08-2012 дата публикации

BURIED CHANNEL FINFET SONOS WITH IMPROVED P/E CYCLING ENDURANCE

Номер: US20120217467A1
Автор: Quek Elgin, Tan Shyue Seng (Jason), Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer. 1. A method comprising:forming p-type silicon fins protruding from a first oxide layer;forming an n-type silicon layer over exposed surfaces of the fins;forming a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer; andforming a polysilicon layer on the third oxide layer.2. The method according to claim 1 , comprising forming the n-type silicon layer by n-type plasma doping the fins or by epitaxially growing in-situ n-doped silicon on the fins.3. The method according to claim 2 , comprising:forming the fins in a p-type silicon substrate; andforming the first oxide layer on the p-type silicon substrate around the fins.4. The method according to claim 3 , comprising forming the first oxide layer by:depositing an oxide over the substrate and the fins; andtime etching the oxide to a thickness of 2 nm to 20 nm.5. The method according to claim 4 , comprising forming the p-type silicon fins by:forming a hard mask on the p-type silicon substrate;patterning a photoresist on the hard mask with openings;etching the p-type silicon substrate through the openings in the patterned photoresist; andremoving the photoresist.6. The method according to claim 5 , further comprising: ...

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Номер записи: 15
06-09-2012 дата публикации

P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION

Номер: US20120223318A1
Автор: CHU Sanford, LEUNG Ying Keung, Quek Elgin, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer. 1. A method comprising:forming a dummy gate stack on a substrate;forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack;forming spacers on the layer;forming raised source/drains;removing the dummy gate stack, forming a cavity between the spacers; andforming a memory gate stack in the cavity.2. The method according to claim 1 , comprising forming the layer of a narrow bandgap material.3. The method according to claim 2 , comprising forming the raised source/drains by deep source/drain implantation in the layer.4. The method according to claim 2 , comprising forming the raised source/drains by in situ doping the layer during selective epitaxial growth.5. The method according to claim 2 , further comprising:recess etching the layer, leaving only the portion under the spacers;forming a second layer, by selective epitaxial growth on the substrate, adjacent the first layer and to substantially the same thickness as the first layer; andsubsequently forming the raised source/drains by deep source/drain implantation in the second layer.6. The method according to claim 5 , comprising forming the second layer of a wide bandgap material.7. The method according to ...

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Номер записи: 16
06-09-2012 дата публикации

SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES

Номер: US20120223394A1
Автор: Quek Elgin, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. 1. A method comprising:forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on a shallow trench isolation (STI) region, and a first inter layer dielectric (ILD) between the first and second metal gate stacks;forming an etch stop layer on the first and second metal gate stacks;forming a second ILD on the etch stop layer, with openings over the first and second gate stacks;forming first and second spacers on the edges of the openings;forming a third ILD over the second ILD and the first and second spacers;removing the first ILD over the source/drain regions and the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the first spacers, and over a portion of the first spacers, forming first trenches;removing the third ILD over the second high-k metal gate stack and over a portion of the second spacers, forming second trenches; andforming contacts in the first and second trenches.2. The method according to claim 1 , ...

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Номер записи: 17
13-09-2012 дата публикации

LDMOS WITH IMPROVED BREAKDOWN VOLTAGE

Номер: US20120228695A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An LDMOS is formed with a field plate over the ndrift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials. 1. A method comprising:forming a first well and a second well in a substrate, the second well surrounding the first well;doping the first well with a first conductivity type dopant and the second well with a second conductivity type dopant;forming a source in the first well and a drain in the second well;forming a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively; andtuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack than for the first gate stack.2. The method according to claim 1 , comprising tuning the work functions by:forming a high-k dielectric layer and a metal gate as the first gate stack; andforming an oxide layer and a polysilicon or amorphous silicon (a-Si) field plate as the second gate stack.3. The method according to claim 2 , comprising:forming an oxide ...

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Номер записи: 18
13-09-2012 дата публикации

LDMOS WITH IMPROVED BREAKDOWN VOLTAGE

Номер: US20120228705A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An LDMOS is formed with a second gate stack over the n drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics. 1. A method comprising:forming a first well and a second well in a substrate, the second well surrounding the first well;doping the first well with a first-type dopant and the second well with a second-type dopant;forming a source in the first well and a drain in the second well;forming a doped region of the first-type dopant in the first well, the doped region functioning as a body contact to the first well;forming a first gate stack on a portion of the first well;forming a second gate stack on a portion of the second well; wherein the first and second gate stacks have a common gate electrode, and the second gate stack has a higher work function than the first gate stack.2. The method according to claim 1 , comprising forming the first and second gate stacks by:forming an oxide layer on the portion of the second well;forming a high-k dielectric layer on the oxide layer and on either the portion of the first well or on a thin oxide over the portion of the first well; andforming a common metal gate electrode on the high-k dielectric layer.3. The method according to claim 2 , comprising forming the first ...

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Номер записи: 19
22-11-2012 дата публикации

CORNER TRANSISTOR SUPPRESSION

Номер: US20120292735A1
Автор: LEUNG Ying Keung, Quek Elgin, Tan Shyue Seng (Jason)
Принадлежит: GLOBALFOUNDRIES Singapore Pte.Ltd.

The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners. 1. A method comprising:forming a trench, having side surfaces and a bottom surface, in a substrate;forming an oxide liner on the side surfaces and bottom surface of the trench; andforming a layer of high-K dielectric material on the oxide liner.2. The method according to claim 1 , further comprising filling the trench with an insulating material.3. The method according to claim 1 , wherein the substrate comprises a semiconductor material claim 1 , the method further comprising:forming a pad oxide layer on an upper surface of the substrate; andforming a pad nitride layer on the pad oxide layer, both prior to forming the trench in the substrate;filling the trench with insulating material forming an overburden on the pad nitride layer subsequent to forming the layer of high-K dielectric material; and 'the layer of high-K dielectric material extends proximate corners of the trench.', 'planarizing such that an upper surface of the insulating material is substantially coplanar with an upper surface of the pad nitride layer, wherein'}4. The method according to claim 3 , further comprising:removing the pad oxide and pad nitride layers from the upper surface of the substrate, leaving the filled trench as a trench isolation region; and 'the layer of high-K dielectric material increases a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.', 'forming transistors on the substrate separated by the trench isolation region, wherein,'}5. A method ...

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Номер записи: 20
24-01-2013 дата публикации

MEMORY CELL WITH DECOUPLED CHANNELS

Номер: US20130020626A1
Автор: Quek Elgin, Tan Shyue Seng, TANG Yanzhe, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. 1. A device comprising: an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,', 'an erase gate being disposed over the common S/D region, and', 'a program gate being disposed over the first storage S/D region,, 'a substrate prepared with a memory cell region having first and second memory cells, each of the memory cells includes'}wherein such an arrangement of the memory cell decouples a program channel and an erase channel.2. The device of wherein the first and second memory cells are coupled in series to form a memory cell pair.3. The device of wherein the memory cells of the memory cell pairs are configured as mirror images of each other.4. The device of wherein the first storage S/D region of the first memory cell is common with the first storage S/D region of the second memory cell.5. The device of wherein the erase gate contacts the substrate and common S/D region and isolated from a storage and an access gate by gate sidewall dielectric layers.6. The device of wherein the storage layer includes first and second storage gate electrodes claim 1 , wherein:the first ...

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Номер записи: 21
31-01-2013 дата публикации

Split-gate flash memory exhibiting reduced interference

Номер: US20130026552A1
Автор: Elgin Quek, Eng Huat Toh, Shyue Seng (Jason) Tan
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

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Номер записи: 22
14-02-2013 дата публикации

DOUBLE GATED FLASH MEMORY

Номер: US20130037877A1
Автор: Quek Elgin, Tan Shyue Seng (Jason), Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate. 1. A method comprising:providing a fin structure on a substrate;providing a memory gate stack proximate a first side surface of the fin structure; andproviding a select gate proximate a second side surface of the fin structure.2. The method according to claim 1 , comprising:providing a first channel region under the memory gate stack; andproviding a second channel region under the select gate.3. The method according to claim 2 , wherein the first channel region is for program and/or erase and the second channel region is for read.4. The method according to claim 1 , comprising providing the memory gate stack and the select gate on opposite side surfaces of the fin structure.5. The method according to claim 4 , comprising providing the fin structure by etching the substrate.6. The method according to claim 5 , comprising:etching to form the fin structure having an upper surface; depositing floating gate material on the first side surface of the fin structure;', 'depositing select gate material on the second side surface of the fin structure;', 'planarizing the floating gate material and select gate material to be substantially coplanar with the upper surface of the fin structure; and', 'depositing control gate material proximate a side surface of the floating gate material., 'providing the memory gate stack and the select gate stack by7. The method according to claim 6 , wherein the floating gate material is the same as the select gate material.8. The method according to claim 6 , comprising:oxidizing the first and second side surfaces of the fin structure prior to depositing the floating gate and select gate material; andforming a dielectric layer on a side surface of the floating gate material prior to depositing the control gate material.9 ...

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Номер записи: 23
11-04-2013 дата публикации

DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF

Номер: US20130087889A1
Автор: CHONG Yung Fu, CHU Sanford, Quek Elgin, Tan Shyue Seng, TEO Lee Wee
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. 120-. (canceled)21. A method for forming a device comprising:providing a substrate;forming a gate structure over the substrate;forming first and second diffusion regions in the substrate on opposed sides of the gate structure;forming at least one diffusion barrier having cavities in the substrate, wherein the diffusion barrier abuts ends of the first and second diffusion regions, the diffusion barrier reduces out-diffusion of dopants from the first and second diffusion regions.22. The method of wherein the diffusion barrier abuts bottom ends of the first and second diffusion regions.23. The method of comprising:forming a plurality of shallow trench isolation (STI) regions in the substrate.24. The method of wherein the diffusion barrier spans a substantial distance from one STI region to another adjacent STI region.25. The method of wherein forming the diffusion barrier comprises:implanting an implant medium in the substrate to form an implant region of which the diffusion barrier is to be formed; andannealing the implant region to form the cavities.26. The method of wherein the implant medium comprises He claim 25 , hydrogen claim 25 , argon atoms or a combination thereof.27. The method of wherein forming the first and second diffusion regions comprises:forming spacers adjacent to sidewalls of the gate structure; andimplanting the dopants to form the first and second diffusion regions.28. The method of wherein the diffusion barrier comprises:first and second diffusion barriers, wherein the first diffusion barrier abuts a bottom of the first diffusion region and the second diffusion barrier abuts a bottom of the second diffusion barriers.29. The method ...

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Номер записи: 24
29-08-2013 дата публикации

COMPACT RRAM DEVICE AND METHODS OF MAKING SAME

Номер: US20130221308A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer. 1. A RRAM device , comprising:a gate electrode;a conductive sidewall spacer; andat least one variable resistance material layer positioned between said gate electrode and said conductive sidewall spacer.2. The device of claim 1 , further comprising a liner layer positioned between said gate electrode and said at least one variable resistance material layer.3. The device of claim 1 , wherein at least one variable resistance material layer has a generally L-shaped configuration.4. The device of claim 1 , wherein said at least one variable resistance material layer is comprised of at least one of the following materials: a perovskite material claim 1 , such as a colossal magnetoresistive (CMR) material or a high temperature superconducting (HTSC) material claim 1 , for example Pr.Ca.MnO(PCMO) claim 1 , GdCaOBaCoO claim 1 , a transition metal oxide such as hafnium oxide claim 1 , titanium oxide claim 1 , nickel oxide claim 1 , tungsten oxide claim 1 , tantalum oxide claim 1 , copper oxide claim 1 , manganites claim 1 , titanates (e.g. claim 1 , STO:Cr) claim 1 , zirconates (e.g. claim 1 , SZO:Cr claim 1 , CaNbO:Cr claim 1 , TaO:Cr) claim 1 , and high Tc superconductors (e.g. claim 1 , YBCO) claim 1 , etc.5. The device of claim 1 , wherein at least a portion of said at least one variable resistance material layer is formed on a surface of a semiconducting substrate and wherein said portion of said at least one variable resistance material layer is positioned between said substrate and a bottom of said conductive sidewall spacer.6. The device of claim 1 , wherein said conductive sidewall spacer is comprised of a metal ...

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Номер записи: 25
12-09-2013 дата публикации

SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES

Номер: US20130234253A1
Автор: Quek Elgin, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. 1. A device comprising:a substrate;an STI region in a portion of the substrate;a first high-k metal gate stack having first spacers thereon, on the substrate between source/drain regions;a second high-k metal gate stack having second spacers thereon on the STI region;an etch stop layer on the first and second high-k metal gate stacks, the etch stop layer having an opening over a portion of the second high-k metal gate stack;a pair of third spacers on the etch stop layer over the first high-k metal gate stack;a pair of fourth spacers on the etch stop layer on the second high-k metal gate stack;an ILD between the third spacers;a first contact on each side of the first high-k metal gate and over a portion of the first spacers; anda second contact between and over a portion of the fourth spacers.2. The device according to claim 1 , further comprising a silicide on the source/drain regions.3. The device according to claim 2 , wherein the silicide comprises nickel silicide.4. The device according to claim 1 , wherein the etch ...

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Номер записи: 26
19-09-2013 дата публикации

THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME

Номер: US20130240821A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line. 1. An RRAM device , comprising:a first electrode for a first bit line;a second electrode for a second bit line;a common electrode positioned between said first and second electrodes;a first variable resistance material layer positioned between said first electrode and said common electrode, wherein said first variable resistance material layer is conductively coupled to said first electrode and said common electrode; anda second variable resistance material layer positioned between said second electrode and said common electrode, wherein said second variable resistance material layer is conductively coupled to said second electrode and said common electrode.2. The device of claim 1 , further comprising an access/selector device that is conductively coupled to said common electrode.3. The device of claim 2 , wherein said access/selector device comprises a diode.4. The device of claim 2 , wherein said access/selector device comprises a bipolar junction transistor.5. The device of claim 2 , further comprising a conductive word line that is conductively coupled to said access/selector device.6. The device of claim 1 , further comprising a diode and a conductive word line claim 1 , wherein said diode is positioned between said conductive word line and said common electrode and wherein said diode is conductively coupled to both said conductive word line and said common electrode.7. The device of claim 1 , further comprising a bipolar junction transistor that is conductively coupled ...

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Номер записи: 27
17-10-2013 дата публикации

RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME

Номер: US20130270501A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material. 1. An RRAM device , comprising:first and second sidewall spacers positioned above a semiconducting substrate, wherein said first and second sidewall spacers are comprised of at least a conductive material;a conductive word line electrode positioned between said first and second sidewall spacers;first and second regions of variable resistance material positioned between said conductive word line electrode and said conductive material of said first and second sidewall spacers, respectively;a base region of a bipolar junction transistor formed in said substrate below said conductive word line electrode;an emitter region of said bipolar junction transistor formed in said substrate below said base region; andfirst and second spaced-apart collector regions formed in said substrate within said base region, wherein said first collector region is positioned at least partially under said first region of variable resistance material and said second collector region is positioned at least partially under ...

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Номер записи: 28
17-10-2013 дата публикации

Semiconductor device with reduced contact resistance and method of manufacturing thereof

Номер: US20130270654A1
Автор: Chung Foong Tan, Elgin Quek, Eng Huat Toh, Jae Gon Lee, Shiang Yang Ong
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

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Номер записи: 29
31-10-2013 дата публикации

CORNER TRANSISTOR SUPPRESSION

Номер: US20130288452A1
Автор: LEUNG Ying Keung, Quek Elgin, Tan Shyue Seng
Принадлежит:

The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners. 1. A method comprising:forming a trench, having side surfaces and a bottom surface, in a substrate;forming an oxide liner on the side surfaces and bottom surface of the trench; andforming a layer of high-K dielectric material on the oxide liner.2. The method according to claim 1 , comprising forming the trench by reactive ion etching (RIE).3. The method according to claim 1 , comprising forming the trench to a width of 500 to 1000 and a depth of 1500 Å to 4000 Å.4. The method according to claim 1 , comprising forming the oxide liner to a thickness of 10 Å to 40 Å.5. The method according to claim 1 , comprising forming the high-K dielectric layer to a thickness of 20 Å to 80 Å.6. The method according to claim 1 , further comprising filling the trench with an insulating material.7. The method according to claim 6 , comprising filling the trench by a high aspect ratio process.8. The method according to claim 1 , wherein the substrate comprises a semiconductor material claim 1 , the method further comprising:forming a pad oxide layer on an upper surface of the substrate; andforming a pad nitride layer on the pad oxide layer, both prior to forming the trench in the substrate; andforming the layer of high-K dielectric material on an upper surface of the pad nitride layer and on side surfaces of the pad oxide and pad nitride layers concurrently with forming the layer of high-K dielectric material on the oxide liner.9. The method according to claim 8 , comprising:forming the pad ...

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Номер записи: 30
07-11-2013 дата публикации

METHOD AND APPARATUS FOR UTILIZING CONTACT-SIDEWALL CAPACITANCE IN A SINGLE POLY NON-VOLATILE MEMORY CELL

Номер: US20130292756A1
Автор: Quek Elgin, TANG Yan Zhe
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An approach for utilizing electrical capacitance between a plurality of contacts and sidewalls to provide voltage coupling between a floating gate (FG) and a control gate (CG) is disclosed. Embodiments include providing an FG and a CG laterally separated from each other; coupling a plurality of parallel polysilicon lines to the FG; providing a plurality of contacts between the plurality of the parallel polysilicon lines and coupling the contacts to the CG; and forming an electrical capacitance between the plurality of contacts and sidewalls of the plurality of parallel polysilicon lines to provide voltage coupling between the CG and the FG. 1. A device comprising:a single polysilicon memory cell on a substrate including a control gate (CG) and a floating gate (FG), the CG being laterally separated from the FG;a plurality of contacts coupled to the CG and arranged in lines in a first direction on the substrate; anda plurality of parallel polysilicon lines coupled to the FG and arranged in the first direction on the substrate alternating with and in substantially close proximity with the lines of contacts, each parallel polysilicon line having sidewalls,wherein electrical capacitance between a contact and an adjacent polysilicon sidewall provides voltage coupling between the CG and the FG.2. The device according to claim 1 , further comprising:a dielectric medium of silicon nitride (SiN) arranged between the plurality of CG contacts and the polysilicon sidewalls.3. The device according to claim 2 , wherein the polysilicon thickness is 80 nanometers (nm).4. The device according to claim 1 , further comprising a first metal layer vertically coupled to the contacts.5. The device according to claim 4 , wherein the CG is formed of the contacts and the first metal layer.6. The device according to claim 5 , wherein the FG is formed of logic polysilicon.7. The device according to claim 5 , further comprising a word line (WL) formed of the logic polysilicon.8. The device ...

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Номер записи: 31
14-11-2013 дата публикации

LOCALIZED DEVICE

Номер: US20130299764A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A device is disclosed. The device includes a gate disposed on a substrate in a device region, the gate having first and second sidewalls. The gate includes a gate electrode and a resistive layer disposed between the gate electrode and substrate. First doped regions of a first polarity type are disposed in the substrate adjacent to the first and second sidewalls of the gate. The gate overlaps the first doped regions by a first distance to form overlap portions. A portion of the resistive layer between the gate electrode and overlap portions form first and second storage elements of a multi-bit resistive memory cell. 1. A device comprising:a gate disposed on a substrate in a device region, the gate having first and second sidewalls, the gate includes a gate electrode and a resistive layer disposed between the gate electrode and substrate;first doped regions of a first polarity type disposed in the substrate adjacent to the first and second sidewalls of the gate, wherein the gate overlaps the first doped regions by a first distance to form overlap portions; andwherein a portion of the resistive layer between the gate electrode and overlap portions form first and second storage elements of a multi-bit resistive memory cell.2. The device in wherein the first distance is short enough to form a low number of conduction paths in the resistive layer when an appropriate voltage is applied.3. The device in wherein the number of conduction paths is about 1-2.4. The device in wherein the first distance is about 1-10 nm.5. The device in comprises first and second sidewall spacers on the first and second sidewalls of the gate.6. The device in comprises second doped regions of a second polarity type disposed in the substrate adjacent to first and second sidewall spacers of the gate.7. The device in wherein the second doped regions are disposed within the first doped regions.8. The device in comprises a deep well of a second polarity type disposed in the substrate encompassing the ...

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Номер записи: 32
21-11-2013 дата публикации

Finfet with stressors

Номер: US20130307038A1
Автор: Chung Foong Tan, Elgin Quek, Eng Huat Toh, Jae Gon Lee
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

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Номер записи: 33
12-12-2013 дата публикации

NON-VOLATILE MEMORY USING PYRAMIDAL NANOCRYSTALS AS ELECTRON STORAGE ELEMENTS

Номер: US20130328118A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Tan Shyue Seng, Yin Chunshan
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. 1. A non-volatile memory device that comprises:a floating gate that comprises at least one pyramidal silicon nanocrystal.2. The non-volatile memory device that is set forth in wherein the at least one pyramidal silicon nanocrystal is located on a tunnel oxide layer of the floating gate.3. The non-volatile memory device that is set forth in comprising a gate oxide layer that is formed over the tunnel oxide layer and over the at least one pyramidal silicon nanocrystal.4. The non-volatile memory device that is set forth in wherein electrons tunnel through the gate oxide layer from the at least one pyramidal silicon nanocrystal.5. The non-volatile memory device that is set forth in wherein the at least one pyramidal silicon nanocrystal wherein the at least one pyramidal silicon nanocrystal has a base that is in a range of approximately eight nanometers (8 nm) to fifteen nanometers (15 nm) and has a height that is in a range of approximately eight nanometers (8 nm) to fifteen nanometers (15 nm).6. The non-volatile memory device that is set forth in further comprising:a tunnel oxide layer;wherein the floating gate that comprises the at least one pyramidal silicon nanocrystal is formed over the tunnel oxide layer; anda gate oxide layer that is formed over the tunnel oxide layer and over the at least one pyramidal silicon nanocrystal.7. The non-volatile memory device that is set forth in wherein electrons tunnel through the gate oxide layer from the at least ...

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Номер записи: 34
19-12-2013 дата публикации

INTEGRATION OF MEMORY, HIGH VOLTAGE AND LOGIC DEVICES

Номер: US20130334584A1
Автор: LEUNG Ying Keung, Quek Elgin, Tan Shyue Seng, TANG Yan Zhe
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (T) is disposed in the first region. A high voltage (HV) transistor having a second stack height (T) is disposed in the second region and a logic transistor having a third stack height (T) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate. 1. A device comprising:a substrate having first, second and third regions, the first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region;{'sub': 'SM', 'a memory cell which includes a memory transistor having a first stack height (T) is disposed in the first region;'}{'sub': 'SHV', 'a high voltage (HV) transistor having a second stack height (T) is disposed in the second region; and'}{'sub': 'SL', 'a logic transistor having a third stack height (T) is disposed in the third region, wherein the first, second and third stack heights are substantially the same across the substrate.'}2. The device of wherein the memory transistor includes a floating gate transistor.3. The device of wherein:the floating gate transistor includes a first gate electrode over a first gate dielectric layer on the substrate, a second gate electrode over the first gate electrode with an isolation layer in between the first and second gate electrodes; and{'sub': 'SM', 'the Tis defined by a total thickness of the first gate electrode, isolation layer and the final thickness of the second gate electrode.'}4. The device of wherein the second gate electrode includes a heavily doped polysilicon layer.5. The device of wherein:the HV transistor includes a HV gate ...

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Номер записи: 35
09-01-2014 дата публикации

METHOD AND APPARATUS FOR EMBEDDED NVM UTILIZING AN RMG PROCESS

Номер: US20140008713A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate. 1. A method comprising:forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate;forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures;forming an inter-layer dielectric (ILD) adjacent to an exposed sidewall of each spacer;removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers; andforming a high-k/metal gate (HKMG) in the first cavity, wherein the HKMG comprises an access gate.2. The method according to claim 1 , further comprising forming the first and second dual polysilicon gate-stack structures by:forming a floating gate layer on a tunnel-oxide layer, on the upper surface of the substrate;forming a blocking oxide layer on the floating gate layer;forming a control gate layer on the blocking oxide layer; andetching the floating gate, the blocking oxide, and the control gate layers.3. The method according to claim 1 , further comprising:forming source/drain regions in the substrate for each of the first and second dual polysilicon gate-stack structures prior to forming the ILD.4. The method according to claim 3 , further comprising:forming a hard-mask layer over the HKMG and the second dual polysilicon gate-stack structure; andforming contacts on the source/drain regions through the ILD.5. The method according to claim 3 , further ...

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Номер записи: 36
20-02-2014 дата публикации

NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY

Номер: US20140048865A1
Автор: LIM Khee Yong, Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBAL FOUNDRIES Singapore Pte. Ltd.

A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack. 1. A method comprising:forming a gate stack on a substrate;forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack;forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack;forming a charge-trapping (CT) spacer on each tunnel oxide liner; andforming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.2. The method according to claim 1 , further comprising:forming an interlayer dielectric (ILD) over an upper surface of the substrate surrounding the gate stack and the CT spacers, after forming the source and drain.3. The method according to claim 2 , comprising:forming, through the ILD over the drain, a first contact at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; andforming, through the ILD over the source, a second contact.4. The method according to claim 3 , comprising:removing the gate stack, forming a cavity between each of the tunnel oxide liners;forming a high-k dielectric layer in the cavity; andforming a replacement metal gate (RMG) electrode on the high ...

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Номер записи: 37
20-02-2014 дата публикации

MULTI-TIME PROGRAMMABLE MEMORY

Номер: US20140048867A1
Автор: LIM Khee Yong, Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2, x is a whole number greater or equal to 1. A transistor can interchange between a select transistor and a storage transistor. 1. A device comprising:a substrate; and{'sup': 'x', 'a fin structure disposed on the substrate, the fin structure serves as a common body of n transistors, the transistors comprise separate charge storage layers and gate dielectric layers, the charge storage layers disposed over a top surface of the fin structure and the gate dielectric layers disposed on sidewalls of the fin structure, wherein n=2, x is a whole number greater or equal to 1, wherein a transistor can interchange between a select transistor and a storage transistor.'}2. The device in wherein the device is a multi-bit memory cell with n number of bits.3. The device in wherein the transistor comprises n number of gates claim 1 , a gate can interchange between a select gate and a control gate.4. The device in wherein the gate comprises a gate electrode which wraps around the fin structure.5. The device in wherein the gate comprises first and second sub-gates which are separated by sidewalls of the fin structure.6. The device in comprises doped regions in the fin structure adjacent to the gate.7. The device in wherein the charge storage layers comprise an oxide-nitride-oxide stack.8. A method of forming a device comprising:providing a substrate; and{'sup': 'x', 'forming a fin structure disposed on the substrate, the fin structure serves as a common body of n transistors, the transistors comprise separate charge storage layers and gate dielectric layers, the charge storage layers ...

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Номер записи: 38
06-03-2014 дата публикации

FIN-TYPE MEMORY

Номер: US20140061576A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. 1. A method of forming a device comprising:providing a substrate prepared with a lower electrode level with bottom electrodes;forming fin stack layers on the lower electrode level;forming spacers on top of the fin stack layers, wherein the spacers have a width which is less than a lithographic resolution;patterning the fin stack layers using the spacers as a mask to form fin stacks, the fin stacks contacting the bottom electrodes;forming an interlevel dielectric (ILD) layer on the substrate, filling spaces around the fin stacks; andforming an upper electrode level on the ILD layer, the upper electrode level having top electrodes in contact with the fin stacks, the electrodes and fin stacks form one or more fin-type memory cells.2. The method of comprises forming dielectric liner lining sides of the fin stacks and top of the lower electrode level.3. The method of wherein forming the spacers comprises:forming a hard mask over the fin stack layers;patterning the hard mask; andforming the spacers on sides of the hard mask.4. The method of wherein patterning the fin stack layers using the spacers form first and second fin stacks.5. The method of comprises forming a dielectric liner on the substrate lining sides of the fin ...

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Номер записи: 39
13-03-2014 дата публикации

NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR

Номер: US20140070159A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. 1. A method comprising:defining a shallow trench isolation (STI) region in a substrate;implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate;forming a hardmask on the active areas;removing a top portion of the STI region to form a cavity;forming an RRAM liner on side and bottom surfaces of the cavity;forming a top electrode in the cavity;removing a portion of the hardmask to form spacers on opposite sides of the cavity; andimplanting a dopant of the second polarity in a portion of each active area remote from the cavity.2. The method according to claim 1 , wherein the bottom surface of the cavity is above a top surface of the band of a second polarity.3. The method according to claim 1 , comprising forming the active areas with a shallow implant and implanting the dopant of the second polarity in each active area using multiple energies.4. The method according to claim 3 , comprising activating all of the dopants after ...

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Номер записи: 40
01-01-2015 дата публикации

SIMPLE AND COST-FREE MTP STRUCTURE

Номер: US20150001608A1
Автор: KOO Jeoung Mo, QUEK Elgin Kiok Boone, Shum Danny, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells. 1. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:a substrate;first and second wells disposed in the substrate;a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region; anda control gate disposed over the first well, wherein the control gate is coupled to the floating gate and the control and floating gates comprise the same gate layer extending across the first and the second wells.2. The memory cell of wherein the first well is of a first polarity type and the second well is of a second polarity type different from the first polarity type.3. The memory cell of claim 2 , wherein the first well is an n-type well and the second well is a p-type well claim 2 , wherein each of the floating gate and the select gate comprises an n-type metal-oxide-semiconductor (NMOS) claim 2 , and wherein the control gate comprises an n-type capacitor.4. The memory cell of claim 3 , wherein the memory cell is programmable by Flowler-Nordheim (FN) tunneling effect or channel hot electron (CHE) injection.5. The memory cell of claim 3 , wherein the memory cell is erasable by FN tunneling effect.6. The memory cell of claim 3 , wherein an area ratio between the control gate and the floating gate is 0.8:0.2 claim 3 , wherein a ...

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Номер записи: 41
01-01-2015 дата публикации

INTEGRATED CIRCUITS HAVING IMPROVED SPLIT-GATE NONVOLATILE MEMORY DEVICES AND METHODS FOR FABRICATION OF SAME

Номер: US20150001610A1
Автор: LIM Khee Yong, Quek Elgin, Zhang Zufa
Принадлежит:

Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate. 1. A method for fabricating an integrated circuit comprising:forming a source/drain region in a semiconductor substrate;forming a charge storage structure overlying the semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity overlying the source/drain region;forming a control gate in the interior cavity;forming a first select gate overlying the semiconductor substrate and adjacent the first sidewall, wherein a first memory cell is formed by the control gate and the first select gate; andforming a second select gate overlying the semiconductor substrate and adjacent the second sidewall, wherein a second memory cell is formed by the control gate and the second select gate.2. The method of further comprising:forming a first drain/source region in the semiconductor substrate adjacent the first select gate; andforming a second drain/source region in the semiconductor substrate adjacent the second select gate.3. The method of further comprising:forming a first control gate channel in the semiconductor substrate adjacent the first sidewall;forming a second control gate channel in the semiconductor substrate adjacent the second sidewall;forming a ...

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Номер записи: 42
04-01-2018 дата публикации

FIN-BASED NONVOLATILE MEMORY STRUCTURES, INTEGRATED CIRCUITS WITH SUCH STRUCTURES, AND METHODS FOR FABRICATING SAME

Номер: US20180006158A1
Автор: LIM Khee Yong, Quek Kiok Boone Elgin, Tsai Ming-Tsang
Принадлежит:

Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure. 1. An integrated circuit comprising:a substrate; and a primary fin structure, a first adjacent fin structure and a second adjacent fin structure laterally extending in parallel over the substrate, wherein the primary fin structure includes a source region, a channel region, and a drain region, wherein the first adjacent fin structure includes a first program/erase gate, and wherein the second adjacent fin structure includes a second program/erase gate;', 'a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure;', 'a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure; and', 'a control gate adjacent the primary fin structure., 'a dual-bit nonvolatile memory (NVM) structure overlying the substrate and including2. The integrated circuit of wherein the primary fin structure is located between the first adjacent fin structure and the second adjacent fin structure.3. The integrated circuit of wherein the control gate includes a first control ...

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Номер записи: 43
08-01-2015 дата публикации

DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF

Номер: US20150008528A1
Автор: CHONG Yung Fu, CHU Sanford, Quek Elgin, Tan Shyue Seng, TEO Lee Wee
Принадлежит:

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. 1. A method of forming a device comprising:providing a substrate;forming a gate structure over the substrate;forming first and second diffusion regions in the substrate on opposed sides of the gate structure; andforming a diffusion barrier having cavities in the substrate in between the first and second diffusion regions, wherein the diffusion barrier is formed immediately below a channel region which is disposed below the gate structure.2. The method of wherein the diffusion barrier is formed at a depth corresponding to lower portions of the first and second diffusion regions.3. The method of wherein forming the diffusion barrier comprises:providing a mask on top of the substrate, the mask comprises a cavity that exposes a portion of a top surface of the substrate of which the gate structure is to be formed;implanting an implant medium in the portion exposed by the cavity to form an implant region below a portion of the substrate which forms the channel region; andannealing the implant region to form the cavities.4. The method of wherein the mask comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.5. The method of wherein the mask comprises a polymer-based photoresist material.6. The method of wherein the implant medium comprises He claim 3 , hydrogen claim 3 , argon atoms or a combination thereof.7. The method of wherein implanting the implant medium is performed at an energy in the range of from around 2 keV to around 100 keV and at a dose of around 1×10to around 5×10cm.8. The method of wherein forming the gate structure comprises:forming a gate dielectric layer over the exposed portion of the top surface of the ...

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Номер записи: 44
14-01-2021 дата публикации

Nanogap sensors and methods of forming the same

Номер: US20210010997A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Shyue Seng Tan, Xinshu CAI
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.

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Номер записи: 45
09-01-2020 дата публикации

SELECTIVE SHIELDING OF AMBIENT LIGHT AT CHIP LEVEL

Номер: US20200013908A1
Автор: LIM Khee Yong, NAIR Rajesh, Quek Kiok Boone Elgin, SEET CHIM SENG, TAN Juan Boon, YI Wanbing
Принадлежит:

A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad. 1. A semiconductor device comprising:a substrate;at least one photo-detecting region formed in the substrate;at least one bond pad on the substrate;a first passivation layer over the substrate and over step portions at edges of the bond pad;a trench having sidewalls and a bottom surface in the substrate;a light shielding layer over the first passivation layer covering the substrate and the step portions at the edges of the bond pad and covering the trench sidewalls, wherein portions of the light shielding layer are removed forming end portions thereof at the photo-detecting region, at the step portions at the edges of the bond pad and at the bottom surface of the trench;a second passivation layer over the light shielding layer; anda third passivation layer over the second passivation layer and covering the end portions of the light shielding layer at the photo-detecting region and at the step portions at the edges of the bond pad.2. The device of claim I wherein the device is un-encapsulated and permits the photo-detecting region to be exposed to visible light.3. The device of claim I wherein the light shielding layer is electrically isolated by the first , ...

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Номер записи: 46
03-02-2022 дата публикации

COMPACT MEMORY CELL WITH A SHARED CONDUCTIVE WORD LINE AND METHODS OF MAKING SUCH A MEMORY CELL

Номер: US20220037348A1
Автор: Quek Kiok Boone Elgin, Sun Yongshun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells. 1. A device , comprising:a semiconductor substrate having an upper surface;a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate and a first gate cap above the first memory gate;a first sidewall spacer positioned adjacent the first memory gate;a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate and a second gate cap above the second memory gate; anda second sidewall spacer positioned adjacent the second memory gate;a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells, wherein an upper surface of the conductive word line structure is above an upper surface of the first gate cap and an upper surface of the second gate cap,a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first sidewall spacer; anda second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second sidewall spacer.2. The device of claim 1 , wherein:the first sidewall ...

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Номер записи: 47
03-02-2022 дата публикации

COMPACT MEMORY CELL WITH A SHARED CONDUCTIVE SELECT GATE AND METHODS OF MAKING SUCH A MEMORY CELL

Номер: US20220037349A1
Автор: Quek Kiok Boone Elgin, Sun Yongshun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells. 1. A device , comprising:a semiconductor substrate having an upper surface;a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate;a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate; anda conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.2. The device of claim 1 , further comprising:a first sidewall spacer positioned adjacent the first memory gate; anda second sidewall spacer positioned adjacent the second memory gate, wherein the conductive select gate structure physically contacts both the first and second sidewall spacers.3. The device of claim 1 , further comprising:a first doped region in the semiconductor substrate, wherein the first doped region functions as a source line for the first and second memory cells; anda second doped region in the semiconductor substrate, wherein the second doped region functions as a bit line for the first and second memory cells.4. The device of claim 1 , further comprising:a layer of insulating material positioned between a bottom surface of the conductive select gate structure and the upper surface of the semiconductor substrate;a first gate cap positioned above the ...

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Номер записи: 48
28-01-2016 дата публикации

RESISTIVE MEMORY DEVICE

Номер: US20160028009A1
Автор: QUEK Elgin Kiok Boone, SUN YUAN, Tan Shyue Seng, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors. 1. A method for forming a device comprising:providing a substrate prepared with a lower cell dielectric layer with gate conductors disposed in a first direction, the gate conductors separated the lower cell dielectric layer;forming a body unit conductor on the lower cell dielectric layer and gate conductors, wherein the body unit conductor is disposed along a second direction and traverses the gate conductors;forming memory element conductors on the body unit and lower cell dielectric layer, the memory element conductors are disposed along the first direction over the gate conductors; andforming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and memory element conductors, the upper cell dielectric layer isolating the memory element conductors.2. The method of wherein the gate conductors have a planar surface with the lower cell dielectric layer.3. The method of wherein:the gate conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating gate conductor mesas;the body unit conductor is disposed on the gate conductor mesas, creating body mesas; andforming memory element conductors on the body mesas.4. The method of wherein:the gate conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating gate conductor recesses;the body unit conductor is disposed on the lower cell ...

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Номер записи: 49
04-02-2016 дата публикации

FINFET WITH STRESSORS

Номер: US20160035873A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит:

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. 1. A device comprising:a substrate prepared with a dielectric layer on its top surface;a fin structure disposed on the substrate in the dielectric layer, wherein the fin structure includes a bottom portion and a top portion, the top portion extending above a top surface of the dielectric layer;a gate traversing the fin structure;S/D regions in the fin structure adjacent to the gate;a channel between the S/D regions below the gate; and a first portion and a second portion above the first portion, and', 'a feature which reduces junction capacitance, wherein the feature is disposed partially beneath the gate and separating the first and second portions of the fin structure., 'a first stressor to cause the channel to have a first strain to improve carrier mobility, wherein the fin structure comprises'}2. The device of wherein the feature comprises a dielectric material.3. The device of wherein the dielectric material comprises a material which can be selectively removed with respect to the dielectric layer on the substrate.4. The device of wherein the first stressor is disposed in the first portion of the fin structure to cause the channel to have the first strain from below the channel.5. The device of wherein the first stressor comprises S/D stressors disposed on the S/D regions to cause the channel to have the first strain from above the channel.6. The device of wherein the first stressor comprises embedded raised S/D stressors disposed in recesses in the S/D regions to cause the channel to have the ...

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Номер записи: 50
01-02-2018 дата публикации

FIN SELECTOR WITH GATED RRAM

Номер: US20180033963A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A phase-change random access memory (PCRAM) comprising:a semiconductor substrate;a heater layer formed on the semiconductor substrate, the heater layer and the semiconductor substrate forming a fin-like structure;an interlayer dielectric (ILD) formed on side surfaces of the fin-like structure;{'sub': 2', '2', '5, 'a GeSbTe(GST) material formed in contact with the heater layer; and'}a top electrode formed on the GST layer, to form the PCRAM.2. The PCRAM according to claim 1 , comprising:a hardmask on the heater layer, the GST layer on a top surface of the ILD on each side of the fin-like structure and on each side surface of the heater layer and the hardmask, and a top electrode on each side of the fin-like structure; orthe GST layer on the heater layer, and the top electrode over the GST layer and the ILD on each side of the fin-like structure.3. The PCRAM according to claim 1 , wherein the heater layer comprises: TaN claim 1 , TiN claim 1 , titanium tungsten (TiW) claim 1 , titanium silicon nitride (TiSiN) claim 1 , or tantalum silicon nitride (TaSiN) claim 1 , and formed to a thickness of 3 to 20 nm ...

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Номер записи: 51
24-02-2022 дата публикации

SINGLE WELL ONE TRANSISTOR AND ONE CAPACITOR NONVOLATILE MEMORY DEVICE AND INTEGRATION SCHEMES

Номер: US20220059554A1
Автор: CAI Xinshu, Quek Kiok Boone Elgin, TAN Juan Boon, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate. 1. A nonvolatile memory device comprising:an active region surrounded by an isolation structure;a floating gate having a first end, a second end opposite to the first end, a middle portion between the first end and the second end, a first side adjacent to the middle portion and a second side opposite to the first side, wherein the middle portion is over the active region, and the first end and the second end of the floating gate are over the isolation structure;a first doped region in the active region adjacent to the first side of the floating gate and a second doped region in the active region adjacent to the second side of the floating gate; anda first capacitor over the floating gate, wherein a first electrode of the first capacitor is electrically coupled to the floating gate.2. The nonvolatile memory device of claim 1 , wherein an area of the first capacitor is at least equal to an area of the floating gate.3. The nonvolatile memory device of claim 1 , wherein an area of the first capacitor is larger than an area of the floating gate.4. The nonvolatile memory device of further comprising:a second capacitor, wherein a first electrode of the second capacitor is over the isolation ...

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Номер записи: 52
07-02-2019 дата публикации

INCREASED GATE COUPLING EFFECT IN MULTIGATE TRANSISTOR

Номер: US20190043991A1
Автор: Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A non-volatile memory (NVM) device and a method for forming the NVM device are presented. The NVM device includes a substrate having a device region, a gate stack having a floating gate (FG) and a control gate (CG) over the device region, and source/drain (S/D) regions adjacent to the sidewalls of the gate. The FG includes a FG dielectric and a FG electrode. The CG includes a composite CG dielectric and a CG electrode. The composite CG dielectric includes a first CG dielectric and a ferroelectric second CG dielectric. The ferroelectric second CG dielectric is configured to have a negative capacitance to increase gate coupling ratio of the NVM device. 1. A device comprising:a substrate defined with a device region; [ a FG dielectric disposed over the substrate, and', 'a FG electrode disposed over the FG dielectric, and, 'a floating gate (FG), the FG includes'}, [ a first CG dielectric disposed over the FG electrode, the first CG dielectric comprising a silicon oxide gate dielectric, and', 'a second CG dielectric disposed over the first CG dielectric, the second CG dielectric comprises a ferroelectric second CG dielectric, and, 'a composite CG dielectric comprising'}, 'a CG electrode disposed over the ferroelectric second CG dielectric;, 'a control gate (CG), the CG includes'}], 'a gate stack comprising'}a first source/drain (S/D) region disposed adjacent to the first sidewall of the gate stack;a second S/D region disposed adjacent to the second gate sidewall of the second gate; andwherein the ferroelectric second CG dielectric is configured to have a negative capacitance to increase gate coupling ratio.2. The device of wherein the first CG dielectric comprises an oxide-nitride-oxide combo (ONO) dielectric.3. The device of wherein{'sub': 'top', 'the first CG dielectric produces a parasitic capacitance C;'}{'sub': 'fe', 'the ferroelectric second CG dielectric produces a parasitic ferroelectric capacitance C;'}{'sub': 'bottom', 'the FG dielectric produces a parasitic ...

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Номер записи: 53
22-05-2014 дата публикации

COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL

Номер: US20140138603A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines. 1. A memory cell comprising:a substrate;a bottom electrode disposed on the substrate;a doped layer disposed on the substrate, wherein the doped layer and bottom electrode form a diode;a storage layer; anda top electrode, wherein the storage layer is disposed between the top and bottom electrodes on the substrate.2. The device in claim 1 , wherein the storage layer comprises variable resistance material.3. The device in claim 1 , wherein the bottom electrode comprises a conductive word line conductively coupled to the diode.4. The device in claim 1 , wherein the doped layer comprises a first polarity type dopants which is opposite to a second polarity type dopants of the bottom electrode.5. The device in claim 1 , wherein the doped layer is disposed on the bottom electrode.6. A RRAM device claim 1 , comprising:a substrate with an active region;a conductive bit line electrode;a variable resistance layer positioned between said conductive bit line electrode and said active region;a diffusion region in the substrate in the active region positioned under said variable resistance layer;a first semiconductor layer having first polarity type dopants; anda second semiconductor layer having second polarity type dopants wherein said first semiconductor layer is positioned between said conductive bit line electrode and said second semiconductor material.7. The device in claim 6 , wherein said first and second semiconductor layers form a diode device coupled to said bit line electrode.8. The device in claim 6 , wherein said diffusion region comprises a conductive word line conductively coupled to said variable resistance layer.9. The device in claim 6 , wherein said first ...

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Номер записи: 54
22-05-2014 дата публикации

COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY

Номер: US20140138605A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. 1. A method comprising:defining a shallow trench isolation (STI) region in a substrate;implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a channel of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each channel of second polarity at the surface of the substrate;forming an RRAM liner on the active area and STI region;forming a sacrificial top electrode on the RRAM liner;forming spacers on opposite sides of the sacrificial top electrode and RRAM liner;implanting a dopant of the second polarity in the active area on opposite sides of the sacrificial top electrode;forming a silicon oxide adjacent the spacers;removing at least a portion of the sacrificial top electrode, forming a cavity;forming inner spacers, adjacent the spacers, in the cavity; andforming a top electrode in the cavity.2. The method according to claim 1 , comprising forming the STI regions extending in a first direction and forming the RRAM liner extending in a second direction perpendicular to the first ...

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Номер записи: 55
03-03-2016 дата публикации

INTEGRATED CIRCUITS WITH FINFET NONVOLATILE MEMORY

Номер: US20160064398A1
Автор: QUEK Elgin Kiok Boone, Shum Danny, TAN Shyue Seng Jason, Toh Eng Huat
Принадлежит:

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection. 1. A method of producing an integrated circuit comprising:forming a first fin overlying a substrate, wherein the first fin extends in a first direction, and wherein the first fin comprises a first fin left end;forming a second fin overlying the substrate, wherein the second fin extends in a second direction different than the first direction, and wherein the second fin intersects the first fin at a fin intersection;forming a tunnel dielectric adjacent to the first fin;forming a floating gate adjacent to the first fin such that the tunnel dielectric is positioned between the floating gate and the first fin;forming an interpoly dielectric adjacent to the floating gate;forming a control gate adjacent to the interpoly dielectric such that the interpoly dielectric is positioned between the floating gate and the control gate; andremoving the control gate, the interpoly dielectric, the floating gate, and the tunnel dielectric from over the first fin except for at a floating gate position, wherein the floating gate position is between the first fin left end and the fin intersection.2. The method of further comprising:forming a ...

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Номер записи: 56
04-03-2021 дата публикации

Memory cells with extended erase gate, and process of fabrication

Номер: US20210066324A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Shyue Seng Tan, Xinshu CAI
Принадлежит: 198703584k, GLOBALFOUNDRIES SINGAPORE PTE LTD

A flash memory device is provided. The device comprises a substrate and a source region in the substrate. A first gate stack is positioned above the substrate and adjacent to the source region. A dual function gate structure having an upper portion and a lower portion is positioned above the source region. The upper portion of the dual function gate structure overlaps the first gate stack and the lower portion is adjacent to the first gate stack. A second gate is positioned above the substrate on an opposite side of the first gate stack from the dual function gate. A drain region is in the substrate adjacent to the second gate.

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Номер записи: 57
12-03-2015 дата публикации

FINFET

Номер: US20150069512A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит:

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance. 1. A device comprising:a substrate having a device region, wherein the device region comprises a doped isolation well;a dielectric layer disposed on the substrate, wherein the dielectric layer comprises a non selectively etched dielectric top surface;a fin structure disposed on the substrate in the dielectric layer, wherein the fin structure comprises a bottom device portion and a top device portion, the top device portion extends above the non-selectively etched dielectric top surface;a gate structure disposed on the dielectric layer, wherein the gate structure traverses the fin structure; andfirst and second source/drain (S/D) regions disposed in the fin structure adjacent to the gate structure.2. The device of wherein the dielectric layer comprises silicon nitride or silicon oxide.3. The device of comprising SD contact pads which are coupled to ends of the fin structure.4. The device of wherein the top device portion of the fin structure determines a height of a device in the device region and the non-selectively etched dielectric top surface reduces height variation of fin structures across the substrate.5. The device of comprising a dielectric hard mask disposed on the top device portion of the fin structure.6. The device of wherein:the dielectric hard mask is disposed between the gate structure and the top device portion of the fin structure; andthe dielectric hard mask separates a first gate dielectric layer from a second gate dielectric layer.7. The device of comprising a counter doped region disposed below ...

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Номер записи: 58
09-03-2017 дата публикации

GATE-GROUNDED METAL OXIDE SEMICONDUCTOR DEVICE

Номер: US20170069619A1
Автор: Quek Kiok Boone Elgin, Toh Eng Huat
Принадлежит:

A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Land reduce beta, increasing performance of the ESD protection. 1. A method of forming a device comprising:providing a substrate with a device region;forming a gate on the substrate in the device region;forming a base extension region having second polarity type dopants adjacent to a second side of the gate;forming first and second source/drain (S/D) regions, wherein the first and second S/D regions comprise first polarity type dopants, the first and second S/D regions are disposed adjacent to first and second sides of the gate, wherein forming the second S/D region comprises forming an elevated second S/D region disposed over the base extension region; andforming interconnections between the second S/D region and gate with ground to form a gate-grounded metal oxide semiconductor (GGMOS) device.2. The method of wherein forming the elevated second S/D region comprises:forming a second S/D epitaxial layer on the device region adjacent to the second side of the gate over the base extension region; anddoping the second S/D epitaxial layer with first polarity type dopants.3. The method of wherein forming the base extension region forms an elevated base extension region adjacent to the second side of the gate comprising:forming a base extension epitaxial layer on the device region adjacent to the second side of the gate;doping the base extension epitaxial layer with second polarity type dopants; andwherein the elevated second S/D region is formed over the elevated base extension region.4. The method wherein doping the base extension S/D epitaxial layer comprises ion implantation.5. The method of wherein forming the base extension region forms a non-elevated base extension region ...

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Номер записи: 59
09-03-2017 дата публикации

Integrated circuits having tunnel transistors and methods for fabricating the same

Номер: US20170069753A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.

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Номер записи: 60
17-03-2016 дата публикации

Selector-resistive random access memory cell

Номер: US20160079310A1
Автор: Elgin Kiok Boone Quek, Eng Huat Toh, Shyue Seng Tan, Xuan Anh TRAN, Yuan Sun
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.

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Номер записи: 61
24-03-2022 дата публикации

Split gate flash memory cells with a trench-formed select gate

Номер: US20220093765A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Shyue Seng Tan, Xinshu CAI
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.

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Номер записи: 62
12-06-2014 дата публикации

NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR

Номер: US20140158970A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. 1. A device comprising:a substrate;a well of a first polarity in the substrate;a shallow trench isolation (STI) region formed in the substrate extending partially into the well;bands of a second polarity in the substrate, over the well, at opposite sides of the STI region;an area of the first polarity at a top surface of the substrate over each band;an area of the second polarity in the substrate over each band, adjacent each area of the first polarity and remote from the STI region;a recess in a top surface of a portion of the STI region, wherein a bottom surface of the recess is above a top surface of the band;a resistive random access memory (RRAM) liner on side and bottom surfaces of the recess; anda top electrode in the recess.2. The device according to claim 1 , wherein the RRAM liner comprises an oxide of a transition metal.3. The device according to claim 1 , wherein a thickness of the RRAM liner is 3 nm to 900 nm.4. The device according to claim 1 , wherein the top electrode comprises a transition metal claim 1 , titanium nitride (TiN) claim 1 , TiN/Ti claim 1 , or polysilicon.5. The device according to claim 1 , further comprising silicon nitride (SiN) spacers ...

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Номер записи: 63
22-03-2018 дата публикации

MULTI-TIME PROGRAMMABLE (MTP) MEMORY CELLS, INTEGRATED CIRCUITS INCLUDING THE SAME, AND METHODS FOR FABRICATING THE SAME

Номер: US20180083008A1
Автор: Guo Pengfei, Quek Kiok Boone Elgin, Tan Shyue Seng
Принадлежит:

Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate including a CMOS device region and a DMOS device region. The MTP memory cell further includes a high voltage (HV) p-well in the CMOS device region and in the DMOS device region of the semiconductor substrate. An n-channel transistor is disposed over the HV p-well in the CMOS device region and includes a transistor gate. Also, the MTP memory cell includes an n-well overlying the HV p-well in the DMOS region of the semiconductor substrate. An n-channel capacitor is disposed over the n-well and includes a capacitor gate. The capacitor gate is coupled to the transistor gate. 1. A multi-time programmable (MTP) memory cell comprising:a semiconductor substrate including a complementary metal oxide semiconductor (CMOS) device region and a double-diffused metal oxide semiconductor (DMOS) device region;a high voltage (HV) p-well in the CMOS device region and in the DMOS device region of the semiconductor substrate;an n-channel transistor disposed over the HV p-well in the CMOS device region and including a transistor gate;a first diffusion region and a second diffusion region in the CMOS device region;an n-well overlying the HV p-well in the DMOS region of the semiconductor substrate;an n-channel capacitor disposed over the n-well in the DMOS region and including a capacitor gate, wherein the capacitor gate is coupled to the transistor gate; anda capacitor diffusion region in the DMOS region, wherein the n-channel capacitor gate is located between the capacitor diffusion region and the CMOS device region, and wherein the first diffusion region, the second diffusion region, and the capacitor diffusion region are n-doped regions.2. The MTP memory cell of wherein the n-channel transistor includes a first lightly doped diffusion (LDD) region located in the HV p ...

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Номер записи: 64
24-03-2016 дата публикации

NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY CROSSBAR DEVICES WITH MAXIMIZED MEMORY ELEMENT DENSITY AND METHODS OF FORMING THE SAME

Номер: US20160087197A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

Non-volatile resistive random access memory crossbar devices and methods of fabricating the same are provided herein. In an embodiment, a non-volatile resistive random access memory crossbar device includes a crossbar array including a bitline and a wordline. A hardmask that includes dielectric material is disposed over the bitline. The hardmask and the bitline include a first sidewall. A memory element layer and a selector layer are disposed in overlying relationship on the first sidewall of the bitline and hardmask. The memory element layer and a selector layer are further disposed between the bitline and the wordline, to form a first memory element and selector pair. 1. A non-volatile resistive random access memory crossbar device comprising:a crossbar array comprising a bitline and a wordline;a hardmask comprising dielectric material and disposed over the bitline, wherein the hardmask and the bitline comprise a first sidewall; anda memory element layer and a selector layer disposed in overlying relationship on the first sidewall of the bitline and hardmask, and further disposed between the bitline and the wordline, to form a first memory element and selector pair.2. The non-volatile resistive random access memory crossbar device of claim 1 , wherein the hardmask and the bitline further comprise a second sidewall on an opposing side thereof from the first sidewall claim 1 , and wherein the memory element layer and the selector layer are further disposed over the second sidewall of the bitline and hardmask.3. The non-volatile resistive random access memory crossbar device of claim 2 , wherein the memory element layer is further disposed over a top surface of the hardmask.4. The non-volatile resistive random access memory crossbar device of claim 3 , wherein the memory element layer is continuous over the first sidewall claim 3 , the top surface of the hardmask claim 3 , and the second sidewall claim 3 , and wherein the selector layer is discontinuous over the top ...

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Номер записи: 65
19-06-2014 дата публикации

Floating body cell

Номер: US20140167161A1
Автор: Elgin Quek, Eng Huat Toh, Shyue Seng Tan
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.

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Номер записи: 66
31-03-2016 дата публикации

DOUBLE GATED FLASH MEMORY

Номер: US20160093630A1
Автор: Quek Elgin, Tan Shyue Seng (Jason), Toh Eng Huat
Принадлежит:

A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

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Номер записи: 67
21-03-2019 дата публикации

METHOD FOR MANUFACTURING COMPACT OTP/MTP TECHNOLOGY

Номер: US20190088783A1
Автор: QUEK Elgin Kiok Boone, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate. 1. A method comprising:providing a substrate having a buried oxide (BOX) layer formed over the substrate;forming a cavity between the substrate and the BOX layer and between a pair of isolation structures formed on the substrate;forming a silicon-on-insulator (SOI) region over a portion of the BOX layer between the pair of isolation structures; forming first and second replacement metal gates (RMGs), laterally separated, over and perpendicular to the SOI region;recessing the SOI region between the first and second RMGs down to the BOX layer, forming at least one trench;forming at least one third RMG perpendicular to the SOI region in the at least one trench;forming a source/drain (S/D) region in the SOI region adjacent to the first and second RMGs, respectively, remote from the at least one third RMG;utilizing each of the first and second RMGs as a word line (WL);utilizing the at least one third RMG as a source line (SL) or connecting a SL to the S/D region; andconnecting a bit line (BL) to the S/D region or the at least one third RMG.2. The method according to claim 1 , comprising forming the first claim 1 , second claim 1 , and at least one third RMGs by: ...

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Номер записи: 68
16-04-2015 дата публикации

MEMORY CELL WITH DECOUPLED CHANNELS

Номер: US20150104915A1
Автор: Quek Elgin, Tan Shyue Seng, TANG Yanzhe, Toh Eng Huat
Принадлежит:

A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. 1. A method of fabricating a device comprising:providing a substrate prepared with a memory cell region; and forming an access transistor and a storage transistor, wherein the access transistor includes first and second access source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions, wherein the access and storage transistors are coupled in series and the second S/D regions being a common S/D region,', 'forming an erase gate over the common S/D region, and', 'forming a program gate over the first storage S/D region, wherein such an arrangement of the memory cell decouples a program channel and an erase channel., 'forming a memory cell on the memory cell region, wherein forming the memory cell comprises'}2. The method of wherein forming the access and storage transistor comprises:forming a first gate dielectric layer on a top surface of the substrate;forming a first gate electrode layer on the first gate dielectric layer;forming an intergate dielectric layer on the first gate electrode layer;patterning the intergate dielectric layer, wherein portions of the intergate dielectric layer are removed from regions of the substrate where access gates of the access transistors are formed;forming a second gate electrode layer over the first gate electrode and intergate dielectric layers; andpatterning the first ...

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Номер записи: 69
12-04-2018 дата публикации

MULTI-TIME PROGRAMMABLE DEVICE

Номер: US20180102178A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, Zheng Ping
Принадлежит:

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. 1. A memory device comprising:a substrate comprising a device region and first and second isolation regions surrounding the device region; and a gate having a gate electrode disposed on a programmable resistive layer, wherein the gate electrode covers an entire top surface of the programmable resistive layer, the programmable resistive layer is disposed over a transistor channel region having first and second channel sub-regions in the device region, wherein a first portion of the programmable resistive layer overlaps the first channel sub-region and a second portion of the programmable resistive layer overlaps the second channel sub-region,', 'wherein the first portion of the programmable resistive layer directly contacts a top surface of the substrate, and', 'wherein the second portion of the programmable resistive layer is more susceptible for programming relative to the first portion of the programmable resistive layer., 'a multi-time programmable (MTP) memory cell having a single transistor, wherein the transistor includes'}2. The memory device of comprising a buffer layer ...

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Номер записи: 70
26-03-2020 дата публикации

INCREASED GATE COUPLING EFFECT IN MULTIGATE TRANSISTOR

Номер: US20200098769A1
Автор: Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively. 1. A device structure comprising:a substrate including a device region; anda multi-gate transistor in the device region, the multi-gate transistor including a first gate, a second gate adjacent to the first gate, a first gate dielectric and a second gate dielectric between the first gate and the substrate, and a third gate dielectric between the second gate and the substrate,wherein the second gate dielectric is comprised of a ferroelectric material.2. The device structure of wherein the ferroelectric material is barium-titanium oxide.3. The device structure of wherein the ferroelectric material is doped hafnium oxide containing silicon.4. The device structure of wherein the ferroelectric material is doped hafnium oxide containing aluminum.5. The device structure of wherein the first gate dielectric and the third gate dielectric are silicon oxide.6. The device structure of wherein the first gate is comprised of metal gate electrode material.7. The device structure of wherein the first gate dielectric is thinner than the third gate dielectric.8. The device structure of wherein the first gate dielectric is positioned between the ...

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Номер записи: 71
26-03-2020 дата публикации

Magnetoresistive random access memory structures having two magnetic tunnel junction elements

Номер: US20200098822A1
Автор: Bin Liu, Eng Huat Toh, Kiok Boone Elgin Quek
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Magnetoresistive random access memory (MRAM) structures and arrays, methods for fabricating MRAM structures and arrays, and methods for operating MRAM structures and arrays are provided. An exemplary MRAM structure includes an access transistor having a source and a drain, a first magnetic tunnel junction (MTJ) element coupled to the source of the access transistor, and a second magnetic tunnel junction (MTJ) element coupled to the drain of the access transistor.

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Номер записи: 72
04-04-2019 дата публикации

SIDEWALL ENGINEERING FOR ENHANCED DEVICE PERFORMANCE IN ADVANCED DEVICES

Номер: US20190103474A1
Автор: Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A method of sidewall engineering with negative capacitance materials is disclosed. For example, the negative capacitance material is a ferroelectric material. The method includes providing a dielectric liner on the sidewall of the gate and providing a negative capacitance liner or spacer over the dielectric liner. In one embodiment, the dielectric liner is an oxide liner and the negative capacitance liner or spacer is a ferroelectric liner or spacer. The engineered negative capacitance liner or spacer enhances the gate-to-S/D region and gate-to-contact coupling and hence the device I-Iperformance is improved. 111-. (canceled)12. A method of forming a device comprising:forming a substrate with a device region;forming a gate and source/drain (S/D) regions in the device region; and forming a first dielectric spacer liner deposited on the sidewalls of the gate, and', 'forming a second dielectric spacer liner or layer on the first dielectric spacer liner, wherein the second dielectric spacer liner or layer comprises a second negative capacitance spacer liner or layer coupled with the S/D regions, the negative capacitance spacer liner or layer enhances gate-to-S/D region coupling between the gate and the S/D regions., 'forming one or more spacer units on sidewalls of the gate, wherein forming the one or more spacer units comprises'}13. The method of wherein forming the first dielectric liner comprises forming a first L-shaped oxide liner claim 12 , wherein the first L-shaped oxide liner is formed by chemical vapor deposition (CVD) or in situ stream generation (ISSG).14. The method of wherein forming the second negative capacitance spacer liner or layer comprises forming a second L-shaped ferroelectric liner claim 13 , wherein the second L-shaped ferroelectric liner is formed by atomic layer deposition (ALD) or physical vapor deposition (PVD).15. The method of wherein forming the one or more spacer units further comprise forming a dielectric spacer claim 14 , wherein the ...

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Номер записи: 73
21-04-2016 дата публикации

INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME

Номер: US20160111629A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer. 1. A method for fabricating a spin torque transfer magnetic random access memory integrated circuit comprising:forming a bottom electrode layer;forming a fixed layer over the bottom electrode layer;forming a silicon oxide layer over the fixed layer;forming a hardmask layer over the silicon oxide layer;forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layers;forming a conformal barrier layer along the sidewalls and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer;forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer; andforming a top electrode layer over the free layer.2. The method of claim 1 , wherein forming the bottom electrode layer comprises forming a material layer comprising tantalum or titanium.3. ...

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Номер записи: 74
20-04-2017 дата публикации

Low power embedded one-time programmable (otp) structures

Номер: US20170110465A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Ping Zheng, Yuan Sun
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

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Номер записи: 75
07-05-2015 дата публикации

FIN-TYPE MEMORY

Номер: US20150123068A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. 1. A device comprising:a substrate prepared with a lower electrode level with at least one bottom electrode;fin stacks disposed on and contacts the bottom electrodes at the lower electrode level;an interlevel dielectric (ILD) layer disposed on the substrate, the ILD layer fills spaces around the fin stacks; and the fin stacks comprise at least one secondary fin body and at least one main fin body disposed over and contacts the at least one secondary fin body, and', 'the at least one secondary fin body contacts the at least one bottom electrode while the at least one main fin body contacts the at least one top electrode., 'an upper electrode level disposed on the ILD layer, the upper electrode level having at least one top electrode in contact with the fin stacks, the electrodes and fin stacks form fin-type memory cells, wherein'}2. The device of wherein the at least one main fin body is coupled to its respective secondary fin body.3. The device of comprising dielectric liners lining sides of the fin stacks and top surface of the lower electrode level.4. The device of comprising an interfin dielectric (IFD) layer claim 2 , wherein the IFD layer fills the space between adjacent fin stacks.5. The device of wherein the IFD ...

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Номер записи: 76
18-04-2019 дата публикации

THYRISTOR RANDOM ACCESS MEMORY

Номер: US20190115350A1
Автор: QUEK Elgin Kiok Boone, SHUM Danny Pak-Chum, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. 1. A method of forming a device comprising:providing a substrate having a top surface, the substrate includes a cell region, the cell region is surrounded by a cell trench isolation region, the cell region is prepared with a first polarity type cell well, the cell well extends from the top surface of the substrate; and forming a gate dielectric layer lining a surface of the substrate and an upper portion of the gate trench,', 'forming a gate electrode layer on the substrate, the gate electrode layer covering the gate dielectric layer and filling the upper portion of the gate trench,', 'patterning the gate electrode and gate dielectric layers to form a gate in the cell region which protrudes above the top surface of the substrate from the gate trench,', 'forming first and second first self-aligned epitaxial layers on the substrate in the cell region by selective epitaxial growth, the first and second first self-aligned epitaxial layers comprise second polarity type first and second first self-aligned epitaxial layers, wherein the first and second first epitaxial layers abut the gate dielectric layer,', 'forming first and second gate sidewall spacers on opposing first and second gate sidewalls,', 'forming first and second second self- ...

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Номер записи: 77
18-04-2019 дата публикации

INCREASED GATE COUPLING EFFECT IN MULTIGATE TRANSISTOR

Номер: US20190115354A1
Автор: Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively. 110-. (canceled)11. A method of forming a device comprising:providing a substrate prepared with a device region; forming a first gate having first and second gate sidewalls,', 'forming a second gate having first and second gate sidewalls,', 'disposing a first source/drain (S/D) region adjacent to the first gate sidewall of the first gate,', 'disposing a second S/D region adjacent to the second gate sidewall of the second gate, and', 'disposing a negative capacitance element within the first gate, wherein the negative capacitance element reduces total overlap capacitance of the multi-gate transistor;, 'forming a multi-gate transistor in the device region, wherein forming the multi-gate transistor comprises'}forming an interlevel dielectric (ILD) layer on the substrate, wherein the ILD layer covering the multi-gate transistor; andforming first and second contacts in the ILD layer, wherein the first and second contacts are coupled to the first and second S/D regions.12. The method of claim 11 , wherein forming the device further comprises:forming a first terminal of the first gate, the first terminal of the first gate serves as ...

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Номер записи: 78
18-04-2019 дата публикации

Reduced capacitance coupling effects in devices

Номер: US20190115441A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Shyue Seng Tan
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

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Номер записи: 79
14-05-2015 дата публикации

MULTI-TIME PROGRAMMABLE DEVICE

Номер: US20150129975A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, Zheng Ping
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. 19-. (canceled)10. A method of forming a device comprising:providing a substrate comprising a device region prepared with first and second isolation regions surrounding the device region; forming a gate having first and second sidewalls disposed over a channel region in the substrate, the channel region comprises first and second sub-regions, the gate includes a gate electrode and gate dielectric comprising a programmable resistive layer disposed between the gate electrode and substrate, and the gate partially overlaps the second isolation region adjacent to the second sidewall of the gate; and', 'forming a heavily doped region of a first polarity type in the substrate in between the first isolation region and the first sidewall of the gate,', 'wherein the gate dielectric above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive layer above the other ...

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Номер записи: 80
27-05-2021 дата публикации

NON-VOLATILE MEMORY BIT CELLS WITH NON-RECTANGULAR FLOATING GATES

Номер: US20210159234A1
Автор: CAI Xinshu, Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat, Wang Lanxiang
Принадлежит:

Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape. 1. A structure for a non-volatile memory bit cell , the structure comprising:a field-effect transistor including a channel region and a first gate electrode positioned over the channel region; anda capacitor including a second gate electrode,wherein the second gate electrode is coupled to the first gate electrode to define a floating gate, and the first gate electrode has a non-rectangular shape.2. The structure of wherein the first gate electrode has a first gate length and a second gate length that is less than the first gate length.3. The structure of wherein the first gate electrode and the second gate electrode are positioned along a longitudinal axis claim 1 , and the first gate electrode includes a side surface that is angled relative to the longitudinal axis.4. The structure of wherein the first gate electrode and the second gate electrode are positioned along a longitudinal axis claim 1 , the first gate electrode includes a first side surface and a second side surface opposite to the first side surface claim 1 , the first side surface is angled relative to the longitudinal axis claim 1 , and the second side surface that is angled relative to the longitudinal axis.5. The structure of wherein the first gate electrode includes a side surface and a notch that extends into the side surface.6. The structure of wherein the notch has a rectangular shape.7. The structure of wherein the notch has a non-rectangular shape.8. The structure of wherein the notch has a V-shape.9. The structure of wherein the notch is positioned fully over the channel region.10. The structure of ...

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Номер записи: 81
12-05-2016 дата публикации

INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY HAVING INCREASED MEMORY CELL DENSITY AND METHODS FOR FABRICATING THE SAME

Номер: US20160133669A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

STT-MRAM integrated circuit and method for fabricating the same are disclosed. An integrated circuit includes a word line layer, a bit line layer, and an MRAM stack in contact with the bit line metal layer. The integrated circuit further includes a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer including conductivity-determining ions of a first type, and a second doped silicon layer in contact with the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer including conductivity-determining ions of a second type that is opposite the first type. Still further, the integrated circuit includes a third doped silicon layer in contact with the second doped silicon layer and a source line layer in electrical contact with the third doped silicon layer. 1. An integrated circuit comprising:a word line layer;a bit line layer;a magnetic random access memory (MRAM) stack in contact with the bit line metal layer;a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer comprising conductivity-determining ions of a first type;a second doped silicon layer in contact with the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer comprising conductivity-determining ions of a second type that is opposite the first type;a third doped silicon layer in contact with the second doped silicon layer; anda source line layer in electrical contact with the third doped silicon layer.2. The integrated circuit of claim 1 , wherein the third doped silicon layer comprises conductivity ions of the first type.3. The integrated circuit of claim 2 , wherein each of the word line layer claim 2 , bit line layer claim 2 , and source line layers comprise a metal material.4. The integrated circuit of claim 1 , wherein the source line layer comprises a third doped silicon layer in contact with the second doped silicon layer claim 1 , ...

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Номер записи: 82
11-05-2017 дата публикации

INTEGRATED CIRCUITS HAVING MULTIPLE GATE DEVICES WITH DUAL THRESHOLD VOLTAGES AND METHODS FOR FABRICATING SUCH INTEGRATED CIRCUITS

Номер: US20170133373A1
Автор: Quek Kiok Boone Elgin, Tan Shyue Seng
Принадлежит:

Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage. 1. A method for fabricating an integrated circuit , the method comprising:etching a semiconductor substrate to form a semiconductor fin structure with a first sidewall, a second sidewall opposite the first sidewall, and an upper surface;doping the semiconductor fin structure through the first sidewall to form a first doped region adjacent the first sidewall of the semiconductor fin structure;doping the semiconductor fin structure through the second sidewall to form a second doped region adjacent the second sidewall of the semiconductor fin structure, wherein the second doped region is doped differently from the first doped region;forming a first gate along the first sidewall of the semiconductor fin structure; andforming a second gate along the second sidewall of the semiconductor fin structure;wherein the first gate has a first threshold voltage and the second gate has a second threshold voltage different from the first threshold voltage.2. (canceled)3. The method of wherein:doping the semiconductor fin structure through the first sidewall to form the first doped region comprises performing a first implantation process and doping the semiconductor fin structure through the first sidewall and the semiconductor fin structure through the second ...

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Номер записи: 83
03-06-2021 дата публикации

ON-CHIP TEMPERATURE SENSING WITH NON-VOLATILE MEMORY ELEMENTS

Номер: US20210164845A1
Автор: LIU BIN, Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element. 1. A structure comprising:a first non-volatile memory element;a second non-volatile memory element; andtemperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.2. The structure of wherein the first non-volatile memory element and the second non-volatile memory element are resistive memory elements.3. The structure of wherein the first non-volatile memory element has a first electrical resistance claim 2 , and the second non-volatile memory element has a second electrical resistance that is less than the first electrical resistance.4. The structure of wherein the first non-volatile memory element has a first electrical resistance with a first temperature dependence claim 2 , and the second non-volatile memory element has a second electrical resistance with a second temperature dependence that exhibits a greater variation with increasing temperature than the first temperature dependence.5. The structure of wherein the first non-volatile memory element and the second non-volatile memory element each have either a low-resistance state or a high-resistance state when programmed claim 1 , the first non-volatile memory element has the high-resistance state claim 1 , and the second non-volatile memory element does not have either the low-resistance state or the high-resistance state.6. The structure of wherein the first non-volatile memory element and the second non-volatile memory element each have either a low-resistance state or a high-resistance state when programmed claim 1 , the first non-volatile memory element has the high-resistance state claim 1 , and the second non-volatile memory ...

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Номер записи: 84
28-05-2015 дата публикации

INTEGRATED CIRCUITS HAVING IMPROVED SPLIT-GATE NONVOLATILE MEMORY DEVICES AND METHODS FOR FABRICATION OF SAME

Номер: US20150145024A1
Автор: Elgin Quek Kiok Boone, LIM Khee Yong, Zufa Zhang
Принадлежит:

Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region. The integrated circuit also includes a control gate overlying the source/drain region. Further, the integrated circuit includes a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. 1. An integrated circuit comprising:a source/drain region in a semiconductor substrate;a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region;a control gate overlying the source/drain region; anda first select gate overlying the semiconductor substrate and adjacent the first sidewall, wherein a first memory cell is formed by the control gate and the first select gate.2. The integrated circuit of further comprising a first vertically oriented control gate channel region in the semiconductor substrate claim 1 , wherein the first sidewall of the charge storage structure is adjacent the first vertically oriented control gate channel region.3. The integrated circuit of wherein the first select gate is horizontally oriented.4. The integrated circuit of further comprising:a first drain/source region in the semiconductor substrate adjacent the first select gate; anda first channel in the semiconductor substrate between the source/drain region and the first drain/source region.5. The integrated circuit of further comprising:a first control gate channel in the semiconductor substrate adjacent the first sidewall; anda first select gate channel in the semiconductor substrate underlying the first select gate.61. The integrated circuit of wherein the charge storage structure comprises:a lower dielectric layer;a charge trapping layer ...

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Номер записи: 85
30-04-2020 дата публикации

Memory arrays and methods of forming the same

Номер: US20200135275A1
Автор: Kiok Boone Elgin Quek, Shyue Seng Tan, Xinshu CAI
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A device having at least one memory cell over a substrate is provided. The at least one memory cell includes a source region and a drain region in the substrate, and a first gate and a second gate over the substrate. The first and second gates are arranged between the source region and the drain region. The first and second gate are separated by an intergate dielectric. The first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell. The second gate comprises a floating gate and a control gate over the floating gate. The device further includes source/drain (S/D) contacts extending from the source region and the drain region. The source region and the drain region are coupled to either one of a source line (SL) or a bit line (BL) through the S/D contacts.

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Номер записи: 86
09-05-2019 дата публикации

SEMICONDUCTOR DEVICE WITH IMPROVED NARROW WIDTH EFFECT AND METHOD OF MAKING THEREOF

Номер: US20190140079A1
Автор: LIU Xinfu, Quek Kiok Boone Elgin, TAN Xueming Dexter
Принадлежит:

A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (V) implant is performed with a desired level of second polarity type dopants into the substrate. The Vimplant forms a Vadjust region to obtain a desired Vof a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the Vimplanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate. 1. A high voltage (HV) device comprising:a substrate prepared with a device isolation region, wherein the device isolation region defines a device region in the substrate;a device well disposed in the substrate within the device region, wherein the device well includes second polarity type dopants;{'sub': T', 'T, 'a threshold voltage (V) adjust region disposed at a top portion of the substrate in the device well, wherein the Vadjust region includes second polarity type dopants;'}a HV transistor gate comprising a gate electrode and a gate dielectric layer disposed on the substrate;first and second source/drain (S/D) regions comprising first polarity type dopants, wherein the first and second S/D regions are disposed within the device well and adjacent to sides of the HV transistor gate, wherein a channel region of the HV transistor gate is located under the HV transistor gate between the first and second S/D regions; anda diffusion suppression (DS) region comprising carbon, wherein the DS region traverses the channel region and the first and second S/D regions.2. The device of wherein:{'sub': 'T', 'the second polarity type dopants of the device well and Vadjust region ...

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Номер записи: 87
15-09-2022 дата публикации

NONVOLATILE MEMORY DEVICE WITH AN ERASE GATE OVERHANG AND INTEGRATION SCHEMES

Номер: US20220293614A1
Автор: CAI Xinshu, Quek Kiok Boone Elgin, Tan Shyue Seng
Принадлежит:

A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged below a control gate, and between an erase gate and a word line. A first side portion of the floating gate and a second side portion of the floating gate may extend laterally beyond the control gate in substantially equal amounts. The erase gate may overhang the first side portion of the floating gate. A first control gate spacer may be arranged between the control gate and the word line. The first control gate spacer may at least partially cover a top surface of the second side portion of the floating gate. 1. A nonvolatile memory device comprising:a floating gate below a control gate, and between an erase gate and a word line, wherein a first side portion of the floating gate and a second side portion of the floating gate extend laterally beyond the control gate in substantially equal amounts;the erase gate overhangs the first side portion of the floating gate; anda first control gate spacer between the control gate and the word line, wherein the first control gate spacer at least partially covers a top surface of the second side portion of the floating gate.2. The nonvolatile memory device of claim 1 , wherein the first control gate spacer completely covers the top surface of the second side portion of the floating gate.3. The nonvolatile memory device of claim 1 , further comprising:a second control gate spacer between the control gate and the erase gate.4. The nonvolatile memory device of claim 3 , wherein the second control gate spacer is thinner than the first control gate spacer.5. The nonvolatile memory device of claim 3 , further comprising:a tunnel dielectric layer between the erase gate and the floating gate, wherein the tunnel dielectric layer covers a top surface of the first side portion of the floating gate.6. The nonvolatile memory device of claim 5 , wherein the tunnel dielectric layer is adjacent to the second control gate spacer.7. The ...

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Номер записи: 88
16-05-2019 дата публикации

SELECTOR-RESISTIVE RANDOM ACCESS MEMORY CELL

Номер: US20190148454A1
Автор: QUEK Elgin Kiok Boone, SUN YUAN, Tan Shyue Seng, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer. 1. A device comprising:a substrate; and a first selector comprising a first bipolar junction transistor (BJT) having a first collector terminal, a first emitter terminal and a first base terminal, and', 'a first resistive storage element having first and second first storage terminals, wherein the first first storage terminal is coupled to the first base terminal;, 'a memory cell disposed in a device region of the substrate, the memory cell includes'}a first wordline coupled to the second first storage terminal;a first source line coupled to the first collector terminal; anda first bitline coupled to the first emitter terminal.2. The device of wherein in the memory cell with the first selector and the first resistive storage element comprises a 1-bit memory cell with one bit.3. The device of wherein the first BJT comprises:a first doped region in the device region of the substrate, wherein the first doped region comprises second polarity type dopants and extend from a surface of the substrate to a first depth of the first doped region, the first doped region serves as the first base terminal; andfirst and second S/D regions disposed in the first doped region, the first and second S/D regions comprise first polarity type dopants and are separated by a channel region comprising the first doped region, the first and second S/D regions extend from a surface of the ...

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Номер записи: 89
11-06-2015 дата публикации

FINFET WITH ISOLATION

Номер: US20150162436A1
Автор: QUEK Elgin Kiok Boone, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided. 1. A method for forming a device comprising:providing a substrate prepared with a device region;forming a fin in the device region, the fin includes top and bottom portions;forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed;forming at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor;forming source/drain (S/D) regions in the top portions of the fin; andforming a gate wrapping around the fin.2. The method of wherein the isolation layer comprises an initial thickness Tand forming the fin comprises:providing a patterned hard mask having a shape correspond to the fin; andremoving portions of the substrate unprotected by the hard mask to form the fin.3. The method of comprising:forming a dummy gate over the substrate; andforming protective liners after forming the dummy gate.4. The method of wherein the dummy gate is formed by:providing a dummy gate layer over the substrate;providing a patterned gate hard mask having a shape corresponding to the dummy gate; andremoving portions of the dummy gate layer unprotected by the gate hard mask to form the dummy gate.5. The method of wherein the at least ...

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Номер записи: 90
17-06-2021 дата публикации

Sensors having resistive elements

Номер: US20210184059A1
Автор: Eng Huat Toh, Kiok Boone Elgin Quek, Lanxiang Wang, Shyue Seng Tan
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.

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Номер записи: 91
28-08-2014 дата публикации

Field effect transistor with self-adjusting threshold voltage

Номер: US20140239371A1
Автор: Elgin Kiok Boone Quek, Eng Huat Toh, Shyue Seng Tan
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer.

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Номер записи: 92
28-08-2014 дата публикации

LDMOS WITH IMPROVED BREAKDOWN VOLTAGE

Номер: US20140239391A1
Автор: Lee Jae Gon, Quek Elgin, Tan Chung Foong, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte.Ltd.

An LDMOS is formed with a field plate over the n drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials. 1. A device comprising:a substrate;a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;a source in the first well and a drain in the second well;a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;first and second coplanar gate stacks on the substrate, the first gate stack being formed on a portion of the first well, and the second gate stack being formed on a portion of the second well; whereinthe work function of the second gate stack is higher than the work function of the first gate stack.2. The device according to claim 1 , comprising:a first oxide layer and a polysilicon or amorphous silicon (a-Si) field plate as the second gate stack; anda high-k dielectric layer, or a second oxide and a high-k dielectric layer, and a metal gate as the first gate stack.3. The device according to claim 2 , ...

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Номер записи: 93
24-06-2021 дата публикации

IMAGE SENSOR WITH REDUCED CAPACITANCE TRANSFER GATE

Номер: US20210193713A1
Автор: LIM Khee Yong, Quek Kiok Boone Elgin, YEO Chia Ching
Принадлежит:

An image sensor pixel comprises a semiconductor substrate and a gate having a dielectric layer with a first section and a second section over the semiconductor substrate. The first section of the dielectric layer is thinner than the second section. A photodiode is disposed substantially beneath the gate. A gate well region is disposed beneath the gate and overlying the photodiode. A first doped semiconductor region separates the gate well region from a second doped semiconductor region. The second doped semiconductor region is in the semiconductor substrate and is adjacent to the gate. 1. An image sensor pixel comprising:a semiconductor substrate;a gate having a dielectric layer with a first section and a second section over the semiconductor substrate, wherein the first section of the dielectric layer is thinner than the second section;a photodiode is disposed substantially beneath the gate;a gate well region is disposed beneath the gate and overlying the photodiode, wherein a first doped semiconductor region separates the gate well region from a second doped semiconductor region; andthe second doped semiconductor region is in the semiconductor substrate, wherein the second doped semiconductor region is adjacent to the gate.2. The image sensor according to claim 1 , wherein the second section of the dielectric layer is adjacent to the second doped semiconductor region.3. The image sensor according to claim 1 , wherein the gate further comprises a gate electrode layer covering the first section of the dielectric layer and a portion of the second section of the dielectric layer;wherein the first section of the dielectric layer is over the gate well region; andwherein the portion of the second section of the dielectric layer covered by the gate electrode layer is adjacent to the gate well region.4. The image sensor according to further comprising:dielectric spacers on side surfaces of the gate.5. The image sensor according to claim 1 , wherein the photodiode further ...

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Номер записи: 94
18-09-2014 дата публикации

FIN SELECTOR WITH GATED RRAM

Номер: US20140264228A1
Автор: Quek Elgin, Tan Shyu Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A method comprising:forming a bottom electrode layer and a hardmask on a semiconductor substrate;etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure;forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively;forming spacers on vertical surfaces of the first and second dummy gate stacks;forming an interlayer dielectric (ILD) surrounding the spacers;removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure;forming a resistive random access memory (RRAM) layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; andfilling each of the first and second cavities with a top electrode.2. The method according to claim 1 , comprising forming the RRAM layer of a transition metal.3. The method according to claim 1 , comprising forming the bottom electrode to a thickness of 3 to 20 nanometers and of titanium nitride (TiN) claim 1 , tantalum oxide (TaN) claim 1 , tungsten ( ...

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Номер записи: 95
18-09-2014 дата публикации

BACK-GATED NON-VOLATILE MEMORY CELL

Номер: US20140264554A1
Автор: LIM Khee Yong, QUEK Elgin Kiok Boone, Tan Kian Ming
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate. 1. A memory device comprising:a substrate; anda memory cell disposed on the substrate, wherein the memory cell comprises a single transistor, the single transistor includes a first gate which functions as a control gate disposed on the substrate and a second gate which functions as a select gate embedded in the substrate.2. The memory device of where the second gate is a back gate to the first gate.3. The memory device of wherein the substrate is a crystalline-on-insulator (COI) substrate that includes an insulator layer claim 1 , wherein the insulator layer comprises a buried oxide (BOX) layer sandwiched by a top or body substrate and a bottom or base substrate.4. The memory device of wherein the body substrate comprises silicon claim 3 , thereby forming a silicon body.5. The memory device of wherein the second gate embedded in the substrate is disposed over and within the bottom/base substrate.6. The memory device of wherein a first polarity band/well is disposed over and within the bottom/base substrate to isolate a second polarity doped back gate control layer.7. The memory device of wherein the thickness of the body substrate is less than about 30 nm and the thickness of the BOX layer is less than about 5 nm.8. The memory device of wherein the BOX layer and back gate control layer serve as the second gate to control the memory device threshold voltage.9. The memory device of wherein the first gate includes a first gate electrode and a first gate dielectric claim 8 , wherein the first gate electric comprises a dielectric stack that includes a charge trapping layer.10. A method for forming a memory device ...

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Номер записи: 96
23-06-2016 дата публикации

FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE

Номер: US20160181440A1
Автор: QUEK Elgin Kiok Boone, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer. 1. A method comprising:forming a gate oxide layer above a channel region in a substrate; and forming a dummy gate on the gate oxide layer;', 'forming an ILD surrounding the gate oxide layer and the dummy gate;', 'removing the dummy gate;', 'forming a cavity; and', 'depositing a self-adjusting threshold voltage material on side surfaces of the cavity., 'forming a self-adjusting threshold voltage layer by2. The method according to claim 1 , further comprising:forming the self-adjusting threshold voltage layer above a source-side end and the drain-side end of the gate oxide layer.3. The method according to claim 1 , further comprising:depositing a gate material on side surfaces of the cavity, leaving exposed a middle portion of the self-adjusting threshold voltage layer.4. The method according to claim 3 , wherein the gate material is poly-Si or metal.5. The method according to claim 3 , further comprising:masking the self-adjusting threshold voltage layer with a hardmask, exposing the middle portion of the self-adjusting threshold voltage layer, prior to removing the middle portion of the self-adjusting threshold voltage layer.6. The method according to claim 5 , further comprising:removing at least a middle portion of the self-adjusting threshold voltage layer.7. The method according to claim 1 , comprising forming the self-adjusting threshold voltage layer to a thickness of 1 to 10 nm.8. The method according to claim 7 , comprising forming the self-adjusting threshold voltage layer to a width of 5 to 20% a width of ...

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Номер записи: 97
02-07-2015 дата публикации

THREE-DIMENSIONAL NON-VOLATILE MEMORY

Номер: US20150187784A1
Автор: QUEK Elgin Kiok Boone, Tan Shyue Seng, Toh Eng Huat
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

A three-dimensional one-transistor non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a primary fin disposed on a substrate along a first direction, first and second secondary fins disposed on the substrate along a second direction, and a first gate of a first memory cell disposed on the substrate in a gate region thereof. The first gate includes a program gate, a floating gate and a control gate. 1. A memory device , comprising:a primary fin disposed on a substrate along a first direction;first and second secondary fins disposed on the substrate along a second direction; and a program gate disposed on the substrate, wherein the program gate is displaced from the primary fin by a dielectric block which is disposed on the substrate and adjacent to the primary fin, and wherein the dielectric block has a height which is less than that of the program gate,', 'a floating gate disposed over the program gate, wherein the program gate is separated from the floating gate and the primary fin by an inter-gate dielectric, and wherein the floating gate comprises a floating gate tip disposed adjacent to the program gate and the dielectric block and between the program gate and the primary fin, and', 'a control gate disposed adjacent to the floating gate and the program gate, wherein the control gate is separated from the substrate, the program gate, and the floating gate by the inter-gate dielectric., 'a first gate of a first memory cell disposed on the substrate in a gate region thereof, wherein the first gate comprises'}2. The memory device of claim 1 , further comprising a source region and a drain region in the primary fin and disposed on opposing sides of the first gate.3. The memory device of claim 1 , further comprising a first well region in the substrate and in electrical contact with the program gate claim 1 , wherein during a program operation electrons flow from the program gate to the floating gate through a poly-to ...

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Номер записи: 98
02-07-2015 дата публикации

COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY

Номер: US20150188047A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. 1. A device comprising:a substrate;a well of a first polarity in the substrate;a shallow trench isolation (STI) region formed in the substrate extending partially into the well;a channel of a second polarity in the substrate, over the well, at opposite sides of the STI region;an active area of the first polarity in the substrate over the channel at opposite sides of the STI region;an RRAM liner on the active area and STI region;a top electrode on the RRAM liner;spacers on opposite sides of the RRAM liner and top electrode; anddoped regions of the second polarity in the substrate adjacent the spacers, laterally remote from the RRAM liner.2. The device according to claim 1 , wherein the RRAM liner comprises an oxide of a transition metal.3. The device according to claim 1 , wherein a thickness of the RRAM liner is 1 nm to 100 nm.4. The device according to claim 1 , wherein the top electrode comprises a transition metal claim 1 , titanium nitride (TiN) claim 1 , TiN/Ti claim 1 , or polysilicon.5. The device according to claim 1 , wherein each spacer comprises a top section and a bottom section claim 1 , the ...

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Номер записи: 99
04-06-2020 дата публикации

INTEGRATED CIRCUITS WITH SENSORS AND METHODS FOR PRODUCING THE SAME

Номер: US20200173959A1
Автор: LIU BIN, Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well. 1. An integrated circuit comprising:a detection layer;a substrate;a transistor comprising a transistor gate electrode, a transistor source, and a transistor drain;a capacitor gate electrode overlying the substrate, wherein the transistor gate electrode and the capacitor gate electrode are electrically connected with each other and with the detection layer;a capacitor well defined within the substrate; anda gate insulator positioned between the capacitor well and the capacitor gate electrode, wherein a capacitor comprises the capacitor gate electrode, the gate insulator, and the capacitor well.2. The integrated circuit of wherein:the transistor gate electrode has a transistor gate bottom surface at a gate level; andthe capacitor gate electrode has a capacitor gate bottom surface at the gate level.3. The integrated circuit of further comprising:a buried insulator layer underlying the transistor.4. The integrated circuit of wherein the buried insulator layer underlies the capacitor well.5. The integrated circuit of further comprising:a capacitor second plate, where the capacitor second plate comprises the capacitor well, a capacitor first terminal, and a capacitor second terminal, and wherein the capacitor well, the capacitor first terminal, and the capacitor second terminal are electrically ...

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Номер записи: 100
29-06-2017 дата публикации

Semiconductor device with improved narrow width effect and method of making thereof

Номер: US20170186852A1
Автор: Kiok Boone Elgin Quek, Xinfu Liu, Xueming Dexter TAN
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (V T ) implant is performed with a desired level of second polarity type dopants into the substrate. The V T implant forms a V T adjust region to obtain a desired V T of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the V T implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

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Номер записи: 101
11-06-2020 дата публикации

SENSOR DEVICE AND A METHOD FOR FORMING THE SENSOR DEVICE

Номер: US20200182826A1
Автор: LIM Khee Yong, LIU BIN, Quek Kiok Boone Elgin, Tan Shyue Seng, Toh Eng Huat, TSAI Ming Tsang
Принадлежит:

A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device. 1. A sensor device comprising:a substrate; a first source region at least partially disposed within the substrate comprising a first source resistance;', 'a first drain region at least partially disposed within the substrate;', 'a first channel region between the first source region and the first drain region; and', 'a first gate structure disposed over the first channel region, wherein the first gate structure is configured to receive a solution and a change in pH in the solution causes a change in a first current flow through the first channel region;, 'a first semiconductor structure comprising a second source region at least partially disposed within the substrate comprising a second source resistance;', 'a second drain region at least partially disposed within the substrate;', 'a second channel region disposed between the second source region and the second drain region; and', 'a second gate structure disposed over the second channel region,', 'wherein the sensor device is configured such that when the first current flow through the first channel region changes due to the change in pH in the solution, a ...

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Номер записи: 102
13-07-2017 дата публикации

TRANSISTOR WITH SOURCE-DRAIN SILICIDE PULLBACK

Номер: US20170200649A1
Автор: CHA Jae Han, CHONG Yung Fu, LIM Khee Yong, Quek Kiok Boone Elgin, YEO Chia Ching
Принадлежит:

The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor. 1. A method of forming a device comprising: a low voltage (LV) device region, and', 'a medium voltage (MV) device region;, 'providing a substrate, wherein the substrate is prepared with'}forming a LV gate in the LV region,forming LV lightly doped (LD) regions in the substrate in the LV device region adjacent to the LV gate,forming a MV gate in the MV region;forming MV lightly doped (LD) regions in the substrate in the MV device region adjacent to the MV gate;forming a spacer layer on the substrate, the spacer layer lines the substrate, the LV gate and the MV gate; forms non-extended spacers on first and second sidewalls of the LV gate, and', 'at least one extended L shaped (extended L) spacer on at least one sidewall of the MV gate;', 'forming LV heavily doped (HD) regions in the substrate adjacent to the non-extended spacers on first and second sidewalls of the LV gate;', 'forming MV heavily doped (HD) regions in the substrate adjacent to the extended L spacers on at least one sidewall of the MV gate, wherein the extended L spacer displaces the MV HD regions a greater distance from at least one sidewall of the MV gate to reduce gate induced drain leakage (GIDL) and impact ionization of a MV ...

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Номер записи: 103
06-08-2015 дата публикации

FIN SELECTOR WITH GATED RRAM

Номер: US20150221867A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A device comprising:a semiconductor substrate;a bottom electrode layer on a semiconductor substrate;a hardmask on the bottom electrode layer, the semiconductor substrate, bottom electrode layer, and hardmask forming a fin-like structure;first and second resistive random access memory (RRAM) layers on the first and second side surfaces of the fin-like structure, respectively;first and second top electrodes on the first and second RRAM layers, respectively;spacers on vertical surfaces of the first and second top electrodes; andan interlayer dielectric (ILD) surrounding the spacers.2. The device according to claim 1 , wherein the RRAM layers comprise a transition metal.3. The device according to claim 1 , wherein the bottom electrode is formed to a thickness of 3 to 20 nanometers and comprises titanium nitride (TiN) claim 1 , tantalum oxide (TaN) claim 1 , tungsten (W) claim 1 , platinum (Pt) claim 1 , or a multilayer with an oxygen vacancies layer.4. The device according to claim 1 , further comprising an oxide on the first and second sides of the substrate of the fin-like structure claim 1 , and an ...

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Номер записи: 104
26-07-2018 дата публикации

COMPACT OTP/MTP TECHNOLOGY

Номер: US20180212058A1
Автор: QUEK Elgin Kiok Boone, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate. 1. A method comprising:providing a substrate having a buried oxide (BOX) layer formed over the substrate;forming first and second fins on the BOX layer, wherein the second fin is arranged opposite the first fin on the BOX layer such that an end of the second fin is aligned to an end of the first fin with a gap in between;forming first and second gates, laterally separated, over and perpendicular to the first and second fins, respectively;forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of the first fin, the second fin, or both fins;forming at least one additional pair of separated first and second fins parallel to and vertically spaced from the first and second fins;extending the first and second gates over one or more of the additional first and second fins, respectively;forming a source/drain (S/D) region in each of the first and second fins adjacent to the first and second gates, respectively, remote from the at least one third gate;utilizing each of the first and second gates as a word line (WL);utilizing each at least one third gate as a source line (SL) ...

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Номер записи: 105
25-06-2020 дата публикации

MAGNETIC MEMORY DEVICES WITH MAGNETIC FIELD SENSING AND SHIELDING

Номер: US20200203597A1
Автор: AGARWAL Samarth, JAIN Ruchil Kumar, LIU BIN, Quek Kiok Boone Elgin, Toh Eng Huat
Принадлежит:

In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value. 1. A magnetic memory device comprising:a memory component comprising a plurality of magnetic storage elements for storing memory data;at least one sensor component configured to detect a magnetic field external to the memory component, wherein the at least one sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field; andwherein the memory component is configured to be terminated when the signal is above a predetermined threshold value.2. The magnetic memory device of claim 1 , further comprising a safety device configured to terminate the memory component based on the signal from the at least one sensor component.3. The magnetic memory device of claim 2 , wherein the detected magnetic field comprises a first direction; and further comprising at least one coil configured to generate a magnetic field in a second direction opposite to the first direction claim 2 , wherein the generated magnetic field reduces or eliminates an impact to the memory component of the detected external magnetic field.4. The magnetic memory device of claim 2 , further comprising an external memory device coupled to the magnetic memory device; wherein the memory component of the magnetic memory device is configured to transfer memory data to ...

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Номер записи: 106
04-08-2016 дата публикации

MAGNETIC MEMORY CELLS WITH LOW SWITCHING CURRENT DENSITY

Номер: US20160225423A1
Автор: NAIK Vinayak Bharat, Quek Kiok Boone Elgin, Toh Eng Huat
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Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit is defined on the substrate. The cell selector unit includes at least one select transistor. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled to the selector unit. The MTJ element includes a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers. A spin-orbit-torque (SOT) layer is coupled to the selector unit and is in direct contact with the free layer. A strain induced layer is coupled to a digital line (DL) and is in direct contact with the SOT layer. When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer. 1. A memory cell comprising:a substrate defined with a memory cell region;a cell selector unit defined on the substrate, wherein the cell selector unit comprises at least one select transistor;a storage element which comprises a magnetic tunnel junction (MTJ) element coupled to the selector unit, wherein the MTJ element comprises a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers;a spin-orbit-torque (SOT) layer coupled to the selector unit and is in direct contact with the free layer; anda strain induced layer coupled to a digital line (DL) and in direct contact with the SOT layer, wherein when the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer.2. The memory cell of wherein the SOT layer comprises heavy metal material and the strain induced layer comprises a piezo electric or a ferroelectric material.3. The memory cell of wherein:the cell selector unit comprises first and second select transistors, wherein a select transistor comprises a gate and first and second source/drain (S/D) regions disposed adjacent to first and second sides of the gate;the first select transistor ...

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Номер записи: 107
04-08-2016 дата публикации

HIGH SENSING MARGIN RESISTIVE MEMORY

Номер: US20160225426A1
Автор: NAIK Vinayak Bharat, Quek Kiok Boone Elgin, Toh Eng Huat
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A memory device and a method for forming a memory device are disclosed. The memory device includes a memory cell having a storage unit coupled to a cell selector unit. The storage unit includes first and second storage elements. Each of the first and second storage elements includes first and second terminals. The second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL). The cell selector unit includes first and second selectors. The first selector includes a write select transistor (T) and the second selector includes a first read transistor (T) and a second read transistor (T). The first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit. 1. A memory device comprising: the storage unit comprises first and second storage elements, wherein each of the first and second storage elements comprises first and second terminals, wherein the second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL), and', {'sub': W', 'R1', 'R2, 'the cell selector unit comprises first and second selectors, wherein the first selector comprises a write select transistor (T) and the second selector comprises a first read transistor (T) and a second read transistor (T), wherein the first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.'}], 'a memory cell having a storage unit coupled to a cell selector unit, wherein'}2. The memory device of wherein the memory cell is a spin torque transfer-magnetic random access memory (STT-MRAM).3. The memory device of ...

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Номер записи: 108