PROCESS FOR THE PREPARATION OF TRIFLUOROMETHYL BENZENES FROM THE CORRESPONDING TRICHLORO OR TRIBROMO METHYL BENZENES

TERMINATING OF TRANSACTION

Un système comprend une unité centrale de traitement (10), un bus d'interconnexion (1), et une pluralité de modules fonctionnels (11-15, 21) correspondant à des domaines d'alimentation distincts, et capables de communiquer entre eux et/ou avec l'unité centrale de traitement via le bus d'interconnexion. Au moins un module esclave (22) est associé à l'un des domaines d'alimentation, et est configuré pour se substituer à un module fonctionnel esclave (21) du domaine d'alimentation lorsque l'alimentation du domaine d'alimentation est coupée par l'unité centrale de traitement. Il signale une erreur en réponse à toute requête d'une transaction en cours entre le module fonctionnel esclave et un module fonctionnel maître au moment de la coupure d'alimentation.

PROCEDURE FOR THE PRODUCTION OF TRI FLUORINE METHYL BENZENE FROM AGREEING TRI CHLORINE OR TRI BROMINE METHYL BENZENE.

ANION EXCHANGE RESINS

ABSTRACT OF THE DISCLOSURE The present invention relates to a method of preparing an anion exchange resin, comprising polymerising at least one vinylaromatic compound, either alone or in combination with at least one copolymerisable monomer, followed by bromination then amination of the polymer obtained, characterised in that the vinylaromatic monomer is substituted on the aromatic moiety by one or more alkyl groups containing 1 to 3 carbon atoms and the brominating agent is an N-bromoamide or an N-bromoimide.

TERMINATING OF TRANSACTION

PROCESS FOR THE PREPARATION OF FLUOROBENZONITRILES

PREPARATION OF ANION-EXCHANGE RESINS BY BROMINATION OF VINYLAROMATIC POLYMERS, AND PRODUCTS OBTAINED

Transaction Terminator

A system comprises a central processing unit (), an interconnection bus (), and a plurality of functional modules (-) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module () of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off. 111.-. (canceled)12. A power management system , comprising:a central processing unit;an interconnection bus;a plurality of functional modules corresponding to distinct power domains, able to communicate with each other, with the central processing unit, or both, via the interconnection bus, wherein the plurality of functional modules includes a slave functional module and an associated master functional module; anda terminator module associated with a power domain of the slave functional module, and configured to be substituted for the slave functional module when the power to the power domain of the slave functional module is turned off by the central processing unit, and to signal an error to the master functional module in response to a request of a transaction that is in progress between the slave functional module and the master functional module at the moment the power is turned off.13. The system of claim 12 , wherein the terminator module comprises a first logic unit adapted to produce a response signaling an error if a read operation is in progress at the moment the power is turned off claim 12 , and to do so for the entire duration of the read response expected by the master functional module.14. The system of claim 13 , wherein the terminator module comprises a second logic unit adapted to produce a response signaling an ...

PREPARATION OF ANION EXCHANGE RESINS BY BROMATION OF VINYLAROMATIC POLYMERS

PROCEDE DE PREPARATION DE RESINES ECHANGEUSES D'ANIONS QUI CONSISTE A POLYMERISER UN COMPOSE VINYLAROMATIQUE POSSEDANT AU MOINS UN GROUPE ALKYLE CONTENANT 1 A 3ATOMES DE CARBONE, SEUL OU EN MELANGE AVEC UN MONOMERE COPOLYMERISABLE, EVENTUELLEMENT EN PRESENCE D'UN SUPPORT MINERAL, A BROMER LES GROUPES ALKYLE DU POLYMERE AU MOYEN D'UN N-BROMOAMIDE OU D'UN N-BROMOIMIDE, PUIS A AMINER LE PRODUIT BROME OBTENU. APPLICATION DES RESINES ECHANGEUSES D'ANIONS DANS LES INDUSTRIES CHIMIQUE, PHARMACEUTIQUE, ALIMENTAIRE ET METALLURGIQUE. PROCESS FOR THE PREPARATION OF ANION EXCHANGER RESINS WHICH CONSISTS OF POLYMERIZING A VINYLAROMATIC COMPOUND HAVING AT LEAST ONE ALKYL GROUP CONTAINING 1 TO 3 ATOMS OF CARBON, ALONE OR IN A MIXTURE WITH A COPOLYMERISABLE MONOMER, POSSIBLY WITH THE SUPPORT IN MINERAL ALKYL GROUPS OF THE POLYMER BY MEANS OF AN N-BROMOAMIDE OR AN N-BROMOIMIDE, THEN TO AMINATE THE BROMINE PRODUCT OBTAINED. APPLICATION OF ANION EXCHANGING RESINS IN THE CHEMICAL, PHARMACEUTICAL, FOOD AND METALLURGIC INDUSTRIES.

PROCEDURE FOR THE PREPARATION OF ANION EXCHANGE RESINS BY BROMINATION OF VINYLAROMATIC POLYMERS AND ANION PART EXCHANGE RESIN

INTEGRATED CIRCUIT COMPRISING A PARTIALLY USED REGISTER BANK

PROCESS FOR THE PREPARATION OF FLUOROBENZONITRILES

LA PRESENTE INVENTION CONCERNE UN PROCEDE DE PREPARATION DE FLUOROBENZONITRILES PAR REACTION DES CHLOROBENZONITRILES CORRESPONDANTS AVEC AU MOINS UN FLUORURE ALCALIN EN MILIEU SOLVANT APROTIQUE CARACTERISE EN CE QUE LA REACTION A LIEU EN PRESENCE D'AU MOINS UN AGENT SEQUESTRANT DE FORMULE:N-CHR-CHR-O-(CHR-CHR-O)-RDANS LAQUELLE N EST UN NOMBRE ENTIER SUPERIEUR OU EGAL A 0 ET INFERIEUR OU EGAL A ENVIRON 10 (0 N 10), R, R, R ET R IDENTIQUES OU DIFFERENTS REPRESENTENT UN ATOME D'HYDROGENE OU UN RADICAL ALKYLE AYANT DE 1 A 4 ATOMES DE CARBONE ET R REPRESENTE UN RADICAL ALKYLE OU CYCLOALKYLE AYANT DE 1 A 12 ATOMES DE CARBONE, UN RADICAL PHENYLE OU UN RADICAL -CH-O OU CH2M1-O-, OU M EST COMPRIS ENTRE 1 ET 12 (1 M 12). LES PRODUITS OBTENUS SONT UTILES COMME INTERMEDIAIRES DE SYNTHESE DE COMPOSES AYANT UNE ACTIVITE PHARMACEUTIQUE OU PHYTOSANITAIRE. THE PRESENT INVENTION CONCERNS A PROCESS FOR THE PREPARATION OF FLUOROBENZONITRILES BY REACTION OF THE CORRESPONDING CHLOROBENZONITRILS WITH AT LEAST ONE ALKALINE FLUORIDE IN AN APROTIC SOLVENT MEDIUM CHARACTERIZED IN THAT THE REACTION TAKES PLACE IN THE PRESENCE OF NONE CHRANT-AGENT: AT LEAST ONE CHRANT-AGENT: -O- (CHR-CHR-O) -R IN WHICH N IS A WHOLE NUMBER GREATER OR EQUAL TO 0 AND LESS OR EQUAL TO ABOUT 10 (0 N 10), R, R, R AND R IDENTICAL OR DIFFERENT REPRESENT AN ATOM D 'HYDROGEN OR A RADICAL ALKYL HAVING 1 TO 4 CARBON ATOMS AND R REPRESENTS A RADICAL ALKYL OR CYCLOALKYL HAVING 1 TO 12 CARBON ATOMES, A PHENYL RADICAL OR A RADICAL -CH-O OR CH2M1-O-, OR M IS INCLUDED BETWEEN 1 AND 12 (1 M 12). THE PRODUCTS OBTAINED ARE USEFUL AS INTERMEDIARIES FOR THE SYNTHESIS OF COMPOUNDS HAVING A PHARMACEUTICAL OR PHYTOSANITARY ACTIVITY.

Output buffer register, electronic circuit and method for delivering signals using same

An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Preparation of fluorobenzonitriles

Fluorobenzonitriles are prepared by reacting their corresponding chlorobenzonitriles with at least one alkali metal fluoride, in an aprotic solvent reaction medium, in the presence of at least one tertiary amine sequestering agent having the structural formula: N--CHR.sub.1 --CHR.sub.2 --O--(CHR.sub.2 --CHR.sub.4 --O).sub.n R.sub.5 ] 3 .

PROCESS FOR THE PREPARATION OF TRIFLUOROMETHYLBENZENES FROM THE CORRESPONDING TRICHLORO- OR TRIBROMO-METHYLBENZENES

L'INVENTION CONCERNE UN PROCEDE CONTINU DE PREPARATION D'UN TRIFLUOROMETHYLBENZENE A PARTIR DU TRICHLORO- OU TRIBROMO-METHYLBENZENE CORRESPONDANT PAR ACTION SUR CE DERNIER D'ACIDE FLUORHYDRIQUE CARACTERISE EN CE QUE L'ON MET EN OEUVRE LA REACTION EN FAISANTPASSER A CONTRE-COURANT UN COURANT ASCENDANT D'ACIDE FLUORHYDRIQUE EN PHASE GAZEUSE A TRAVERS UNE PLURALITE DE COUCHES LIQUIDES SUCCESSIVES MOBILES DU TRICHLORO- OU TRIBROMO-METHYLBENZENE. THE INVENTION CONCERNS A CONTINUOUS PROCESS FOR THE PREPARATION OF A TRIFLUOROMETHYLBENZENE FROM THE TRICHLORO- OR TRIBROMO-METHYLBENZENE CORRESPONDING BY ACTION ON THE LAST FLUORHYDRIC ACID CHARACTERIZED IN THAT IT CARRIES OUT THE REACTION AN ASCENDER OF FLUORHYDRIC ACID IN THE GASEOUS PHASE THROUGH A PLURALITY OF MOBILE SUCCESSIVE LIQUID LAYERS OF TRICHLORO- OR TRIBROMO-METHYLBENZENE.

OUTPUT STAMP REGISTER, ELECTRONIC CIRCUIT, AND SIGNAL DELIVERY METHOD USING THE SAME

INTEGRATED CIRCUIT INCLUDING A MASTER CIRCUIT, OPERATING AT A FIRST FREQUENCY, TO CONTROL SLAVE CIRCUITS OPERATING AT A SECOND FREQUENCY

Integrated circuit with master and slave circuits operating at a first and second frequency respectively

Control or master circuit (1) has a register (R1) with a clock input to receive a second, clock signal (Ck2) in addition to a first clock signal (Ck1), a data input, for memorization of the command signal during the leading edge of the second clock signal and an output connected to the slave circuit input (2). The master circuit (1) receives a first clock signal (Ck1) and the slave circuit the second clock signal (Ck2).

Process for the preparation of trifluoromethylbenzenes from the corresponding trichloro- or tribromo-methylbenzenes

This invention relates to a continuous process for the preparation of trifluoromethylbenzenes from the corresponding trichloro- or tribromo-methylbenzenes with hydrofluoric acid. The process is characterized by passing an ascending stream of gaseous hydrofluoric acid, countercurrently through a plurality of mobile successive liquid layers of the trichloro- or tribromo-methylbenzenes.

IMPROVEMENT TO ELECTRONIC SYSTEMS COMPRISING A SYSTEM BUS

System and method for communicating with an integrated circuit

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and device for transmission with an integrated circuit

System and method for communicating with an integrated circuit

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

Apparatus and method for shadowing processor information

An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

PROCEDURE FOR THE PREPARATION OF ANION EXCHANGE RESINS BY BROMINATION OF VINYLAROMATIC POLYMERS AND ANION PARTICULAR RESINES IN PARTICULAR FORM

BASIC MEMORY CIRCUIT

Machines d'etats pour circuit integre fonctionnant a frequence elevee

System and method for communicating with an integrated circuit

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and method for communicating with an integrated circuit

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and method for communicating with an integrated circuit

System and method for communicating with an integrated circuit

A debugging system includes an interface protocol for flow control between an integrated circuit and an external system using a high-speed link and/or a JTAG link. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. The high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. Information transmitted over the JTAG or high-speed link may be compressed. Processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

Transaction terminator

A system comprises a central processing unit (10), an interconnection bus (1 ), and a plurality of functional modules (11-15, 21 ) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one slave module (22) is associated with one of the power domains, and is configured to be substituted for a slave functional module (21) of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.

Perfectionnement aux systemes electroniques comprenant un bus systeme

Un module de resynchronisation destiné à être utilisé dans un système électronique comprenant un bus système comprend des moyens de chevauchement pour faire chevaucher les transactions destinées à et/ou provenant dudit module fonctionnel associé. Les moyens de chevauchement comprennent un premier circuit tampon (63) et au moins un second circuit tampon (64) connectés en parallèle, adaptés chacun pour stocker des données de transaction d'une transaction déterminée.

System and method for communicating with an integrated circuit