Semiconductor arrangement with active drift zone

Semiconductor arrangement with active drift zone

Semiconductor arrangement with active driftzone

There is described a semiconductor device arrangement, comprising: at least two series circuits 11-1p connected in parallel. Each series circuit 11-1p comprising a first semiconductor device (2 figure 16) having a load path and a control terminal and, a plurality of second semiconductor devices (31-n figure 16), each having a load path between a first and a second load terminal and a control terminal; a drive terminal 112; at least one resistor R1-Rp connected between the control terminal 111 of the first semiconductor device of one series circuit and the drive terminal. The second semiconductor devices of each series circuit have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the sec­ond semiconductor devices of each series circuit has its control terminal connected to the load terminal of one of the other second semiconductor devices, or to one of the load terminals of the first semiconductor device. One resistor ...

Lateral power semiconductor device and method for manufacturing a lateral power semiconductor device

A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode.

Method of Manufacturing a Semiconductor Device with Device Separation Structures and Semiconductor Device

A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.

Semiconductor arrangement with active drift zone

A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

Semiconductor arrangement with active drift zone

Semiconductor arrangement with active drift zone

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Integrated memory cell array

The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower regionof said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices.

Method for manufacturing IC

A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Method for manufacturing semiconductor device with buried gate electrode structure, and semiconductor device

The invention discloses a method for manufacturing a semiconductor device with a buried gate electrode structure, and a semiconductor device. The method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected ...

Semiconductor device and method for manufacturing a semiconductor device

The invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.

Methods for manufacturing a structure on or in a substrate, imaging layer for generating sublithographic structures, method for inverting a sublithographic pattern, device obtainable by manufacturing

One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Integrated circuit having a memory cell array and method of forming an integrated circuit

Method for fabricating a memory cell array, and memory cell array

Transistor device and method for producing a transistor device

The invention relates to a transistor device and a method for producing a transistor device. The transistor device includes at least one transistor cell. The at least one transistor cell includes a semiconductor fin, and a source region, a drain region, a drift region and a body region in the semiconductor fin. The body region is arranged adjacent the source region and the drift region in a first direction of the semiconductor fin. The source region is arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer. The drift region is arranged adjacent the drain region in the first direction and has a doping concentration lower than a doping concentration of the drain region. A gate electrode is adjacent the body region in a third direction of the semiconductor fin.

Method for forming battery element, battery element and battery

The invention relates to a method for forming a battery element, the battery element and a battery. The method for forming the battery element includes etching trenches into a substrate and crystal orientation dependent etching of the trenches. Further, the method includes forming solid state battery structures within the trenches.

Manufacturing method for an integrated semiconductor memory device and corresponding semiconductor memory device

Battery element, battery and method for forming battery

The invention relates to a battery element, a battery and a method for forming the battery. The battery element includes a substrate with a plurality of trenches extending into the substrate. At least a part of each trench of the plurality of trenches is filled with a solid state battery structure. Further, the battery element includes a front side battery element electrode arranged at a front side of the substrate and electrically connected to a first electrode layer of the solid state battery structures within the plurality of trenches. Additionally, the battery element includes a backside battery element electrode arranged at a backside of the substrate and electrically connected to a second electrode layer of the solid state battery structures within the plurality of trenches.

Integrated transistor device and corresponding manufacturing method

Super junction semiconductor device comprising a cell area and an edge area

A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.

Integrated memory cell array

Transistor Arrangement with a First Transistor and with a Plurality of Second Transistors

A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor. 1. A transistor arrangement , comprising:a first transistor with a drift region; anda plurality of second transistors, each second transistor having a source region, a drain region and a gate electrode,wherein the second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor, andwherein the source regions of the second transistors are coupled to the drift region and wherein the gate electrodes of the second transistors are coupled to the drift region such that the source region and the gate electrode of each of the second transistors are coupled to the drift region at different locations in a physical layout of the transistor arrangement.2. The transistor arrangement of claim 1 , wherein the drift region has a current flow direction and wherein the gate electrode and the source region of each of the second transistors are coupled to the drift region at different locations in the current flow directions.3. The transistor arrangement of claim 2 , wherein the source region and the drain region of the second transistors are arranged distant from each other in the current flow direction.4. The transistor arrangement of claim 2 , wherein the source region and the drain region of the second transistors are arranged distant from each other in a direction that is perpendicular to the current flow direction.5. The transistor arrangement of claim 1 , wherein the second transistors each comprise a plurality of transistor cells claim 1 , wherein the transistor cells of one second transistor have a common gate electrode.6. The transistor arrangement of claim 2 , wherein the second ...

Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. 1. A semiconductor device arrangement , comprising:a first semiconductor device having a load path; anda plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,wherein each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, andwherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device.2. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device comprises a transistor.3. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device comprises a diode.4. The semiconductor device arrangement of claim 1 ,wherein one of the second transistors that has its load path directly connected to the load path of the first semiconductor device has its control terminal connected to a first load terminal of the first semiconductor device; andwherein each of the other second transistors has its control terminal connected to a first load terminal of an adjacent second transistor.5. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device and ...

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. 1. A semiconductor device arrangement , comprising:a semiconductor layer;at least one series circuit with a first semiconductor device and with a plurality of n second semiconductor devices, with n>1, the first semiconductor device having a load path and having active device regions integrated in the semiconductor layer, each of the second semiconductor devices having active device regions integrated in the semiconductor layer and having a load path between a first and a second load terminal and a control terminal, the second semiconductor devices having their load paths connected in series and connected in series to the load path of the first semiconductor device, each of the second semiconductor devices having its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices having its control terminal connected to one of the load terminals of the first semiconductor device; andan edge termination structure.2. The semiconductor ...

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Integrated Switching Device with Parallel Rectifier Element

An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer. 1. An integrated circuit comprising:a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body;a switching device with a control terminal and a load path between a first load terminal and a second load terminal;a rectifier element connected in parallel with at least one section of the load path; andwherein the switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer.2. The integrated circuit of claim 1 , wherein the second semiconductor layer comprises:a first partial layer of a first doping type;a second partial layer of a second doping type complementary to the first doping type; andwherein the first partial layer is electrically coupled to the first load terminal and the second partial layer is electrically coupled to the second load terminal.3. The integrated circuit of claim 2 , wherein the second semiconductor layer further comprises:a third partial layer arranged between the first partial layer and the second partial layer and having a lower doping concentration than the first partial layer and the second partial layer or being intrinsic.4. The integrated circuit of claim 2 , wherein the first semiconductor layer is of the first doping type.5. The integrated ...

Semiconductor Device and Method for Manufacturing a Semiconductor Device

A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches. 1. A semiconductor device comprising:a semiconductor substrate comprising a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type, the body region being disposed on a side of a first surface of the semiconductor substrate;a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface;doped portions of the second conductivity type adjacent to a lower portion of a sidewall of the trenches, the doped portions being electrically coupled to the body region via contact regions; anda gate electrode disposed in an upper portion of the trenches.2. The semiconductor device of claim 1 , wherein the first region includes a drift zone adjacent to the doped portions.3. The semiconductor device of claim 1 , wherein the doped portions of the second conductivity type line the sidewall and a bottom side of each of the trenches.4. The semiconductor device of claim 1 , wherein the semiconductor device is a vertical superjunction device including a charge compensation zone formed ...

INTEGRATED CIRCUIT WITH AT LEAST TWO SWITCHES

A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. 1. A circuit arrangement comprising:a circuit with a first semiconductor switch and a second semiconductor switch, each of the first semiconductor switch and the second semiconductor switch comprising a load path and control terminal and having their load paths connected in series,wherein at least one of the first and second semiconductor switches comprises:a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the semiconductor switch;a plurality of second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device andwherein each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and wherein one of the second semiconductor devices has its control terminal connected to one of ...

Circuit Arrangement with a Rectifier Circuit

A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices. 1. A circuit arrangement comprising a rectifier circuit , the rectifier circuit comprising:a first and a second load terminal;a first semiconductor device having a load path and a control terminal;a plurality of second semiconductor devices each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device, and wherein a series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals of the rectifier circuit, andwherein the control terminal of one of the second semiconductor devices is connected to one of the load terminals of the first semiconductor device, and wherein the control terminals of the second semiconductor devices other than the one second semiconductor device are connected to a load terminal of the one second semiconductor device.2. The circuit arrangement of claim 1 , wherein the first ...

Circuit Arrangement with a Rectifier Circuit

A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. 1. A circuit arrangement comprising a rectifier circuit , the rectifier circuit comprising:a first and a second load terminal;a first semiconductor device having a load path and a control terminal;a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device, the series circuit with the first semiconductor device and the second semiconductor devices connected between the load terminals of the rectifier circuit;wherein each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices; andwherein one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.2. The circuit arrangement of claim 1 , wherein the first semiconductor device is a diode.3. The ...

Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. 138-. (canceled)39. A semiconductor device arrangement , comprising:a first transistor having a load path between load terminals and a control terminal configured to receive a drive voltage that switches on or switches off the first transistor;a plurality of second transistors, each second transistor having a load path between a first load terminal and a second load terminal and a control terminal;wherein the second transistors have their load paths connected in series and connected in series to the load path of the first transistor;wherein each but one of the second transistors has its control terminal connected to the load terminal of another one of the second transistors;wherein one of the second transistors has its control terminal connected to one of the load terminals of the first transistor; andwherein the first transistor comprises a normally-off transistor.40. The semiconductor device arrangement of claim 39 , wherein one of the second transistors that has its load path directly connected to the load path of the first transistor and has its control terminal connected to a first load terminal of the first transistor and wherein each of the other second transistors has its control terminal connected to a first load terminal of an adjacent second transistor.41. The transistor arrangement of claim 39 , wherein the first transistor and/or one or ...

Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. 128-. (canceled)29. A semiconductor device arrangement , comprising:a semiconductor layer;at least one series circuit with a first semiconductor device and with a plurality of n second semiconductor devices where n>1, the first semiconductor device having a load path and having active device regions integrated in the semiconductor layer, each of the second semiconductor devices having active device regions integrated in the semiconductor layer and having a load path between a first and a second load terminal and a control terminal, the second semiconductor devices having their load paths connected in series and connected in series to the load path of the first semiconductor device, each of the second semiconductor devices having its control terminal connected to the load terminal of one of the other second semiconductor devices or to one of the load terminals of the first semiconductor device; andan edge termination structure,wherein the active device regions of the first semiconductor device and the active ...

Method of Manufacturing a Semiconductor Device with Device Separation Structures and Semiconductor Device

A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way. 1. A method of manufacturing a semiconductor device , the method comprising:introducing at least a first trench pattern and a second trench pattern from a first surface into a semiconductor substrate, wherein the trench patterns include array trenches and wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns;providing buried gate electrode structures in the first and second trench patterns; andintroducing, in a single etch process, a device separation trench having a first width into the array isolation portion and cell separation trenches having at most a second width smaller than the first width into semiconductor fins between the array trenches.2. The method according to claim 1 , further comprising:providing an insulator layer filling the cell separation trenches,lining sidewalls of the device separation trench, andexposing a bottom portion of the device separation trench.3. The method according to claim 1 , further comprising depositing an insulator layer claim 1 , wherein said depositing is controlled to fill the cell separation trenches claim 1 , to line at least sections of sidewalls of the device ...

SEMICONDUCTOR DEVICE WITH BURIED GATE ELECTRODE STRUCTURES

A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner. 1. A method of manufacturing a semiconductor device , the method comprising:introducing at least a first trench pattern and a second trench pattern from a first surface into a semiconductor substrate, wherein an array isolation region of the semiconductor substrate separates the first and second trench patterns and at least the first trench pattern includes array trenches and a contact trench structurally connected with the array trenches;providing a gate electrode structure in a lower section of the first trench pattern, in a distance to the first surface; andproviding a connection plug between the first surface and the gate electrode structure in the contact trench.2. The method according to claim 1 , wherein the array trenches have at most a first width and the contact trench has a second width greater than the first width claim 1 , and wherein providing the connection plug comprises:depositing a fill layer filling the array trenches and lining an upper section of the contact trench between the first surface and the gate electrode structure; anddepositing a conductive material to fill the ...

Semiconductor Device with Vertical Transistor Channels and a Compensation Structure

A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure. 1. A semiconductor device , comprising:transistor cells having vertical channels perpendicular to a first surface of a semiconductor portion;a buried compensation structure between the transistor cells and a second surface of the semiconductor portion parallel to the first surface, the compensation structure comprising first areas and second areas alternatingly arranged along a lateral direction parallel to the first surface; anda contiguous impurity layer of a first conductivity type separating the transistor cells and the compensation structure.2. The semiconductor device according to claim 1 , whereinthe first areas have the first conductivity type and the second areas have a complementary, second conductivity type and the first and second areas form pn junctions.3. The semiconductor device according to claim 2 , whereina lateral integrated impurity concentration in the first areas deviates by not more than 10% from a lateral integrated impurity concentration in the second areas at the same distance to the first surface.4. The semiconductor device according to claim 1 , whereinthe second areas are electrically connected which each other and a conductive structure.5. The semiconductor device according to claim 1 , whereinthe contiguous impurity layer is structurally connected with the first areas.6. The semiconductor device according to claim 1 , further comprising:gate electrodes between the ...

Method for Filling a Trench and Semiconductor Device

A method includes forming a first trench in a semiconductor body between two semiconductor fins, filling the first trench with a first filling material, partially removing the first filling material by forming a second trench such that the second trench has a lower aspect ratio than the first trench, and at least partially filling the second trench with a second filling material so as to form a continuous material layer on the first filling material. A semiconductor device includes a first trench in a semiconductor body between two semiconductor fins, the first trench being filled with a first filling material, and a second trench having a lower aspect ratio than the first trench and being at least partially filled with a second filling material which forms a continuous material layer on the first filling material. 1. A method , comprising:forming a first trench in a semiconductor body between two semiconductor fins;filling the first trench with a first filling material;partially removing the first filling material by forming a second trench such that the second trench has a lower aspect ratio than the first trench; andat least partially filling the second trench with a second filling material so as to form a continuous material layer on the first filling material.2. The method of claim 1 , wherein each of the first filling material and the second filling material is a dielectric.3. The method of claim 1 , wherein the first filling material and the second filling material are of the same material type.4. The method of claim 1 , wherein the second trench is aligned with the first trench.5. The method of claim 4 , wherein an aspect ratio of the first trench is at least 10:1.6. The method of claim 4 , wherein an aspect ratio of the second trench is at most 6:1.7. The method of claim 1 , wherein filling the first trench comprises a deposition process.8. The method of claim 1 , wherein filling the second trench comprises a deposition process.9. The method of claim 1 , ...

Transistor Device and Method for Producing a Transistor Device

A transistor device includes at least one transistor cell. The at least one transistor cell includes a semiconductor fin, and a source region, a drain region, a drift region and a body region in the semiconductor fin. The body region is arranged adjacent the source region and the drift region in a first direction of the semiconductor fin. The source region is arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer. The drift region is arranged adjacent the drain region in the first direction and has a doping concentration lower than a doping concentration of the drain region. A gate electrode is adjacent the body region in a third direction of the semiconductor fin. 1. A transistor device comprising at least one transistor cell , the at least one transistor cell comprising:a semiconductor fin;a source region, a drain region, a drift region and a body region in the semiconductor fin, the body region arranged adjacent the source region and the drift region in a first direction of the semiconductor fin, the source region arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer, the drift region arranged adjacent the drain region in the first direction and having a doping concentration lower than a doping concentration of the drain region; anda gate electrode adjacent the body region in a third direction of the semiconductor fin.2. The transistor device of claim 1 , wherein the gate electrode is dielectrically insulated from the body region by a gate dielectric.3. The transistor device of claim 1 , wherein the gate electrode adjoins the body region.4. The transistor device of claim 1 , wherein the at least one transistor cell further comprises:two gate electrodes adjacent the body region on opposite sides of the semiconductor fin.5. The transistor device of claim 1 , wherein ...

ELECTRONIC CIRCUIT WITH A TRANSISTOR DEVICE, A LEVEL SHIFTER AND A DRIVE CIRCUIT

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region. 1. An electronic circuit , comprising:a first transistor device integrated in an inner region of a first semiconductor body;a level shifter integrated in a level shifter region of the first semiconductor body, wherein the level shifter region is located in an edge region surrounding the inner region of the semiconductor body; anda drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, wherein the drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, and wherein the drive circuit region is arranged closer to the inner region than the level shifter region.2. The electronic circuit of claim 1 , further comprising:an input circuit integrated in the drive circuit region and coupled between a second input and the level shifter.3. The electronic circuit of claim 1 , wherein the drive circuit comprises at least one inverter.4. The electronic circuit of claim 1 , wherein the first transistor device comprises a plurality of transistor cells claim 1 , each comprising:a drift region of a first doping type;a source region of the first doping type connected to a source node;a body region of a second doping type complementary to the first doping type;a ...

Super Junction Semiconductor Device Comprising a Cell Area and an Edge Area

A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region. 1. A super junction semiconductor device , comprising:one or more doped zones formed in a cell area;a doped layer of a first conductivity type; anda drift layer between the doped layer and the one or more doped zones, the drift layer comprising first regions of the first conductivity type and second regions of a second conductivity type opposite to the first conductivity type; whereinin an edge area surrounding the cell area the first regions include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction, the first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.2. The super junction semiconductor device of claim 1 , whereinthe first and second portions have widths equal to or greater than a mean width of the first regions in the cell area.3. The super junction semiconductor device of claim 1 , whereinmore than 50% of an area of the first regions of the edge area is connected with one or more of the first regions of the cell ...

SOLID-STATE SWITCHING DEVICE HAVING A HIGH-VOLTAGE SWITCHING TRANSISTOR AND A LOW-VOLTAGE DRIVER TRANSISTOR

According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor. 1. A solid-state switching device , comprising:a high-voltage switching transistor comprising a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal; anda switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit comprising a low-voltage driver transistor comprising a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.2. The solid-state switching device of claim 1 , further comprising a logic circuit operationally connected to the low-voltage driver transistor and adapted for providing the switching signal.3. The solid-state switching device of claim 1 , wherein the high-voltage switching transistor and the low-voltage driver transistor are electrically connected in a cascode circuit.4. The solid-state switching device of claim 1 , wherein the high-voltage switching transistor is a field-effect depletion-mode transistor.5. The solid-state switching device of claim 1 , wherein the ...

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices. 123-. (canceled)24. A semiconductor device arrangement , comprising:a first semiconductor device having a load path;a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal;wherein the second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device;wherein each of the second semiconductor devices has its control terminal connected to one of the first and second load terminals of one of the other second semiconductor devices, or to one load terminal of the first semiconductor device;wherein each of the second semiconductor devices has at least one device characteristic; andwherein at least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.25. The semiconductor device arrangement of claim 24 , wherein the second semiconductor devices are MOSFETs claim 24 ...

Semiconductor Device with a Laterally Varying Doping Profile, and Method for Manufacturing Thereof

A semiconductor device includes a semiconductor substrate having a first side. At least a first doping region is formed in the semiconductor substrate. The first doping region has a laterally varying doping dosage and/or a laterally varying implantation depth. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate having a first side;forming a first implantation mask having a varying thickness on the first side of the semiconductor substrate;defining regions for respective semiconductor elements in the semiconductor substrate; andimplanting dopants into the semiconductor substrate through the first implantation mask so as to form at least a first doping region arranged at least partially below a first group of semiconductor elements and which has a laterally varying doping dosage and/or a laterally varying implantation depth.2. The method of claim 1 , wherein the first doping region comprises sub-regions of different mean dopant dosage claim 1 , wherein a first sub-region of the first doping region is formed to be arranged at least partially below a first semiconductor element claim 1 , and wherein a second sub-region of the first doping region having a mean dopant dosage different than the mean doping dosage of the first sub-region is formed to be arranged at least partially below a second semiconductor element.3. The method of claim 1 , wherein the first doping region laterally extends across the first group of semiconductor elements when seen in a plane projection onto the first side of the semiconductor substrate.4. The method of claim 1 , further comprising:forming a second implantation mask having a varying thickness on the first side;implanting dopants into the semiconductor substrate through the second implantation mask so as to form at least a second doping region arranged at least partially below a second group of semiconductor elements and which has a laterally varying doping dosage, wherein the ...

Electronic Circuit with a Transistor Device and a Level Shifter

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; and a first drive circuit integrated in a first drive circuit region of the semiconductor body. The first drive circuit is configured to be connected to a level shifter and to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body. 1. An electronic circuit , comprising:a first transistor device integrated in an inner region of a first semiconductor body; anda first drive circuit integrated in a first drive circuit region of the semiconductor body, the first drive circuit configured to be connected to a level shifter and to drive a second transistor device,wherein the first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.2. The electronic circuit of claim 1 , further comprising:the level shifter integrated in a level shifter region of the first semiconductor body,wherein the level shifter region is located in the edge region, andwherein the level shifter region is arranged closer to the inner region than the first drive circuit region.3. The electronic circuit of claim 2 , further comprising:a second drive circuit integrated in a second drive circuit region in the edge region of the first semiconductor body,wherein the second drive circuit is configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, andwherein the second drive circuit region is arranged closer to the inner region than the level shifter region.4. The electronic circuit of claim 3 , further comprising:an input circuit integrated in the second drive circuit region and coupled between a second input and the level shifter.5. The electronic circuit of claim 3 , wherein the second drive circuit comprises at least one inverter.6. The ...

Semiconductor Device with Contact Structures Extending Through an Interlayer and Method of Manufacturing

A layer stack is formed on a main surface of a semiconductor layer, wherein the layer stack includes a dielectric capping layer and a metal layer between the capping layer and the semiconductor layer. Second portions of the layer stack are removed to form gaps between remnant first portions. Adjustment structures of a second dielectric material are formed in the gaps. An interlayer of the first or a third dielectric material is formed that covers the adjustment structures and the first portions. Contact trenches are formed that extend through the interlayer and the capping layer to metal structures formed from remnant portions of the metal layer in the first portions, wherein the capping layer is etched selectively against the auxiliary structures. 1. A method of manufacturing a semiconductor device , the method comprising:forming transistor cells in a semiconductor portion;forming a layer stack on a main surface of a semiconductor layer, wherein the layer stack comprises a dielectric capping layer and a metal layer between the capping layer and the semiconductor layer;removing second portions of the layer stack to form gaps between remnant first portions of the layer stack, wherein from the metal layer first metal structures that directly adjoin source constructions of the transistor cells and second metal structures are formed that directly adjoin drain constructions of the transistor cells;forming auxiliary structures of a second dielectric material in the gaps;forming an interlayer of the first or a third dielectric material, wherein the interlayer covers the auxiliary structures and the first portions; andforming contact trenches extending through the interlayer and the capping layer to the first and second metal structures formed from remnant portions of the metal layer in the first portions of the layer stack, wherein the capping layer is etched selectively against the auxiliary structures.2. The method of claim 1 , wherein forming the contact trenches ...

FILL PATTERN FOR POWER TRANSISTOR AND DIODE DEVICES

According to an embodiment of a semiconductor device, the device includes: a transistor or diode device formed in a semiconductor substrate; an insulating material at least partially covering a lateral drift zone of the transistor or diode device or a termination region; and a fill pattern disposed over the lateral drift zone or termination region, the fill pattern having a variable density that follows equipotential lines of an electric field distribution expected between the fill pattern at a surface of the lateral drift zone or termination region during operation of the semiconductor device. Corresponding methods of producing the semiconductor device are also described. 1. A semiconductor device , comprising:a transistor or diode device formed in a semiconductor substrate;an insulating material at least partially covering a lateral drift zone of the transistor or diode device or a termination region; anda fill pattern disposed over the lateral drift zone or termination region, the fill pattern having a variable density that follows equipotential lines of an electric field distribution expected between the fill pattern at a surface of the lateral drift zone or termination region during operation of the semiconductor device.2. The semiconductor device of claim 1 , wherein the fill pattern comprises lines having a uniform width and variable spacing between the lines claim 1 , and wherein the variable spacing coincides with the equipotential lines of the electric field distribution expected between the fill pattern at the surface of the lateral drift zone or termination region during operation of the semiconductor device.3. The semiconductor device of claim 1 , wherein the insulating material contacts the semiconductor substrate claim 1 , wherein the fill pattern comprises gaps formed in the insulating material and filled with material of the semiconductor substrate claim 1 , and wherein each one of the gaps follows an equipotential line of the electric field ...

Integrated Circuit with a Plurality of Transistors and at Least One Voltage Limiting Structure

An integrated circuit includes a semiconductor body with a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer. The integrated circuit further includes a plurality of transistors each including a load path and a control node The load paths are connected in series, and the plurality of transistors are at least partially integrated in the second semiconductor layer. A voltage limiting structure is connected in parallel with the load path of one of the plurality of transistors, wherein the voltage limiting structure is integrated in the first semiconductor layer and is connected to the one of the plurality of transistors through two electrically conducting vias extending through the insulation layer. 1. An integrated circuit , comprising:a semiconductor body comprising a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer;a plurality of transistors each comprising a load path and a control node, wherein the load paths are connected in series to form a transistor series circuit, and wherein the plurality of transistors are at least partially integrated in the second semiconductor layer; anda voltage limiting structure connected in parallel with the load path of one of the plurality of transistors, wherein the voltage limiting structure is integrated in the first semiconductor layer and is connected to the one of the plurality of transistors through two electrically conducting vias extending through the insulation layer.2. The integrated circuit of claim 1 , further comprising a further voltage limiting structure integrated in the second semiconductor layer and connected in parallel with the load path of one of the plurality transistors.3. The integrated circuit of claim 1 , further comprising a plurality of voltage limiting structures claim 1 , wherein each of the plurality of voltage limiting ...

Method of Forming a Super Junction Semiconductor Device Having Stripe-Shaped Regions of the Opposite Conductivity Types

A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type. 1. A method of forming a super junction semiconductor device , the method comprising:forming at least a portion of a drift layer on a doped layer of a first conductivity type;implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order; andperforming a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type.2. The method of claim 1 , wherein the openings to form the stripe-shaped first implant regions and the stripe-shaped second implant regions are formed in the same mask.3. The method of claim 1 , wherein the openings are aligned to each other such that the stripe-shaped first implant regions are separated from the stripe-shaped second implant regions at uniform distances.4. The method of claim 1 , wherein the diffusion is controlled such that neighboring ones of the stripe-shaped first and second regions directly adjoin each other.5. The ...

Insulation Structure Formed in a Semiconductor Substrate and Method for Forming an Insulation Structure

A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.

Semiconductor Device with Enhancement and Depletion FinFET Cells

A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins. 1. A semiconductor device , comprising:enhancement FinFET (fin field effect transistor) cells comprising first gate structures separating first semiconductor fins;depletion FinFET cells comprising second gate structures separating second semiconductor fins; anda connection structure arranged between the first and second gate structures and separating the first semiconductor fins from the second semiconductor fins, wherein a specific conductance of the connection structure is higher than in the second semiconductor fins.2. The semiconductor device of claim 1 , whereinthe connection structure includes heavily doped semiconducting zones which are effective as drain zones for the enhancement FinFET cells and as source zones for the depletion FinFET cells.3. The semiconductor device of claim 1 , whereina vertical extension of the connection structure is greater than a vertical extension of the first semiconductor fins.4. The semiconductor device of claim 1 , whereinthe connection structure includes a semiconducting zone of the conductivity type of channel zones formed in the second semiconductor fins and an impurity concentration in the semiconducting zone is at least ten times as high as a mean net impurity concentration in the channel zones.5. The semiconductor device of claim 1 , further comprising:a metal contact structure directly adjoining the connection structure.6. The semiconductor device of claim 1 , further comprising:a ...

Circuit Arrangement Having a First Semiconductor Switch and a Second Semiconductor Switch

A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area. 1. A circuit arrangement , comprising:a circuit having a first semiconductor switch and a second semiconductor switch, each of the first semiconductor switch and the second semiconductor switch comprising a load path and a control terminal and having their load paths connected in series, a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the corresponding semiconductor switch; and', 'a second semiconductor device having a load path between a first load terminal and a second load terminal, and a control terminal;, 'wherein each of the first and the second semiconductor switches compriseswherein each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device,wherein the second semiconductor devices and the first semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices,wherein the first semiconductor switch and the ...

Methods of Manufacturing a Semiconductor Device with a Buried Doped Region and a Contact Structure

A method of manufacturing a semiconductor device includes: forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate; forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane; removing the second section of the semiconductor column; and forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure includes a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound. 1. A method of manufacturing a semiconductor device , the method comprising:forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate;forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane;removing the second section of the semiconductor column; andforming a contact structure extending from the main surface plane to the doped region, wherein the contact structure comprises a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound.2. The method of claim 1 , wherein the doped region is formed in the first claim 1 , section of the semiconductor column after ...

Semiconductor Device, Integrated Circuit and Method of Forming a Semiconductor Device

A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface. 1. A semiconductor device comprising a transistor in a semiconductor body having a first main surface , the transistor comprising:a source region;a drain region;a channel region;a drift zone;a source contact electrically connected to the source region;a drain contact electrically connected to the drain region;a gate electrode at the channel region, the channel region and the drift zone being disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region having a shape of a first ridge extending along the first direction,one of the source contact and the drain contact being adjacent to the first main surface, the other one of the source contact and the drain contact being adjacent to a second main surface that is opposite to the first main surface.2. The semiconductor device according to claim 1 , further comprising a back side metallization over the second main surface claim 1 , the back side metallization being connected to the source contact or the drain contact being adjacent to the second main surface.3. The semiconductor ...

Lateral Superjunction Transistor Device and Method for Producing Thereof

A transistor arrangement and a method are disclosed. The transistor arrangement includes: a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, the first semiconductor regions and the second semiconductor regions being arranged alternatingly in a vertical direction of a semiconductor body; a source region adjoining the plurality of first semiconductor regions; a drain region adjoining the plurality of second semiconductor regions and arranged spaced apart from the source region in a first lateral direction; and a plurality of gate regions each of which adjoins at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. At least one of the first and semiconductor regions, but less than each of the first and second semiconductor regions has a doping dose that varies in the first lateral direction. 1. A transistor arrangement , comprising:a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, wherein the first semiconductor regions and the second semiconductor regions are arranged alternatingly in a vertical direction of a semiconductor body;a source region adjoining the plurality of first semiconductor regions;a drain region adjoining the plurality of second semiconductor regions and arranged spaced apart from the source region in a first lateral direction; anda plurality of gate regions, each of the plurality of gate regions adjoining at least one of the plurality of second semiconductor regions and being arranged between the source region and the drain region,wherein at least one of the first and second semiconductor regions has a doping dose that varies in the first lateral direction, andwherein the remainder of the first and second semiconductor regions each have an essentially homogenous doping dose.2. The transistor arrangement of ...

SEMICONDUCTOR DEVICE HAVING BURIED GATE ELECTRODE STRUCTURES

A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure. 1. A semiconductor device , comprising:a first gate electrode structure buried in a semiconductor portion and comprising array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes;a second gate electrode structure buried in the semiconductor portion and comprising array stripes inside a second cell array of transistor cells, wherein an array isolation region of the semiconductor portion separates the first and second gate electrode structures; anda connection plug extending between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure.2. The semiconductor device of claim 1 , wherein the contact stripe is wider than the array stripes.3. The semiconductor device of claim 1 , wherein a fill structure extends between the first surface and the array stripes and a spacer structure from a material of the fill structure extends along the connection plug between the first surface and the first gate electrode structure.4. The semiconductor device of claim 1 , comprising at least one spacer stripe structurally connecting the array stripes with the contact stripe.5. The ...

SEMICONDUCTOR DIE WITH A POWER DEVICE AND METHOD OF MANUFACTURING THE SAME

The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode. 1. A semiconductor die comprising a transistor device , the transistor device having:a channel region formed in a semiconductor body;a gate region aside the channel region and configured to control a channel formation;a drift region formed in the semiconductor body; anda field electrode in a field electrode trench,wherein the field electrode trench extends from a frontside of the semiconductor body vertically into the drift region,wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer,wherein a capacitor electrode formed in the insulating layer is conductively connected to at least a portion of the field electrode.2. The semiconductor die of claim 1 , wherein the field electrode comprises a first and a second field electrode structure claim 1 , wherein the first field electrode structure is capacitively coupled to a first section of the drift region claim 1 , wherein the second field electrode structure is capacitively coupled to a second section of the drift region claim 1 , and wherein the second section is arranged vertically above the first section.3. The semiconductor die of claim 2 , wherein the capacitor electrode formed in the insulating layer is conductively connected to the first field ...

Power Transistor with Field-Electrode

A semiconductor device includes at least two transistor cells. Each of these at least two transistor cells includes: a drain region, a drift region, and a body region in a semiconductor fin of a semiconductor body; a source region adjoining the body region; a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and a field electrode dielectrically insulated from the drift region by a field electrode dielectric, and connected to the source region. The field electrode dielectric is arranged in a first trench between the semiconductor fin and the field electrode. The at least two transistor cells include a first transistor cell, and a second transistor cell. The semiconductor fin of the first transistor cell is separated from the semiconductor fin of the second transistor cell by a second trench different from the first trench. 1. A power transistor comprising at least two transistor cells , each comprising:a drain region, a drift region, and a body region in a semiconductor fin of a semiconductor body;a source region adjoining the body region;a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric;a field electrode dielectrically insulated from the drift region by a field electrode dielectric, and connected to the source region, wherein the field electrode dielectric is arranged in a first trench between the semiconductor fin and the field electrode;wherein the at least two transistor cells comprise a first transistor cell, and a second transistor cell, andwherein the semiconductor fin of the first transistor cell is separated from the semiconductor fin of the second transistor cell by a second trench different from the first trench.2. The power transistor of claim 1 , wherein the at least two transistor cells comprise a third transistor cell claim 1 , wherein the first transistor cell and the third transistor cell have the same field electrode.3. The ...

SEMICONDUCTOR COMPONENT WITH FIELD ELECTRODE BETWEEN ADJACENT SEMICONDUCTOR FINS AND METHOD FOR PRODUCING SUCH A SEMICONDUCTOR COMPONENT

A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides. 1. A semiconductor component , comprising:semiconductor fins formed between a base plane and a main surface of a semiconductor body, each semiconductor fin comprising a source region formed between the main surface and a channel/body region and a drift zone formed between the channel/body region and the base plane;gate electrode structures on two mutually opposite sides of each channel/body region;a field electrode structure between mutually adjacent ones of the semiconductor fins, each field electrode structure being separated from the drift zones by a field dielectric and extending from the main surface as far as the base plane, wherein the gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from at least two sides;{'sup': '−3', 'a buried connection layer having a net dopant concentration of at least 1E18 cmbetween the base plane and a rear-side surface opposite the main surface; and'}a transistor connection connected to the connection layer and comprising a contact or a highly doped column extending from the main surface as far as the ...

Semiconductor Device with Buried Doped Region and Contact Structure

A semiconductor device includes a buried doped region at a first distance to a main surface of a semiconductor body. A contact structure extends from the main surface to the doped region. The contact structure includes a contact layer formed from a metal-semiconductor alloy that directly adjoins the doped region. The contact structure further includes a fill structure formed from a metal or a conductive metal compound. An insulator structure surrounds the contact structure in cross-sections parallel to the main surface.

Circuit Arrangement Having Semiconductor Switches

A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area. 1. A circuit arrangement , comprising:a circuit having a first semiconductor switch and a second semiconductor switch, each of the first semiconductor switch and the second semiconductor switch comprising a load path and a control terminal and having their load paths connected in series, a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the corresponding semiconductor switch; and', 'a second semiconductor device having a load path between a first load terminal and a second load terminal, and a control terminal;, 'wherein each of the first and the second semiconductor switches compriseswherein each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device,wherein the second semiconductor devices and the first semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices,wherein the first semiconductor switch and the ...

SEMICONDUCTOR DEVICE WITH DEVICE SEPARATION STRUCTURES

A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches. 1. A semiconductor device , comprising:a first gate electrode structure buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion, the first gate electrode structure including parallel array stripes;a second gate electrode structure buried in the semiconductor portion in a second cell array adjacent to the first cell array, the second gate electrode structure including parallel array stripes;a device separation structure between the first and second cell arrays, the device separation structure having a first width; andcell separation structures having at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.2. The semiconductor device according to claim 1 , wherein the device separation structure includes a first section oriented to the first surface and an extension section oriented to a second surface of the semiconductor portion parallel to the first surface ...

HALF-BRIDGE CIRCUIT HAVING AT LEAST TWO SOLID-STATE SWITCHING DEVICES CONNECTED IN SERIES

According to an embodiment, a half-bridge circuit includes at least two solid-state switching devices connected in series. Each switching device has a high-voltage switching transistor configured to switch a high voltage based on a switching signal and a switching driver circuit operationally connected to the high-voltage switching transistor. The switching driver circuit includes a low-voltage driver transistor having a source, a drain and a gate, connected in series to the high-voltage switching transistor and being configured to transfer the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor. 1. A half-bridge circuit , comprising: a high-voltage switching transistor configured to switch a high voltage based on a switching signal; and', 'a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit comprising a low-voltage driver transistor comprising a source, a drain and a gate, connected in series to the high-voltage switching transistor and being configured to transfer the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor., 'at least two solid-state switching devices connected in series, each switching device having2. The half-bridge circuit of claim 1 , wherein at least one of the solid-state switching devices comprises an active drift zone.3. The half-bridge circuit of claim 1 , further comprising a logic circuit operationally connected to the low-voltage driver transistor and configured to provide the switching signal.4. The half-bridge circuit of claim 1 , wherein the high-voltage switching transistor and the low-voltage driver transistor are electrically connected in a cascode circuit.5. The half-bridge circuit of claim 1 , ...

Power Converter Circuit

A power converter circuit includes an input and an output. A supply circuit is configured to receive an input signal from the input and to generate a number of supply signals from the input signal. A number of converter units are provided. Each of the plurality of converter units is configured to receive one of the plurality of supply signals and to output an output signal to the output.

Method of Manufacturing a Semiconductor Device with Buried Channel/Body Zone and Semiconductor Device

A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins. 1. A semiconductor device , comprising:a source zone of a first conductivity type formed in a first electrode fin extending from a first surface into a semiconductor portion;a drain region of the first conductivity type formed in a second electrode fin extending from the first surface into the semiconductor portion; anda channel/body zone formed in a transistor fin extending between the first and second electrode fins at a distance to the first surface,wherein the first and second electrode fins extend along a first lateral direction,wherein a width of first gate sections arranged on opposing sides of the transistor fin along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins.2. The semiconductor device of claim 1 , whereinthe transistor fin has a rectangular cross-section in a plane parallel to the first lateral direction and perpendicular to the first surface.3. The semiconductor device of claim 1 , whereinsidewalls of the transistor fin extending perpendicular to the first surface are {111} crystallographic planes of a silicon crystal.4. The semiconductor device of claim 1 , whereinthe width of the first ...

Method for Manufacturing a Semiconductor Device and a Semiconductor Device

A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel region and a drift zone between the source region and the drain region. The source and drain regions are arranged along a first direction parallel to the main surface. Gate trenches and a gate electrode are formed in the gate trenches. The gate trenches have a distance corresponding to a width d of the channel region, where d≦2*ld and ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode. An auxiliary trench formed in the main surface extends in a second direction intersecting the first direction. The source region is formed using a doping method that introduces dopants via a sidewall of the auxiliary trench. 1. A method of forming a semiconductor device comprising forming a transistor in a semiconductor substrate having a main surface , the method further comprising:forming a source region and a drain region;forming a channel region and a drift zone arranged between the source region and the drain region, the source region and the drain region being arranged along a first direction parallel to the main surface;{'b': 1', '1', '1, 'forming gate trenches and a gate electrode in the gate trenches, the gate trenches having a distance corresponding to a width d of the channel region, the width d fulfilling: d≦2*ld, where ld denotes a length of a depletion zone formed at an interface between the channel region and a gate dielectric adjacent to the gate electrode; and'}forming an auxiliary trench in the main surface, the auxiliary trench extending in a second direction intersecting the first direction, the source region being formed using a doping method that introduces dopants via a sidewall of the auxiliary trench.2. The method according to claim 1 , wherein forming the auxiliary trench comprises an anisotropic etching process ...

Bidirectionally blocking electronic switch arrangement

An electronic circuit includes first and second electronic switches each having a load path and a control node, a plurality of switch units each having a load path between a first load node and a second load node, and a plurality of drive units. The load paths of the electronic switches and switch units are connected in series to form a load path of the electronic circuit. A series circuit with the load paths of the switch units is connected between the load paths of the electronic switches. The load path of the electronic circuit includes a plurality of taps. Each drive unit is associated with one of the switch units, is coupled to at least two different taps of the plurality of taps, and is configured to drive the associated switch unit based on an electrical potential at one of the at least two different taps.

Circuit Arrangement with a Rectifier Circuit

A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices. 1. A circuit arrangement comprising a rectifier circuit , the rectifier circuit comprising:a first and a second load terminal;a first semiconductor device having a load path and a control terminal;a plurality of second semiconductor devices each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device, and wherein a series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals of the rectifier circuit, andwherein the control terminal of one of the second semiconductor devices is connected to one of the load terminals of the first semiconductor device, and wherein the control terminals of the second semiconductor devices other than the one second semiconductor device are connected to a load terminal of the one second semiconductor device.2. The circuit arrangement of claim 1 , wherein the first ...

Semiconductor Device and Method for Producing a Semiconductor Device

A method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, the first implantation regions and the second implantation regions being arranged alternatingly. 1. A method , comprising:forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier,wherein forming the layer stack comprises forming a plurality of epitaxial layers on the carrier,wherein forming each of the plurality of epitaxial layers comprises depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions,wherein the first implantation regions and the second implantation regions are arranged alternatingly.2. The method of claim 1 , wherein each of the plurality of epitaxial layers comprises a first number of first implantation regions and a second number of second implantation regions claim 1 , wherein the first number is different from the second number or the first number equals the second number.3. The method of claim 1 , wherein forming each implantation ...

Transistor Arrangement and Method of Producing Thereof

A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer. 1. A transistor arrangement , comprising:a layer stack comprising a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type;a first source region of a first transistor device adjoining the plurality of first semiconductor layers;a first drain region of the first transistor device adjoining the plurality of second semiconductor layers and spaced apart from the first source region in a first direction;a plurality of gate regions of the first transistor device, wherein each of the plurality of gate regions adjoins at least one of the plurality of second semiconductor layers, is arranged between the first source region and the first drain region, and is spaced apart from the first source region and the first drain region;a third semiconductor layer adjoining the layer stack and each of the first source region, the first drain region, and the plurality of gate regions; andactive regions of a second transistor device ...

Semiconductor Device Having Silicide Layers

A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer. 1. A semiconductor device , comprising:a semiconductor substrate having a first side;a trench structure having a bottom and a sidewall, the bottom having at least a first bottom portion and a second bottom portion laterally adjacent to the first bottom portion, wherein each of the first and second bottom portions have a concave shape with a ridge formed between the first and second bottom portions;an insulating material covering the sidewall and the first bottom portion of the trench structure while leaving the second bottom portion of the trench structure uncovered;a mesa region extending to the first side of the semiconductor substrate and forming the sidewall of the trench structure;a first silicide layer on a top region of the mesa region;a second silicide layer on the second bottom portion of the trench structure;a first metal layer on and in contact with the first silicide layer; anda second metal layer on and in contact with the second silicide layer.2. The semiconductor device of claim 1 , wherein the second metal layer has a larger thickness than the first metal layer and extends from the ...

Method for Manufacturing a Semiconductor Device Having Silicide Layers

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate having a first side;forming a trench having a bottom, the trench extending from the first side of the semiconductor substrate into the semiconductor substrate and separating a first mesa region formed in the semiconductor substrate from a second mesa region formed in the semiconductor substrate;filling the trench with an insulating material;removing the second mesa region relative to the insulating material filled in the trench to form a recess in the semiconductor substrate, the recess having at least one side wall covered with the insulating material and a bottom; andforming, in a common process, a first silicide layer on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer on and in contact with the bottom of the recess.2. The method of claim 1 , wherein a distance between the first side of the semiconductor substrate and the bottom of the recess is at least 500 nm.3. The method of claim 1 , further comprising:depositing a common metal layer on and in contact with the first silicide layer and on and in contact with the second silicide layer;forming a mask layer on the metal layer; ...

Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device

A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode. 1. A lateral power semiconductor device , comprising:a semiconductor body having a first surface and a second surface opposite the first surface;a first main electrode comprising at least two sections arranged on the first surface;a second main electrode arranged on the first surface and between the two sections of the first main electrode;a plurality of switchable semiconductor cells arranged between a respective one of the two sections of the first main electrode and the second main electrode and configured to provide a controllable conductive path between the first main electrode and the second main electrode; andat least one curved semiconductor portion between the first main electrode and the second main electrode with increasing doping concentration from the first main electrode to the second main electrode.2. The lateral power semiconductor device according to claim 1 , wherein claim 1 , in a cross-section perpendicular to the first surface claim 1 , for any location in the curved semiconductor portion between the ...

Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. 1. A semiconductor device arrangement , comprising:a first semiconductor device having a load path between load terminals; anda plurality of second transistors, each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,wherein each but one of the second transistors has its control terminal connected to the load terminal of another one of the second transistors, andwherein one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.2. The semiconductor device arrangement of claim 1 ,wherein one of the second transistors has its load path directly connected to the load path of the first semiconductor device and has its control terminal connected to a first load terminal of the first semiconductor device; andwherein each of the other second transistors has its control terminal connected to a first load terminal of an adjacent second transistor.3. The semiconductor device arrangement of claim 1 , wherein the first semiconductor device and/or one or more of the second transistors is one of a MOSFET claim 1 , a MISFET claim 1 , a MESFET claim 1 , an IGBT claim 1 , a JFET claim 1 , a HEMT claim 1 , a ...

Circuit Arrangement with a Rectifier Circuit

In accordance with an embodiment, a method includes receiving by a drive circuit electrical power from a voltage tap of a first rectifier circuit that includes a load path and a voltage tap, and using the electrical power by the drive circuit to drive a second rectifier circuit that includes a load path. The load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node. 1. A circuit arrangement , comprising:a first rectifier circuit comprising a load path and a voltage tap;a second rectifier circuit comprising a load path and a drive input, and configured to be switched on and off by a drive signal received at the drive input; anda drive circuit comprising a first supply input coupled to the voltage tap of the first rectifier circuit and a first drive output coupled to the drive input of the second rectifier circuit,wherein the load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node, andwherein the drive circuit is configured to drive at least the second rectifier circuit using electrical power received from the voltage tap of the first rectifier circuit.2. The circuit arrangement of claim 1 , wherein the load path of the first rectifier circuit and the load path of the second rectifier circuit are connected in parallel.3. The circuit arrangement of claim 2 , wherein the second rectifier circuit comprises:a transistor comprising a drive node coupled to the drive input of the second rectifier circuit and a load path; anda rectifier element,wherein the rectifier element is connected in parallel with the load path of the transistor, andwherein the load path of the transistor forms the load path of the second rectifier circuit.4. The circuit arrangement of claim 3 , wherein the drive circuit is configuredto detect at least one of a current through the first rectifier circuit and a voltage across the first rectifier circuit, andto ...

Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices

A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices. 1. A circuit arrangement , comprising:a first semiconductor device having a load path;a plurality of second semiconductor devices, each second semiconductor device having a control terminal and a load path between a first load terminal and a second load terminal, the second semiconductor devices having their load paths connected in series and connected in series with the load path of the first semiconductor device, wherein a load terminal of a first one of the second semiconductor devices is connected to a first load terminal of an adjacent one of the second semiconductor devices; anda voltage limiting element coupled between the control terminal of the first one of the second semiconductor devices and the second load terminal of the adjacent one of the second semiconductor devices, wherein the voltage limiting element comprises a transistor.2. The circuit arrangement of claim 1 , wherein the voltage limiting element comprises a normally-on transistor.3. The circuit arrangement of claim 2 , wherein the normally-on transistor comprises one of a JFET claim 2 , a depletion MOSFET claim 2 , and a FINFET.4. The circuit arrangement of claim 2 , wherein the normally-on transistor comprises one of a SiC JFET claim 2 , ...

Battery Element, a Battery and a Method for Forming a Battery

A battery element includes a substrate with a plurality of trenches extending into the substrate. At least a part of each trench of the plurality of trenches is filled with a solid state battery structure. Further, the battery element includes a front side battery element electrode arranged at a front side of the substrate and electrically connected to a first electrode layer of the solid state battery structures within the plurality of trenches. Additionally, the battery element includes a backside battery element electrode arranged at a backside of the substrate and electrically connected to a second electrode layer of the solid state battery structures within the plurality of trenches.

Method for Forming a Battery Element, a Battery Element and a Battery

A method for forming a battery element includes etching trenches into a substrate and crystal orientation dependent etching of the trenches. Further, the method includes forming solid state battery structures within the trenches. 1. A method for forming a battery element , the method comprising:etching trenches into a substrate;performing a crystal orientation dependent etching of the trenches; andforming solid state battery structures within the trenches.2. The method of claim 1 , wherein the crystal orientation dependent etching comprises a wet chemical etch process.3. The method of claim 1 , wherein the crystal orientation dependent etching comprises etching with Potassium hydroxide or ammonium hydroxide.4. The method of claim 1 , wherein etching the trenches into the substrate comprises performing a dry chemical etch process.5. The method of claim 1 , wherein the trenches comprise a substantially rectangular lateral shape or a substantially quadratic lateral shape.6. The method of claim 1 , wherein the trenches are distributed over the substrate according to a hexagonal pattern or a quadratic pattern.7. The method of claim 1 , wherein forming the solid state battery structures within the trenches comprises forming a solid state electrolyte layer between a first electrode layer and a second electrode layer.8. The method of claim 7 , wherein the solid state electrolyte layer comprises lithium phosphorus oxynitride.9. The method of claim 7 , wherein the first electrode layer comprises an anode layer comprising carbon or silicon.10. The method of claim 7 , wherein the second electrode layer comprises a cathode layer comprising lithium cobalt oxide and a collector layer comprising titan nitride.11. The method of claim 1 , wherein the trenches extend into the substrate to a depth greater than 500 μm.12. The method of claim 1 , wherein the trenches comprise an aspect ratio larger than 10.13. The method of claim 1 , wherein the trenches comprise a maximal width of less ...

Method of Manufacturing a Semiconductor Device Having a Buried Channel/Body Zone

A method of manufacturing a semiconductor device includes etching cavities into a semiconductor layer by crystallographic etching having an etch rate that depends upon an orientation of crystal planes, wherein a transistor fin is formed between two of the cavities at a distance to a first surface of the semiconductor layer, forming a channel/body zone of a transistor cell in the transistor fin, and forming source zones and drain regions of the transistor cell in the semiconductor layer, wherein junctions between the channel/body zone and the source zones as well as the drain regions are formed at a distance to the first surface. 1. A method of manufacturing a semiconductor device , the method comprising:etching cavities into a semiconductor layer by crystallographic etching having an etch rate that depends upon an orientation of crystal planes, wherein a transistor fin is formed between two of the cavities at a distance to a first surface of the semiconductor layer;forming a channel/body zone of a transistor cell in the transistor fin; andforming source zones and drain regions of the transistor cell in the semiconductor layer, wherein junctions between the channel/body zone and the source zones as well as the drain regions are formed at a distance to the first surface.2. The method of claim 1 , further comprising:forming first gate sections in the cavities on opposing sides of the transistor fin.3. The method of claim 1 , further comprising:forming separation trenches between electrode fins, wherein the cavities extend from a bottom of the separation trenches into the semiconductor layer and the source zones and drain regions are formed in portions of the electrode fins.4. The method of claim 3 , wherein a plurality of transistor fins is formed between each pair of electrode fins.5. The method of claim 1 , further comprising:forming a gate dielectric covering exposed surfaces of the transistor fins before providing the gate electrode.6. The method of claim 5 , ...

Method for Forming Complementary Doped Semiconductor Regions in a Semiconductor Body

A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region. 1. A method , comprising:forming a first trench and a second trench in a semiconductor body;forming a first material layer on the semiconductor body in the first trench and the second trench such that a first residual trench remains in the first trench and a second residual trench remains in the second trench, the first material layer including dopants of a first doping type;removing the first material layer from the second trench;forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench, the second material layer including dopants of a second doping type, complementary to the first doping type; anddiffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.2. The method of claim 1 , wherein one of the first material layer and the second material layer comprises BSG.3. The method of claim 2 , wherein the other one of the first ...

Semiconductor Device and Method of Producing the Same

A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.

Semiconductor Device Having a Channel Region Patterned into a Ridge by Adjacent Gate Trenches

A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface. 1. A semiconductor device comprising a transistor in a semiconductor body having a first main surface , the transistor comprising:a source region;a drain region;a channel region;a drifta source contact electrically connected to the source region;a drain contact electrically connected to the drain region;a gate electrode at the channel region, the channel region and the drift zone being disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region patterned into a first ridge by adjacent gate trenches formed in the first main surface of the semiconductor substrate, the adjacent gate trenches being spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the first ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction, respectively; andat least one of the source contact and the drain contact being adjacent to a second main surface that is opposite to the first main ...

Transistor Arrangement Including Power Transistors and Voltage Limiting Means

A Transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer. 1. A transistor arrangement in a semiconductor body , the transistor arrangement comprising:a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body;a voltage limiting device with at least two device cells;wherein each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell, wherein the voltage limiting device is separated from the power transistor by a dielectric layer.2. The transistor arrangement according to claim 1 , wherein each transistor cell comprisesa drain region, a drift region, and a body region in a semiconductor fin of a semiconductor body;a source region adjoining the body region;a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric;a field electrode dielectrically insulated from the drift region by a field electrode dielectric, and connected to the source region, wherein the field electrode dielectric is arranged in a first trench between the semiconductor fin and the field electrode;wherein the at least two transistor cells comprise a first transistor cell, and a second transistor cell, andwherein the semiconductor fin of the first transistor cell is separated from the semiconductor fin of the second transistor cell by a second trench different from the first trench.3. The transistor arrangement of claim 1 , wherein each device cell comprises a cathode region claim 1 , an anode region and an additional ...

Method for Forming a Power Semiconductor Device and a Power Semiconductor Device

A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated. 1. A method for forming a power semiconductor device , the method comprising:providing a semiconductor layer of a first conductivity type extending to a first side and comprising a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the semiconductor layer; and forming a trench which extends from the first side into the semiconductor layer and comprises, in a vertical cross-section perpendicular to the first side, a wall;', 'forming a compensation semiconductor region of the first conductivity type at the wall, the compensation semiconductor region comprising a second doping concentration of the first dopants higher than the first doping concentration; and', 'filling the trench with a dielectric material,, 'forming a deep trench isolation, comprisingwherein an amount of the first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type, which are trapped in the trench, is, next to the wall, at least partly ...

Electronic Circuit with Several Electronic Switches Connected in Series and a Drive Circuit

An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch. 1. An electronic circuit , comprising:a first electronic switch;a drive circuit comprising an output coupled to a control node of the first electronic switch, and an input;a switch circuit with a plurality of second electronic switches, wherein load paths of the second electronic switches are connected in series, and wherein the switch circuit is connected between a first load node of the first electronic switch and a reference node;a first signal input configured to receive a first input signal;a level shifter coupled between the first signal input and the input of the drive circuit and comprising a plurality of cascaded level shifter cells,wherein each of the plurality of level shifter cells comprises a signal input, a signal output, a first supply node and a second supply node,wherein each of the plurality of level shifter cells is associated with a respective one of the plurality of second electronic switches,wherein the first supply node of each of the plurality of level shifter cells is coupled to a first load node of the associated second electronic switch, and the second ...

SEMICONDUCTOR DEVICE ARRANGEMENT WITH A FIRST SEMICONDUCTOR DEVICE AND WITH A PLURALITY OF SECOND SEMICONDUCTOR DEVICES

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. 1. A semiconductor device arrangement , comprising:a normally-off device having a load path between load terminals; anda plurality of normally-on devices, each having a load path between a first load terminal and a second load terminal and a control terminal;wherein the normally-on devices have their load paths connected in series and connected in series to the load path of the normally-off device, andwherein each but one of the normally-on devices has its control terminal connected to the load terminal of another one of the normally-on devices.2. The semiconductor device arrangement of claim 1 ,wherein one of the normally-on devices has its control terminal connected to one of the load terminals of the normally-off device.3. The semiconductor device arrangement of claim 1 ,wherein one of the normally-on devices has its load path directly connected to the load path of the normally-off device and has its control terminal connected to a first load terminal of the normally-off device; andwherein each of the other normally-on devices has its control terminal connected to a first load terminal of an adjacent normally-on device.4. The semiconductor device arrangement of claim 1 , wherein the normally-off device and/or one or more of the normally-on devices is one of a MOSFET claim 1 , a MISFET claim 1 , a MESFET claim 1 , an IGBT claim 1 , a JFET claim 1 , ...

Circuit Arrangement with a Rectifier Circuit

In accordance with an embodiment, a method includes receiving by a drive circuit electrical power from a voltage tap of a first rectifier circuit that includes a load path and a voltage tap, and using the electrical power by the drive circuit to drive a second rectifier circuit that includes a load path. The load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node. 1a first rectifier circuit comprising a load path and a voltage tap;a second rectifier circuit comprising a load path and a drive input, and configured to be switched on and off by a drive signal received at the drive input; anda drive circuit comprising a first supply input coupled to the voltage tap of the first rectifier circuit and a first drive output coupled to the drive input of the second rectifier circuit,wherein the load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node, andwherein the drive circuit is configured to drive at least the second rectifier circuit using electrical power received from the voltage tap of the first rectifier circuit.. A circuit arrangement, comprising: This application is a continuation of U.S. patent application Ser. No. 14/630,217 filed on Feb. 24, 2015, which application is hereby incorporated herein by reference in its entirety.This disclosure in general relates to an electronic circuit arrangement including a rectifier circuit and, more particularly, an active rectifier circuit.Rectifiers are electronic circuits or electronic devices that allow a current to flow in a first direction, while substantially preventing a current to flow in an opposite second direction. Such rectifiers are widely used in a variety of electronic circuits in automotive, industrial and consumer applications, in particular in power conversion and drive applications.Conventional rectifiers can be implemented with a diode that conducts a current when ...

Semiconductor Device and Method of Producing the Same

A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. The first and second semiconductor layers are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each of at least one second semiconductor region of the first semiconductor device adjoins at least one of the plurality of second semiconductor layers, and is spaced apart from the first semiconductor region. Each of at least one barrier layer configured to form a diffusion barrier is arranged in parallel to the first surface and to the second surface and adjacent to one of the first semiconductor layers, or adjacent to one of the second semiconductor layers, or both. 1. A semiconductor device , comprising:a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type, the first semiconductor layers and the second semiconductor layers being arranged alternatingly between a first surface and a second surface of the layer stack;a first semiconductor region of a first semiconductor device adjoining the plurality of first semiconductor layers;at least one second semiconductor region of the first semiconductor device, each of the at least one second semiconductor region adjoining at least one of the plurality of second semiconductor layers and spaced apart from the first semiconductor region; andat least one barrier layer configured to form a diffusion barrier, each of the at least one barrier layer arranged in parallel to the first surface and to the second surface and adjacent to one of the first semiconductor layers, or adjacent to one of the second semiconductor layers, or both.2. The ...

Mechanical seal

Method for forming a battery element, a battery element and a battery

A method for forming a battery element includes etching trenches into a substrate and crystal orientation dependent etching of the trenches. Further, the method includes forming solid state battery structures within the trenches.

Battery element, a battery and a method for forming a battery

A battery element includes a substrate with a plurality of trenches extending into the substrate. At least a part of each trench of the plurality of trenches is filled with a solid state battery structure. Further, the battery element includes a front side battery element electrode arranged at a front side of the substrate and electrically connected to a first electrode layer of the solid state battery structures within the plurality of trenches. Additionally, the battery element includes a backside battery element electrode arranged at a backside of the substrate and electrically connected to a second electrode layer of the solid state battery structures within the plurality of trenches.

Semiconductor device having a channel region patterned into a ridge by adjacent gate trenches

A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

Integrated circuit having a memory cell array and method of forming an integrated circuit

An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

Semiconductor device, integrated circuit and method of manufacturing a semiconductor device

Eine Halbleitervorrichtung umfasst einen Transistor, der in einem Halbleiterkörper gebildet ist, der eine erste Hauptoberfläche hat. Der Transistor umfasst einen Sourcebereich, einen Drainbereich, einen Kanalbereich, eine Driftzone, einen Sourcekontakt, der elektrisch mit dem Sourcebereich verbunden ist, einen Drainkontakt, der elektrisch mit dem Drainbereich verbunden ist, und eine Gateelektrode an dem Kanalbereich. Der Kanalbereich und die Driftzone sind längs einer ersten Richtung zwischen dem Sourcebereich und dem Drainbereich angeordnet, wobei die erste Richtung parallel zu der ersten Hauptoberfläche ist. Der Kanalbereich hat eine Gestalt eines ersten Kammes, der sich längs der ersten Richtung erstreckt. Ein Kontakt aus dem Sourcekontakt und dem Drainkontakt ist benachbart zu der ersten Hauptoberfläche, und der andere Kontakt aus dem Sourcekontakt und dem Drainkontakt ist benachbart zu einer zweiten Hauptoberfläche, die entgegengesetzt zu der ersten Hauptoberfläche ist. A semiconductor device includes a transistor formed in a semiconductor body having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift region, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are arranged along a first direction between the source region and the drain region, wherein the first direction is parallel to the first main surface. The channel region has a shape of a first crest extending along the first direction. One contact from the source contact and the drain contact is adjacent to the first main surface, and the other contact from the source contact and the drain contact is adjacent to a second major surface that is opposite the first main surface.

Device for controlling the transporting speed of piles (stacks)

The invention relates to a device for controlling the transporting speed of piles to be moved horizontally, as a function of the pile density at pile deliveries and at pile feeding devices. Previously known pile deliveries have the drawback that further transporting of the folded sheets out of the region of sheet depositing does not take place continuously. The invention is based on the object of realising a pile transporting speed which adapts itself in a way corresponding to the conditions which exist. This object is achieved by there being arranged within the plane of the pile board a sheet trap and by there also being arranged a sensor, preferably a light barrier, and also a further light barrier and an aperture disc. If the light barriers simultaneously deliver a pulse, the conveying speed of the pile is reduced, making the latter denser. If there is no sheet in the sheet trap, the conveying speed is increased and the pile becomes looser, so that the depositing space also becomes free. <IMAGE>

Methods for Manufacturing a Structure on or in a Substrate, Imaging Layer for Generating Sublithographic Structures, Method for Inverting a Sublithographic Pattern, Device Obtainable by Manufacturing a Structure

One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Transistor device

In an embodiment, a transistor device is provided that comprises a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type, the body region forming an interface with the source region, a drain region extending to the main surface and having the first conductivity type, a drift region having the first conductivity type and extending between the body region and the drain region and a gate electrode arranged on the main surface laterally between the source region and the drain region and electrically insulated from the semiconductor body by an insulation structure. The insulation structure comprises a gate dielectric arranged on the main surface and a shallow trench arranged in the drift region and filled with electrically insulating material. The shallow trench has at least partly a wedge shape and the electrically insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface of the semiconductor body.

Integrated circuit with a split function gate

An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV.

Solid-state switching device having a high-voltage switching transistor and a low-voltage driver transistor

According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.

Storage capacitor and method of manufacturing a storage capacitor

A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

DRAM cell pair and DRAM memory cell array with stack and trench memory cells, and method of fabricating a DRAM memory cell array

In einem DRAM-Speicherzellenfeld sind Stack- und Trench-Speicherzellen (22, 21) vorgesehen. Die Stack- und Trench-Speicherzellen (22, 21) sind zu gleichartigen Zellenpaaren (2) mit jeweils einem Trenchkondensator (4), einem Stackkondensator (5) sowie einem Halbleitersteg (14) angeordnet, in dem die aktiven Gebiete (31, 31') zweier Auswahltransistoren zur Adressierung des Trench- bzw. des Stackkondensators (4, 5) ausgebildet sind. Die Halbleiterstege (14) sind in Längsrichtung hintereinander zu Zellenzeilen (15) angeordnet und dabei durch jeweils einen Trenchkondensator (4) voneinander beabstandet. Jeweils benachbarte Zellenzeilen (15) sind durch Grabenisolatorstrukturen (16) voneinander separiert und um die halbe Länge eines Zellenpaares (2) gegeneinander versetzt. Die Halbleiterstege (14) werden von mindestens zwei zu den Zellenzeilen (15) orthogonalen aktiven Wortleitungen (7) zur Adressierung der im Halbleitersteg (14) realisierten Auswahltransistoren gekreuzt. Ferner kreuzen pro Zellenpaar (2) zwei passive Wortleitungen (7, 7') zur Adressierung von in den benachbarten Zellenzeilen (15) ausgeführten Auswahltransistoren. Die Bitleitungen (8) verlaufen oberhalb der Grabenisolatorstrukturen (16) parallel zu den Zellenzeilen (15). Der Flächenbedarf pro Speicherzelle beträgt 4 F È 2 F mit F als kleinster photolithographisch darstellbarer Strukturgröße. Sowohl die Trenchkondensatoren (4) als auch die Stackkondensatoren (5) lassen sich in maximaler Packungsdichte anordnen. ... In a DRAM memory cell array stack and trench memory cells (22, 21) are provided. The stack and trench memory cells (22, 21) are arranged to similar cell pairs (2) each having a trench capacitor (4), a stack capacitor (5) and a semiconductor fin (14), in which the active regions (31, 31 '. ) of two selection transistors for addressing the trench or stack capacitor (4, 5) are formed. The semiconductor bars (14) are arranged one behind the other in the longitudinal direction to cell rows ...

Fabricating a memory cell arrangement

A method is described for fabricating a DRAM memory cell, which includes a trench capacitor and a select transistor. After the capacitor trench has been etched and optionally the first capacitor electrode has been produced, the trench is filled with a dummy filling. After the gate electrode and the first and second source/drain regions have been provided, the dummy filling is removed, and the capacitor dielectric and the second capacitor electrode are provided. As a result, it is possible to use temperature-sensitive materials for the capacitor dielectric and the second capacitor electrode despite the use of high-temperature steps. In the memory cell arrangement formed by this method, the direction of the conductive channel, which connects first and second source/drain regions to one another, can differ from the direction of the bit lines and of the word lines (e.g., by 45°).

Method of manufacturing a semiconductor device with device separation structures

A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.

SEMICONDUCTOR DEVICE WITH A CONTINUOUS CONTACT STRUCTURE AND MANUFACTURING PROCESS

Ein Schichtstapel (600) wird auf einer Hauptoberfläche (101a) einer Halbleiterschicht (100a) gebildet, wobei der Schichtstapel (600) eine dielektrische Deckschicht (210a) und eine Metallschicht (310a) zwischen der Deckschicht (210a) und der Halbleiterschicht (100a) umfasst. Zweite Teile (620) des Schichtstapels (600) werden entfernt, um Spalte (611) zwischen zurückbleibenden ersten Teilen (610) zu bilden. Justierstrukturen (220) eines zweiten dielektrischen Materials werden in den Spalten (611) gebildet. Eine Zwischenschicht (230) des ersten oder eines dritten dielektrischen Materials wird gebildet und bedeckt die Justierstrukturen (220) und die ersten Teile (610). Kontakttrenches (301) werden gebildet, die sich durch die Zwischenschicht (230) und die Deckschicht (210a) zu Metallstrukturen (311, 321) erstrecken, die von verbleibenden Teilen der Metallschicht (310a) in den ersten Teilen (610) gebildet sind, wobei die Deckschicht (210a) selektiv gegenüber den Hilfsstrukturen (220) geätzt wird. A layer stack (600) is formed on a main surface (101a) of a semiconductor layer (100a), the layer stack (600) comprising a dielectric cap layer (210a) and a metal layer (310a) between the cap layer (210a) and the semiconductor layer (100a) , Second portions (620) of the layer stack (600) are removed to form gaps (611) between remaining first portions (610). Alignment structures (220) of a second dielectric material are formed in the gaps (611). An interlayer (230) of the first or third dielectric material is formed covering the alignment features (220) and the first portions (610). Contact trenches (301) are formed which extend through the intermediate layer (230) and the cap layer (210a) to metal structures (311, 321) formed of remaining parts of the metal layer (310a) in the first parts (610) the cover layer (210a) is etched selectively with respect to the auxiliary structures (220).

Integrated circuit having a memory cell array and method of forming an integrated circuit

Lateral superjunction transistor device and method for producing thereof

A transistor arrangement and a method are disclosed. The transistor arrangement includes: a plurality of first semiconductor regions (11) of a first doping type and a plurality of second semiconductor regions (12) of a second doping type, wherein the first semiconductor regions (11) and the second semiconductor regions (12) are arranged altematingly in a vertical direction (z) of a semiconductor body (100); a source region (13) adjoining the plurality of first semiconductor regions (11); a drain region (15) adjoining the plurality of second semiconductor regions (120) and arranged spaced apart from the source region (13) in a first lateral direction (x); and a plurality of gate regions (14), wherein each of the plurality of gate regions (14) adjoins at least one of the plurality of second semiconductor regions (12) and is arranged between the source region (13) and the drain region (15). At least one of the first and semiconductor regions (11, 12), but less than each of the first and second semiconductor regions (11 12) has a doping dose that varies in the first lateral direction (x).

Cell field for DRAMs comprises memory cells having lower source/drain regions with sections of trenched source/drain layer perforated by perforated trenches and word line trenches

A cell field comprises memory cells (2) having lower source/drain regions (33) with sections of a trenched source/drain layer (332) perforated by perforated trenches (20) and word line trenches (7). An independent claim is also included for the production of a cell field.

STI formation for vertical and planar transistors

A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

METHOD FOR PRODUCING COMPLEMENTARY DOTED SEMICONDUCTOR AREAS IN A SEMICONDUCTOR BODY AND SEMICONDUCTOR ASSEMBLY

Es sind ein Verfahren und eine Halbleiteranordnung offenbart. Das Verfahren beinhaltet: Erzeugen eines ersten Grabens (11) und eines zweiten Grabens (12) in einem Halbleiterkörper (100); Erzeugen einer ersten Materialschicht (21) auf dem Halbleiterkörper (100) in dem ersten Graben (11) und dem zweiten Graben (12) derart, dass in dem ersten Graben (11) ein erster Restgraben (13) verbleibt und in dem zweiten Graben (12) ein zweiter Restgraben (14) verbleibt; Entfernen des ersten Materials (21) aus dem zweiten Graben; und Erzeugen einer zweiten Materialschicht (22) auf der ersten Materialschicht (21) in dem ersten Restgraben (13) und auf dem Halbleiterkörper (100) in dem zweiten Graben (12). Die erste Materialschicht (21) enthält Dotierstoffe eines ersten Dotierungstyps und die zweite Materialschicht (22) enthält Dotierstoffe eines zum ersten Dotierungstyp komplementären zweiten Dotierungstyps. Das Verfahren beinhaltet weiterhin das Diffundieren von Dotierstoffen aus der ersten Materialschicht (21) in dem ersten Graben (11) in den Halbleiterkörper (100), um ein erstes dotiertes Gebiet (31) zu erzeugen, und aus der zweiten Materialschicht (22) in dem zweiten Graben (12) in den Halbleiterkörper (100), um ein zweites dotiertes Gebiet zu erzeugen. A method and a semiconductor device are disclosed. The method includes: generating a first trench (11) and a second trench (12) in a semiconductor body (100); Producing a first material layer (21) on the semiconductor body (100) in the first trench (11) and the second trench (12) such that in the first trench (11) a first residual trench (13) remains and in the second trench ( 12) a second residual trench (14) remains; Removing the first material (21) from the second trench; and producing a second material layer (22) on the first material layer (21) in the first residual trench (13) and on the semiconductor body (100) in the second trench (12). The first material layer (21) contains dopants of a first doping type and the second ...

Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Method of manufacturing a transistor and a method of forming a memory device

A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between the two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

Arc deceleration device

Process of fabricating DRAM cells with collar isolation layers

A process of preparing DRAM cells with collar isolation layers that isolate the trench top with vertical cell and active area from the buried plate to eliminate the space normally required by a final collar, comprising: a) etching a deep trench (DT) in a substrate over which a patterned pad stack serving as a mask is positioned; b) depositing a silicon nitride sacrificial collar liner in a top art of the trench; c) etching below the sacrificial collar to form a bottle structure in a lower part of the trench; d) forming an oxide layer, a nitride layer over the oxide layer, depositing a resist fill, and affecting a recess of the resist fill to a recess depth below the top of the bottle formation; e) affecting a nitride etch followed by a resist strip f) affecting thermal oxidation using the nitride layer as a mask to form a closed layer of oxide at the top of the trench bottle shaped structure; g) affecting a nitride strip; and h) forming a buried plate by gas phase doping to cause isolation between the active area and the buried plate.

Mechanical seal

Semiconductor device having a high breakdown voltage

A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. A fourth semiconductor region adjoins the first semiconductor layers, is spaced apart from the first semiconductor region, and is arranged in the first device region between the first end of the first semiconductor region and the third semiconductor region.

Circuit arrangement with a rectifier circuit

A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices.

Manufacturing process for memory cells with collar insulation layers

Herstellungsverfahren für DRAM-Zellen mit Kragenisolationsschichten, welche den oberen Bereich des Grabens mit vertikaler Zelle und aktivem Gebiet von der vergrabenen Platte isolieren, umfassend das Ätzen eines tiefen Grabens (DT) in einem Substrat, über welchem ein strukturierter Padstapel, welcher als eine Maske dient, positioniert ist; das Ablagern eines Siliziumnitrid-Liners als Opferkragen in einem oberen Bereich des Grabens; das Ätzen unterhalb des Opferkragens, um eine flaschenförmige Struktur in einem unteren Bereich des Grabens auszubilden; das Ausbilden einer Oxid-Schicht, einer Nitrid-Schicht über der Oxid-Schicht, das Ablagern einer Resistfüllung und Bewirken einer Einsenkung der Resistfüllung bis zu einer Tiefe der Einsenkung unterhalb des oberen Endes der gebildeten flaschenförmigen Struktur; das Bewirken einer Nitrid-Ätzung gefolgt von einem Entfernen des Resists; das Bewirken thermischer Oxidation unter Verwendung der Nitrid-Schicht als eine Maske zur Ausbildung einer geschlossenen Oxid-Schicht am oberen Ende der flaschenförmigen Grabenstruktur; das Bewirken eines Entfernens des Nitrids; und das Ausbilden einer vergrabenen Platte durch Dotierung aus der Gasphase, um eine Isolation zwischen dem aktiven Bereich und der vergrabenen Platte zu bewirken. Das Verfahren vermeidet den Platzbedarf, welcher normalerweise durch einen Abschlusskragen erfordert wird. Manufacturing method for DRAM cells with collar isolation layers that isolate the top of the vertical cell and active area trench from the buried plate, comprising etching a deep trench (DT) in a substrate, over which a patterned pad stack serves as a mask , is positioned; depositing a silicon nitride liner as a sacrificial collar in an upper region of the trench; etching below the sacrificial collar to form a bottle-shaped structure in a lower region of the trench; forming an oxide layer, a nitride layer over the oxide layer, depositing a resist fill, and causing the resist fill to sink to a depth of ...

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Fabricating a memory cell array

A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.

Storage capacitor and method of manufacturing a storage capacitor

An integrated circuit including a storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

Memory cell with a trench capacitor and method for its manufacture

Die Erfindung betrifft eine Speicherzelle (1), die einen Graben (3) aufweist, in dem ein Grabenkondensator (32) gebildet ist. Weiterhin ist in dem Graben (3) ein vertikaler Transistor oberhalb des Grabenkondensators (32) gebildet. Die Dotiergebiete (15, 16) des vertikalen Transistors sind im Substrat (2) angeordnet. Zum Anschluß der Gate-Elektrode (12) des vertikalen Transistors an eine Wortleitung ist eine dielektrische Schicht (17) mit einer Innenöffnung im Graben (3) oberhalb der Gate-Elektrode (12) angeordnet. Die dielektrische Schicht (17) ist als seitliche Randstege (18) ausgebildet, die über den Querschnitt des Grabens (3) hinausragen und somit einen Teil des Substrates (2) bedecken. Die seitlichen Randstege (18) ermöglichen eine selbstjustierte Bildung eines Isolationsgrabens (21). The invention relates to a memory cell (1) which has a trench (3) in which a trench capacitor (32) is formed. Furthermore, in the trench (3), a vertical transistor above the trench capacitor (32) is formed. The doping regions (15, 16) of the vertical transistor are arranged in the substrate (2). For connecting the gate electrode (12) of the vertical transistor to a word line, a dielectric layer (17) having an internal opening in the trench (3) is arranged above the gate electrode (12). The dielectric layer (17) is formed as lateral edge webs (18) which protrude beyond the cross section of the trench (3) and thus cover a part of the substrate (2). The lateral edge webs (18) allow a self-aligned formation of an isolation trench (21).

A manufacturing method of an integrated semiconductor memory device and corresponding semiconductor memory device

Herstellungsverfahren für eine integrierte Halbleiterspeichervorrichtung umfassend die Schritte: – Bereitstellen eines Halbleitersubstrats (1); – Ausbilden einer Mehrzahl von Reihen aktiver Gebiete (AA1, AA2, AA3) auf dem Halbleitersubstrat (1), wobei jede der Reihen aktiver Gebiete (AA1, AA2, AA3) eine Mehrzahl von Speicherzellen-Auswahltransistoren mit einem zugehörigen Wortleitungs-Kontakt (WC), einem Bitleitungs-Kontakt (CB) und mit einem Knoten-Kontakt (N1–N4), aufweist; – Ausbilden einer Mehrzahl gefüllter Isoliergräben (IT), welche zwischen den Reihen aktiver Gebiete (AA1, AA2, AA3) angeordnet sind; – Ausbilden einer Mehrzahl von Verdrahtungsstreifen (u1', u2', u2'', u3', u3'', u4', u4'', u5', u5'', u6', u6'', u7'), von denen jeder einen zugeordneten Knoten-Kontakt (N1–N4) eines Speicherzellen-Auswahltransistors von einer Reihe aktiver Gebiete (AA1, AA2, AA3) oberhalb eines benachbarten gefüllten Isoliergrabens (IT) verdrahtet, um einen entsprechenden verdrahteten Knoten-Kontakt (N1'–N4') zu bilden, wobei das Ausbilden einer Mehrzahl von Verdrahtungsstreifen (u1', u2', u2'', u3', u3'', u4', u4'', u5', u5'', u6', u6'', u7') ein Ausbilden einer Umverdrahtungsschicht... A manufacturing method for an integrated semiconductor memory device comprising the steps of: - providing a semiconductor substrate (1); - Forming a plurality of rows of active areas (AA1, AA2, AA3) on the semiconductor substrate (1), each of the rows of active areas (AA1, AA2, AA3) having a plurality of memory cell selection transistors with an associated word line contact (WC) , a bit line contact (CB) and to a node contact (N1-N4); - Formation of a plurality of filled isolation trenches (IT) which are arranged between the rows of active areas (AA1, AA2, AA3); - Forming a plurality of wiring strips (u1 ', u2', u2 '', u3 ', u3' &# ...