PRODUCING A MONO-CRYSTALLINE SHEET

A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy. 122-. (canceled)23. A method for producing a mono-crystalline sheet of a semiconductor material comprising:providing at least two aperture elements forming a gap in between;providing a molten alloy comprising the semiconductor material in the gap between said at least two aperture elements;providing a gaseous precursor medium delivering the semiconductor material in the vicinity of the molten alloy;providing a nucleation crystal in the vicinity of the molten alloy; andbringing in contact said nucleation crystal and the molten alloy.24. The method of claim 23 , comprising: positioning the aperture elements and the molten alloy such that the molten alloy is held between the aperture elements by surface tension.25. The method of claim 24 , comprising: retracting the nucleation crystal gradually from the molten alloy.26. The method of claim 25 , comprising: heating the aperture elements.27. The method of claim 26 , wherein the semiconductor material is released from the gaseous precursor medium comprising the semiconductor material into the molten ...

Nanowire devices

A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

THERMOELECTRIC ELEMENTS

A thermoelectric element includes a body formed of a single thermoelectric material and extending in a first direction along which a thermal gradient is established in thermoelectric operation, wherein the body has at least first and second adjacent sections in the first direction; at least one of the sections is subject to stress which is applied to that section substantially all around a central axis of the body in the first direction; and the arrangement is such that the stress results in different strain in the first and second sections producing an energy barrier in the body to enhance thermoelectric operation. 1. A thermoelectric element , comprising:a body formed of a single thermoelectric material and extending in a first direction along which a thermal gradient is established in thermoelectric operation,wherein the body has at least first and second adjacent sections in the first direction;at least one of the sections is subject to stress which is applied to that section substantially all around a central axis of the body in the first direction; andthe arrangement is such that the stress results in different strain in the first and second sections producing an energy barrier in the body to enhance thermoelectric operation.2. The thermoelectric element of claim 1 , wherein at least one of the sections has a stressor layer formed on the surface thereof to apply stress to that section.3. The thermoelectric element of claim 2 , wherein the stressor layer surrounds the section around the axis.4. The thermoelectric element of claim 2 , wherein the stressor layer is adapted to reduce thermal conductance in the body.5. The thermoelectric element of claim 1 , wherein a stressor layer is formed on only one of the sections.6. The thermoelectric element of claim 5 , wherein the stress applied by the stressor layer results in the different strain producing the energy barrier.7. The thermoelectric element of claim 1 , wherein both of the first and second sections are ...

THERMOELECTRIC DEVICE

A thermoelectric device for transferring heat from a heat source to a heat sink. The device includes a first thermoelectric leg pair having a first leg including an n-type semiconductor material and a second leg including a p-type semiconductor material, wherein the first leg and the second leg are electrically coupled in series; a second thermoelectric leg pair has a third leg including an n-type semiconductor material and a fourth leg including a p-type semiconductor material, wherein the third leg and the fourth leg are electrically coupled in series; a first contact placed between the first leg and the fourth leg and a second contact placed between the second leg and the third leg. A method for manufacturing a thermoelectric device is also provided. 1. A thermoelectric device for transferring heat from a heat source to a heat sink , the thermoelectric device comprising:a first thermoelectric leg pair having a first leg including an n-type semiconductor material and a second leg including a p-type semiconductor material, wherein the first leg and the second leg are electrically coupled in series;a second thermoelectric leg pair having a third leg including an n-type semiconductor material and a fourth leg IRA-including a p-type semiconductor material, wherein the third leg and the fourth leg are electrically coupled in series;a first contact placed between the first leg the fourth leg; anda second contact placed between the second leg and the third leg.2. The thermoelectric device of claim 1 , wherein the first and the second thermoelectric leg pair are thermally coupled in series between the heat source and the heat sink.3. The thermoelectric device of claim 1 , wherein the first leg and the second leg are thermally coupled in parallel between the heat source and the heat sink and the third leg and the fourth leg are thermally coupled in parallel between the heat source and the heat sink.4. The thermoelectric device of claim 1 , wherein the first contact and the ...

Array of optoelectronic structures and fabrication thereof

A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

PRODUCING A MONO-CRYSTALLINE SHEET OF SEMICONDUCTOR MATERIAL

A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy. 1. A mono-crystalline silicon sheet of a semiconductor material produced by a method of:providing at least two aperture elements forming a gap in between;providing a molten alloy comprising a mono-crystalline sheet of semiconductor material in the gap between said at least two aperture elements, whereby the molten alloy is held between the gaps by surface tension below a horizontal arrangement of the at least two aperture elements;providing a gaseous precursor medium delivering the semiconductor material in the vicinity of the molten alloy;providing a nucleation crystal below the molten alloy;bringing in contact said nucleation crystal and the molten alloy; andretracting the mono-crystalline sheet of semiconductor material that is continuously growing below the molten alloy.2. A solar cell arrangement comprising a mono-crystalline sheet of a semiconductor material produced by a method of:providing at least two aperture elements forming a gap in between;providing a molten alloy comprising a mono-crystalline sheet of semiconductor material in the ...

DEVICE COMPRISING POLYMORPHIC RESISTIVE CELLS

A device comprising a control unit and a plurality of resistive cells. The plurality of resistive cells each comprises a first terminal, a second terminal and a polymorphic layer comprising a polymorphic material. The polymorphic layer is configured to form a tunnel barrier. The polymorphic layer is arranged between the first terminal and the second terminal. The first terminal, the second terminal and the polymorphic layer form a tunnel junction. 1. A device , comprising:a control unit and a plurality of resistive cells, the resistive cells comprising:a first terminal;a second terminal; anda polymorphic layer comprising a polymorphic material, the polymorphic layer being configured to form a tunnel barrier and being arranged between the first terminal and the second terminal, wherein a crystalline form of the polymorphic material is variable among at least two crystalline structures of stable lattices;wherein the first terminal, the second terminal and the polymorphic layer form a tunnel junction.2. The device according to claim 1 , wherein the polymorphic layer is configured to exhibit a first crystalline form and a second crystalline form claim 1 , the first crystalline form has a first resistance state and the second crystalline form has a second resistance state.3. The device according to claim 2 , wherein the control unit is configured to apply heat to the resistive cells in order to switch interchangeably between the first and the second crystalline form and its corresponding first and second resistance state.4. The device according to claim 2 , wherein the control unit is configured to switch enantiotropically between the first and the second crystalline form and its corresponding first and second resistance state.5. The device according to claim 2 , wherein the polymorphic material is configured to show a kinetically irreversible transition between the first and the second crystalline form.6. The device according to claim 2 , wherein at least one of the ...

RECONFIGURABLE TUNNEL FIELD-EFFECT TRANSISTORS

A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region. 1. A tunnel field-effect transistor (TFET) device , comprising:first and second semiconductor contact regions separated by a semiconductor channel region;a channel gate overlying the channel region; andfirst and second doping gates overlying the first and second contact regions respectively;wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region.2. The TFET device of claim 1 , wherein the channel region is configured such that formation of a tunnel junction results from application of a bias voltage to the channel gate.3. The TFET device of claim 1 , wherein the channel region is configured such that claim 1 , on application of the positive and negative voltage levels to the doping gates claim 1 , a tunnel junction exists when no bias voltage is applied to the channel gate.4. The TFET device of claim 1 , wherein each of the contact regions comprises a substantially undoped semiconductor.5. The TFET device of claim 1 , wherein the channel region and the contact regions are formed from the same semiconductor.6. The TFET device of claim 1 , wherein the channel region and the contact ...

Nanowire devices

A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

NANOWIRE DEVICES

A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device. 1. A method for forming a nanowire device , the method comprising:forming a semiconductor nanowire between a first support and a second support;forming a stressor layer circumferentially surrounding the semiconductor nanowire, wherein, due to the stressor layer, the nanowire is subjected to radial strain;wherein the stressor layer is formed by forming a preliminary layer on the nanowire; and processing the preliminary layer to activate the preliminary layer to apply stress to the nanowire.2. The method of claim 1 , further comprising forming a fixation layer over the preliminary layer prior the processing of the preliminary layer to substantially maintain an outer surface geometry of the preliminary layer.3. The method of claim 2 , wherein the preliminary layer comprises an amorphous chalcogenide-based alloy.4. The method of claim 3 , wherein the preliminary layer comprises GeTe selectively formed as a conformal coating by chemical vapor deposition (CVD) claim 3 , having a thickness of about 10 to 20 nanometers (nm).5. The method of claim 2 , wherein the fixation layer comprises TaN claim 2 , formed by atomic layer deposition (ALD) claim 2 , at a thickness of about 10 nm.6. The method of claim 5 , wherein the ALD is performed at a temperature below a crystallization temperature of the preliminary layer.7. The method of claim 2 , wherein the processing of the preliminary layer further comprises heating the preliminary ...

DEVICE FOR STORING ELECTRICAL ENERGY

A device for storing electrical energy comprises a photo electrode, having a semiconductor layer with a photo dye thereon, a counter electrode, a reservoir comprising a solvent, a first redox mediator for enabling a redox reaction at the photo electrode, a second redox mediator for enabling a redox reaction at the counter electrode, wherein the photo electrode and the counter electrode are at least partly in the solvent, the first redox mediator is adapted to form an entity that is soluble in the solvent when the first redox mediator is in its reduced state, and an entity that is insoluble in the solvent when the first redox mediator is in its oxidized state. 2. A device according to claim 1 , wherein the second redox mediator is adapted to form: 'an entity that is insoluble in the solvent when the first redox mediator is in its reduced state.', 'an entity that is soluble in the solvent when the second redox mediator is in its oxidized state; and'}3. A device according to claim 1 , wherein the working electrode comprises a non-soluble coating claim 1 , the coating comprising the second redox mediator.4. A device according to claim 2 , the device being operable to perform in a charging cycle the steps of:injecting, upon solar spectrum excitation, electrons by the photo dye into the semiconductor layer that travel via a charging circuit from the photo electrode to the counter electrode;oxidizing the first redox mediator at the photo electrode, thereby depositing the first redox mediator at the photo electrode and releasing electrons to the photo electrode in order to reduce the photo dye;reducing the second redox mediator at the counter electrode by means of the electrons that travelled from the photo electrode to the counter electrode, thereby depositing the second redox mediator at the counter electrode.5. A device according to claim 2 , the device being operable to perform in a discharging cycle the steps of:oxidizing, at the counter electrode, the second redox ...

Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.

THERMOELECTRIC DEVICE

A thermoelectric device for transferring heat from a heat source to a heat sink includes at least one thermoelectric leg pair having a first leg including an n-type semiconductor material and a second leg including a p-type semiconductor material. The first leg and the second leg are electrically coupled in series. A resistive element electrically couples the first leg and the second leg between the heat source and the heat sink. 1. A thermoelectric device for transferring heat from a heat source to a heat sink , comprising:at least one thermoelectric leg pair having a first leg including an n-type semiconductor material and a second leg including a p-type semiconductor material, wherein the first leg and the second leg are electrically coupled in series; anda resistive element electrically coupling the first leg and the second leg between the heat source and the heat sink.2. The thermoelectric device of claim 1 , wherein the first leg and the second leg are thermally coupled in parallel between the heat source and the heat sink.3. The thermoelectric device of claim 1 , wherein the at least one resistive element is adapted to at least partially bypass an electric current through a junction between the first leg and the second leg.4. The thermoelectric device of claim 1 , wherein the at least one resistive element is arranged between the first leg and the second leg such that a Joule heating of the legs is concentrated towards the side of the heat sink.5. The thermoelectric device of claim 1 , wherein a cross section of the first and/or the second leg varies along a direction from the heat source to the heat sink.6. The thermoelectric device of claim 1 , wherein the at least one resistive element comprises a material having a temperature-dependent conductance.7. The thermoelectric device of claim 1 , wherein the at least one resistive element comprises a material that is arranged between the first leg and the second leg and extends at least partially along the first ...

Fabrication of semiconductor junctions

A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

Array of optoelectronic structures and fabrication thereof

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

SEMICONDUCTOR DEVICE

A semiconductor device for use in an optical application and a method for fabricating the device. The device includes: an optically passive aspect that is operable in a substantially optically passive mode; and an optically active material having a material that is operable in a substantially optically active mode, wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure, and the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect. 1. A semiconductor device for use in an optical application comprising:an optically passive aspect that is operable in a substantially optically passive mode;an optically active material having a material that is operable in a substantially optically active mode;wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure; andwherein the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect.2. The semiconductor device as claimed in claim 1 , wherein the optically active material is substantially selectively formed in the predefined structure.3. The semiconductor device as claimed in claim 1 , wherein the optically active material is formed relative to the optically passive aspect so as to exceed an area of the predefined structure.4. The semiconductor device as claimed in claim 3 , wherein excess optically active material is removed so that the optically active material is provided in the predefined structure.5. The semiconductor device as claimed in claim 4 , wherein the excess optically active material is removed by wet-chemical etching or chemical mechanical polishing.6. The semiconductor device as claimed in claim 1 , wherein a structural characteristic of the predefined structure is chosen to facilitate the optically active ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE FOR USE IN AN OPTICAL APPLICATION

A semiconductor device for use in an optical application and a method for fabricating the device. The device includes: an optically passive aspect that is operable in a substantially optically passive mode; and an optically active material having a material that is operable in a substantially optically active mode, wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure, and the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect. 1. A method for fabricating a semiconductor device for use in an optical application , the method comprising:providing an optically passive aspect that is operable in a substantially optically passive mode;providing an optically active material having a material that is operable in a substantially optically active mode;wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure; andwherein the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect.2. The method according to claim 1 , wherein the optically active material is substantially selectively formed in the predefined structure.3. The method according to claim 1 , wherein the optically active material is formed relative to the optically passive aspect so as to exceed an area of the predefined structure.4. The method according to claim 3 , wherein excess optically active material is removed so that the optically active material is provided in the predefined structure.5. The method according to claim 4 , wherein the excess optically active material is removed by wet-chemical etching or chemical mechanical polishing.6. The method according to claim 1 , wherein a structural characteristic of the predefined structure is chosen to facilitate the optically active material to be ...

OPTICAL SPECTROMETER

An optical spectrometer contains a photodiode and a straining mechanism for imposing adjustable strain on the photodiode. The spectrometer includes a measurement apparatus for measuring variation of photocurrent with strain at different values of the adjustable strain imposed by the straining mechanism. Adjusting the strain allows adjustment of the band gap Eof the photosensitive region of the photodiode, and this determines the cut-off energy for absorption of photons. Measuring variation of photocurrent with strain at different values of the adjustable strain imposed by the straining mechanism allows study of photons within a desired energy range of the band gap energy corresponding to each strain value. 1. An optical spectrometer comprising:a photodiode;a straining mechanism for imposing adjustable strain on the photodiode; anda measurement apparatus for measuring variation of photocurrent with strain at different values of said adjustable strain imposed by the straining mechanism.2. The optical spectrometer as claimed in claim 1 , wherein the measurement apparatus comprises:a measurement circuit for measuring a photocurrent-versus-strain characteristic as said strain is adjusted by the straining mechanism; anda measurement processor for processing said characteristic to determine variation of photocurrent with strain at different values of said adjustable strain.3. The optical spectrometer as claimed in claim 1 , wherein:the straining mechanism is adapted to impose strain having an adjustable constant strain component and a time-varying strain component; andthe measurement apparatus comprises a measurement circuit for measuring photocurrent variation due to said time-varying strain component.4. The optical spectrometer as claimed in claim 3 , wherein the time-varying strain component oscillates at a predetermined frequency f.5. The optical spectrometer as claimed in claim 4 , wherein the measurement circuit is adapted to measure the photocurrent variation at a ...

SEMICONDUCTOR NANOWIRE FABRICATION

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×10nm. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure. 1. A method for fabricating a semiconductor nanowire on a substrate , the method comprising:{'sup': 4', '2, 'forming a nanowire template defining an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface, the seed surface being exposed to the tunnel and having an area up to about 2×10nm; and'}via said opening, selectively growing the semiconductor nanowire in the template from the seed surface.2. The method according to claim 1 , wherein the area of the seed surface is no greater than about 10nm.3. The method according to claim 2 , wherein the area of the seed surface is such that growth of the nanowire proceeds from a single nucleation point on the seed surface.4. The method according to claim 1 , wherein the seed surface has a width of up to about 100 nm and a breadth claim 1 , perpendicular to said width claim 1 , of up to about 100 nm.5. The method according to claim 1 , wherein the seed surface occludes one end of the tunnel.6. The method according to claim 5 , wherein the seed surface is perpendicular to the longitudinal axis of the tunnel.7. The method according to claim 1 , wherein the seed surface is a monocrystalline semiconductor surface.8. The method according ...

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND ELECTRONIC DEVICE

A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material. 1. A semiconductor structure comprising:a substrate comprising a first semiconductor material;a dielectric layer on the substrate;a second semiconductor material on the dielectric layer, the second semiconductor material including a portion directly on the substrate, the second semiconductor material being crystalline and having an essentially flat lateral surface; anda third semiconductor material grown on the lateral surface.2. The semiconductor structure of claim 1 , further comprising a different crystalline semiconductor material spaced apart from the second semiconductor material.3. The semiconductor structure of claim 1 , further comprising a further dielectric material on the second semiconductor material and on the third semiconductor material.4. The semiconductor structure of claim 3 , wherein:the second semiconductor material including a second lateral surface opposition the essentially flat lateral surface; andthe further dielectric material is on second lateral surface.5. The semiconductor structure of claim 1 , further ...

Semiconductor device with epitaxially grown active layer adjacent a subsequently grown optically passive region

A semiconductor device 1 comprising an optically passive aspect 2 and an optically active material 3 wherein the optically passive aspect 2 further comprises at least a crystalline seed layer (4), the optically active material 3 being epitaxially grown in a predefined structure 5 provided in the optically passive aspect 2 that extends to at least an upper surface 4 of the seed layer 4, and the optically passive aspect 2 is structured to comprise a passive photonic structure 6 subsequent to the growth of the optically active material 3. The active material 3 may be implemented as a light emitting structure e.g. a laser, an LED or a optical amplifier amongst others. The predefined structure 5 may be a hole or a trench. The photonic structure 6 may be a waveguide. The device may include a VCSEL. Holes (11 in figure 4) may be formed in the photonic structure 6 and the active region 3. The size of the holes may be tapered to increase towards the photonic structure 6 or may be the same size. The device may comprise a 2D photonic crystal.

Temperature sensing

SThM apparatus includes a heated sensor 5, heated support 4 and analyser 11. The analyzer signal extractor 15 includes a low pass filter (23) to extract a DC signal component representing time averaged values and a lock-in amplifier (24) to extract an AC signal component representing time dependent values. A sample temperature controller 12 causes a periodic sinusoidal modulation in sample temperature, generating a heat flux between sample and sensor on contact. The signal components are processed to determine their amplitude/ magnitude ratio, used to indicate sample temperature for each measurement position. Different aspects include control of power to maintain temperature by feedback and analysis of two AC components representing Joule and Peltier heating and cooling.

Organic opto-electronic devices

The present invention pertains to new flip-chip organic opto-electronic structures and methods for making the same. The new organic opto-electronic device includes at least two separate parts. Each part comprises an electrode and at least one of these electrodes carries an organic stack. After completion of these separate parts both are brought together to form the complete opto-electronic device. It is a crucial aspect of the new flip-chip approach that spacers are integrated on one or both sides of the parts and that an interface formation process is employed.

Producing a mono-crystalline sheet

A method for producing a mono-crystalline sheet (11), in particular a silicon sheet (11), comprises: providing at least two aperture elements (1, 2) forming a gap (3) in-between; providing a molten alloy (4) comprising silicon in the gap (3) between said at least two aperture elements (1, 2); providing a gaseous precursor medium (5) comprising silicon in the vicinity of the molten alloy (4); providing a silicon nucleation crystal (6) in the vicinity of the molten alloy (4); and bringing in contact said silicon nucleation crystal (6) and the molten alloy (4). A device (10, 20) for producing a mono-crystalline sheet (11), in particular a silicon sheet (11), comprises at least two aperture elements (1, 2) at a predetermined distance (D) from each other thereby forming a gap (3), and being adapted to be heated for holding a molten alloy (4) comprising silicon by surface tension in the gap (3) between the aperture elements (1,2 ); a means (15) for supplying a gaseous precursor medium (5) comprising silicon in the vicinity of the molten alloy (4); and a positioning means (16) for holding and moving a nucleation crystal (6) in the vicinity of the molten alloy (2).

High-resolution patterning

Semiconductor nanowire fabrication

Methods are provided for fabricating semiconductor nanowires 12, 40, 41, 45, 57 on a substrate 1, 20, 50. A nanowire template 3, 6; 22, 24; 31, 32 is formed on the substrate. The nanowire template defines an elongate tunnel 8, 26, 33 which extends, laterally over the substrate, between an opening 7, 25 in the template and a seed surface 10, 27, 34. The seed surface 10, 27, 34 is exposed to the tunnel and of area up to about 2x 4 10 nm 2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface 10, 27, 34 is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface.

Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

A method for manufacturing a semiconductor structure 1 comprises: providing a substrate 2 including a first semiconductor material; forming a dielectric layer 3 on a surface of the substrate 2; forming an opening in the dielectric layer 3 having a bottom reaching the substrate 2; providing a second semiconductor material 7B in the opening and on the substrate 2, the second semiconductor material 7B being encapsulated by a further dielectric material 6 forming a filled cavity; melting the second semiconductor material 7B in the cavity; recrystallizing the second semiconductor material 7B in the cavity; laterally removing the second semiconductor material 7B at least partially for forming a lateral surface at the second semiconductor material 7B; and forming a third semiconductor material 11 on the lateral surface of the second semiconductor material 7B. Also disclosed is the semiconductor structure 1 produced by the above method. The invention seeks to form compound semiconductor layers on silicon substrates without lattice mismatch deformations.

Tunnel field effect devices

An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

Organic light emitting device, method for producing thereof and array of organic light emitting devices

The present invention is directed to an organic light emitting device (OLED) including a first electrode, a second electrode, at least one layer of organic material arranged between the first electrode and the second electrode, and a dielectric capping layer arranged on the second electrode opposite to the first electrode, wherein the capping layer comprises an outer surface, opposite to the second electrode, for emission of light generated in the at least one layer of organic material. The capping layer has the effect that a reflectance of external light is reduced whereas outcoupling of the light generated in the at least one layer of organic material through the capping layer is increased.

Metal-Oxide-Semiconductor Device Including an Energy Filter

A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

High-resolution patterning

The present invention describes a method to pattern organic and/or inorganic or biological molecules by a printing technique for the use in semiconductor devices, circuits, sensors, biological patterns, biochips, and displays using these layers. One or more species or mixtures of organic molecules, oligomers or nanoparticles (22) are added to a phase-change transfer material (24). The obtained mixture (20) or part of it is heated (21) to the melting temperature of the phase-change material and deposited onto a substrate e.g. a thin film transistor for a full-color display. The heated mixture (21) solidifies instantaneously when it hits the substrate. The phase-change material is then removed by sublimation and a patterned layer of organic and/or inorganic or biological molecules remains on the substrate. The deposition can be repeated to cast multiple layers on top of each other.

Semiconductor unit

Die vorliegende Erfindung bezieht sich auf eine Halbleiter-Einheit (1) zur Verwendung in wenigstens einer optischen Anwendung, die aufweist: wenigstens einen optisch passiven Aspekt (2), der in im Wesentlichen einem optisch passiven Modus betreibbar ist, und wenigstens ein optisch aktives Material (3), das wenigstens ein Material aufweist, das in im Wesentlichen einem optisch aktiven Modus betreibbar ist, wobei: der optisch passive Aspekt (2) des Weiteren wenigstens eine kristalline Kristallkeimschicht (4) aufweist, das optisch aktive Material (3) epitaxial in wenigstens einer vordefinierten Struktur (5) aufgewachsen ist, die in dem optisch passiven Aspekt (2) bereitgestellt ist, die sich bis wenigstens zu einer Oberseite (4') der kristallinen Kristallkeimschicht (4) erstreckt, und der optisch passive Aspekt (2) so strukturiert ist, dass er wenigstens eine passive photonische Struktur (6) aufweist, wobei die kristalline Kristallkeimschicht (4) einen kristallinen Wafer aufweist und wobei das optisch aktive Material (3) wenigstens eines aufweist von: einem III-V-Material und einem II-VI-Material.

Array of optoelectronic structures and fabrication thereof

A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Hybrid semiconductor structure

A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole.

Nanowire devices

Device and method for patterning structures on a substrate

A device for patterning structures on a substrate comprising an imaging device having a scanning tip a light emitting device, and a space around the scanning tip, which space comprises a vapour of a material which is suitable for Chemical Vapour Deposition onto the substrate when decomposed, wherein the light emitting device is adapted to emit a light beam, which light beam has an intensity that is not capable to decompose the vapour, onto the scanning tip in such a way that an electromagnetic field induced by the light beam near the scanning tip is high enough to decompose the vapour.

Device and method for patterning structures on a substrate

A device for patterning structures on a substrate includes an imaging device having a scanning tip, a light emitting device, and a space around the scanning tip. The space comprises a vapour of a material which is suitable for Chemical Vapour Deposition onto the substrate when decomposed. The light emitting device is adapted to emit a light beam, which has an intensity not capable to decompose the vapour, onto the scanning tip in such a way that an electromagnetic field induced by the light beam near the scanning tip is high enough to decompose the vapour.

Device and method for patterning structures on a substrate

A device for patterning structures on a substrate includes an imaging device having a scanning tip, a light emitting device, and a space around the scanning tip. The space comprises a vapor of a material which is suitable for Chemical Vapor Deposition onto the substrate when decomposed. The light emitting device is adapted to emit a light beam, which has an intensity not capable to decompose the vapor, onto the scanning tip in such a way that an electromagnetic field induced by the light beam near the scanning tip is high enough to decompose the vapor.

Thermoelectric device

Thermoelectric device

A thermoelectric device (1) for transferring heat from a heat source (2) to a heat sink (3) comprises a first thermoelectric leg pair (10) having a first leg (4) including an n-type semiconductor material and a second leg (5) including a p-type semiconductor material, wherein the first leg (4) and the second leg (5) are electrically coupled in series. A second thermoelectric leg pair (11) has a third leg (7) including an n-type semiconductor material and a fourth leg (8) including a p-type semiconductor material, wherein the third leg (7) and the fourth leg (8) are electrically coupled in series. A first contact (12) placed between the first leg (4) and the fourth leg (8); and a second contact (13) placed between the second leg (5) and the third leg (7). A method for manufacturing a thermoelectric device or module comprises the steps of: providing a first thermoelectric leg pair (10) having a first leg (4) including an n-type semiconductor material and a second leg (5) including a p-type semiconductor material; electrically coupling the first leg (4) and the second leg (5) of the first thermoelectric leg pair (10) in series; providing a second thermoelectric leg pair (11) having a third leg (7) including an n-type semiconductor material and a fourth leg (8) including a p-type semiconductor material; electrically coupling the third leg (7) and the fourth leg (8) of the second thermoelectric leg pair (11) in series; placing a first contact (12) between the first leg (4) and the fourth leg (8); and placing a second contact (13) between the second leg (5) and the third leg (7).

Method of forming compound semiconductor

A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.

Reconfigurable tunnel field-effect transistors

A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region.

Metal-Oxide-Semiconductor Device Including an Energy Filter

A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Metal-oxide-semiconductor device including an energy filter

A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Method of forming compound semiconductor

Thermoelectric device

A thermoelectric device for transferring heat from a heat source to a heat sink includes at least one thermoelectric leg pair having a first leg including an n-type semiconductor material and a second leg including a p-type semiconductor material. The first leg and the second leg are electrically coupled in series. A resistive element electrically couples the first leg and the second leg between the heat source and the heat sink.

Method for fabricating a semiconductor device for use in an optical application

A semiconductor device for use in an optical application and a method for fabricating the device. The device includes: an optically passive aspect that is operable in a substantially optically passive mode; and an optically active material having a material that is operable in a substantially optically active mode, wherein the optically passive aspect is patterned to include a photonic structure with a predefined structure, and the optically active material is formed in the predefined structure so as to be substantially self-aligned in a lateral plane with the optically passive aspect.

Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.

Optical spectrometer

An optical spectrometer contains a photodiode and a straining mechanism for imposing adjustable strain on the photodiode. The spectrometer includes a measurement apparatus for measuring variation of photocurrent with strain at different values of the adjustable strain imposed by the straining mechanism. Adjusting the strain allows adjustment of the band gap E g of the photosensitive region of the photodiode, and this determines the cut-off energy for absorption of photons. Measuring variation of photocurrent with strain at different values of the adjustable strain imposed by the straining mechanism allows study of photons within a desired energy range of the band gap energy corresponding to each strain value.

Fabrication of semiconductor junctions

A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

Thermoelectric elements

A thermoelectric element includes a body formed of a single thermoelectric material and extending in a first direction along which a thermal gradient is established in thermoelectric operation, wherein the body has at least first and second adjacent sections in the first direction; at least one of the sections is subject to stress which is applied to that section substantially all around a central axis of the body in the first direction; and the arrangement is such that the stress results in different strain in the first and second sections producing an energy barrier in the body to enhance thermoelectric operation.

Producing a mono-crystalline sheet of semiconductor material

A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy.