Vorspannungs- und Vorladungsschaltung für eine Bitzeile mit EPROM-Speicherzellen in CMOS-Technologie.

Speisespannungsschalteranordnung für nichtflüchtige Speicher in MOS-Technologie.

Speisespannungsschalteranordnung für nichtflüchtige Speicher in MOS-Technologie.

Vorspannungs- und Vorladungsschaltung für eine Bitzeile mit EPROM-Speicherzellen in CMOS-Technologie.

BIAS AND PRECHARGING CIRCUIT FOR BIT LINE OF EPROM MEMORY CELL IN CMOS TECHNIQUE

PURPOSE: To reduce the current consumption of a circuit by constituting a precharging section which turns off a bias and the precharger section of a circuit immediately after a sense amplifier reads cells according to the precharge. CONSTITUTION: The biasing section 5 and the precharging section 6 of a bit line 1 are disposed. The sense amplifier section 7 operates by the voltage comparison of a dummy bit line 2 and the bit line 1. The output of the FF 21 of the precharging section 6 forms a signal C acted by a generator 11 in such a system as to change over the signal A and the signal inversion A to such a logic level as to turn off the precharging section and the biasing section 5 after reading with the sense amplifier 7. The external signal D applied on the generator 11 is used for starting the precharge. The current consumption of the circuit is thus reduced. COPYRIGHT: (C)1990,JPO ...

VOLTAGE SUPPLYING SWITCHING DEVICE FOR NON-VOLATILE MEMORY

PURPOSE: To omit a voltage multiplier and to simplify circuits by forming section transistors of P type and holding substrate biases at the max. voltages applied on external pins at the point of this time. CONSTITUTION: The comparator 10 of a switching control unit 9 compares the voltages VPP and VCC based on a signal EPR at all times and makes output UC to an 'H' when the voltage VPP is higher than VCC A switching circuit 12 switches the P type section TRs 5, 6 by the output UC and a programming signal PGR and supplies the voltage VPP or VCC from the external pins 2, 3 to a node 4. At this time, a substrate bias circuit 11 outputs the max. potential VPP or VCC of this moment as the substrate biases Vb and Vbb to suppress the charge implantation to the substrate. As a result, the voltage multiplier for controlling the section TRs is omitted and the circuits are simplified. COPYRIGHT: (C)1990,JPO ...